Semiconductor device including a scribeline and method of manufacturing the semiconductor device

Abstract

A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes: a substrate including a first portion and a second portion; a memory cell disposed on the first portion; an insulating layer disposed on the first portion and the second portion, the insulating layer covering the memory cell, and a portion of the insulating layer disposed on the second portion including a stepped sidewall; and a first pattern group disposed on the second portion and disposed in the portion of the insulating layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall, and the stepped sidewall includes an upper sidewall, a lower sidewall, and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall and has a surface roughness different from that of the upper sidewall.

Description

[0001] This patent application claims the priority of Korean Patent Application No. 10-2019-0163727, filed with the Korean Intellectual Property Office (KIPO) on December 10, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device including a scribe line and a method of manufacturing a semiconductor device. Background Art

[0003] The process of manufacturing a semiconductor device includes a process of forming a plurality of semiconductor chips and a scribe line between the plurality of semiconductor chips on a substrate. A plurality of test patterns and a plurality of alignment key patterns may be provided on the scribe line. Various studies have been conducted to effectively arrange the plurality of test patterns and the plurality of alignment key patterns in the scribe line.

[0004] To evaluate the electrical performance of elements constituting a semiconductor device (e.g., an integrated circuit chip), a predetermined pattern of measurement elements or test elements (so-called test element group (TEG)) is formed on the scribe line of a semiconductor wafer. Electrical tests are performed on the TEG to determine whether the elements are properly formed in the semiconductor device formed on the semiconductor wafer.

[0005] In addition to the TEG, various forms of wafer alignment keys are inserted into the scribe line for performing a lithography process. In such a scribe line, there are various shapes of steppers, including a laser step alignment mark, a field image alignment mark, a K-TV, a target for mounting a die, a covering cursor, a deformed cursor, a rotating cursor, etc. Summary of the Invention

[0006] The inventive concept provides a semiconductor device that effectively sets test patterns and alignment key patterns and a method of manufacturing a semiconductor device.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a first part and a second part; a memory cell disposed on the first part; an insulating layer disposed on the first part and the second part, the insulating layer covering the memory cell, a portion of the insulating layer disposed on the second part including a stepped sidewall; and a first pattern group disposed on the second part and disposed in the portion of the insulating layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall, and the stepped sidewall includes an upper sidewall, a lower sidewall, and a connection surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall and has a surface roughness different from that of the upper sidewall.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a first portion and a second portion connected to a first side of the first portion; an insulating layer disposed on the second portion and the first portion, the insulating layer including an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, a portion of the insulating layer on the second portion including a stepped sidewall, the stepped sidewall including a lower sidewall, an upper sidewall, and a connecting surface connecting the lower sidewall and the upper sidewall, the lower sidewall including a sidewall of the isolation layer and a part of a sidewall of the lower insulating layer, and the upper sidewall including a sidewall of the intermediate insulating layer and another part of a sidewall of the lower insulating layer; a memory cell disposed in the lower insulating layer disposed on the first portion; and a first pattern group disposed on the second portion of the substrate. The lower sidewall is disposed under the upper sidewall, closer to the substrate than the upper sidewall, and has a surface roughness greater than that of the upper sidewall. The insulating layer is disposed between the stepped sidewall and the first pattern group. The memory cell includes: a cell transistor; a first electrode connected to the cell transistor; a second electrode disposed on the first electrode; and a capacitor dielectric layer disposed between the first electrode and the second electrode.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: a printed circuit board; and a plurality of semiconductor chips stacked on the printed circuit board. At least one of the plurality of semiconductor chips includes: a substrate including a first portion and a second portion connected to a first side of the first portion; an insulating layer disposed on the second portion and the first portion, the insulating layer including an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, a portion of the insulating layer on the second portion including a stepped sidewall, the stepped sidewall including a lower sidewall, an upper sidewall, and a connecting surface connecting the lower sidewall and the upper sidewall, the lower sidewall including a sidewall of the isolation layer and a part of a sidewall of the lower insulating layer, and the upper sidewall including a sidewall of the intermediate insulating layer and another part of a sidewall of the lower insulating layer; a memory cell disposed in the lower insulating layer disposed on the first portion; and a first pattern group disposed on the second portion of the substrate. The lower sidewall is disposed under the upper sidewall, closer to the substrate than the upper sidewall, and has a surface roughness greater than that of the upper sidewall. The insulating layer is disposed between the stepped sidewall and the first pattern group. The memory cell includes: a cell transistor; a first electrode connected to the cell transistor; a second electrode disposed on the first electrode; and a capacitor dielectric layer disposed between the first electrode and the second electrode.

[0010] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: providing a substrate including a first chip region, a second chip region, and a scribe line located between the first chip region and the second chip region, the scribe line including a first region, a second region, and a division region disposed between the first region and the second region; forming an insulating layer on the substrate; forming a first pattern group on the first region of the scribe line; forming a second pattern group on the second region; and forming a trench in the insulating layer. The trench overlaps with the division region and separates the second pattern group from the first pattern group. Description of the Drawings

[0011] The inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 and Figure 2 is a cross-sectional view of a part of a semiconductor wafer for describing an exemplary embodiment according to the inventive concept of the present invention;

[0013] Figure 3 and Figure 4 is an enlarged view of a part of Figure 1 showing an exemplary embodiment according to the inventive concept of the present invention;

[0014] Figure 5 is an enlarged view of a part of Figure 4 showing an exemplary embodiment according to the inventive concept of the present invention;

[0015] Figure 6 is a layout of a semiconductor wafer for describing an exemplary embodiment according to the inventive concept of the present invention;

[0016] Figure 7 and Figure 8 is an enlarged view of a part of Figure 6 showing an exemplary embodiment according to the inventive concept of the present invention;

[0017] Figures 9 to 13 is a cross-sectional view of a semiconductor wafer of a semiconductor device for describing an exemplary embodiment according to the inventive concept of the present invention;

[0018] Figure 14 is an enlarged view of a part of a semiconductor wafer as shown in Figure 6 showing an exemplary embodiment according to the inventive concept of the present invention;

[0019] Figure 15 and Figure 16 is a cross-sectional view of a semiconductor device for describing an exemplary embodiment according to the inventive concept of the present invention;

[0020] Figure 17 and Figure 18 is an enlarged view of a part of a semiconductor wafer as shown in an exemplary embodiment according to the inventive concept of the present invention;Figure 6 An enlarged view of a part of a semiconductor wafer shown in

[0021] Figures 19 to 21 is a cross-sectional view of a semiconductor wafer for describing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0022] Figure 22 is a view showing as in Figure 6 an enlarged view of a part of a semiconductor wafer shown in

[0023] Figure 23 is a cross-sectional view of a semiconductor wafer for describing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0024] Figure 24 is a view showing as in Figure 6 an enlarged view of a part of a semiconductor wafer shown in

[0025] Figure 25 is a cross-sectional view of a semiconductor wafer for describing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0026] Figures 26 to 31 is a cross-sectional view of a semiconductor wafer for describing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0027] Figure 32 is a layout of a semiconductor device for describing an exemplary embodiment of the inventive concept;

[0028] Figures 33 to 35 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0029] Figure 36 is a layout of a semiconductor device for describing an exemplary embodiment of the inventive concept;

[0030] Figure 37 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0031] Figure 38 and Figure 39 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Description

[0032] Figure 1 and Figure 2 are cross-sectional views for describing a part of a semiconductor wafer according to an embodiment, Figure 3 and Figure 4 are views showing Figure 1An enlarged view of a part of Figure 5 shows Figure 4 An enlarged view of a part of Figure 6 is for describing the layout of a semiconductor wafer according to an embodiment, Figure 7 and Figure 8 shows an enlarged view of a part of the wafer as shown in Figure 6 . Figure 1 may be a cross-sectional view taken along line I-I' of Figure 7 . Figure 2 may be a cross-sectional view taken along line II-II' of Figure 7 .

[0033] Referring to Figure 1 , a semiconductor wafer according to an embodiment may include a substrate 21. On the semiconductor wafer, various integrated circuits may be formed using a manufacturing process. For example, the substrate 21 may include a plurality of chip regions CH and a first scribe line SL1, and the wafer may include a first pattern group 49A, a second pattern group 49B, a plurality of insulating layers 23, 31, 33, and 35, a dividing hole 71, an opening 72, memory cells MC, a plurality of guard rings 62, and an upper wiring 64 provided on the substrate 21. In the manufacturing process, the chip regions CH may be separated from the wafer by slicing the wafer through the dividing hole 71, and the separated chip regions CH may be packaged into semiconductor devices. Each of the chip regions may also be referred to as a first part of the substrate 21, and the first scribe line may also be referred to as a second part of the substrate 21.

[0034] The first scribe line SL1 may be provided between the plurality of chip regions CH. The first scribe line SL1 may include a first region SL11, a second region SL12, and a first dividing region SLC1. The second region SL12 may be opposite to the first region SL11. The first dividing region SLC1 may be provided between the first region SL11 and the second region SL12. The first dividing region SLC1 may be provided at a central region between two adjacent chip regions CH. In an embodiment, the first scribe line SL1 may be referred to as a double scribe line.

[0035] The horizontal width of the first scribeline SL1 can be from about 60 μm to about 130 μm. The horizontal width of the first region SL11 can be from about 30 μm to about 60 μm. The horizontal width of the second region SL12 can be from about 30 μm to about 60 μm. The horizontal width of the first divided region SLC1 can be from about 10 μm to about 30 μm. In an embodiment, the horizontal width of the first scribeline SL1 can be about 120 μm. The horizontal width of the first region SL11 can be about 50 μm. The horizontal width of the second region SL12 can be about 50 μm. The horizontal width of the first divided region SLC1 can be about 20 μm. The horizontal width of the first scribeline SL1 can be measured in a direction perpendicular to the length direction of the first scribeline SL1.

[0036] The insulating layers 23, 31, 33, and 35 can include an isolation layer 23 buried in the substrate 21, a lower insulating layer 31 disposed on the isolation layer 23 and the substrate 21, an intermediate insulating layer 33 disposed on the lower insulating layer 31, and an upper insulating layer 35 disposed on the intermediate insulating layer 33. The upper insulating layer 35 can include a first upper insulating layer 35A and a second upper insulating layer 35B disposed on the first upper insulating layer 35A. For ease of description, the isolation layer 23, the lower insulating layer 31, and the intermediate insulating layer 33 can be collectively referred to as the bottom insulating layer.

[0037] Each of the first pattern group 49A and the second pattern group 49B can include a test element group (TEG), an alignment key pattern, or a combination thereof. In an embodiment, each of the first pattern group 49A and the second pattern group 49B can include test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, a lower plug 42, and test patterns 41. The test pads 45, the plurality of intermediate wirings 44, the plurality of intermediate plugs 43, the lower plug 42, and the test patterns 41 can form a TEG for evaluating the electrical performance of elements (e.g., the chip region CH) constituting the integrated circuit chip. Electrical tests can be performed on the TEG to determine whether the elements in the chip region CH are properly formed on the wafer in the manufacturing process.

[0038] Memory cells MC can be provided (i.e., buried) in the lower insulating layer 31 of the plurality of chip regions CH. The memory cells MC can include dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, flash memory cells, magnetoresistive random access memory (MRAM) cells, phase change random access memory (PRAM) cells, ferroelectric random access memory (FeRAM) cells, resistive random access memory (RRAM) cells, or a combination thereof.

[0039] The substrate 21 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The insulating layers 23, 31, 33, and 35 may cover the substrate 21. The isolation layer 23 may be formed to be buried in the substrate 21. The lower insulating layer 31, the intermediate insulating layer 33, the first upper insulating layer 35A, and the second upper insulating layer 35B may be sequentially stacked on the substrate 21. The insulating layers 23, 31, 33, and 35 may include multiple insulating material layers. Each of the insulating layers 23, 31, 33, and 35 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof. The second upper insulating layer 35B may include photosensitive polyimide (PSPI). The intermediate insulating layer 33 may include a material layer having a greater tensile strength than the lower insulating layer 31. For example, the intermediate insulating layer 33 may include a silicon carbonitride (SiCN) layer.

[0040] In an exemplary embodiment, each of the first upper insulating layer 35A and the second upper insulating layer 35B may include a single-layer or multi-layer structure. Each of the first upper insulating layer 35A and the second upper insulating layer 35B may include a first oxide layer such as a high-density plasma (HDP) oxide, a second oxide layer formed using tetraethyl orthosilicate (TEOS) or fluorinated tetraethyl orthosilicate (FTEOS), or a combination thereof.

[0041] The first pattern group 49A may be disposed on the first region SL11 of the first scribe line SL1. The second pattern group 49B may be disposed on the second region SL12 of the first scribe line SL1. The first division region SLC1 may be placed between the first region SL11 and the second region SL12. The second pattern group 49B may be separated from the first pattern group 49A by the first division region SLC1. The second pattern group 49B may be electrically / spatially separated from the first pattern group 49A by the first division region SLC1. For example, the division hole 71 may be formed to overlap with the first division region SLC1. The division hole 71 may separate the second pattern group 49B from the first pattern group 49A. Each of the first pattern group 49A and the second pattern group 49B may include a TEG.

[0042] In an embodiment, the test pattern 41 may be disposed (i.e., buried) in the substrate 21. The test pattern 41 may include a material layer formed simultaneously with at least one of various active / passive elements disposed in the plurality of chip regions CH. For example, the test pattern 41 may be confined in the substrate 21 by the isolation layer 23. The isolation layer 23 may surround the side surface of the test pattern 41. The lower plug 42 may pass through the lower insulating layer 31 and may contact the test pattern 41. Unless otherwise indicated by the context, the term "contact" as used herein refers to a direct connection (i.e., touch).

[0043] A plurality of intermediate plugs 43 and a plurality of intermediate wirings 44 may be disposed in the intermediate insulating layer 33. At least one of the plurality of intermediate wirings 44 may be disposed on the lower insulating layer 31 and may contact the lower plug 42. The plurality of intermediate plugs 43 may be disposed between the plurality of intermediate wirings 44 and between the uppermost one of the plurality of intermediate wirings 44 and the test pad 45. The test pad 45 may be disposed in the first upper insulating layer 35A. The test pad 45 may be disposed on the intermediate insulating layer 33 and may contact at least one of the plurality of intermediate plugs 43 (e.g., the uppermost intermediate plug 43 among the plurality of intermediate wirings 44). The test pad 45 may be electrically connected to the test pattern 41 via the lower plug 42, the plurality of intermediate plugs 43, and the plurality of intermediate wirings 44.

[0044] The test pad 45, the plurality of intermediate wirings 44, the plurality of intermediate plugs 43, and the lower plug 42 may each include a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, or a combination thereof. The test pad 45, the plurality of intermediate wirings 44, the plurality of intermediate plugs 43, and the lower plug 42 may each include aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), silver (Ag), platinum (Pt), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In an embodiment, the test pad 45 may include a material layer different from that of the plurality of intermediate wirings 44. For example, the test pad 45 may include an Al layer, and the plurality of intermediate wirings 44 may include a Cu layer.

[0045] The opening 72 may be disposed on the first scribe line SL1 and may extend into the upper insulating layer 35. For example, the opening 72 may pass through the second upper insulating layer 35B and may extend into an inner portion of the first upper insulating layer 35A. The upper surface of the test pad 45 may be exposed at the bottom of the opening 72. The opening 72 may be connected to the dividing hole 71.

[0046] The dividing hole 71 may overlap with the first dividing region SLC1 and may extend into an inner portion of each of the insulating layers 23, 31, 33, and 35. In an embodiment, the dividing hole 71 may pass through the upper insulating layer 35 and the intermediate insulating layer 33 and may extend into an inner portion of the lower insulating layer 31. The bottom of the dividing hole 71 may be disposed at a level lower than the uppermost end (or upper surface) of the lower insulating layer 31. The distance between the lowermost end of the dividing hole 71 and the substrate 21 may be shorter than the distance between the uppermost end of the lower insulating layer 31 and the substrate 21. The lowermost end of the dividing hole 71 may be disposed at a level lower than the uppermost end of the memory cell MC. The distance between the lowermost end of the dividing hole 71 and the substrate 21 may be shorter than the distance between the uppermost end of the memory cell MC and the substrate 21.

[0047] The distance between the lowermost end of the dividing hole 71 and the substrate 21 may be shorter than the distance between the uppermost end of the test pad 45 and the substrate 21. The lowermost end of the dividing hole 71 may be set at a level lower than the lowermost end of each of the plurality of intermediate wirings 44. The distance between the lowermost end of the dividing hole 71 and the substrate 21 may be shorter than the distance between the lowermost end of each of the plurality of intermediate wirings 44 and each of the plurality of intermediate plugs 43 and the substrate 21.

[0048] A plurality of protection rings 62 may be provided at the boundary between the plurality of chip regions CH and the first scribe line SL1. The plurality of protection rings 62 may each include a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, or a combination thereof. The upper wiring 64 may be provided in the upper insulating layer 35 of each of the plurality of chip regions CH. The upper wiring 64 may be provided on the first upper insulating layer 35A. The second upper insulating layer 35B may cover the upper wiring 64. The upper wiring 64 may include a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, or a combination thereof. In an embodiment, the upper wiring 64 may include the same material layer as the test pad 45. The upper wiring 64 may include an Al layer. The upper wiring 64 may be twice or more times thicker than each of the plurality of intermediate wirings 44. The upper wiring 64 may correspond to a thick top metal (TTM) wiring.

[0049] Referring to Figure 7 a cross-sectional view of a wafer taken along line II-II' shown Figure 2 , a wafer according to an embodiment may include a first pattern group 49A, an isolation layer 23, a lower insulating layer 31, an intermediate insulating layer 33, a first upper insulating layer 35A, and an opening 72 provided on a substrate 21. The first pattern group 49A may include a plurality of test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, a plurality of lower plugs 42, and a test pattern 41.

[0050] Referring to Figure 3 , the memory cell MC may include, for example, a DRAM cell. The memory cell MC may include a substrate 21, an isolation layer 23, an active region 24, a gate dielectric layer 25, a gate electrode 26, a plurality of source / drain regions 27, a gate capping layer 28, a first lower insulating layer 31A, a bit plug 81, a bit line 82, a buried contact plug 84, a ground pad 85, a second lower insulating layer 31B, a first electrode 87, a capacitor dielectric layer 88, a second electrode 89, a lower support 92, an upper support 93, and a third lower insulating layer 31C.

[0051] The active region 24, the gate dielectric layer 25, the gate electrode 26, and the multiple source / drain regions 27 can construct a unit transistor. The unit transistor can correspond to a recessed-channel transistor. In an embodiment, the unit transistor can include a fin field-effect transistor (finFET), a multi-bridge channel (MBC) transistor, a nanowire transistor, a vertical transistor, a recessed-channel transistor, a three-dimensional (3-D) transistor, a planar transistor, or a combination thereof.

[0052] The first electrode 87 can be connected to the unit transistor. For example, the first electrode 87 can be connected to a source / drain region selected from among the multiple source / drain regions 27 via a ground pad 85 and a buried contact plug 84. The first electrode 87 can be referred to as a bottom electrode, a storage electrode, or a storage node. The first electrode 87 can include a pillar structure, a cylindrical structure, or a combination thereof. The second electrode 89 can be disposed on the first electrode 87. The second electrode 89 can be referred to as a top electrode, a plate electrode, or a plate node. A capacitor dielectric layer 88 can be disposed between the first electrode 87 and the second electrode 89. The first electrode 87, the capacitor dielectric layer 88, and the second electrode 89 can construct a unit capacitor. The unit capacitor can include various types of 3-D capacitors.

[0053] Each of the lower support 92 and the upper support 93 can contact a side surface of the first electrode 87. The second electrode 89 can cover the lower support 92 and the upper support 93. The capacitor dielectric layer 88 can extend between the second electrode 89 and the lower support 92 and between the second electrode 89 and the upper support 93.

[0054] The isolation layer 23 can be formed in the substrate 21 by using shallow trench isolation (STI) technology. The active regions 24 can be isolated in the substrate 21 by the isolation layer 23. Each of the multiple gate electrodes 26 can be disposed at a level lower than the upper end (i.e., the upper surface) of the substrate 21. The gate dielectric layer 25 can surround the side surfaces and the bottom of the multiple gate electrodes 26. The gate dielectric layer 25 can be disposed between the multiple gate electrodes 26 and the substrate 21. A gate capping layer 28 can be disposed on the multiple gate electrodes 26. The multiple source / drain regions 27 can be disposed in the substrate 21 adjacent to the multiple gate electrodes 26.

[0055] Each of the gate electrode 26, the bit plug 81, the bit line 82, the buried contact plug 84, the ground pad 85, the first electrode 87, and the second electrode 89 can include a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, or a combination thereof. Each of the gate dielectric layer 25 and the capacitor dielectric layer 88 can include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric, or a combination thereof.

[0056] The lower insulating layer ( Figure 1The 31) may include a first lower insulating layer 31A, a second lower insulating layer 31B, and a third lower insulating layer 31C. In an embodiment, each of the first lower insulating layer 31A and the third lower insulating layer 31C may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. Each of the second lower insulating layer 31B, the lower support 92, and the upper support 93 may include silicon nitride.

[0057] Referring to Figure 4 , for example, the memory cell MC may include a flash memory cell such as a vertical NAND (VNAND) memory cell. The memory cell MC may include a peripheral on-die (COP) structure. For example, the memory cell MC may include a substrate 21, an isolation layer 223, a plurality of transistors 225, a first lower insulating layer 227, a plurality of peripheral circuit wirings 229, a second lower insulating layer 231, a third lower insulating layer 233, a fourth lower insulating layer 235, a horizontal conductive layer 241, a connection conductive layer 245, a support 247, a stacked structure 250, a plurality of unit channel structures 269, a fifth lower insulating layer 272, a plurality of separation patterns 275, a sixth lower insulating layer 279, a plurality of bit plugs 281, and a plurality of bit lines 283.

[0058] The lower insulating layer ( Figure 1 of 31) may include a first lower insulating layer 227, a second lower insulating layer 231, a third lower insulating layer 233, a fourth lower insulating layer 235, a fifth lower insulating layer 272, and a sixth lower insulating layer 279. The third lower insulating layer 233 may correspond to a capping layer. The stacked structure 250 may include a plurality of insulating layers 251 and a plurality of electrode layers 253 that are alternately and repeatedly stacked.

[0059] Referring to Figure 5 , each of the plurality of unit channel structures 269 may include a core pattern 261, a channel layer 262 surrounding an outer portion of the core pattern 261, an information storage pattern 266 surrounding an outer portion of the channel layer 262, and a bit pad 267. The information storage pattern 266 may include a tunnel insulating layer 263 surrounding an outer portion of the channel layer 262, a charge storage layer 264 surrounding an outer portion of the tunnel insulating layer 263, and a blocking layer 265 surrounding an outer portion of the charge storage layer 264.

[0060] Referring to Figure 4 and Figure 5, the horizontal conductive layer 241 may correspond to a source line or a common source line (CSL). The lowermost layer among the plurality of electrode layers 253 may correspond to a gate-induced drain leakage (GIDL) control line. The second layer upward after the lowermost layer among the plurality of electrode layers 253 may correspond to a ground selection layer (GSL). The uppermost layer among the plurality of electrode layers 253 may correspond to a GIDL control line. The second and third layers downward after the uppermost layer among the plurality of electrode layers 253 may correspond to a ground selection layer (GSL). Some of the plurality of electrode layers 253 may correspond to word lines. The plurality of separation patterns 275 may correspond to word line cuts. The plurality of transistors 225 and the plurality of peripheral circuit wirings 229 may construct a peripheral circuit.

[0061] Referring to Figure 6 , a semiconductor wafer according to an embodiment may include a plurality of chip regions CH provided on a substrate 21, and a plurality of first scribing lines SL1 and a plurality of second scribing lines SL2. The plurality of first scribing lines SL1 and the plurality of second scribing lines SL2 may be provided between the plurality of chip regions CH. The plurality of first scribing lines SL1 may be parallel to each other. The plurality of second scribing lines SL2 may be parallel to each other. The plurality of second scribing lines SL2 may intersect the plurality of first scribing lines SL1. In an exemplary embodiment, the plurality of second scribing lines SL2 may be perpendicular to the plurality of first scribing lines SL1. Each of the first scribing lines SL1 may also be referred to as a second portion of the substrate 21, and each of the second scribing lines SL2 may also be referred to as a third portion of the substrate 21.

[0062] Referring to Figure 7 , the first scribing line SL1 and the second scribing line SL2 may be provided between the plurality of chip regions CH. The first scribing line SL1 may include a first region SL11, a second region SL12, and a first dividing region SLC1. The first pattern group 49A may be provided on the first region SL11. The second pattern group 49B may be provided on the second region SL12. As seen in a plan view, the second pattern group 49B may be provided parallel to the first pattern group 49A. The first dividing region SLC1 may be provided between the first region SL11 and the second region SL12.

[0063] In an embodiment, the second scribing line SL2 may be perpendicular to the first scribing line SL1. The second scribing line SL2 may include a third region SL21, a fourth region SL22, and a second dividing region SLC2. The second dividing region SLC2 may be provided between the third region SL21 and the fourth region SL22. The second scribing line SL2 may include a structure similar to the structure of the first scribing line SL1.

[0064] Referring to Figure 8 , as seen in a plan view, the second pattern group 49B may be provided to be shifted from the first pattern group 49A in the direction in which the first dividing region SLC1 extends.

[0065] Figures 9 to 13 is a cross-sectional view of a semiconductor wafer taken along line I-I' of a semiconductor device according to an embodiment. Figure 7

[0066] Referring to Figure 9 , the dividing hole 71 may be disposed within the opening 72 in a top-down view and may extend into an inner portion of the intermediate insulating layer 33. The dividing hole 71 may be connected to the opening 72. The lowermost end (i.e., the bottom surface) of the dividing hole 71 may be disposed at a level higher than the uppermost end (i.e., the upper surface) of the lower insulating layer 31. The intermediate insulating layer 33 may be partially recessed to form the dividing hole 71. For example, the intermediate insulating layer 33 may be partially recessed to form the dividing hole 71. The lowermost end of the dividing hole 71 may be disposed at a level higher than the uppermost end of each of the plurality of lower plugs 42.

[0067] Referring to Figure 10 , in a top-down view, the dividing hole 71 may be disposed within the opening 72. The dividing hole 71 may penetrate the intermediate insulating layer 33. The dividing hole 71 may be connected to the opening 72. The bottom of the dividing hole 71 and the upper surface of the lower insulating layer 31 may be substantially coplanar. In an embodiment, the dividing hole 71 may have various depths.

[0068] Referring to Figure 11 , the test pattern 41 may be disposed (or buried) in the lower insulating layer 31. In an embodiment, the test pattern 41 may be disposed in an inner portion of the substrate 21, an inner portion of the lower insulating layer 31, or an inner portion of the intermediate insulating layer 33.

[0069] Referring to Figure 12 , the sidewall of the dividing hole 71 may have various profiles. The sidewall of the dividing hole 71 may include various inclined surfaces. In an embodiment, the dividing hole 71 may include a plurality of undercut regions UC1. The undercut regions UC1 may be formed under the test pad 45. The lower surface of the test pad 45 may be partially exposed by the undercut regions UC1.

[0070] Referring to Figure 13 , the upper wiring 64 may extend from the chip region CH into the first scribe line SL1. The upper wiring 64 may contact the upper surface of the test pad 45. The upper wiring 64 may correspond to the redistribution layer RDL.

[0071] Figure 14 is an enlarged view showing a part of the semiconductor wafer as shown in Figure 6 Figure 15 is a cross-sectional view of a semiconductor device taken along line 6-6' of Figure 14 Figure 16 is along Figure 14A cross-sectional view taken along line 7-7'.

[0072] Referring to Figures 14 to 16 , the test pattern 41 may include a material layer substantially the same as at least one element selected from among various active / passive elements provided in the substrate 21 and the insulating layers 23, 31, 33, and 35. The test pattern 41 may include a material layer formed simultaneously by using the same process as at least one element selected from among various active / passive elements provided in the substrate 21 and the insulating layers 23, 31, 33, and 35. The test pattern 41 may be provided at substantially the same level as at least one element selected from among various active / passive elements provided in the substrate 21 and the insulating layers 23, 31, 33, and 35. The test pattern 41 may include a 3-D pattern having various structures.

[0073] In an embodiment, each of the first pattern group 49A and the second pattern group 49B may include a test pad 45, an intermediate wiring 44, a plurality of intermediate plugs 43, and a test pattern 41. The test pattern 41 may be provided in the intermediate insulating layer 33. The lowermost end of the dividing hole 71 may be provided at a level lower than the lowermost end of the test pattern 41. The interval between the lowermost end of the dividing hole 71 and the substrate 21 may be shorter than the interval between the lowermost end of the test pattern 41 and the substrate 21. The intermediate insulating layer 33 may be exposed at the sidewall of the dividing hole 71. The dividing hole 71 may pass through the intermediate insulating layer 33 and partially extend into the lower insulating layer 31. A portion of the intermediate insulating layer 33 may be provided between the sidewall of the dividing hole 71 and the test pattern 41, between the sidewall of the dividing hole 71 and the intermediate wiring 44, and between the sidewall of the dividing hole 71 and the plurality of intermediate plugs 43.

[0074] Figure 17 and Figure 18 is an enlarged view showing a part of a semiconductor wafer as shown in Figure 6 , Figures 19 to 21 is a cross-sectional view of a semiconductor wafer for describing a semiconductor device according to an embodiment.

[0075] Referring to Figure 17 , each of the first pattern group 49C and the second pattern group 49D may include an alignment key pattern. The second pattern group 49D may be provided in parallel with the first pattern group 49C. The second pattern group 49D may include an alignment key pattern identical to the alignment key pattern of the first pattern group 49C. The first pattern group 49C may be provided on a first region SL11 of the first scribe line SL1. The second pattern group 49D may be provided on a second region SL12 of the first scribe line SL1. The second pattern group 49D may be separated from the first pattern group 49C by a first division region SLC1. The second scribe line SL2 may include a configuration similar to that of the first scribe line SL1.

[0076] Reference Figure 18 , the second pattern group 49D and the first pattern group 49C can be disposed on opposite sides of the first divided region SLC1. The second pattern group 49D can include alignment key patterns different from those of the first pattern group 49C.

[0077] Reference Figure 19 , each of the first pattern group 49C and the second pattern group 49D can include alignment key patterns. Each of the first pattern group 49C and the second pattern group 49D can be disposed in the substrate 21. The lower insulating layer 31 can cover the first pattern group 49C and the second pattern group 49D. A plurality of dummy metal patterns 45D can be disposed on the intermediate insulating layer 33. The plurality of dummy metal patterns 45D can cover the upper portions of the first pattern group 49C and the second pattern group 49D.

[0078] Reference Figure 20 , in an embodiment, the plurality of dummy metal patterns ( Figure 19 45D) can be omitted.

[0079] Reference Figure 21 , the first pattern group 49C and the second pattern group 49D can be disposed at different levels. For example, the first pattern group 49C can be disposed in the substrate 21, and the second pattern group 49D can be disposed in the intermediate insulating layer 33. The second pattern group 49D can include alignment key patterns different from those of the first pattern group 49C.

[0080] Figure 22 is an enlarged view of a part of a semiconductor wafer as shown in Figure 6 , Figure 23 is a cross-sectional view of a semiconductor wafer for describing a semiconductor device according to an embodiment.

[0081] Reference Figure 22 , the second pattern group 49D can include alignment key patterns different from those of the first pattern group 49A. For example, the first pattern group 49A can include TEG, and the second pattern group 49D can include alignment key patterns.

[0082] Reference Figure 23 , the first pattern group 49A can include TEG. The first pattern group 49A can include test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, a lower plug 42, and test patterns 41. The second pattern group 49D can include alignment key patterns.

[0083] Figure 24 is an enlarged view of a part of a semiconductor wafer as shown in Figure 6 , Figure 25 is for describing a cross-section along a semiconductor device according to an embodimentFigure 24 A cross-sectional view of a semiconductor wafer taken along line III-III'.

[0084] Referring to Figure 24 and Figure 25 , a first scribing line SL1 and a second scribing line SL2 can be provided between a plurality of chip regions CH. The first scribing line SL1 can include a first region SL11, a second region SL12, and a first division region SLC1. A first pattern group 49A can be provided on the first region SL11. A second pattern group 49B can be provided on the second region SL12. The first division region SLC1 can be provided between the first region SL11 and the second region SL12.

[0085] In an embodiment, the second scribing line SL2 can be perpendicular to the first scribing line SL1. The second scribing line SL2 can include a third region SL21, a fourth region SL22, and a second division region SLC2. The second division region SLC2 can be provided between the third region SL21 and the fourth region SL22. The horizontal width of the second scribing line SL2 can be different from the horizontal width of the first scribing line SL1. The horizontal width of the second scribing line SL2 can be narrower than the horizontal width of the first scribing line SL1. The horizontal width of the second scribing line SL2 can be about 40 μm to about 70 μm. The horizontal width of the third region SL21 can be about 20 μm to about 60 μm. The horizontal width of the fourth region SL22 can be about 20 μm to about 60 μm. The horizontal width of the second division region SLC2 can be about 10 μm to about 30 μm. In an embodiment, the horizontal width of the second scribing line SL2 can be about 60 μm. The horizontal width of the third region SL21 can be about 20 μm. The horizontal width of the fourth region SL22 can be about 20 μm. The horizontal width of the second division region SLC2 can be about 20 μm. In an exemplary embodiment, the horizontal width of a scribing line can be measured in a direction perpendicular to the extending direction of the scribing line.

[0086] A third pattern group 49E can be provided on the second scribing line SL2. The third pattern group 49E can overlap with the second division region SLC2. The third pattern group 49E can overlap with the third region SL21, the second division region SLC2, and the fourth region SL22. The third pattern group 49E can include a TEG, an alignment key pattern, or a combination thereof. In an embodiment where the third pattern group 49E includes a TEG, the third pattern group 49E can include test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, a lower plug 42, and a test pattern 41. The test pattern 41 can overlap with the second division region SLC2.

[0087] Figures 26 to 29 is a cross-sectional view of a semiconductor wafer taken along line I-I' for describing a method of manufacturing a semiconductor device according to an embodiment. Figure 7 A cross-sectional view of a semiconductor wafer taken along line I-I'.

[0088] Referring to Figure 26 , a substrate 21 including a plurality of chip regions CH and a first scribeline SL1 between the plurality of chip regions CH can be provided. An isolation layer 23 can be formed in the substrate 21. A lower insulating layer 31, an intermediate insulating layer 33, and a first upper insulating layer 35A can be formed on the substrate 21 and the isolation layer 23. Memory cells MC can be formed in the lower insulating layer 31 of each of the plurality of chip regions CH. A plurality of guard rings 62 can be formed in the lower insulating layer 31, the intermediate insulating layer 33, and the first upper insulating layer 35A. The plurality of guard rings 62 can be formed at the boundary between the plurality of chip regions CH and the first scribeline SL1.

[0089] A first pattern group 49A and a second pattern group 49B can be formed in the lower insulating layer 31, the intermediate insulating layer 33, and the first upper insulating layer 35A. Each of the first pattern group 49A and the second pattern group 49B can include test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, lower plugs 42, and test patterns 41. The test patterns 41 can be formed in the substrate 21. The test patterns 41 can be isolated by the isolation layer 23. The isolation layer 23 can surround the side surfaces of the test patterns 41. The first pattern group 49A can be formed on a first region SL11. The second pattern group 49B can be formed on a second region SL12 opposite to the first region SL11.

[0090] The lower plugs 42 can be formed in the lower insulating layer 31. A plurality of intermediate plugs 43 and a plurality of intermediate wirings 44 can be formed in the intermediate insulating layer 33. The test pads 45 can be formed on the intermediate insulating layer 33. The first upper insulating layer 35A can cover the test pads 45 and the intermediate insulating layer 33.

[0091] Referring to Figure 27 , upper wirings 64 can be formed on the first upper insulating layer 35A of each of the plurality of chip regions CH. The process of forming the upper wirings 64 can include a process of forming a thin film and a patterning process.

[0092] Referring to Figure 28 , the upper surface of the test pads 45 can be exposed by partially removing the first upper insulating layer 35A.

[0093] Referring to Figure 29 , a second upper insulating layer 35B can be formed on the first upper insulating layer 35A of each of the plurality of chip regions CH. The second upper insulating layer 35B can cover the upper wirings 64. An opening 72 passing through the second upper insulating layer 35B can be formed on the first scribeline SL1. The upper surface of the first upper insulating layer 35A and the upper surface of the test pads 45 can be exposed through the opening 72.

[0094] Referring again to Figure 1, a split hole 71 can be formed to overlap with the first split region SLC1. The split hole 71 can be connected to the opening 72.

[0095] Figure 30 and Figure 31 are cross-sectional views of a semiconductor wafer taken along line I-I' for describing a method of manufacturing a semiconductor device according to an embodiment. Figure 7 of the semiconductor wafer.

[0096] Referring to Figure 30 , a redistribution hole 35C that partially exposes the upper surface of the test pad 45 can be formed by partially removing the first upper insulating layer 35A.

[0097] Referring to Figure 31 , an upper wiring 64 can be formed on the first upper insulating layer 35A. The upper wiring 64 can be formed on the first upper insulating layer 35A of each of the plurality of chip regions CH and can extend to the first scribe line SL1. The upper wiring 64 can contact the test pad 45.

[0098] Referring again to Figure 13 , a second upper insulating layer 35B can be formed on the upper wiring 64 and the first upper insulating layer 35A. An opening 72 passing through the second upper insulating layer 35B can be formed on the first scribe line SL1. A split hole 71 can be formed to overlap with the first split region SLC1. The split hole 71 can be connected to the opening 72.

[0099] Subsequently, the chip regions CH described above with reference to Figures 1 to 31 can be divided into semiconductor devices by cutting the wafer along the first split region SLC1 and the second split region SLC2. The process of cutting the wafer along the first split region SLC1 and the second split region SLC2 can include a sawing process using a laser sawing device or a saw blade. Each of the semiconductor devices can have a partial structure of each of the first scribe line SL1 and the second scribe line SL2 in addition to the corresponding chip region CH.

[0100] Figure 32 and Figure 36 are for describing the layout of a semiconductor device according to an embodiment, Figures 33 to 35 is for describing a cross-sectional view of a semiconductor device according to an embodiment taken along line IV-IV' of Figure 32 , Figure 37 is for describing a cross-sectional view of a semiconductor device according to an embodiment taken along line V-V' of Figure 36 of the semiconductor device.

[0101] Referring to Figure 32 and Figure 33, a semiconductor device according to an embodiment may include a substrate 21 separated from a semiconductor wafer. The substrate 21 may include a chip region CH, a first scribe line SL1, and a second scribe line SL2. The semiconductor device may further include a first pattern group 49A, a plurality of insulating layers 23, 31, 33, and 35, a dividing hole 71, an opening 72, memory cells MC, a plurality of guard rings 62, and an upper wiring 64. Each of the substrate 21, the chip region CH, the first scribe line SL1, the second scribe line SL2, the first pattern group 49A, the insulating layers 23, 31, 33, and 35, the dividing hole 71, the opening 72, the memory cells MC, the plurality of guard rings 62, and the upper wiring 64 may include a structure similar to the corresponding structure described above with reference to Figures 1 to 31 The insulating layers 23, 31, 33, and 35 may include an isolation layer 23, a lower insulating layer 31, an intermediate insulating layer 33, and an upper insulating layer 35.

[0102] In an embodiment, the substrate 21 may include a chip region CH and a first scribe line SL1 and a second scribe line SL2. The first scribe line SL1 may be connected to a first side S1 of the chip region CH, and the second scribe line SL2 may be connected to a second side S2 of the chip region CH. The first scribe line SL1 may include a first region SL11 and a first dividing region SLC1. In an exemplary embodiment, due to losses in a sawing process, the first dividing region SLC1 of the semiconductor device may have a horizontal width smaller than half of the horizontal width of the first region SL11 of the wafer. The first region SL11 may be disposed between the first dividing region SLC1 and the chip region CH. The first pattern group 49A may be disposed on the first region SL11.

[0103] A part of the insulating layers 23, 31, and 33 (i.e., the bottom insulating layers) may be stacked with the first scribe line SL1. The part of the bottom insulating layer may include a first sidewall SW1 corresponding to a sidewall of the semiconductor device. The first sidewall SW1 may include an upper sidewall SWU and a lower sidewall SWL. The first sidewall SW1 may be aligned in the first dividing region SLC1. For example, the first sidewall SW1 may be located at a boundary between the first region SL11 and the dividing hole 71. The lower sidewall SWL may be disposed under the upper sidewall SWU. The surface of the upper sidewall SWU may be determined based on the dividing hole 71. The lower sidewall SWL may have a surface roughness different from that of the surface of the upper sidewall SWU. The lower sidewall SWL may include a surface rougher than the surface of the upper sidewall SWU.

[0104] The upper sidewall SWU may correspond to the sidewalls of the intermediate insulating layer 33 and a part of the sidewalls of the lower insulating layer 31. The lower sidewall SWL may correspond to another part of the sidewalls of the lower insulating layer 31 and the sidewalls of the isolation layer 23. The isolation layer 23 may be buried in the substrate 21. At least a part of each of the insulating layers 23, 31, and 33 (i.e., collectively referred to as the bottom insulating layer) may extend into the portion between the first sidewall SW1 and the first pattern group 49A. For example, a part of the bottom insulating layer may be disposed between the first sidewall SW1 and the first pattern group 49A. The first pattern group 49A may include a TEG, an alignment key pattern, or a combination thereof.

[0105] In an embodiment, the first pattern group 49A may include test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, a lower plug 42, and test patterns 41. The test pads 45 may be disposed on the test patterns 41 and may be electrically connected to the test patterns 41.

[0106] In an embodiment, the test patterns 41 may be disposed (i.e., buried) in the substrate 21. The isolation layer 23 may be disposed between the lower sidewall SWL and the test patterns 41. In an embodiment, the test patterns 41 may be disposed in the lower insulating layer 31. The lower insulating layer 31 may extend into the portion between the lower sidewall SWL and the lower plug 42. For example, a part of the lower insulating layer 31 may be disposed between the lower sidewall SWL and the lower plug 42.

[0107] In an exemplary embodiment, the bottom insulating layers 23, 31, and 33 may include a portion on the first scribe line SL1, and this portion of the bottom insulating layers 23, 31, and 33 may include a stepped sidewall. The stepped sidewall may include a lower sidewall SWL, an upper sidewall SWU, and a step portion ST (i.e., a connecting surface) disposed between the lower sidewall SWL and the upper sidewall SWU. The step portion ST may connect the lower sidewall SWL and the upper sidewall SWU. The step portion ST may be determined based on the bottom of the dividing hole 71. The step portion ST may correspond to the recessed upper surface of the lower sidewall SWL. The boundary between the lower sidewall SWL and the upper sidewall SWU may correspond to the recessed upper surface of the lower insulating layer 31. In an embodiment, the boundary between the lower sidewall SWL and the upper sidewall SWU may correspond to the upper surface of a part of the lower insulating layer 31. (See the semiconductor wafer before applying a sawing process to form a semiconductor device Figure 10 .) The said part of the lower insulating layer 31 may be exposed by the intermediate insulating layer 33. The intermediate insulating layer 33 may include a material layer with a tensile strength greater than that of the lower insulating layer 31. The intermediate insulating layer 33 may include a SiCN layer.

[0108] In an embodiment, the second scribe line SL2 may include a structure similar to that of the first scribe line SL1.

[0109] Refer toFigure 34 The lower sidewall SWL may have a slope different from that of the upper sidewall SWU. The upper sidewall SWU may be determined based on the dividing hole 71. The lower sidewall SWL may be determined by a sawing process. A first slope θ1 may be provided between the lower sidewall SWL and the lower surface of the substrate 21. In an embodiment, the first slope θ1 may have an angle between about 75 degrees and about 90 degrees.

[0110] Referring to Figure 35 a first slope θ1 may be provided between the lower sidewall SWL and the lower surface of the substrate 21. In an embodiment, the first slope θ1 may have an angle between about 90 degrees and about 105 degrees.

[0111] Referring to Figure 36 and Figure 37 According to an embodiment, a semiconductor device may include a substrate 21, a chip region CH, a first scribe line SL1, a second scribe line SL2, a first pattern group 49A, a third pattern group 49E, a plurality of insulating layers 23, 31, 33, and 35, and a plurality of guard rings 62. Each of the substrate 21, the chip region CH, the first scribe line SL1, the second scribe line SL2, the first pattern group 49A, the third pattern group 49E, the insulating layers 23, 31, 33, and 35, and the plurality of guard rings 62 may include a structure similar to the corresponding structure described above with reference to Figures 1 to 31 The first scribe line SL1 may include a structure similar to the structure described above with reference to Figures 32 to 35 described.

[0112] In an embodiment, the second scribe line SL2 may be connected to the second side S2 of the chip region CH. The second scribe line SL2 may have a width narrower than that of the first scribe line SL1. The second scribe line SL2 may include a third region SL21 and a second dividing region SLC2. The third region SL21 may be provided between the second dividing region SLC2 and the chip region CH. The third pattern group 49E may be provided on the third region SL21. The second sidewall SW2 of the second scribe line SL2 may be aligned in the second dividing region SLC2. The third pattern group 49E may be exposed at the second sidewall SW2. The third pattern group 49E may include a TEG, an alignment key pattern, or a combination thereof. In an exemplary embodiment, the third pattern group 49 may not operate as expected due to the cutting performed in the sawing process.

[0113] In an embodiment, the third pattern group 49E may include test pads 45, a plurality of intermediate wirings 44, a plurality of intermediate plugs 43, a lower plug 42, and test patterns 41. At least one of the test patterns 41, the lower plug 42, the plurality of intermediate plugs 43, the plurality of intermediate wirings 44, and the test pads 45 may be exposed at the second sidewall SW2. For example, the third pattern group 49E may include partial test patterns 41 and partial test pads 45 disposed on the partial test patterns 41, and the partial test patterns 41 and the partial test pads 45 may be exposed at the second sidewall SW2. At this time, the sidewall of the third pattern group 49E may include the sidewall of the partial test patterns 41 and the sidewall of the partial test pads 45. The second sidewall SW2 may have a surface roughness different from that of the first sidewall SW1. For example, the second sidewall SW2 may include a surface rougher than the surface of the first sidewall SW1 described with reference to Figure 33 , Figure 34 and Figure 35 . The side surface of the third pattern group 49E may include a surface rougher than the side surface of the first pattern group 49A. The second sidewall SW2 may be determined by a sawing process.

[0114] Figure 38 and Figure 39 are cross-sectional views for describing a semiconductor device according to an embodiment. The semiconductor device according to the embodiment may include a Hybrid Memory Cube (HMC), a High Bandwidth Memory (HBM), a Double Data Rate Fifth Generation (DDR5) DRAM, or a combination thereof.

[0115] Referring to Figure 38, a semiconductor device according to an embodiment may include a printed circuit board PC, an interposer substrate IP, a plurality of semiconductor chips CP, BD, and MD1 to MD4, a plurality of bumps 189, 489, 589, and 689, an adhesive layer 195, and an encapsulation material 196. The plurality of semiconductor chips CP, BD, and MD1 to MD4 may include a microprocessor CP, a base chip BD, and a plurality of memory chips MD1 to MD4. In an embodiment, the plurality of memory chips MD1 to MD4 may be sequentially and vertically stacked on the base chip BD. The plurality of memory chips MD1 to MD4 may include memory chips corresponding to various combinations of numbers such as three, four, seven, eleven, twelve, fifteen, sixteen, and nineteen. The plurality of memory chips MD1 to MD4 may include a first memory chip MD1, a second memory chip MD2, a third memory chip MD3, and a fourth memory chip MD4. At least some of the plurality of memory chips MD1 to MD4 may include a plurality of through electrodes 139. The plurality of bumps 189, 489, 589, and 689 may include a plurality of first bumps 189, a plurality of second bumps 489, a plurality of third bumps 589, and a plurality of fourth bumps 689.

[0116] The printed circuit board PC may include a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. The printed circuit board PC may include a multi-layer circuit board. The printed circuit board PC may correspond to a package board or a main board. The plurality of fourth bumps 689 may be disposed on the lower surface of the printed circuit board PC. The interposer substrate IP may be disposed on the printed circuit board PC. The plurality of third bumps 589 may be disposed between the printed circuit board PC and the interposer substrate IP.

[0117] The plurality of semiconductor chips CP, BD, and MD1 to MD4 may be disposed on the interposer substrate IP. The interposer substrate IP may include a semiconductor substrate such as a silicon interposer. In an embodiment, the microprocessor CP and the base chip BD may be disposed on the interposer substrate IP. The plurality of second bumps 489 may be disposed between the microprocessor CP and the interposer substrate IP and between the base chip BD and the interposer substrate IP. The microprocessor CP may include various processors such as a graphics processing unit (GPU) or an application processor (AP). The base chip BD may include various elements such as a memory controller. The base chip BD may be connected to the microprocessor CP via the interposer substrate IP and the plurality of second bumps 489.

[0118] The plurality of memory chips MD1 to MD4 may be sequentially stacked on the base chip BD. Each of the plurality of memory chips MD1 to MD4 may include the same as that referred to above Figures 1 to 37A plurality of components similar to the described component. For example, each of the plurality of memory chips MD1 to MD4 may include a substrate 21, memory cells MC, and a first scribe line SL1 and a second scribe line SL2. A plurality of through electrodes 139 may be provided in a plurality of chip regions. The plurality of through electrodes 139 may pass through the chip regions of the substrate in each of the memory chips MD1 to MD4.

[0119] In an embodiment, an adhesive layer 195 may be provided between the plurality of memory chips MD1 to MD4 and between the first memory chip MD1 and the base chip BD. The adhesive layer 195 may include a non-conductive film (NCF). A plurality of first bumps 189 may be provided between the plurality of memory chips MD1 to MD4 and between the first memory chip MD1 and the base chip BD. The plurality of first bumps 189 may extend into an inner portion of the adhesive layer 195. The plurality of first bumps 189 may pass through the adhesive layer 195. The plurality of memory chips MD1 to MD4 may be connected to the base chip BD via the plurality of first bumps 189 and the plurality of through electrodes 139. An encapsulation material 196 covering the plurality of memory chips MD1 to MD4 may be provided on the base chip BD. The encapsulation material 196 may include an epoxy molding compound (EMC).

[0120] In an embodiment, the base chip BD may include a buffer chip, a logic chip, or a combination thereof. Each of the plurality of memory chips MD1 to MD4 may correspond to a DRAM core chip. In an embodiment, the first memory chip MD1 may correspond to a main chip. Each of the second memory chip MD2, the third memory chip MD3, and the fourth memory chip MD4 may correspond to a slave chip.

[0121] Referring to Figure 39 , a semiconductor device according to an embodiment may include a plurality of memory chips MD1 to MD4 sequentially stacked on a package board PC2. As used herein, a semiconductor device may refer to, for example, a device such as a semiconductor chip (e.g., a memory chip and / or a logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a stacked package device including a plurality of packages. These devices may be formed using ball grid arrays, wire bonding, through-substrate vias, or other electrical connection components, and may include memory elements such as volatile or non-volatile memory devices. A semiconductor package may include a package substrate, one or more semiconductor chips, and an encapsulant formed on the package substrate and covering the semiconductor chips.

[0122] The encapsulation board PC2 may include a printed circuit board such as a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. The plurality of memory chips MD1 to MD4 may include a first memory chip MD1, a second memory chip MD2, a third memory chip MD3, and a fourth memory chip MD4. An adhesive layer 195 may be disposed between the plurality of memory chips MD1 to MD4 and between the first memory chip MD1 and the encapsulation board PC2. The adhesive layer 195 may include NCF. The plurality of memory chips MD1 to MD4 may be connected to the encapsulation board PC2 via a plurality of first bumps 189 and a plurality of through electrodes 139. An encapsulant 196 covering the plurality of memory chips MD1 to MD4 may be disposed on the encapsulation board PC2. The encapsulant 196 may include EMC. A plurality of second bumps 489 may be disposed on the lower surface of the encapsulation board PC2.

[0123] In an embodiment, the first memory chip MD1 may correspond to a main chip. Each of the second memory chip MD2, the third memory chip MD3, and the fourth memory chip MD4 may correspond to a slave chip. Each of the plurality of memory chips MD1 to MD4 may include a plurality of elements similar to the elements described above with reference to Figures 1 to 37 For example, each of the plurality of memory chips MD1 to MD4 may include a substrate 21, a memory cell MC, and a first scribe line SL1 and a second scribe line SL2. A plurality of through electrodes 139 may be disposed in the plurality of chip regions CH. The plurality of through electrodes 139 may pass through the chip regions of the substrate in each of the memory chips MD1 to MD4.

[0124] According to an embodiment, a first pattern group may be disposed on the first region of the scribe line. A second pattern group may be disposed on the second region of the scribe line. The division holes may overlap with the division region between the first region and the second region of the scribe line. Each of the first pattern group and the second pattern group may include a test element group, an alignment key pattern, or a combination thereof. A semiconductor device in which the test element group and the alignment key pattern are effectively disposed may be implemented.

[0125] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate including a first portion and a second portion connected to a first side of the first portion; Memory cells disposed on the first portion of the substrate, An insulating layer disposed on the first portion and the second portion, the insulating layer covering the memory cells on the first portion of the substrate, wherein a portion of the insulating layer on the second portion includes a stepped sidewall; and A first pattern group disposed on the second portion, Wherein a portion of the first pattern group is disposed in the insulating layer, Wherein a first sidewall of the semiconductor device corresponds to the stepped sidewall, the stepped sidewall including an upper sidewall, a lower sidewall, and a connection surface connecting the upper sidewall to the lower sidewall, Wherein the lower sidewall is disposed below the upper sidewall, closer to the substrate than the upper sidewall, and has a surface roughness different from that of the upper sidewall, Wherein a portion of the insulating layer is disposed between the stepped sidewall and the first pattern group.

2. The semiconductor device according to claim 1, Among them, The insulating layer includes an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, Wherein the first pattern group includes a test element group, Wherein the test element group includes: a test pattern; and a test pad disposed on the test pattern and disposed in the upper insulating layer and electrically connected to the test pattern.

3. The semiconductor device according to claim 2, Among them, The test pattern is buried in the substrate, Wherein a portion of the isolation layer is disposed between the lower sidewall and the test pattern, Wherein a sidewall of the isolation layer is a part of the lower sidewall.

4. The semiconductor device according to claim 1, Among them, The insulating layer includes a lower insulating layer on the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, Wherein the first pattern group includes a test element group, Wherein the test element group includes: a test pattern; and a test pad disposed on the test pattern and disposed in the upper insulating layer and electrically connected to the test pattern, Wherein the test pattern is buried in the lower insulating layer, Wherein a portion of the lower insulating layer is disposed between the lower sidewall and the test pattern, Wherein a sidewall of the lower insulating layer is a part of the lower sidewall.

5. The semiconductor device according to claim 2, Among them, The connection surface is a recessed upper surface of the lower insulating layer.

6. The semiconductor device according to claim 2, Among them, The connection surface is a part of the upper surface of the lower insulating layer, Wherein a portion of the upper surface of the lower insulating layer is exposed by the intermediate insulating layer.

7. The semiconductor device according to claim 2, Among them, The intermediate insulating layer includes a material layer having a greater tensile strength than the lower insulating layer.

8. The semiconductor device according to claim 7, Among them, The intermediate insulating layer includes a SiCN layer.

9. The semiconductor device according to claim 2, Among them, The memory cells include dynamic random access memory cells, static random access memory cells, flash memory cells, magnetoresistive random access memory cells, phase change random access memory cells, ferroelectric random access memory cells, resistive random access memory cells, or a combination thereof.

10. The semiconductor device according to claim 1, Among them, The first pattern group includes alignment key patterns.

11. The semiconductor device according to claim 1, Among them, The lower sidewall has a slope different from that of the upper sidewall.

12. The semiconductor device according to claim 2, Among them, The lower sidewall includes a sidewall of the isolation layer and a part of the sidewall of the lower insulating layer, and wherein, the upper sidewall includes another part of the sidewall of the lower insulating layer and the sidewall of the intermediate insulating layer.

13. The semiconductor device according to claim 1, Among them, The substrate further includes: A third part, connected to the second side of the first part; and A second pattern group, disposed on the third part of the substrate.

14. The semiconductor device according to claim 13, Among them, The semiconductor device includes a second sidewall, wherein, the sidewall of the second pattern group is a part of the second sidewall.

15. The semiconductor device according to claim 14, Among them, The second pattern group includes a test element group, and wherein, the test element group includes: partial test patterns; and partial test pads, disposed on the partial test patterns, wherein, the sidewall of the second pattern group includes the sidewall of the partial test patterns and the sidewall of the partial test pads.

16. The semiconductor device according to claim 13, Among them, The side surface of the second pattern group is rougher than the side surface of the first pattern group.

17. The semiconductor device according to claim 13, Among them, The third part has a width narrower than the width of the second part.

18. A semiconductor device, the semiconductor device comprising: A substrate, including a first part and a second part connected to the first side of the first part; An insulating layer, disposed on the second part and the first part, the insulating layer includes an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, wherein, the part of the insulating layer disposed on the second part includes a stepped sidewall, wherein, the stepped sidewall includes a lower sidewall, an upper sidewall, and a connecting surface connecting the lower sidewall and the upper sidewall, wherein, the lower sidewall includes a sidewall of the isolation layer and a part of the sidewall of the lower insulating layer, wherein, the upper sidewall includes a sidewall of the intermediate insulating layer and another part of the sidewall of the lower insulating layer; Memory cells, disposed on the first part, at least a part of the memory cells is disposed in the lower insulating layer; and A first pattern group, disposed on the second part of the substrate, wherein, the lower sidewall is disposed under the upper sidewall, closer to the substrate than the upper sidewall, and has a surface roughness greater than that of the upper sidewall, wherein, a part of the insulating layer is disposed between the stepped sidewall and the first pattern group, wherein, the memory cells include: a unit transistor; a first electrode, connected to the unit transistor; a second electrode, located on the first electrode; and a capacitor dielectric layer, located between the first electrode and the second electrode.

19. A semiconductor device, the semiconductor device comprising: A printed circuit board; And A plurality of semiconductor chips are stacked on a printed circuit board. At least one of the plurality of semiconductor chips includes: a substrate including a first portion and a second portion connected to a first side of the first portion; an insulating layer disposed on the second portion and the first portion, the insulating layer including an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, wherein a portion of the insulating layer on the second portion includes a stepped sidewall, wherein the stepped sidewall includes a lower sidewall, an upper sidewall, and a connecting surface connecting the lower sidewall and the upper sidewall, wherein the lower sidewall includes a sidewall of the isolation layer and a part of a sidewall of the lower insulating layer, and wherein the upper sidewall includes a sidewall of the intermediate insulating layer and another part of a sidewall of the lower insulating layer; Memory cells are disposed on the first portion, and at least a part of the memory cells is disposed in the lower insulating layer; and A first pattern group is disposed on the second portion of the substrate, wherein the lower sidewall is disposed under the upper sidewall, closer to the substrate than the upper sidewall, and has a surface roughness greater than that of the upper sidewall; wherein a part of the insulating layer is disposed between the stepped sidewall and the first pattern group; wherein the memory cells include: a cell transistor; a first electrode connected to the cell transistor; a second electrode located on the first electrode; and a capacitor dielectric layer located between the first electrode and the second electrode.

20. The semiconductor device according to claim 19, wherein the semiconductor device further includes: A via electrode is disposed in the first portion.

21. A method of manufacturing a semiconductor device, the method including: Providing a substrate including a first chip region, a second chip region, and a scribe line between the first chip region and the second chip region, wherein the scribe line includes a first region, a second region, and a dividing region disposed between the first region and the second region; Forming an insulating layer on the substrate; Forming a first pattern group on the first region of the scribe line; Forming a second pattern group on the second region; and Forming a trench in the insulating layer, wherein the trench overlaps with the dividing region and separates the second pattern group from the first pattern group, The method further includes: dividing the first chip region and the second chip region into semiconductor devices by cutting along the dividing region, wherein a first sidewall of the semiconductor device corresponds to the stepped sidewall, wherein a part of the insulating layer is disposed between the stepped sidewall and the first pattern group.

22. The method according to claim 21, Among them, The insulating layer includes an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, wherein the formation of the trench includes partially etching a part of the intermediate insulating layer, and the part of the intermediate insulating layer overlaps with the dividing region.

23. The method according to claim 21, Among them, The insulating layer includes an isolation layer in the substrate, a lower insulating layer on the isolation layer and the substrate, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer, wherein the trench penetrates the intermediate insulating layer and partially extends into the lower insulating layer.

24. The method according to claim 22, Among them, each of the first pattern group and the second pattern group includes a test element group, wherein, the test element group includes: a test pattern; and a test pad disposed on the test pattern and electrically connected to the test pattern.

25. The method according to claim 24, Among them, the distance between the lowermost end of the trench and the substrate is shorter than the distance between the lowermost end of the test pad and the substrate.

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