A low-power, high-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator

Abstract

The invention discloses a low-power consumption, large-bandwidth, high-resolution and low-phase-noise digitally controlled oscillator, comprising: a complementary differential MOS tube compensation circuit, a three-stage capacitor tuning circuit, a capacitor-inductor filtering circuit and a capacitive degradation circuit, wherein a coarse adjustment capacitor array and a medium adjustment capacitor array are connected in parallel between the drains of a compensation NMOS tube and a PMOS tube, the capacitive degradation circuit is connected between the sources of two compensation NMOS tubes, the complementary differential MOS tube compensation circuit provides negative resistance to compensate for the resistance of a resonant cavity, so that the oscillation of the resonant cavity can be sustained; the three-stage capacitor tuning circuit is used to provide variable capacitance under different tuning precisions to achieve frequency change; the capacitor-inductor filtering circuit introduces thermal noise into a ground terminal through a capacitor and provides impedance through an inductor to suppress the flow of flicker noise so as to filter out the flicker noise of the circuit; the capacitive degradation circuit connects the tuning capacitor array to the source of the compensation MOS tube and then converts it to the drain in proportion to achieve a smaller variable capacitance, so as to achieve a higher resolution.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a digitally controlled oscillator with low power consumption, large bandwidth, high resolution and low phase noise. Background Art

[0002] Oscillators are widely used in mobile communications, wireless smart terminals and other fields. At present, oscillators mainly use analog oscillators, which have high power consumption, high cost, low portability and are easily affected by digital signals in the circuit. In recent years, with the continuous reduction of power supply voltage, digital realization of oscillators has gradually become a trend.

[0003] The digital controlled oscillator consists of a capacitor array and a control circuit, and the frequency is tuned by changing the tuning capacitor through the control word. At present, the oscillator improves the phase noise performance through inductance or mutual inductance tuning, but these oscillators have relatively large power consumption and area, and it is difficult to meet the requirements of mobile communications for low power consumption. Therefore, a digital controlled oscillator with low power consumption, large bandwidth, high resolution and low phase noise is indispensable. Summary of the invention

[0004] The purpose of the present invention is to provide a low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator, which is suitable for use in a fully digital phase-locked loop IP core and can be widely used in low-power applications such as mobile communications. At the same time, due to the large bandwidth, the design has high portability and good integration, which can reduce application costs.

[0005] The object of the present invention is achieved through the following technical solution: a low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator, comprising:

[0006] A complementary differential MOS tube compensation circuit, a three-stage capacitor tuning circuit, a capacitor-inductor filter circuit and a capacitive degradation circuit, wherein the coarse adjustment and medium adjustment capacitor arrays are connected in parallel between the drains of the compensation NMOS tube and the PMOS tube, the capacitive degradation circuit is connected between the sources of the two compensation NMOS tubes, and the capacitor-inductor filter circuits are respectively connected between the common mode point of the bias resistors R1 and R2 and the ground, and between the source of the PMOS tube and the power supply, wherein: the complementary differential MOS tube compensation circuit provides negative resistance to compensate the resistance of the resonant cavity so that the oscillation of the resonant cavity can be sustained; the three-stage capacitor tuning circuit is used to provide variable capacitance under different tuning precisions to achieve frequency change; the capacitor-inductor filter circuit introduces thermal noise into the ground terminal through the capacitor and provides impedance through the inductor to suppress the flow of flicker noise to filter out the flicker noise of the circuit; the capacitive degradation circuit connects the tuning capacitor array to the source of the compensation MOS tube and then converts it to the drain in proportion to achieve smaller variable capacitance to achieve higher resolution.

[0007] Furthermore, the complementary differential MOS tube compensation circuit includes two NMOS tubes connected in a cross-coupling manner, the sources of the two NMOS tubes are connected together, the gate of the first NMOS tube is connected to the drain of the second NMOS tube, and the drain of the first NMOS tube is connected to the gate of the second NMOS tube, forming a cross-coupling structure.

[0008] Furthermore, the three-stage capacitor tuning circuit includes coarse tuning, medium tuning, and fine tuning capacitor arrays. The coarse tuning and medium tuning capacitor arrays are connected in parallel to the drains of the compensation NMOS tube and the PMOS tube, the fine tuning capacitor array is connected in parallel between the sources of the two NMOS tubes, the bias resistors R1 and R2 are connected in series to the source of the NMOS tube, and the coarse tuning, medium tuning, and fine tuning control words are connected to the control ends of the coarse tuning, medium tuning, and fine tuning capacitor arrays, respectively.

[0009] Furthermore, the coarse tuning capacitor in the three-stage capacitor tuning circuit is a switched capacitor circuit.

[0010] Furthermore, the middle tuning capacitor in the three-stage capacitor tuning circuit is a varactor diode capacitor circuit.

[0011] Furthermore, the fine tuning capacitor in the three-stage capacitor tuning circuit is a MOS tube capacitor. The source, drain and gate of the two MOS tubes are connected together, and high and low voltages are applied to the gate. High and low capacitances are induced between the source and the gate, thereby achieving a smaller capacitance change.

[0012] Furthermore, four groups of switch capacitors are used in a proportional distribution to form a coarse-tuning capacitor array, five groups of varactor diode capacitors and one group of MOS capacitors are used to form a medium-tuning capacitor array, and four groups of varactor diode capacitor circuits and two groups of MOS capacitors are used to form a fine-tuning capacitor array.

[0013] Furthermore, the capacitor-inductor filter circuit specifically includes: a ground-end filter capacitor and an inductor connected between the common mode point of the bias resistors R1 and R2 and the ground, a source-end filter capacitor and an inductor connected between the power supply and the sources of the two PMOS tubes, and capacitors connected between the sources of the NMOS tubes M3 and M4 and the ground respectively.

[0014] Furthermore, the capacitive degradation circuit achieves a smaller capacitance change by converting the capacitor array connected to the source to the drain in proportion, thereby further improving the resolution. The capacitive degradation circuit achieves a smaller capacitance change by converting the source capacitance to the drain in a certain proportion, thereby achieving a higher resolution.

[0015] The principle of the present invention is: a low-power, large-bandwidth, high-resolution, low-phase-noise digitally controlled oscillator, comprising: a negative resistance compensation circuit, a capacitor tuning circuit, a capacitive degradation circuit, and a noise filtering circuit. The capacitor tuning circuit is connected to the drain of the MOS tube of the negative resistance compensation circuit to form a resonant cavity, the capacitive degradation circuit is connected to the source of the negative resistance compensation MOS tube, and the noise filtering circuit is composed of a capacitor and an inductor connected to the source of the MOS tube. Among them:

[0016] The negative resistance compensation circuit is composed of a pair of NMOS transistors and a pair of PMOS transistors forming a complementary differential pair to form a negative resistance to compensate for the resistance loss of the resonant cavity.

[0017] The capacitance tuning circuit is composed of three-level tuning capacitance arrays of coarse tuning, medium tuning and fine tuning, which respectively realize capacitance changes of different sizes, and the capacitance in each level of capacitance array is distributed in equal proportion.

[0018] The capacitive degradation circuit is composed of a fine-tuning capacitor array connected to the source of the compensation MOS tube, and the degradation is achieved by converting the source capacitance to the drain resonant cavity.

[0019] The noise filtering circuit is composed of a capacitor and an inductor. The capacitor filters out thermal noise, and the inductor filters out flicker noise.

[0020] Beneficial effects:

[0021] The present invention provides an implementation of a low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator, which greatly reduces the power consumption of the oscillator through a complementary differential structure of current multiplexing; at the same time, by adjusting the working state of a three-stage tuning capacitor array, the circuit has a very wide tuning range, can operate in navigation mode, communication mode, and radar mode, and comply with communication protocol standards; finally, the application of a filtering circuit makes it easy for the phase noise of the circuit to meet the requirements of mobile communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 It is the schematic diagram of a single-port oscillator;

[0024] Figure 2 The negative resistance principle diagram provided by the example of the present invention, wherein: Figure 2 (a) is the negative resistance structure of the cross-coupled MOS tube. Figure 2 (b) is the small signal equivalent circuit;

[0025] Figure 3A schematic diagram of a low-power, high-bandwidth, and high-resolution digitally controlled oscillator is provided for an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a coarse tuning capacitor provided in an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of a mid-adjustment capacitor provided in an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of a fine-tuning capacitor provided in an embodiment of the present invention;

[0029] Figure 7 A capacitive degradation circuit schematic diagram provided by an embodiment of the present invention, wherein: Figure 7 (a) is the schematic diagram of the capacitive degradation circuit. Figure 7 (b) Figure 7 (a) Equivalent circuit;

[0030] Figure 8 A circuit noise principle diagram provided by an embodiment of the present invention;

[0031] Fig. 9 A noise suppression principle diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0033] Figure 1 The schematic diagram of the single-port oscillator used in the present invention is shown. The capacitor Cp and the inductor Lp form a resonant cavity, but the parasitic resistance Rp of the capacitor and the inductor causes the energy in the resonant cavity to be continuously lost until the oscillation stops completely. At this time, if an external circuit (Active Circuit) provides a negative resistance -Rp to compensate for the parasitic resistance, the oscillation can be maintained.

[0034] Figure 2 The principle of negative resistance formation is shown in Figure 2. Figure 2 (a) shows the cross-coupled MOS tube negative resistance structure used in the present invention. Figure 2 (a) shows a pair of cross-coupled NMOS transistors, where the sources of M1 and M2 are connected together, the gate of M1 is connected to the drain of M2, and the drain of M1 is connected to the gate of M2, forming a cross-coupled structure. When a positive voltage is applied to the X and Y ports, the current decreases as the voltage increases, and the X and Y ports appear as negative resistances.

[0035] Figure 2 (b) is the small signal equivalent circuit. It can be seen from the figure that

[0036] V 2 -V 1 =V x (1)

[0037] I X =g m1 V 1 =-g m2 V 2 (2)

[0038]

[0039] Among them, g m1 , g m2 for Figure 2 (a) The transconductance of M1 and M2; M1 and M2 are NMOS transistors; V1 and V2 are the gate-source voltages of MOS transistors M1 and M2;

[0040] Right now Figure 2 The cross-coupled MOS tube shown in the figure shows a negative resistance R, which is as shown in formula (4):

[0041]

[0042] Figure 3 The present invention provides a circuit schematic diagram of a low-power, high-bandwidth, high-resolution digitally controlled oscillator. It mainly includes: a negative resistance compensation circuit, a capacitor tuning array, a capacitive degradation circuit, and a noise filtering circuit. Among them:

[0043] In the embodiment of the present invention, the negative resistance compensation circuit is implemented by a pair of NMOS cross-coupled transistors and a pair of PMOS cross-coupled transistors forming a complementary differential circuit. Figure 3 The current shown in the figure flows from the power supply through the PMOS tubes M1 and M2 and then through the NMOS tubes M3 and M4. It is used twice, generating twice the negative resistance under the same current, thereby achieving a low power consumption design. Figure 3 As shown, a pair of NMOS and a pair of PMOS are cross-coupled and connected, the inductor, coarse adjustment (COARSE) and medium (MIDDLE) tuning accuracy capacitor arrays are connected in parallel to the drains of the compensation NMOS tubes and the PMOS tubes, the filter capacitor C2 and the inductor L2 are connected between the power supply and the sources of the PMOS tubes M1 and M2, the fine adjustment capacitor array (FINE) is connected in parallel to the source of the NMOS tube, the bias resistors R1 and R2 are connected in series to the source of the NMOS tube, the ground filter capacitor C1 and the inductor L1 are connected between the common mode point of the bias resistors R1 and R2 and the ground, and the coarse adjustment, medium adjustment and fine adjustment control words (FCW) are connected to the control terminals of the coarse adjustment, medium adjustment and fine adjustment capacitor arrays respectively.

[0044] In the embodiment of the present invention, the capacitor tuning array circuit is a three-level capacitor array of coarse adjustment, medium adjustment and fine adjustment composed of a switch capacitor circuit, a varactor diode capacitor circuit and a MOS tube capacitor circuit.

[0045] Figure 4 The figure shows a switched capacitor circuit. When the control word FCW is 1, MOS tubes M1, M2, and M3 are all turned on, and the two capacitors are connected in parallel to the ground terminal and the resonant cavity. The capacitance of the resonant cavity increases and the resonant frequency decreases. When the control word is 0, MOS tubes M1, M2, and M3 are all disconnected, the capacitor is disconnected from the resonant cavity, the capacitance of the resonant cavity decreases, and the resonant frequency increases. The switched capacitor can be used in situations where a large capacitance change is required.

[0046] Figure 5 The figure shows a varactor diode capacitor circuit. When the control word changes between 0 and 1, the varactor diode capacitor circuit shows different capacitances to the outside. The varactor diode capacitor circuit can achieve a capacitance change of several femtofarads (femtofarad is a unit of capacitance).

[0047] Figure 6 The figure shows the MOS tube capacitor. The source, drain and gate of two MOS tubes are connected together. High and low voltages are applied to the gate. High and low capacitances will be induced between the source and the gate to achieve smaller capacitance changes. Based on the characteristics of the above three capacitor circuits, four groups of switch capacitors can be used in a proportional distribution to form a coarse adjustment capacitor array, five groups of varactor diode capacitors and one group of MOS capacitors can be used to form a medium adjustment capacitor array, and four groups of varactor diode capacitor circuits and two groups of MOS capacitors can be used to form a fine adjustment capacitor array.

[0048] In the embodiment of the present invention, the capacitive degradation circuit converts the source capacitance to the drain in a certain proportion to achieve a smaller capacitance change and a higher resolution. Figure 7 The capacitive degradation circuit principle is shown in Figure 1. Figure 7 In (a), C is the coarse tuning capacitor, L is the resonant inductor, and C is the fine tuning capacitor. Rloss is the parasitic resistance of the capacitor-inductor resonant cavity, and Ced is the equivalent capacitance of the source capacitance converted to the drain resonant cavity.

[0049] Connect the fine-tuning capacitor circuit to the source of the MOS tube and convert it into Figure 7 For the circuit shown in (b), the source capacitance is converted to the drain capacitance as shown in formula (5):

[0050]

[0051] Among them, g m is the transconductance of the MOS tube, C is the source capacitance, w l0 is the resonant frequency;

[0052] In RF circuits, C>>g m / (2w l0 ), then formula (5) is simplified to formula (6),

[0053]

[0054] Among them, g m is the transconductance of the MOS tube, C is the source capacitance, w l0 is the resonant frequency, Q f The conversion factor

[0055] That is, the source capacitance is converted to the drain at a certain ratio, and the conversion factor is controlled by controlling the drain capacitance and the transconductance of the MOS tube to achieve a smaller capacitance change and a higher resolution.

[0056] like Figure 8 The figure shows a noise schematic diagram of the circuit. The circuit mainly includes thermal noise generated by the parasitic resistance of resistors, MOS tubes and inductors, and flicker noise of MOS tubes.

[0057] In the embodiment of the present invention, the noise filtering circuit is as follows: Fig. 9 The dotted box shows that it is used to filter and suppress the flicker noise in the circuit. For thermal noise, capacitors C3 and C4 are mainly used to filter and guide the thermal noise into the ground. For flicker noise, a large inductor is used to provide a large impedance (High Impedance at 2W0) at the second harmonic to suppress its flow in the circuit to achieve the purpose of attenuation.

[0058] The above solution of the embodiment of the present invention mainly has the following beneficial effects:

[0059] (1) The use of three-level tuning capacitors, namely coarse tuning, medium tuning and fine tuning, makes the oscillator have a large tuning range.

[0060] (2) The complementary differential structure current reuse makes the circuit power consumption very small.

[0061] (3) Capacitors and inductors are used to filter noise, and the phase noise is very low.

[0062] (4) The use of capacitive degeneration circuit makes the circuit resolution very high.

[0063] The above is only the best specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A low-power, high-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator, characterized in that: include: A complementary differential MOS tube compensation circuit, a three-stage capacitor tuning circuit, a capacitor-inductor filter circuit and a capacitive degradation circuit, wherein the coarse adjustment and medium adjustment capacitor arrays are connected in parallel between the drains of the compensation NMOS tube and the PMOS tube, the capacitive degradation circuit is connected between the sources of the two compensation NMOS tubes, and the capacitor-inductor filter circuits are respectively connected between the source of the NMOS tube and the ground terminal, and between the source of the PMOS tube and the power supply, wherein: the complementary differential MOS tube compensation circuit provides negative resistance to compensate for the resistance of the resonant cavity so that the oscillation of the resonant cavity can be sustained; the three-stage capacitor tuning circuit is used to provide variable capacitance under different tuning precisions to achieve frequency change; the capacitor-inductor filter circuit introduces thermal noise into the ground terminal through the capacitor, and provides impedance through the inductor to suppress the flow of flicker noise to filter out the flicker noise of the circuit; the capacitive degradation circuit connects the tuning capacitor array to the source of the compensation MOS tube and then converts it to the drain in proportion to achieve a smaller variable capacitance, thereby achieving a higher resolution; The complementary differential MOS transistor compensation circuit comprises two NMOS transistors connected in a cross-coupling manner, wherein the sources of the two NMOS transistors are connected together, the gate of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the gate of the second NMOS transistor, forming a cross-coupling structure; The three-stage capacitor tuning circuit includes coarse tuning, medium tuning and fine tuning capacitor arrays. The coarse tuning and medium tuning capacitor arrays are connected in parallel to the drains of the compensation NMOS tube and the PMOS tube, the fine tuning capacitor array is connected in parallel between the sources of the two NMOS tubes, the bias resistors R1 and R2 are connected in series to the sources of the NMOS tubes, and the coarse tuning, medium tuning and fine tuning control words are connected to the control ends of the coarse tuning, medium tuning and fine tuning capacitor arrays respectively.

2. The low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator according to claim 1, characterized in that: The coarse tuning capacitor in the three-stage capacitor tuning circuit is a switched capacitor circuit.

3. The low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator according to claim 1, characterized in that: The middle tuning capacitor in the three-stage capacitance tuning circuit is a varactor diode capacitance circuit.

4. The low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator according to claim 1, characterized in that: The fine tuning capacitor in the three-stage capacitance tuning circuit is a MOS tube capacitor. The source, drain and gate of the two MOS tubes are connected together, and high and low voltages are applied to the gate. High and low capacitances will be induced between the source and the gate, achieving a smaller capacitance change.

5. The low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator according to claim 1, characterized in that: Four groups of switch capacitors are used in a geometrically distributed manner to form a coarse-tuning capacitor array, five groups of varactor diode capacitors and one group of MOS capacitors form a medium-tuning capacitor array, and four groups of varactor diode capacitor circuits and two groups of MOS capacitors form a fine-tuning capacitor array.

6. The low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator according to claim 1, characterized in that: The capacitor-inductor filter circuit specifically includes: a ground-end filter capacitor and an inductor connected between the common-mode point of the bias resistors R1 and R2 and the ground, a source-end filter capacitor and an inductor connected between the power supply and the source electrodes of the two PMOS tubes, and filter capacitors connected to the source electrodes of the two NMOS tubes and the ground end respectively.

7. The low-power, large-bandwidth, high-resolution, and low-phase-noise digitally controlled oscillator according to claim 1, characterized in that: The capacitive degradation circuit achieves a smaller capacitance change by converting the capacitor array connected to the source to the drain in proportion, thereby further improving the resolution. The capacitive degradation circuit achieves a smaller capacitance change by converting the source capacitance to the drain in a certain proportion, thereby achieving a higher resolution.

Images