Amplifier circuit capable of accurately measuring small electrical signals

Abstract

The amplifier circuit comprises a resistive divider (R REF ) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d1, d2), resistive nodes (q) defined between adjacent resistive elements, and an input current source (I REF ) connected or connectable to said first main node (a). The resistive divider (R REF ) comprises two arrays of addressable switching elements that can be controlled open or closed by a feedback signal (s FB ). The amplifier circuit comprises a differential pair of transistors (T1, T2) wherein the source terminal of each transistor (T1, T2) is connected to the second node (b), the gate terminal of the transistor (T1, T2) is connected to an input signal (v1, v2), the drain terminal of the transistor (T1, T2) is connected to a current source (I1, I2), and the base terminal of the transistor (T1, T2) is connected to the readout node (d1, d2).

Description

Technical Field

[0001] The present invention relates to an amplifier circuit and a method for accurately measuring small electrical signals, such as those converted or generated from sensors or sensor elements including passive infrared (PIR) and thermopile sensors. Background Technology

[0002] Many sensors and converters that convert physical quantities and parameters into electrical signals generate small signals that require sensitive instruments to detect. Typically, these signals are associated with the high output impedance of the sensors and converters, the accumulation of charge within the sensors themselves, operation in noisy environments, and other environmental challenges that require extra attention when connecting and detecting these signals.

[0003] One example is in the field of thermal detection, where thermopile or high-temperature ceramic elements are used in applications such as passive infrared (PIR) detection. This often requires (preferably differentially) measuring small voltages and currents in the sensor to ensure accurate readouts. Readouts of these small voltage and / or current signals will further not affect the normal operation of the sensing element. Converting these signals into a digital representation allows for significant flexibility in processing them for decision-making and other purposes. If this conversion occurs early in the signal chain, environmental factors (such as RF coupling, supply variations, etc.) are less likely to affect the fidelity and accuracy of the signal.

[0004] Requirements for such measuring devices or instruments may include:

[0005] • The ability to operate in a differential manner, and the ability to operate in a single-ended manner when needed (e.g., when the sensor has no differential output);

[0006] • The ability to operate at input voltages above and below 0V (symmetric and asymmetrical);

[0007] • Low noise contribution to ensure maximum signal-to-noise ratio, as the measurement device is typically encountered early in the signal chain (which could affect all downstream systems);

[0008] • Low-power operation, enabling use in battery-powered devices while ensuring optimal energy utilization;

[0009] High dynamic range will ensure accurate detection of signals generated by the sensor over a wide range;

[0010] • It can convert analog signals into digital signals so that they can be further processed earlier in the signal chain;

[0011] High linearity;

[0012] Sufficient bandwidth to ensure accurate tracking of changes in the input signal generated by the sensor; and

[0013] A robust implementation will enable such a measuring device or instrument to be implemented in electronic devices of different natures, including discrete implementations, integrated circuits using CMOS or bipolar technology, or any other implementation that can be used for a given application.

[0014] In prior art disclosure DE102013014810B4, a differential amplifier level satisfying several of the aforementioned requirements is described. This disclosure discloses a digitally controlled string of series resistors for directing a constant reference current to either branch of the differential amplifier based on a feedback signal generated as part of a sigma-delta analog-to-digital converter (ADC). This feedback signal is crucial for establishing the functionality of the differential machine used as part of the sigma-delta converter architecture. One drawback of this approach is that the final noise performance is limited by the resistor connected between the source stages of the two resistors, especially when the resistor value is high due to low current consumption. Summary of the Invention

[0015] This invention provides an amplifier circuit, comprising:

[0016] Resistor voltage divider (R) REF ), including n series-connected resistive elements (r n ), where n>1, where:

[0017] The resistor divider (R) REF It includes two main nodes defined at each end, namely the first main node (a) and the second main node (b);

[0018] The resistor divider (R) REF It also includes two read nodes (d1, d2), namely the first read node (d1) and the second read node (d2);

[0019] The resistor divider (R) REF This includes the resistor node (q) defined between adjacent resistive elements;

[0020] Input current source (I REF ), connected to or potentially connected to the first master node (a);

[0021] The resistor divider (R) REFThe system includes two addressable switch element arrays, wherein a first switch element array is disposed between the respective resistor node (q) of each resistor element and the first readout node (d1), and a second switch element array is disposed between the respective resistor node (q) of each resistor element and the second readout node (d2); and

[0022] The state of the switching element can be fed back by a signal (s) FB The resistive element controls whether the circuit is open or closed, and thus serves as an optional voltage tap associated with the readout nodes (d1, d2).

[0023] A differential pair of transistors (T1, T2) includes a first transistor (T1) having at least four terminals and a transistor (T2) having at least four terminals, wherein:

[0024] The first terminal of each of the transistors (T1, T2) is connected to the second node (b);

[0025] The second terminals of the transistors (T1, T2) are connected to their respective input signals (v1, v2);

[0026] The third terminals of the transistors (T1, T2) are connected to their respective current sources (I1, I2), wherein the differential output signal (v OUT The generation occurs between the third terminals of the transistors (T1, T2); and

[0027] The fourth terminal of each transistor (T1, T2) is connected to the respective readout node (d1, d2);

[0028] The amplifier circuit is configured to function as a differential amplifier because the transistors (T1, T2) form differential amplifiers with their respective input signals (v1, v2) at their second terminals; and

[0029] The fourth terminal affects the threshold of each of the transistors (T1, T2) in order to be based on the feedback signal (s) FB The resistor divider (R) determined by the given information REF The voltage signal generated by the operation of the resistor divider (R) is added to or subtracted from the voltage signal generated by the resistor divider (R). REF The differential signal of the readout node (d1, d2).

[0030] The input signals (v1, v2) can originate from an external source. The external source can be a sensor.

[0031] The transistors (T1, T2) can be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The transistors (T1, T2) can be n-type MOSFETs or p-type MOSFETs.

[0032] The terminals of the transistors (T1, T2) can be as follows:

[0033] First terminal = source end terminal;

[0034] Second terminal = gate terminal;

[0035] Third terminal = drain terminal; and / or

[0036] The fourth terminal is the base terminal.

[0037] The readout nodes (d1, d2) can be considered as differential nodes. In other words, the signals at the readout nodes (d1, d2) can be the feedback signal (s). FB The difference representation of ).

[0038] The amplifier circuit can be configured to perform the function of an integrator. The integrator function can be performed whereby the differential pair formed by the transistors (T1, T2), the current sources (I1, I2), and the node parasitic capacitance and resistance is located at a node connected to the third terminal of each of the respective transistors (T1, T2), and the amplifier circuit operates as a differential amplifier relative to the differential signals (v1, v2) and (d1, d2) such that the differential output (v... OUT This displays the characteristics of the integral output. Additional capacitors can be added to the nodes connected to the third terminal of each transistor (T1, T2) to change the integrator's operation.

[0039] The amplifier circuit can utilize the fourth terminal (e.g., the base terminal) of each transistor (T1, T2) to form a "second gate," that is, another terminal that affects the threshold voltage of each transistor. In other words, with the feedback signal (s FB Feedback in the form of ) can be directly applied to transistors (T1, T2), thereby effectively generating a differential amplifier that is directly applied to the sigma-delta converter. Due to the feedback signal (s) FB The feedback signal (s) can be a digital signal that controls the state of a switching element (e.g., open or closed), therefore the feedback signal (s) FB The polarity of ) can be easily controlled. Furthermore, and according to the feedback signal (s) FB The content and form of the voltage signals at the readout nodes (d1, d2) may be correlated, or these voltage signals may be controlled independently. In one example application, as part of the intended operation of the amplifier circuit, the voltage signals at the readout nodes (d1, d2) may vary in opposite directions.

[0040] The amplifier circuit can be configured to receive the respective input signals (v1, v2) from the sensors:

[0041] Differential signal, in the case where the sensor provides a differential output signal; or

[0042] Variable input signal and fixed or grounded input signal, in the case where the sensor only provides a single-ended output.

[0043] The respective input signals (v1, v2) can be (relatively) negative and positive input signals (v1, v2) respectively. IN v IP The negative input signal (v) IN ) can be connected to the gate terminal of the first transistor (T1), and the positive input signal (v IP It can be connected to the gate terminal of the second transistor (T2).

[0044] In other words, the resistor divider (R) REF It can be composed of multiple individual resistive elements (r) n The resistor divider (R) consists of switching elements configured to provide two programmable voltage taps at the readout nodes (d1, d2), allowing addressable reading of the resistor divider (R). REF The nodes inside the resistor divider. From these voltage taps, the voltage signal at the readout nodes (d1, d2) can be obtained. When current flows through the resistor divider (R... REF When this occurs, a voltage divider will occur across each of the resistive elements, allowing the readout nodes (d1, d2) to read the data based on the feedback signal (s). FB The specific state (open or closed) of the switching element is determined by reading R. REF The discrete distribution of the entire voltage. Therefore, a feedback signal (s) can be applied appropriately. FB In the case of ), the resistor divider (R) is selected by reading nodes (d1, d2). REF The specific partial voltage value on the surface.

[0045] The amplifier circuit can form part of a Sigma-Delta ADC (analog-to-digital converter). For this purpose, the transistors (T1, T2) can be configured as summing nodes, or form part of a summing node. The resistor divider (R...) REFThe current sources (I1, I2), with auxiliary circuitry, can be configured to function as integrators or form part of an integrator. The sigma-delta ADC can be considered a measurement circuit, where the aforementioned amplifier circuitry constitutes part of the sigma-delta ADC. The ADC output can be provided to the feedback logic to generate S. FB To control R REF Taps d1 and d2 to generate analog signals applied to the bases of transistors T1 and T2, thereby allowing the feedback signal to be subtracted from or added to the original ADC output.

[0046] The Sigma-Delta ADC may include a comparator. The input of the comparator may be connected to the differential output signal (V) of the amplifier circuit. OUT ).

[0047] The Sigma-Delta ADC may include, for example, decimation ADC (analog-to-digital converter) logic. The inputs of the ADC logic may be connected to the output of the comparator.

[0048] The Sigma-Delta ADC may include feedback logic. The feedback logic may be connected to the output of the ADC logic. The feedback logic may be configured to generate the feedback signal (s). FB The output of the ADC can be log2(n) bits.

[0049] This invention provides a method for operating an amplifier circuit, the method comprising:

[0050] Provide resistor dividers (R) REF ), including n series-connected resistive elements (r n ), where n>1, where:

[0051] The resistor divider (R) REF It includes two main nodes defined at each end, namely the first main node (a) and the second main node (b);

[0052] The resistor divider (R) REF It also includes two read nodes (d1, d2), namely the first read node (d1) and the read node (d2);

[0053] The resistor divider (R) REF This includes the resistor node (q) defined between adjacent resistive elements;

[0054] Input current source (I REF), connected to or potentially connected to the first master node (a);

[0055] The resistor divider (R) REF It includes two addressable switching element arrays, wherein the first switching element array is disposed in the resistive element (r n Each of the resistor nodes (q) and the first readout node (d1) is located between the resistor node (r) and the first readout node (d1), and the second switching element array is disposed between the resistor nodes (r) and the first readout node (d1). n Between their respective resistor nodes (q) and the second readout node (d2); and

[0056] The state of the switching element can be determined by a feedback signal (s). FB The resistor element (r) controls the opening or closing of the circuit. n Therefore, it is used as an optional voltage tap associated with the readout nodes (d1, d2);

[0057] A transistor differential pair (T1, T2) is provided, comprising a first transistor (T1) having at least four terminals and a second transistor (T2) having at least four terminals, wherein:

[0058] The first terminal of each of the transistors (T1, T2) is connected to the second node (b);

[0059] The second terminals of the transistors (T1, T2) are connected to their respective input signals (v1, v2);

[0060] The third terminals of the transistors (T1, T2) are connected to their respective current sources (I1, I2), wherein the differential output signal (v OUT The generation occurs between the third terminals of the transistors (T1, T2); and

[0061] The fourth terminals of the transistors (T1, T2) are connected to their respective readout nodes (d1, d2);

[0062] The amplifier circuit performs the function of a differential amplifier because the transistor forms a differential amplifier with its respective input signals (v1, v2) at its second terminal; and

[0063] The fourth terminal of each transistor (T1, T2) affects the transconductance of its respective transistor (T1, T2) so as to be based on the feedback signal (s) FB The resistor divider (R) determined by the given information REF The voltage signal generated by the operation of the resistor divider (R) is added to or subtracted from the voltage signal generated by the resistor divider (R). REF The differential signal of the readout node (d1, d2). Attached Figure Description

[0064] The invention will now be further described by way of example with reference to the accompanying drawings.

[0065] In the attached diagram:

[0066] Figure 1 A circuit diagram of an amplifier circuit according to the present invention is shown;

[0067] Figure 2 It shows Figure 1 The circuit diagram of the resistor divider in the amplifier circuit;

[0068] Figure 3 It shows Figure 1 A more detailed circuit diagram of the amplifier circuit described above;

[0069] Figure 4 A schematic diagram of a Sigma-Delta ADC is shown, in which... Figure 1 The amplifier circuit described above can form part of an ADC;

[0070] Figure 5 It shows Figure 4 The circuit and schematic diagram of a first embodiment of the Sigma-Delta ADC in a more detailed form;

[0071] Figure 6 It shows Figure 4 The circuit and schematic diagram of a second embodiment of the Sigma-Delta ADC in more detail;

[0072] Figure 7-9 It shows Figure 2 Circuit diagram of an alternative form of the described resistor divider. Detailed Implementation

[0073] Figure 1 An amplifier circuit 100 according to the present invention is shown. The amplifier circuit 100 includes a resistor divider (R... REF It includes n series-connected resistive elements (r n ), where n>1. Figure 2 and Figure 7-9 The resistor divider (R) is shown in more detail below. REF The resistor divider (R) REF It includes two master nodes defined at each end, namely the first master node (a) and the second master node (b). Resistor voltage divider (R) REF It also includes two read nodes (d1, d2), namely the first read node (d1) and the second read node (d2). In this example configuration, the read nodes (d1, d2) are differential and therefore can be considered as differential nodes (d1, d2).

[0074] Input current source (I REF ) is connected to or can be connected to the first master node (a). Input current source (I) REF It is constant or nearly constant and can be considered as a bias current source.

[0075] Resistor voltage divider (R) REF ) includes adjacent resistive elements (r1…r n The resistance nodes defined between (in) Figure 7-9 (represented by the letter (q) in Chinese). Resistor voltage divider (R) REF It includes two addressable switching element arrays (S a1 S a2 ), wherein the first switching element array (S a1 ) set in the resistor element (r1…r n Between their respective resistor nodes (q) and the first readout node (d1), and between the second switching element array (S) a2 ) set in the resistor element (r1…r n Between their respective resistor nodes (q) and the second readout node (d2). Each switching element (S) a1 S a2 The state of ) can be fed back by a signal (s) FB Individual control of opening or closing, resistor element (r1…r) n Therefore, it is used as an optional voltage tap associated with the readout nodes (d1, d2).

[0076] Amplifier circuit 100 has a differential pair of transistors (T1, T2), including a first transistor (T1) and a second transistor (T2). In this example, transistors (T1, T2) are MOSFETs, and each transistor has four terminals, which is generally expected in modern CMOS processes. Amplifier circuit 100 has the terminals of transistors (T1, T2) connected as follows:

[0077] The first terminal of each transistor (T1, T2), which is the source terminal in this example configuration, is connected to the second node (b);

[0078] The second terminal of the transistors (T1, T2), which is the gate terminal in this example configuration, is connected to their respective input signals (v1, v2);

[0079] The third terminals of transistors (T1, T2), which are drain terminals in this example configuration, are connected to their respective current sources (I1, I2); and

[0080] The fourth terminal of the transistors (T1, T2), which is the base terminal in this example configuration, is connected to their respective readout nodes (d1, d2).

[0081] Therefore, in which respectively have the label v OUT + and v OUT A differential output signal (v) is generated between the drain terminals of transistors (T1, T2) at a voltage level of -. OUT The amplifier circuit 100 is configured to perform the function of a differential amplifier because the transistors form a differential amplifier with their respective input signals (v1, v2) at their gate terminals. The base terminals affect the threshold voltage of each transistor (T1, T2) so as to be based on the feedback signal (s) FB The determined resistor divider (R) REF The voltage signal generated by the operation of the resistor divider (R) is added to or subtracted from the voltage signal generated by the operation of the resistor divider (R). REF The differential signal of the readout node (d1, d2).

[0082] Figure 2 The resistor divider (R) is shown in further detail below. REF ()( Figure 7-9 Its variants are described in [the document]. A single resistive element (r1…r) n The sizes of the resistor nodes (q1…q) can be equal or unequal. n-1 ) is defined as the adjacent resistors (r1…r) within the master nodes a and b at each end. n Between ) . In this example, there are 2*n switching elements, respectively set at the resistor node (q1…q) in (1). n-1 ) and the second master node (b) and (2) readout nodes (d1, d2). Figure 7 An example with 2*(n+1) switching elements is shown. Figure 8 An example is shown where a switching element is connected to master node a (but not master node b), and Figure 9 An example is shown where 2*(n-1) switching elements are connected only to resistor nodes (q1…q). n-1 (but not connected to the master nodes a and b)

[0083] Regardless of precise configuration, switching elements can be used as programmable voltage taps to enable operation based on feedback signals (s). FB Connect the readout nodes (d1, d2) to the selected individual resistor element (r1…r2). n From these voltage taps, two signals can be obtained at the readout nodes (d1, d2). This occurs when current flows through the resistor divider (R...). REF When the resistors are connected in series, voltage division occurs throughout the entire array of individual resistors, resulting in a voltage drop according to the feedback signal (s). FB The specific closure of the switching element is determined by the two taps, which can be read through the readout nodes (d1, d2) of the resistor divider (R). REF The discrete distribution of the entire voltage.

[0084] The input signal (v1, v2) can come from a sensor and can be specified as v IN and v IP These inputs are connected to the gate terminals of transistors (T1, T2), respectively. If the sensor provides a differential output signal, the signal will be differential. If the sensor only provides a single-ended output, one of these inputs will be grounded or connected to a fixed potential. Signal v IN and v IP The reference can be positive or negative, or one or both of them can be connected to the reference.

[0085] refer to Figure 3 Circuit 200 performs the functions of a differential amplifier and an integrator, both of which are essential for the operation of a Sigma-Delta analog-to-digital converter. One aspect of the invention relates to the extraction of signals from the output signal (v... OUT Subtract the feedback signal (s) from the input. FB This is done in a way that allows for the implementation of the required differential functionality.

[0086] In existing circuits, the base connection is connected to a constant potential, when v IN =v IP At that time, the tail current I REF It will be evenly divided between branches 1 and 2. IN and v IP Any imbalance between them will cause a change in the transistor's transconductance, thus directing more tail current into one branch. The transistor's output impedance at the drain node is finite, and because the impedance is related to the current sources I1 and I2, this results in v... OUT It is an amplified form of imbalance between inputs.

[0087] However, in this invention, the base terminals of each transistor (T1, T2) are used to form a "second gate," which is another terminal that affects the transconductance of each transistor (T1, T2). The base terminals of each transistor (T1, T2) are connected such that the base terminal of the first transistor (T1) is connected to the signal from the readout node (d1), and the base terminal of the second transistor (T2) is connected to the signal from the readout node (d2).

[0088] Therefore, the feedback can be directly applied to the differential pair of transistors (T1, T2), thereby effectively generating a differential amplifier that is directly applied to the sigma-delta converter. According to Figure 2 Due to the feedback signal (s) FB ) is usually a digital signal that controls the state of a switching element, and the feedback signal (s) FB The polarity of ) can be easily controlled. Furthermore, based on the feedback signal (s) FBThe content and form of the signals at the readout nodes (d1, d2) can be correlated or can be controlled independently. In a typical application, as part of the expected operation of amplifier circuits 100 and 200, the signals at the readout nodes (d1, d2) will change in opposite directions.

[0089] Current sources I1 and I2, along with their parasitic resistance and capacitance, provide the drain gain and integration function of transistors (T1, T2). An additional capacitor 210 can be added to the drain terminals to alter and enhance the integration function.

[0090] Since amplifier circuits 100 and 200 are intended to be used as part of a Sigma-Delta analog-to-digital converter, it may be necessary to explain the individual functions of the circuits in this context. Figure 4 A typical architecture, or functional block diagram, of a one- or multi-bit sigma-delta ADC250 is shown. A summing node (40) must be present so that the feedback signal from the DAC can be subtracted from it. The error signal is processed by an integrator (41) and sent to a comparator (42) for a decision. The digital circuitry (ADC logic) (43) uses the comparator output signal to generate a digital representation of the input signal. This representation is fed back to the summing node via an analog-to-digital converter (44) to be subtracted from the current input signal. This method is generally well known to those skilled in the art.

[0091] In this configuration, amplifier circuits 100 and 200 can uniquely and effectively combine the functions of the summing node (40), integrator (41), and DAC converter (44). The subtraction function of the summing node (40) is performed using a differential pair of transistors (T1, T2) with the technique described above. The feedback signal (s) FB The signal originates from the ADC output, and the feedback signal (s) is used to... FB ) Applied to resistor dividers (R REF The integrator (41) can perform the function of DAC (44) to generate a base voltage used by the differential pair of transistors (T1, T2) as part of a subtraction operation. The integration of the integrator (41) occurs at the drain terminals of the differential pair of transistors (T1, T2).

[0092] Figure 5 The Sigma-Delta ADC 300 is shown, which includes amplifier circuitry 200. The differential pair of transistors (T1, T2) is a PMOS transistor and accepts a differential input signal (v... IN -v IP The signals generated by the DAC (54) function from the differential readout nodes (d1, d2) are used to subtract the feedback from the input through the operation of the differential pair (50). Due to the node characteristics of the integrator (50), the differential output signal (v)OUT The differential form of the differential signal is represented and then sent to the comparator (52) and fed back to the ADC logic (53), which converts the one-bit comparator output signal into a multi-bit signal. The ADC output is compiled by the feedback logic of a portion of the DAC (54) to generate a suitable feedback signal (s). FB ), so that when selecting the feedback tap, it can be applied to the resistor divider (R) REF This generates a signal at the readout node (d1, d2) and ends the feedback loop.

[0093] exist Figure 5 In the example shown, during fully differential operation, the signals at the readout nodes (d1, d2) shift symmetrically in opposite directions. That is, if d1 increases, d2 will decrease by the same proportion. If the implementation is a multi-bit implementation, there will be a relationship between the ADC output and the number of components in the reference resistor, such as... Figure 6 The relationship shown.

[0094] In another form of the measuring device, the circuit may include NMOS transistors of opposite polarities forming a differential pair, and wherein the current source (I REF ) and reference resistor (R) REF The polarity and position of the transistor are adapted accordingly to provide the same function to the circuit. In fact, any field-effect transistor in which the base or body terminal can be used as a second input to control the transconductance can be employed.

[0095] Figure 6 Another form of the Sigma-Delta ADC 400 is shown, in which the amplifier circuit 200 can accept single-ended inputs, for example, one input is grounded and a signal is applied to the other input. Either input can be grounded, while the other inputs accept both positive and negative input signals.

[0096] The Sigma-Delta ADC 300 and 400 can be considered as measurement circuits or measurement devices. The amplifier circuits 100 and 200 and / or the Sigma-Delta ADC 300 and 400 can be integrated circuits or parts thereof.

[0097] Examples of this invention constitute a method for measuring physical parameters such as temperature, radiation, and thermal characteristics from signals generated by a sensor that senses parameters. A novel method is used to generate a differential function between the sensor's differential (but possibly single-ended) input signal and the feedback signal (typically in digital form), which must be subtracted from the input signal as part of a sigma-delta analog-to-digital converter, while adhering to the previously described requirements of the measuring device. Power consumption is minimized because the reference current is also used as the operating current of the differential amplifier.

[0098] The device can be used in a variety of applications, but its implementation is primarily geared towards integrated semiconductor circuits and devices. The device can be manufactured using cost-effective, industry-standard manufacturing processes such as silicon-based CMOS (complementary metal-oxide-semiconductor). The device is found to be used in sensor applications, such as in the readout circuitry of passive infrared (PIR) sensors, thermopile sensors, and other sensors where a wide dynamic range of input signal measurement and discretization is required.

[0099] By constructing the amplifier circuits 100 and 200 described herein, or the measuring devices 300 and 400 including the amplifier circuits 100 and 200, some or all of the requirements listed in the background art are achieved. Furthermore, the novel amplifier circuits 100 and 200 or the measuring devices 300 and 400 disclosed herein can achieve significant advantages compared to the prior art, such as lower noise operation and additional degrees of freedom in the control feedback signal.

Claims

1. An amplifier circuit, comprising: Resistor voltage divider (R) REF ), including n series-connected resistive elements (r n ), where n > 1, where: The resistor divider (R) REF It includes two master nodes defined at each end, namely the first master node (a) and the second master node (b); The resistor divider (R) REF It also includes two read nodes (d1, d2), namely the first read node (d1) and the second read node (d2). The resistor divider (R) REF This includes the resistance node (q) defined between adjacent resistive elements; Input current source (I REF ), connected to the first master node (a); The resistor divider (R) REF It includes two addressable arrays of switching elements, wherein the first array of switching elements is disposed in the resistor divider (R). REF The second switching element array is disposed between the respective resistor node (q) and the first readout node (d1) of the resistor divider (R), and wherein the second switching element array is disposed between the resistor node (q) and the first readout node (d1). REF Between their respective resistor nodes (q) and the second readout node (d2); and The state of the switching element is determined by the feedback signal (s). FB The readout nodes (d1, d2) are thus used as optional voltage taps connected to the resistive element, controlling whether it is open or closed. A differential pair of transistors (T1, T2) includes a first transistor (T1) having at least four terminals and a second transistor (T2) having at least four terminals, wherein: The source terminal of each transistor (T1, T2) is connected to the second master node (b); The gate terminals of the transistors (T1, T2) are connected to their respective input signals (v1, v2). The drain terminals of the transistors (T1, T2) are connected to their respective current sources (I1, I2), where the differential output signal (v OUT ) is generated between the drain terminals of the transistors (T1, T2); and The base terminals of the transistors (T1, T2) are connected to their respective readout nodes (d1, d2), wherein the base terminal of the first transistor (T1) is connected to the first readout node (d1), and the base terminal of the second transistor (T2) is connected to the second readout node (d2). The amplifier circuit is configured to function as a differential amplifier because the transistors (T1, T2) form differential amplifiers with their respective input signals (v1, v2) at their gate terminals; and The base terminals are configured to function as second gates because they affect the threshold values ​​of their respective transistors (T1, T2) based on the feedback signal (s). FB The resistor divider (R) determined by the given information REF The voltage signal generated by the operation of the resistor divider (R) is added to or subtracted from the voltage signal generated by the resistor divider (R). REF The differential signal of the readout node (d1, d2).

2. The amplifier circuit as described in claim 1, wherein, The gate terminals of the transistors (T1, T2) are connected to the sensor and the respective input signals (v1, v2), which originate from the sensor.

3. The amplifier circuit as described in claim 1, wherein, The transistors (T1, T2) are metal-oxide-semiconductor field-effect transistors (MOSFETs).

4. The amplifier circuit as described in claim 1, wherein, The readout nodes (d1, d2) are differential nodes, and the signal at the readout nodes (d1, d2) is the feedback signal (s). FB The difference representation of ).

5. The amplifier circuit of claim 1, configured to perform the function of an integrator, wherein the differential pair formed by the transistors (T1, T2), the current sources (I1, I2), the node parasitic capacitance, and the resistance is located at a node connected to the drain terminal of the respective transistors (T1, T2), and the amplifier circuit operates as a differential amplifier relative to the respective input signals (v1, v2) and the readout nodes (d1, d2) such that the differential output signal (v1, v2) is... OUT This displays the characteristics of the integrated output.

6. The amplifier circuit as described in claim 5, wherein, A capacitor is added to the node connected to the drain terminals of the respective transistors (T1, T2) to change the operation of the integrator.

7. The amplifier circuit as described in claim 6, wherein, With the feedback signal (s) FB Feedback in the form of ) is directly applied to the transistors (T1, T2), effectively producing a differential amplifier that is directly applied to the sigma-delta converter.

8. The amplifier circuit of claim 1, configured to receive the respective input signals (v1, v2): Differential signal; or Variable input signals and fixed or grounded input signals.

9. The amplifier circuit as claimed in claim 1 is an integrated circuit, or forms part of an integrated circuit.

10. A sigma-delta analog-to-digital converter, comprising the amplifier circuit as claimed in claim 1.

11. The sigma-delta analog-to-digital converter of claim 10, comprising a summing node, and wherein, The transistors (T1, T2) are configured to serve as the summing node, or to form part of the summing node.

12. The sigma-delta analog-to-digital converter of claim 10, comprising a DAC digital-to-analog converter, wherein, The resistor divider (R) REF It is configured to be used as the DAC, or to form part of the DAC.

13. The sigma-delta analog-to-digital converter of claim 10, comprising an integrator and wherein, The current sources (I1, I2) have auxiliary circuitry and are configured to function as integrators or form part of an integrator.

14. The sigma-delta analog-to-digital converter of claim 10, comprising a comparator, wherein the input of the comparator is connected to the differential output signal (v) of the amplifier circuit. OUT ).

15. The sigma-delta analog-to-digital converter of claim 14, comprising ADC analog-to-digital converter logic, and wherein, The input of the ADC logic is connected to the output of the comparator.

16. The sigma-delta analog-to-digital converter of claim 15, comprising feedback logic connected to the output of the ADC logic and configured to generate the feedback signal (s FB ).

17. The sigma-delta analog-to-digital converter as claimed in claim 10 is an integrated circuit, or forms part of an integrated circuit.

18. A method of operating an amplifier circuit, the method comprising: Provide resistor dividers (R) REF ), including n series-connected resistive elements (r n ), where n > 1, where: The resistor divider (R) REF It includes two master nodes defined at each end, namely the first master node (a) and the second master node (b); The resistor divider (R) REF It also includes two read nodes (d1, d2), namely the first read node (d1) and the second read node (d2). The resistor divider (R) REF This includes the resistor node (q) defined between adjacent resistive elements; Input current source (I REF ), connected to the first master node (a); The resistor divider (R) REF It includes two addressable arrays of switching elements, wherein the first array of switching elements is disposed in the resistor divider (R). REF The second switching element array is disposed between the respective resistor node (q) and the first readout node (d1) of the resistor divider (R), and the second switching element array is disposed between the resistor node (q) and the first readout node (d1). REF Between their respective resistor nodes (q) and the second readout node (d2); and The state of the switching element is determined by a feedback signal (s). FB The readout nodes (d1, d2) are thus used to connect to the resistive element (r) to control the opening or closing of the circuit. n ) Optional voltage taps; A transistor differential pair (T1, T2) is provided, comprising a first transistor (T1) having at least four terminals and a second transistor (T2) having at least four terminals, wherein: The source terminal of each transistor (T1, T2) is connected to the second master node (b); The gate terminals of the transistors (T1, T2) are connected to their respective input signals (v1, v2). The drain terminals of the transistors (T1, T2) are connected to their respective current sources (I1, I2), where the differential output signal (v OUT ) is generated between the drain terminals of the transistors (T1, T2); and The base terminals of the transistors (T1, T2) are connected to their respective readout nodes (d1, d2), wherein the base terminal of the first transistor (T1) is connected to the first readout node (d1), and the base terminal of the second transistor (T2) is connected to the second readout node (d2). The amplifier circuit performs the function of a differential amplifier because the transistor forms a differential amplifier with the respective input signals (v1, v2) at its gate terminal; and The base terminals of the transistors (T1, T2) affect the transconductance of their respective transistors (T1, T2) so as to be based on the feedback signal (s) FB The resistor divider (R) determined by the given information REF The voltage signal generated by the operation of the resistor divider (R) is added to or subtracted from the voltage signal generated by the resistor divider (R). REF The differential signals of the readout nodes (d1, d2) are obtained, so that the base terminal is configured as a second gate.

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