A quantitative evaluation method and device for single-particle upset protection design of block memory

Abstract

The present invention provides a method and device for quantitatively evaluating the design of single-particle upset protection for block memory. The method includes: determining the storage resource data, corresponding refresh cycles, and corresponding unit data upset rates of each module in the configurable logic unit and block memory in an SRAM-type FPGA; in the case of single-particle protection effectiveness in which two errors occur simultaneously in three paths of the same storage unit, based on different algorithm models, respectively obtaining the error rate caused by the block memory site error, the error rate caused by the self-refresher error, and the error rate caused by the voter error; based on the error rate caused by the block memory site error, the error rate caused by the self-refresher error, and the error rate caused by the voter error, obtaining the quantitative evaluation result of the block memory error rate. The method disclosed in the present invention can realize quantitative evaluation of single-particle protection effectiveness, and improve the efficiency and reliability of optimized configuration between resource use and protection effect.

Description

Technical Field

[0001] The present invention relates to the field of computer application technology, and in particular to a method and device for quantitatively evaluating a block memory single particle upset protection design, and also to an electronic device and a non-transient computer-readable storage medium. Background Art

[0002] SRAM FPGAs are widely used in digital signal processing and control due to their powerful computing power and repeatable configuration capabilities. The biggest advantage of SRAM FPGAs is that they can be configured repeatedly and repeatedly in theory at a very fast speed. One of the biggest disadvantages of SRAM FPGAs is volatility. Configuration data disappears after power failure, and reconfiguration is required every time power is turned on. At present, the common solution is to design a non-volatile memory to save configuration data. After power is turned on, the SRAM FPGA automatically reads the configuration data from the non-volatile memory for configuration. SRAM FPGAs are very sensitive to single particle upsets, which limits their application in the aerospace field. Although SRAM FPGAs are prone to single particle upset effects when exposed to space radiation particles in aerospace applications, resulting in errors in signal processing, SRAM FPGAs are still considered for use in aerospace applications due to their strong signal processing capabilities. Mainstream SRAM FPGA manufacturers such as Xilinx have adopted a series of protective measures to protect SRAM FPGAs from single particle upset effects. Among them, single event upset (SEU) is the phenomenon that the stored information of a digital storage unit changes from "0" to "1" or from "1" to "0" under the irradiation of a single high-energy particle. The storage resources of SRAM-type FPGA mainly consist of two parts: Configurable Logic Block (CLB) and Block RAM (BRAM).

[0003] The single event upset protection measures for configurable logic cells include: triple module redundancy (TMR), partial reconfiguration plus timed refresh. Figure 3As shown in the figure, the original group of combinatorial logic processing in the configurable logic unit is divided into three paths. The input signal is divided into three independent paths, and the output is also three independent paths after each group of combinatorial logic. These three outputs are output after passing through the majority voter (TRV). The majority voter is a voting circuit whose output is the majority of the three inputs. For example, if the three inputs are 1, 1, and 0 respectively, the output of the majority voter is 1. Both the combinatorial logic and the majority voter are constructed using configurable logic unit resources. This three-mode redundancy protection can prevent errors caused by single-particle upsets in a single-path combinatorial logic or majority voter. In other words, all single-point failures (failures caused by a single fault source) on the signal processing path are eliminated, and the reliability of the FPGA can be effectively improved. The majority voter in the configurable logic unit implements the three-mode redundancy by using a lookup table method. If the three-way input data of the majority voter is regarded as an address bit, the corresponding CLB stores the 8-bit data 11101000. If the number of SEUs in the storage cells of the CLB increases over time, and if SEU errors occur in two or more parts of the TMR protection design (combinatorial logic or majority voter), the TMR protection design can no longer correct the errors. Therefore, it is necessary to refresh the CLB storage cells regularly to avoid the accumulation of SEU errors.

[0004] At present, SRAM-type FPGAs have developed a dynamic partial reconfiguration function, that is, during the normal operation of the SRAM-type FPGA, a part of the configuration data is reconfigured, so that the correct code stream can be continuously overwritten with the CLB, effectively avoiding the accumulation of SEU errors and reducing the protection effect of TMR. The BRAM part provides data storage for SRAM-type FPGAs during signal processing. Since the data stored in BRAM is frequently read and written, and is usually changing data, the dynamic partial reconfiguration function of CLB cannot be applied to BRAM. For SEU protection of BRAM using TMR, in order to regularly refresh the BRAM data of TMR to reduce the impact of SEU error accumulation, it is necessary to use CLB resources, design a data refresher by yourself, and regularly refresh the data in the BRAM using TMR. This protection structure is called BRAM self-refresh triple-mode redundant single-particle protection design.

[0005] like Figure 4As shown, the BRAM resource adopts TMR design to store the same data in three BRAMs respectively. The BRAM of FPGA is usually a dual-port design, that is, ports A and B independently accept the read address to read the data. In the data write operation, the write enable port WEN can be controlled according to the state machine to prevent ports A and B from performing write / write operations or read / write operations on the data of the same address at the same time. Therefore, after the BRAM data is refreshed, the data is output by the OutB port, and the voting result is written back to DataA through the TRV majority voter. The control of the state machine is implemented by configuring the CLB resource as COUNTER. At the same time, COUNTER is also TMR protected and refreshed by the dynamic partial reconfiguration function of the CLB. The main functions of COUNTER include address counting and port enable control. Its specific structure is shown as follows Figure 5 As shown, the minority voter used is such a voter. When its own data is in the minority compared with the other two input data, it indicates that its own data is wrong and outputs the indication signal 1. CEN_BSCNTR is an address transfer enable voter, and its input is three CNT_TR signals. Only when the three CNT_TR signals require the address bit to be transferred, CEN_BSCNTR will output the transfer instruction.

[0006] like Figure 5As shown, the comparator COMPARATOR implements state control to avoid conflicts caused by simultaneous write operations of ports A and B. ADDRA_[0|1|2]+WEA[0|1|2] inputs the A port address and write enable status of the BRAM; Address_CNTR is the B port address; Error_indication[0|1|2] is the output of the minority voting port ERROR in the data voter Data_Voter, which serves as an error indication. That is, when one of the three data is different from the other data, an error indication is issued, indicating that the data of this path needs to be corrected. The correct data is output by the majority voting port VD in Data_Voter. The state control of the comparator COMPARATOR is as follows: (1) When Error_indication[0|1|2] does not receive an error indication, the WEB write enable is not turned on, CNT_TR issues an address increment operation, and the address counter jumps to the next address. (2) When Error_indication[0|1|2] receives an error indication, it first compares whether ADDRA and ADDRB are consistent. If they are inconsistent, it means that the operation addresses of port A and port B are different at this time. The data of port B can be corrected. At this time, WEB is enabled. After the write operation cycle ends, CNT_TR issues an address increment operation to refresh the data of the next address. If ADDRA and ADDRB are consistent, but WEA write enable is not enabled, the data of port B can also be corrected. At this time, WEB is enabled. After the write operation cycle ends, CNT_TR issues an address increment operation to refresh the data of the next address. Only when ADDRA and ADDRB are consistent and WEA write enable is enabled, WEB is closed, CNT_TR does not issue an address increment operation, and the data correction of port B is in standby state. Except for BRAM_block0, BRAM_block1 and BRAM_block2, other functional blocks are implemented by CLB resources, and these CLB resources will use TMR and partial reconfiguration plus timed refresh for SEU protection.

[0007] Due to the full TMR protection, any functional block eliminates the SRU single point failure, that is, if one of the three functional blocks using TMR has an SEU, it will not cause the BRAM to output incorrect data. The timed refresh of CLB and BRAM further reduces the possibility of more than one of the three functional blocks of TMR having an SEU failure, thereby greatly mitigating the SEU of BRAM.

[0008] The existing SEU evaluation technology mainly evaluates the on-orbit flip rate of storage units. The specific method is to first conduct device-level ground simulation tests on the CLB and BRAM of SRAM-type FPGAs, use high-energy heavy ion sources and high-energy proton sources with different energies to irradiate the devices, record the energy, injection and number of errors of the irradiated particles, and obtain the SEU cross-sections of CLB and BRAM through test data processing. Then input the mission conditions, including operating time, operating orbit, shielding conditions, etc., to predict the space radiation environment on the orbit where the FPGA will perform the mission. Using models such as IRPP, input the predicted orbital high-energy heavy ion and high-energy proton energy spectrum and SEU cross-section data, the SEU flip rate of each storage unit of CLB and BRAM can be obtained respectively.

[0009] Although the existing SEU protection technology of the BRAM module of the SRAM type FPGA can effectively mitigate the output data errors caused by the SEU effect from the design principle, these protections require the consumption of relatively more additional resources (CLB and BRAM). Therefore, it is necessary to quantitatively evaluate the effectiveness of the SEU protection measures so that designers can weigh the consumed resources and the protection effect achieved. However, the existing FPGA on-track SEU flip rate evaluation method is mainly for a single storage unit. After the SEU protection measures are adopted, the single-bit error may not be transmitted to the outside. The protection measures of BRAM are relatively complex, and some existing evaluation methods for protection measures are not fully applicable to the evaluation of BRAM protection effectiveness. Therefore, how to design an effective and reliable quantitative evaluation of block memory single particle flip protection design has become an important research topic in this field. Summary of the invention

[0010] To this end, the present invention provides a block memory single particle upset protection design quantitative evaluation method and device to solve the problem that the block memory single particle upset protection design quantitative evaluation scheme in the prior art consumes more additional resources, resulting in low configuration efficiency.

[0011] The present invention provides a quantitative evaluation method for single-particle upset protection design of a block memory, comprising:

[0012] Determine the storage resource data, corresponding refresh cycle and corresponding unit data flip rate of each module in the configurable logic unit and block memory in the SRAM type FPGA; wherein the storage resource data includes first type storage resource data, second type storage resource data and third type storage resource data;

[0013] Based on the first type of storage resource data, the refresh cycle, the unit data flip rate and a preset first block memory error rate algorithm model, an error rate caused by a location error of the block memory is obtained;

[0014] Based on the second type of storage resource data, the refresh cycle, the unit data flip rate and a preset second block memory error rate algorithm model, obtaining an error rate caused by the self-refresh device error;

[0015] Based on the third type of storage resource data, the refresh cycle, the unit data flip rate and a preset third block memory error rate algorithm model, obtaining the error rate caused by the voter error;

[0016] Based on the error rate caused by the block memory part error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error, a quantitative evaluation result of the block memory error rate is obtained.

[0017] Furthermore, the first category of storage resource data is the storage resource data used by the block memory module in the block memory; the second category of storage resource data is the storage resource data used by the comparator module, the address generator module, and the address enabler module in the configurable logic unit; the self-refresher includes the comparator module, the address generator module, and the address enabler module; the third category of storage resource data is the storage resource data used by the data voter in the configurable logic unit.

[0018] Furthermore, the algorithm expression corresponding to the first memory error rate algorithm model is:

[0019]

[0020] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M b Storage resource data used by the block memory module.

[0021] Furthermore, the algorithm expression corresponding to the second memory error rate algorithm model is:

[0022] M cac =M com +M Add +M CEN

[0023]

[0024] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; tc Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M com The storage resource data used by the comparator module; M Add The storage resource data used by the address generator module; M CEN The storage resource data used by the address enabler module; M cac Storage resource data used by the self-refresh device.

[0025] Furthermore, the algorithm expression corresponding to the third memory error rate algorithm model is:

[0026]

[0027] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M VD Storage resource data used by the data voter module.

[0028] Furthermore, in the case of single particle protection effectiveness when two-way errors occur simultaneously in three ways of the same storage unit, the error rates caused by errors of different modules are obtained respectively.

[0029] Accordingly, the present invention also provides a block memory single-particle upset protection design quantitative evaluation device, comprising:

[0030] Determine the storage resource data, corresponding refresh cycle and corresponding unit data flip rate of each module in the configurable logic unit and block memory in the SRAM type FPGA; wherein the storage resource data includes first type storage resource data, second type storage resource data and third type storage resource data;

[0031] Based on the first type of storage resource data, the refresh cycle, the unit data flip rate and a preset first block memory error rate algorithm model, an error rate caused by a location error of the block memory is obtained;

[0032] Based on the second type of storage resource data, the refresh cycle, the unit data flip rate and a preset second block memory error rate algorithm model, obtaining an error rate caused by the self-refresh device error;

[0033] Based on the third type of storage resource data, the refresh cycle, the unit data flip rate and a preset third block memory error rate algorithm model, obtaining the error rate caused by the voter error;

[0034] Based on the error rate caused by the block memory part error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error, a quantitative evaluation result of the block memory error rate is obtained.

[0035] Furthermore, the first category of storage resource data is the storage resource data used by the block memory module in the block memory; the second category of storage resource data is the storage resource data used by the comparator module, the address generator module, and the address enabler module in the configurable logic unit; the self-refresher includes the comparator module, the address generator module, and the address enabler module; the third category of storage resource data is the storage resource data used by the data voter in the configurable logic unit.

[0036] Furthermore, the algorithm expression corresponding to the first memory error rate algorithm model is:

[0037]

[0038] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M b Storage resource data used by the block memory module.

[0039] Furthermore, the algorithm expression corresponding to the second memory error rate algorithm model is:

[0040] M cac =M com +M Add +M CEN

[0041]

[0042] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M com The storage resource data used by the comparator module; M Add The storage resource data used by the address generator module; M CEN The storage resource data used by the address enabler module; M cacStorage resource data used by the self-refresh device.

[0043] Furthermore, the algorithm expression corresponding to the third memory error rate algorithm model is:

[0044]

[0045] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M VD Storage resource data used by the data voter module.

[0046] Furthermore, in the case of single particle protection effectiveness when two-way errors occur simultaneously in three ways of the same storage unit, the error rates caused by errors of different modules are obtained respectively.

[0047] Correspondingly, the present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the quantitative evaluation method for single particle upset protection design of block memory as described in any one of the above items are implemented.

[0048] Accordingly, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the quantitative evaluation method for single-particle upset protection design of a block memory as described in any one of the above.

[0049] By adopting the block memory single particle upset protection design quantitative evaluation method described in the present invention, the block memory self-refresh triple-mode redundant single particle protection effectiveness can be quantitatively evaluated, and the probability of failure of the block memory adopting the single particle upset protection measure can be obtained, so that designers can make a trade-off between resource usage and protection effect, effectively improving the efficiency and reliability of the optimized configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic diagram of a flow chart of a quantitative evaluation method for single-particle upset protection design of a block memory provided by an embodiment of the present invention;

[0052] Figure 2 A complete flow chart of a quantitative evaluation method for single-particle upset protection design of a block memory provided by an embodiment of the present invention;

[0053] Figure 3 A schematic diagram of the TMR protection structure of a CLB provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of a TMR protection structure of a BRAM provided in an embodiment of the present invention;

[0055] Figure 5 A diagram of a TMR protection structure of a BRAM provided in an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of the structure of a quantitative evaluation device for single-event upset protection design of a block memory provided by an embodiment of the present invention;

[0057] Figure 7 A schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] The following is a detailed description of an embodiment of the block memory single-particle upset protection design quantitative evaluation method according to the present invention. Figure 1 and Figure 2 As shown, it is a flow chart of a quantitative evaluation method for single-particle upset protection design of a block memory provided by an embodiment of the present invention, and the specific implementation process includes the following steps:

[0060] Step 101: Determine the storage resource data, corresponding refresh cycle and corresponding unit data flip rate of each module in the configurable logic unit and block memory in the SRAM type FPGA. The storage resource data includes a first type of storage resource data, a second type of storage resource data and a third type of storage resource data. Specifically, the first type of storage resource data is the storage resource data used by the block memory module in the block memory; the second type of storage resource data is the storage resource data used by the comparator module, the address generator module and the address enabler module in the configurable logic unit; the self-refresher includes the comparator module, the address generator module and the address enabler module; the third type of storage resource data is the storage resource data used by the data voter in the configurable logic unit.

[0061] Step 102: Based on the first type of storage resource data, the refresh cycle, the unit data flip rate and a preset first block memory error rate algorithm model, obtain the error rate caused by the block memory location error.

[0062] Specifically, the first block memory error rate algorithm model is a preset block memory error rate algorithm formula caused by a block memory location error.

[0063] In the embodiment of the present invention, the algorithm expression corresponding to the first block memory error rate algorithm model is:

[0064]

[0065] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M b Storage resource data used by the block memory module.

[0066] Step 103: Based on the second type of storage resource data, the refresh cycle, the unit data flip rate and a preset second block memory error rate algorithm model, obtain the error rate caused by the self-refresh device error.

[0067] Specifically, the second block memory error rate algorithm model is a preset block memory error rate algorithm formula caused by a self-refresh error in the configurable logic unit.

[0068] The algorithm expression corresponding to the second memory error rate algorithm model is:

[0069] M cac =Mcom +M Add +M CEN

[0070]

[0071] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M com The storage resource data used by the comparator module; M Add The storage resource data used by the address generator module; M CEN The storage resource data used by the address enabler module; M cac Storage resource data used by the self-refresh device.

[0072] Step 104: Based on the third type of storage resource data, the refresh cycle, the unit data flip rate and a preset third block memory error rate algorithm model, obtain the error rate caused by the voter error.

[0073] Specifically, the third block memory error rate algorithm model is a preset block memory error rate algorithm formula caused by a voter error in the configurable logic unit.

[0074] The algorithm expression corresponding to the third memory error rate algorithm model is:

[0075]

[0076] Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; b is the unit data flip rate corresponding to the block memory; t c Refresh cycle corresponding to configurable logic unit; t b The refresh cycle corresponding to the block memory; M VD Storage resource data used by the data voter module.

[0077] Step 105: Obtain a quantitative evaluation result of the block memory error rate based on the error rate caused by the block memory part error, the error rate caused by the self-refresh error, and the error rate caused by the voter error.

[0078] like Figure 4 As shown in the figure, the output error of BRAM is defined as two or more errors in the three-way A port output data, and its error rate is recorded as λ BRAM .

[0079] In a complete embodiment, it is first necessary to determine the storage resources used by each module. As shown in Table 1, since each part uses TMR, Table 1 shows the resources used by a single module, and the total module resources should be multiplied by 3. And determine the refresh cycle corresponding to each part, the dynamic partial reconfiguration refresh cycle t of CLB c and the refresh cycle t of BRAM b Among them, the TMR protection structure of CLB is as follows Figure 3 shown.

[0080]

[0081] Table 1 Resource situation of each part

[0082] Further, the single-bit flip rate, the evaluation results of the single-bit on-track SEU flip rate of the CLB part and the BRAM part are determined as λ c and λ b The single-bit on-track SEU rate of CLB and BRAM in current SRAM-based FPGAs is usually around 10 -7 h -1 Up to 4*10 -11 h -1 The refresh cycle is from a few seconds to a few minutes, usually not more than 1 hour, so the condition defined in this application based on the actual situation is λ c ×t c <<1 and λ b ×t b <<1.

[0083] It should be noted that due to λ c ×t c <<1 and λ b ×t b <<1, the single point failure of both CLB and BRAM has been eliminated during the refresh cycle, and the probability of causing BRAM errors is much smaller, and the impact of single particle effects can be ignored. In addition, in this protection structure, since Address_CNTR has a voting function, the logic path COMPARATOR, Address_CNTR, and CEN_BSCNTR structures can be combined into 1 module recorded as CAC, called a self-refresher. Due to the protection of TMR, the situation where two faults occur simultaneously in different paths and modules of CAC, Data_Voter and BRAM in CLB can also be eliminated, and the impact of single particle effects can be ignored. In addition, since the probability of single particle flips occurring in more than two parts at the same time is particularly small, only the single particle protection performance of two errors occurring simultaneously in three paths of the same module is evaluated.

[0084] During the BRAM refresh cycle tb In the case of more than two SEUs occurring in the three same address storage bits of the BRAM corresponding to the TMR, the refresher can no longer correct the error. Since the single point failure has been eliminated, the failure caused by the second-order effect is considered, and the third-order effect is much smaller than the second-order effect. The BRAM error rate caused by the error in this part is as shown in formula (1).

[0085]

[0086] It can be seen that the total BRAM error rate is proportional to the refresh time. If the circuit only uses TMR protection for BRAM without using self-refresh circuit, t b It can be considered as the life cycle of data, that is, the storage time of data in BRAM. If the data is loaded into BRAM at the beginning and is not rewritten until the FPGA is powered off and restarted, the refresh time at this time is the interval between two power-ons. For missions that run continuously on orbit, the longest power-on and power-off time can reach several years, that is, 104h, which is comparable to the refresh cycle of 10 seconds. -3 h, the difference between the two can be more than 7 orders of magnitude. Among them, the detailed TMR protection structure of BRAM is as follows Figure 5 shown.

[0087] During the CLB refresh cycle t c In the case of TMR, two CACs corresponding to the TMR have SEUs, and the refresher can no longer correct the error. Since the single point failure has been eliminated, the failure caused by the second-order effect is considered, and the third-order effect is much smaller than the second-order effect. The BRAM error rate caused by the error in this part is as shown in formula (2).

[0088] M cac =M com +M Add +M CEN

[0089]

[0090] During the CLB refresh cycle t c In the case of TMR, two paths of Data_Voter have SEU, and the refresher can no longer correct the error. Since the single point failure has been eliminated, the failure caused by the second-order effect is considered, and the third-order effect is much smaller than the second-order effect. The BRAM error rate caused by the error in this part is as shown in formula (3).

[0091]

[0092] Based on the above analysis, the total BRAM error rate is as shown in formula (4). The quantitative evaluation result of the block memory error rate can be obtained by calculating using formula (4).

[0093] λBRAM =λ BRAM-B +λ BRAM-cac +λ BRAM-VD (4)

[0094] By adopting the quantitative evaluation method for the single particle upset protection design of the block memory described in the embodiment of the present invention, the effectiveness of the single particle protection of the self-refresh triple-mode redundant block memory can be quantitatively evaluated, and the probability of failure of the block memory adopting the single particle upset protection measure can be obtained, so that designers can make a trade-off between resource usage and protection effect, effectively improving the efficiency and reliability of the optimized configuration.

[0095] Corresponding to the above-mentioned block memory single particle upset protection design quantitative evaluation method, the present invention also provides a block memory single particle upset protection design quantitative evaluation device. Since the embodiment of the device is similar to the above-mentioned method embodiment, the description is relatively simple. For relevant parts, please refer to the description of the above-mentioned method embodiment. The embodiment of the block memory single particle upset protection design quantitative evaluation device described below is only illustrative. Please refer to Figure 6 As shown, it is a structural schematic diagram of a block memory single-particle upset protection design quantitative evaluation device provided by an embodiment of the present invention.

[0096] The block memory single-particle upset protection design quantitative evaluation device described in the present invention specifically includes the following parts:

[0097] The target data determination unit 601 is used to determine the storage resource data, the corresponding refresh cycle and the corresponding unit data flip rate of each module in the configurable logic unit and the block memory in the SRAM type FPGA; wherein the storage resource data includes the first type of storage resource data, the second type of storage resource data and the third type of storage resource data;

[0098] A first error rate analysis unit 602, configured to obtain an error rate caused by a location error of the block memory based on the first type of storage resource data, the refresh cycle, the unit data flip rate, and a preset first block memory error rate algorithm model;

[0099] A second error rate analysis unit 603, configured to obtain an error rate caused by the self-refresh device error based on the second type of storage resource data, the refresh cycle, the unit data flip rate, and a preset second block memory error rate algorithm model;

[0100] A third error rate analysis unit 604, configured to obtain an error rate caused by the voter error based on the third type of storage resource data, the refresh cycle, the unit data flip rate, and a preset third block memory error rate algorithm model;

[0101] The quantitative evaluation unit 605 is used to obtain a quantitative evaluation result of the block memory error rate based on the error rate caused by the block memory part error, the error rate caused by the self-refresh error and the error rate caused by the voter error.

[0102] By using the block memory single particle upset protection design quantitative evaluation device described in the embodiment of the present invention, the block memory self-refresh triple-mode redundant single particle protection effectiveness can be quantitatively evaluated, and the probability of failure of the block memory using single particle upset protection measures can be obtained, so that designers can make a trade-off between resource usage and protection effect, effectively improving the efficiency and reliability of the optimized configuration.

[0103] Corresponding to the above-mentioned block memory single particle upset protection design quantitative evaluation method, the present invention also provides an electronic device. Since the embodiment of the electronic device is similar to the above-mentioned method embodiment, the description is relatively simple. For relevant parts, please refer to the description of the above-mentioned method embodiment. The electronic device described below is only exemplary. Figure 7 , which is a schematic diagram of the physical structure of an electronic device disclosed in an embodiment of the present invention. The electronic device may include: a processor 701, a memory 702 and a communication bus 703, wherein the processor 701 and the memory 702 communicate with each other through the communication bus 703. The processor 701 can call the logic instructions in the memory 702 to execute the quantitative evaluation method of the single-particle upset protection design of the block memory, which includes: determining the storage resource data, the corresponding refresh cycle and the corresponding unit data flip rate of each module in the configurable logic unit and the block memory in the SRAM type FPGA; wherein the storage resource data includes the first type of storage resource data, the second type of storage resource data and the third type of storage resource data; based on the first type of storage resource data, the refresh cycle, the unit data flip rate and the preset first block memory error rate algorithm model, obtaining the error rate caused by the block memory part error; based on the second type of storage resource data, the refresh cycle, the unit data flip rate and the preset second block memory error rate algorithm model, obtaining the error rate caused by the self-refresher error; based on the third type of storage resource data, the refresh cycle, the unit data flip rate and the preset third block memory error rate algorithm model, obtaining the error rate caused by the voter error; based on the error rate caused by the block memory part error, the error rate caused by the self-refresher error and the error rate caused by the voter error, obtaining the block memory error rate quantitative evaluation result.

[0104] In addition, the logic instructions in the above-mentioned memory 702 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0105] On the other hand, an embodiment of the present invention further provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, and when the program instructions are executed by a computer, the computer can execute the block memory single particle upset protection design quantitative evaluation method provided by the above-mentioned method embodiments, the method comprising: determining storage resource data, corresponding refresh cycles, and corresponding unit data flip rates of each module in a configurable logic unit and a block memory in an SRAM-type FPGA; wherein the storage resource data comprises a first category of storage resource data, a second category of storage resource data, and a third category of storage resource data; based on the first category of storage resource data, the The error rate caused by the block memory location error is obtained based on the refresh cycle, the unit data flip rate and the preset first block memory error rate algorithm model; the error rate caused by the self-refresher error is obtained based on the second type of storage resource data, the refresh cycle, the unit data flip rate and the preset second block memory error rate algorithm model; the error rate caused by the voter error is obtained based on the third type of storage resource data, the refresh cycle, the unit data flip rate and the preset third block memory error rate algorithm model; the quantitative evaluation result of the block memory error rate is obtained based on the error rate caused by the block memory location error, the error rate caused by the self-refresher error and the error rate caused by the voter error.

[0106] On the other hand, an embodiment of the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the block memory single particle upset protection design quantitative evaluation method provided in the above-mentioned embodiments, the method comprising: determining storage resource data, corresponding refresh cycles, and corresponding unit data flip rates of each module in a configurable logic unit and a block memory in an SRAM-type FPGA; wherein the storage resource data comprises first-category storage resource data, second-category storage resource data, and third-category storage resource data; based on the first-category storage resource data, the refresh cycle, the unit data flip rate, and a preset The first block memory error rate algorithm model is used to obtain the error rate caused by the block memory location error; based on the second type of storage resource data, the refresh cycle, the unit data flip rate and the preset second block memory error rate algorithm model, the error rate caused by the self-refresher error is obtained; based on the third type of storage resource data, the refresh cycle, the unit data flip rate and the preset third block memory error rate algorithm model, the error rate caused by the voter error is obtained; based on the error rate caused by the block memory location error, the error rate caused by the self-refresher error and the error rate caused by the voter error, a quantitative evaluation result of the block memory error rate is obtained.

[0107] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0108] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quantitative evaluation method for single-event upset protection design of block memory, characterized in that: include: Determine the storage resource data, corresponding refresh cycle and corresponding unit data flip rate of each module in the configurable logic unit and block memory in the SRAM type FPGA; wherein the storage resource data includes first type storage resource data, second type storage resource data and third type storage resource data; Based on the first type of storage resource data, the refresh cycle, the unit data flip rate and a preset first block memory error rate algorithm model, an error rate caused by a location error of the block memory is obtained; The algorithm expression corresponding to the first memory error rate algorithm model is: Among them, λ b is the unit data flip rate corresponding to the block memory; t b The refresh cycle corresponding to the block memory; M b Storage resource data used by the block memory module; Based on the second type of storage resource data, the refresh cycle, the unit data flip rate and a preset second block memory error rate algorithm model, an error rate caused by a self-refresher error is obtained; The algorithm expression corresponding to the second memory error rate algorithm model is: M cac =M com +M Add +M CEN Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; t c Refresh cycle corresponding to configurable logic unit; M com The storage resource data used by the comparator module; M Add The storage resource data used by the address generator module; M CEN The storage resource data used by the address enabler module; M cac Storage resource data used by the self-refresh device; Based on the third type of storage resource data, the refresh cycle, the unit data flip rate and a preset third block memory error rate algorithm model, obtaining an error rate caused by a voter error; The algorithm expression corresponding to the third memory error rate algorithm model is: Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; t c Refresh cycle corresponding to configurable logic unit; M VD Storage resource data used by the data voting module; Based on the error rate caused by the block memory part error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error, a quantitative evaluation result of the block memory error rate is obtained.

2. The block memory single event upset protection design quantitative evaluation method according to claim 1, characterized in that: The first category of storage resource data is the storage resource data used by the block memory module in the block memory; the second category of storage resource data is the storage resource data used by the comparator module, the address generator module, and the address enabler module in the configurable logic unit; the self-refresher includes the comparator module, the address generator module, and the address enabler module; the third category of storage resource data is the storage resource data used by the data voter in the configurable logic unit.

3. The block memory single event upset protection design quantitative evaluation method according to claim 1, characterized in that: In the case of single-particle protection effectiveness when two-way errors occur simultaneously in three ways of the same storage unit, the error rates caused by different module errors are obtained respectively.

4. A quantitative evaluation device for block memory single event upset protection design, characterized in that: include: A target data determination unit, used to determine storage resource data, corresponding refresh cycles, and corresponding unit data flip rates of each module in a configurable logic unit and a block memory in an SRAM-type FPGA; wherein the storage resource data includes first-category storage resource data, second-category storage resource data, and third-category storage resource data; A first error rate analysis unit, configured to obtain an error rate caused by a position error of the block memory based on the first type of storage resource data, the refresh cycle, the unit data flip rate, and a preset first block memory error rate algorithm model; The algorithm expression corresponding to the first memory error rate algorithm model is: Among them, λ b is the unit data flip rate corresponding to the block memory; t b The refresh cycle corresponding to the block memory; M b Storage resource data used by the block memory module; A second error rate analysis unit, configured to obtain an error rate caused by a self-refresher error based on the second type of storage resource data, the refresh cycle, the unit data flip rate, and a preset second block memory error rate algorithm model; The algorithm expression corresponding to the second memory error rate algorithm model is: M cac =M com +M Add +M CEN Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; t c Refresh cycle corresponding to configurable logic unit; M com The storage resource data used by the comparator module; M Add The storage resource data used by the address generator module; M CEN The storage resource data used by the address enabler module; M cac Storage resource data used by the self-refresh device; A third error rate analysis unit, configured to obtain an error rate caused by a voter error based on the third type of storage resource data, the refresh cycle, the unit data flip rate, and a preset third block memory error rate algorithm model; The algorithm expression corresponding to the third memory error rate algorithm model is: Among them, λ c is the unit data flip rate corresponding to the configurable logic unit; t c Refresh cycle corresponding to configurable logic unit; M VD Storage resource data used by the data voting module; The quantitative evaluation unit is used to obtain a quantitative evaluation result of the block memory error rate based on the error rate caused by the block memory part error, the error rate caused by the self-refresh error and the error rate caused by the voter error.

5. The block memory single event upset protection design quantitative evaluation device according to claim 4, characterized in that: The first category of storage resource data is the storage resource data used by the block memory module in the block memory; the second category of storage resource data is the storage resource data used by the comparator module, the address generator module, and the address enabler module in the configurable logic unit; the self-refresher includes the comparator module, the address generator module, and the address enabler module; the third category of storage resource data is the storage resource data used by the data voter in the configurable logic unit.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the block memory single-particle upset protection design quantitative evaluation method as described in any one of claims 1 to 3 are implemented.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the quantitative evaluation method for single-particle upset protection design of a block memory as described in any one of claims 1 to 3 are implemented.

Images