Packaging structure and manufacturing method thereof

Abstract

A packaging structure includes a circuit redistribution structure, a chip, an internal conductive strengthening element and a protective layer. The circuit redistribution structure includes a first circuit layer and a second circuit layer arranged on the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is arranged on the circuit redistribution structure and electrically connected to the second circuit layer. The internal conductive strengthening element is arranged on the circuit redistribution structure. The internal conductive strengthening element has a Young's modulus of 30 to 200 GPa. The protective layer covers the chip and the side walls of the opening of the internal conductive strengthening element. The packaging structure disclosed herein has sufficient mechanical strength and is not prone to warping.

Description

Technical Field

[0001] The invention relates to a packaging structure and a manufacturing method of the packaging structure. Background Art

[0002] Traditionally, a chip packaging structure includes a substrate, a chip on the substrate, and a packaging material layer covering the chip. Due to the large differences in thermal expansion coefficients among the substrate, the chip, and the packaging material layer, when performing a thermal manufacturing process to form the chip and the packaging material layer on the substrate, the chip packaging structure often warps severely. Therefore, the yield rate of the chip packaging structure mounted on a printed circuit board is reduced.

[0003] On the other hand, when a package-on-package (POP) structure is formed in which one package structure is formed on another package structure, the warping phenomenon also causes difficulties in the manufacturing process. Summary of the invention

[0004] Some embodiments of the present invention provide a packaging structure, including a circuit redistribution structure, a chip, at least one internal conductive strengthening element, and a first protective layer. The circuit redistribution structure includes a first circuit layer and a second circuit layer arranged on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer. The chip is arranged on the circuit redistribution structure and electrically connected to the second circuit layer. The internal conductive strengthening element is arranged on the circuit redistribution structure. The internal conductive strengthening element includes a strengthening layer and a conductive connector. The strengthening layer has a Young's modulus of 30 to 200 GPa, and the strengthening layer has a through hole. The conductive connector is arranged in the through hole. The top and bottom of the conductive connector are exposed outside the strengthening layer and are electrically connected to the second circuit layer. The first protective layer covers the chip.

[0005] In some embodiments, the first protection layer covers the sidewalls of the opening of the inner conductive reinforcement element.

[0006] In some embodiments, an inner conductive strengthening element surrounds the wafer.

[0007] In some embodiments, the strengthening layer includes, but is not limited to, bismaleimide triazine resin, epoxy resin, glass, or ceramic.

[0008] In some embodiments, the upper surface of the inner conductive reinforcement element and the upper surface of the first protection layer are coplanar.

[0009] In some embodiments, the package structure further includes a conductive member disposed at the bottom of the conductive connecting member and electrically connected to the second circuit layer.

[0010] In some embodiments, the package structure further includes an electronic component disposed on the first protection layer and electrically connected to the top of the conductive connection member.

[0011] In some embodiments, the package structure further includes a substrate structure and a second protective layer. The substrate structure is disposed between the first protective layer and the electronic component, and the electronic component is electrically connected to the top of the conductive connector through the substrate structure. The second protective layer covers the electronic component.

[0012] In some embodiments, the package structure further includes a first protection layer filling a gap between the chip and the second redistribution layer.

[0013] In some embodiments, the first protection layer fills a gap between a bottom surface of a portion of the inner conductive reinforcement element and the second redistribution layer.

[0014] Some embodiments of the present invention further provide a method for manufacturing a packaging structure, comprising the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, and the first circuit layer is electrically connected to the second circuit layer; (ii) forming at least one internal conductive strengthening element on the circuit redistribution structure, wherein the internal conductive strengthening element includes: a strengthening layer having a Young's modulus of 30 to 200 GPa, wherein the strengthening layer has a through hole; and a conductive connector disposed in the through hole, wherein the top and bottom of the conductive connector are exposed outside the strengthening layer and are electrically connected to the second circuit layer; (iii) disposing a chip on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; and (iv) forming a first protective layer to cover the chip and the internal conductive strengthening element.

[0015] In some embodiments, operation (ii) includes the following steps: (a) providing a substrate, wherein the substrate has a Young's modulus of 30 to 200 GPa; (b) performing a drilling manufacturing process on the substrate to form a strengthening layer having through holes; (c) forming a conductive connector in the through hole to form an internal conductive strengthening element; and (d) setting the internal conductive strengthening element on the line redistribution structure.

[0016] In some embodiments, the step (ii) of forming an internal conductive strengthening element on the circuit redistribution structure includes forming a conductive element at the bottom of the conductive connecting element and electrically connecting the conductive element to the second circuit layer.

[0017] In some embodiments, the manufacturing method further comprises (v) disposing an electronic component on the first protection layer, wherein the electronic component is electrically connected to the top of the conductive connecting element.

[0018] In some embodiments, in operation (v), the electronic component is disposed on the substrate structure and covered by the second protection layer, and the electronic component is electrically connected to the top of the conductive connection member through the substrate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The various aspects of the present invention will be most easily understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale in accordance with industry standard operating procedures. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0020] Figure 1 It is a schematic cross-sectional view of a packaging structure according to a first embodiment of the present invention.

[0021] Figure 2 It is a schematic top view of a packaging structure according to a first embodiment of the present invention.

[0022] Figure 3 It is a schematic cross-sectional view of a packaging structure according to a second embodiment of the present invention.

[0023] Figures 4 to 12 Schematic cross-sectional views of various stages of a method for manufacturing a packaging structure according to a first embodiment of the present invention.

[0024]

Main component symbol description

[0025] 10, 10': Packaging structure 100: Line redistribution structure

[0026] 110: first circuit redistribution layer 111: first circuit layer

[0027] 112: first insulating layer 112a: via hole

[0028] 113: first conductive contact 120: second circuit redistribution layer

[0029] 121: second circuit layer 122: second insulation layer

[0030] 122a: through hole 123: second conductive contact

[0031] 130: Third circuit redistribution layer 131: Third circuit layer

[0032] 132: third insulating layer 132a: via hole

[0033] 133: third conductive contact 140: conductive pad

[0034] 200: Wafer 210: Metal bump

[0035] 220: welding material 300: internal conductive strengthening element

[0036] 310: Strengthening layer 310a: Through hole

[0037] 320: Conductive connector 330: Conductive member

[0038] 400: first protective layer 410: second protective layer

[0039] 500: Solder ball 510: Solder material

[0040] 600: Electronic components 601: Wires

[0041] 700: substrate structure 710: first conductive pad

[0042] 720: second conductive pad S: substrate

[0043] D1: Horizontal distance DETAILED DESCRIPTION

[0044] In order to make the description of the present invention more detailed and complete, the following is an illustrative description of the implementation and specific embodiments of the present invention; however, this is not the only form of implementing or using the specific embodiments of the present invention. The various embodiments disclosed below can be combined or replaced with each other in beneficial situations, and other embodiments can be added to one embodiment without further recording or explanation. In the following description, many specific details will be described in detail so that the reader can fully understand the following embodiments. However, the embodiments of the present invention can be practiced without such specific details.

[0045] Furthermore, spatially relative terms, such as "below", "under", "above", "on", etc., are used to facilitate the description of the relative relationship between one element or feature and another element or feature. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped 180 degrees up and down, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in this article should also be interpreted in the same way.

[0046] Please refer to Figure 1 , Figure 1 1 is a cross-sectional view of a package structure 10 according to a first embodiment of the present invention. The package structure 10 includes a circuit redistribution structure 100, a chip 200, an internal conductive strengthening element 300, a first protection layer 400, and solder balls 500.

[0047] In some embodiments, the line redistribution structure 100 includes, but is not limited to, one or more line redistribution layers, depending on actual design and requirements.

[0048] In one embodiment, the line redistribution structure 100 includes three layers of line redistribution layers. The line redistribution structure 100 includes a first line redistribution layer 110, a second line redistribution layer 120, a third line redistribution layer 130, and a conductive pad 140. Specifically, the first line redistribution layer 110 includes a first line layer 111, a first insulating layer 112, and a first conductive contact 113. In some embodiments, the first line layer 111 and the first conductive contact 113 include any conductive material, such as metals such as copper, nickel or silver. In some embodiments, the line width and line spacing of the first line layer 111 are less than 8 microns, such as 7 microns, 6 microns, 5 microns, 4 microns, 3 microns, 2 microns, 1 micron or 0.5 microns. The first insulating layer 112 covers the first line layer 111, and the first insulating layer 112 has a via 112a. In some embodiments, the first insulating layer 112 includes a photosensitive dielectric material. The via hole 112 a exposes a portion of the first circuit layer 111 , and the first conductive contact 113 is conformally formed in the via hole 112 a , so that the first conductive contact 113 contacts the first circuit layer 111 .

[0049] The second circuit redistribution layer 120 is disposed on the first circuit redistribution layer 110. Specifically, the second circuit redistribution layer 120 includes a second circuit layer 121, a second insulating layer 122, and a second conductive contact 123. The second circuit layer 121 contacts the first conductive contact 113, so that the second circuit layer 121 is electrically connected to the first circuit layer 111. In some embodiments, the second circuit layer 121 and the second conductive contact 123 include any conductive material, such as metals such as copper, nickel or silver. In some embodiments, the line width and line spacing of the second circuit layer 121 are less than 8 microns, such as 7 microns, 6 microns, 5 microns, 4 microns, 3 microns, 2 microns, 1 micron or 0.5 microns. The second insulating layer 122 covers the second circuit layer 121, and the second insulating layer 122 has a via 122a. In some embodiments, the second insulating layer 122 includes a photosensitive dielectric material. The via hole 122 a exposes a portion of the second circuit layer 121 , and the second conductive contact 123 is conformally formed in the via hole 122 a , so that the second conductive contact 123 contacts the second circuit layer 121 .

[0050] The third line redistribution layer 130 is disposed on the second line redistribution layer 120. Specifically, the third line redistribution layer 130 includes a third line layer 131, a third insulating layer 132, and a third conductive contact 133. The third line layer 131 contacts the second conductive contact 123, so that the third line layer 131 is electrically connected to the second line layer 121. In some embodiments, the third line layer 131 and the third conductive contact 133 include any conductive material, such as metals such as copper, nickel or silver. In some embodiments, the line width and line spacing of the third line layer 131 are less than 8 microns, such as 7 microns, 6 microns, 5 microns, 4 microns, 3 microns, 2 microns, 1 micron or 0.5 microns. The third insulating layer 132 covers the third line layer 131, and the third insulating layer 132 has a via 132a. In some embodiments, the third insulating layer 132 includes a photosensitive dielectric material. The via hole 132 a exposes a portion of the third circuit layer 131 , and the third conductive contact 133 is conformally formed in the via hole 132 a , so that the third conductive contact 133 contacts the third circuit layer 131 .

[0051] The conductive pad 140 contacts the third conductive contact 133, so that the conductive pad 140 is electrically connected to the third wiring layer 131. In some embodiments, the conductive pad 140 includes any conductive material, such as metals such as copper, nickel, or silver.

[0052] The chip 200 is disposed on the circuit redistribution structure 100 and is electrically connected to the third circuit layer 131. Specifically, a plurality of metal bumps 210 (such as chip pins) are disposed on the lower surface of the chip 200, and the metal bumps 210 are bonded to the conductive pads 140 and the third conductive contact members 133 via welding materials 220, so that the chip 200 is electrically connected to the third circuit layer 131.

[0053] The internal conductive reinforcement element 300 is disposed on the circuit redistribution structure 100, and the internal conductive reinforcement element 300 includes a reinforcement layer 310 and a conductive connector 320. In some embodiments, the conductive connector 320 includes any conductive material, such as metals such as copper, nickel or silver. Specifically, the reinforcement layer 310 has a through hole 310a, and the conductive connector 320 is disposed in the through hole 310a. More specifically, the top and bottom of the conductive connector 320 are exposed outside the reinforcement layer 310. In some embodiments, the conductive connector 320 is electrically connected to the third circuit layer 131 via the conductive member 330. In one embodiment, the conductive member includes a solder bump, which is disposed at the bottom of the conductive connector 320, so that the conductive connector 320 is electrically connected to the third circuit layer 131. More specifically, the solder bump can be a solder ball, and its material includes lead, tin, silver, copper, bismuth, antimony, zinc or other welding metals, but is not limited thereto. In some embodiments, the internal conductive reinforcement element 300 further includes two protective layers located on the upper and lower surfaces of the reinforcement layer 310, and the material thereof may be a solder mask material or a resin material, such as epoxy resin. The protective layer may be formed by lamination, printing or coating, for example. More specifically, the top of the conductive connector 320 is exposed outside the upper protective layer and is coplanar with the protective layer, and the conductive member 330 bonded to the bottom of the conductive connector 320 protrudes from the lower protective layer. It should be understood that the reinforcement layer 310 has a Young's modulus of 30 to 200 GPa, such as 100, 150 or 200 GPa. As mentioned above, the conventional chip packaging structure often produces severe warping due to the thermal manufacturing process. In particular, when the size of the chip packaging structure reaches a certain range or more, the warping phenomenon is particularly serious, for example, when the length of the chip packaging structure is more than 15 mm and the width is more than 15 mm. However, by providing the reinforcement layer 310, the packaging structure 10 of the present invention is not prone to warping.

[0054] In detail, the strengthening layer 310 has a Young's modulus of 30 to 200 GPa, thereby providing the package structure 10 with sufficient mechanical strength. Accordingly, even if the thermal expansion coefficients of the various component materials in the package structure 10 are very different, warping is not likely to occur. In some embodiments, the strengthening layer 310 includes but is not limited to bismaleimide-tirazine (BT) resin, epoxy resin, solder paste or copper paste. Preferably, in some embodiments, the strengthening layer 310 has a horizontal distance D1 from the chip 200, and the horizontal distance D1 is 50 to 1000 microns.

[0055] In another embodiment, the circuit redistribution structure 100 includes two circuit redistribution layers. For example, the circuit redistribution structure 100 includes a first circuit redistribution layer 110 and a third circuit redistribution layer 130. The packaging structure 10 with two or three circuit redistribution layers is electrically connected to the chip 20 by the topmost circuit redistribution layer, and the internal conductive reinforcement element 300 is disposed on the topmost circuit redistribution layer. The other components are the same as those in the implementation of the three-layer circuit redistribution layer, so they are not repeated here.

[0056] Figure 2 FIG. 1 is a top view of a packaging structure 10 according to an embodiment of the present invention. Figure 2 As shown, the conductive connectors 320 of the inner conductive reinforcement element 300 are disposed on four sides adjacent to the package structure 10 , and the exposed portion is the top of the conductive connector 320 .

[0057] Back to Figure 1 , the first protective layer 400 covers the sidewalls and part of the bottom surface of the opening of the chip 200 and the internal conductive strengthening element 300, and fills the gap between the chip 200 and the third circuit redistribution layer 130, and the gap between part of the bottom surface of the internal conductive strengthening element 300 and the third circuit redistribution layer 130. Specifically, the upper surface of the internal conductive strengthening element 300 and the upper surface of the first protective layer 400 are coplanar. The first protective layer 400 can protect the metal bumps 210 of the chip 200, the bonding between the welding material 220 and the conductive pad 140, thereby preventing peeling from occurring. On the other hand, the first protective layer 400 can also block moisture and prevent oxidation of the metal bumps 210, the welding material 220, and the conductive pad 140. In some embodiments, the first protective layer 400 includes a resin.

[0058] The solder ball 500 is disposed under the circuit redistribution structure 100. Specifically, the solder ball 500 contacts the first circuit layer 111, so that the solder ball 500 is electrically connected to the first circuit layer 111. In some embodiments, the solder ball 500 includes lead, tin, silver, copper, bismuth, antimony, zinc or other welding metals, but is not limited thereto.

[0059] Please refer to Figure 3 , Figure 3 FIG. 1 is a cross-sectional view of a package structure 10′ according to a second embodiment of the present invention. The package structure 10′ includes a circuit redistribution structure 100, a chip 200, an internal conductive strengthening element 300, a first protective layer 400, a solder ball 500, and an electronic component 600. For details of the circuit redistribution structure 100, the chip 200, the internal conductive strengthening element 300, the first protective layer 400, and the solder ball 500, please refer to FIG. Figure 1 The description of the corresponding relevant paragraphs will not be repeated here.

[0060] The electronic component 600 is disposed on the first protective layer 400 and electrically connected to the top of the conductive connection member 320. Specifically, the electronic component 600 is disposed on the substrate structure 700 and is covered by the second protective layer 410. The substrate structure 700 has a first conductive pad 710, a second conductive pad 720 and an internal circuit, and the internal circuit electrically connects the first conductive pad 710 and the second conductive pad 720. Figure 3 As shown, the electronic component 600 is electrically connected to the first conductive pad 710 through the wire 601. In addition, the second conductive pad 720 is electrically connected to the top of the conductive connector 320 through the welding material 510. In some embodiments, the welding material 510 includes lead, tin, silver, copper, bismuth, antimony, zinc or other welding metals, but is not limited thereto.

[0061] The second protective layer 410 can block moisture and prevent oxidation of the conductive wire 601 and the first conductive pad 710. In some embodiments, the second protective layer 410 includes resin. In some embodiments, the electronic component 600 is a memory.

[0062] The invention also provides a method for manufacturing a packaging structure. Figures 4 to 12 Schematic cross-sectional views of various stages of a method for manufacturing a package structure 10 according to a first embodiment of the present invention.

[0063] like Figure 4 As shown, a release film is formed on the substrate S, and a first circuit layer 111 is formed on the release film. For example, a conductive material is formed on the release film, and the conductive material is patterned to form the first circuit layer 111. In some embodiments, the method of forming the conductive material includes electroplating, chemical vapor deposition, physical vapor deposition, etc., but is not limited thereto.

[0064] Next, if Figure 5 As shown, a first insulating layer 112 is formed to cover the first wiring layer 111, and the first insulating layer 112 includes a via 112a that exposes a portion of the first wiring layer 111. For example, a dielectric material is formed on the first wiring layer 111, and the dielectric material is patterned to form the via 112a. In some embodiments, the method of forming the dielectric material includes chemical vapor deposition, physical vapor deposition, etc., but is not limited thereto. In some embodiments, the method of patterning the conductive material and the dielectric material includes depositing a photoresist on the layer to be patterned, and forming a patterned photoresist layer through exposure and development. Then, the patterned photoresist layer is used as an etching mask to etch the layer to be patterned. Finally, the patterned photoresist layer is removed. Alternatively, in an embodiment where the dielectric material is a photosensitive dielectric material, a portion of the photosensitive dielectric material can be removed by exposure and development to complete the patterning.

[0065] Next, the second circuit layer 121 is formed on the first insulating layer 112, and the first conductive contact 113 is conformally formed in the via hole 112a. For example, a conductive material is formed on the first insulating layer 112, and conformally formed in the via hole 112a. Next, the conductive material is patterned to form the second circuit layer 121 and the first conductive contact 113.

[0066] Next, if Figure 6 As shown, the second insulating layer 122 is formed to cover the second wiring layer 121, and the second insulating layer 122 includes a via hole 122a exposing a portion of the second wiring layer 121. For example, a dielectric material is formed on the second wiring layer 121, and the dielectric material is patterned to form the via hole 122a.

[0067] Next, a third wiring layer 131 is formed on the second insulating layer 122, and a second conductive contact 123 is conformally formed in the via hole 122a. For example, a conductive material is formed on the second insulating layer 122, and conformally formed in the via hole 122a. Next, the conductive material is patterned to form the third wiring layer 131 and the second conductive contact 123.

[0068] Next, if Figure 7 As shown, a third insulating layer 132 is formed to cover the third wiring layer 131, and the third insulating layer 132 includes a via hole 132a exposing a portion of the third wiring layer 131. For example, a dielectric material is formed on the third wiring layer 131, and the dielectric material is patterned to form the via hole 132a.

[0069] Next, a conductive pad 140 is formed on the third insulating layer 132, and a third conductive contact 133 is conformally formed in the via 132a. For example, a conductive material is formed on the third insulating layer 132, and conformally formed in the via 132a. Next, the conductive material is patterned to form the conductive pad 140 and the third conductive contact 133. Thus, a line redistribution structure 100 is formed on the substrate S. It is worth mentioning that the conductive pad 140 has a recess, which provides a specific technical effect. In detail, when the conductive connector 320 is joined to the conductive pad 140, the bottom of the conductive connector 320 is aligned with and squeezed by the conductive member 330 to the inclined surface of the recess of the conductive pad 140.

[0070] Next, if Figure 8 and Fig. 9 As shown, an internal conductive reinforcement element 300 is formed on the circuit redistribution structure 100. For example, a plurality of conductive elements 330 on the lower surface of the internal conductive reinforcement element 300 are bonded to the conductive pad 140, and the conductive elements 330 are used to attach the internal conductive reinforcement element 300 to the third circuit redistribution layer 130.

[0071] Then, if Figure 8 and Fig. 9 As shown, a chip 200 is disposed on the circuit redistribution structure 100. For example, a plurality of metal bumps 210 (eg, chip pins) on the bottom surface of the chip 200 are bonded to the conductive pads 140 using a soldering material 220.

[0072] Next, if Fig.10 As shown, a first protection layer 400 is formed to cover the chip 200 and the internal conductive reinforcement element 300 , and fill the gap between the chip 200 and the third redistribution layer 130 .

[0073] Next, a chemical mechanical polishing (CMP) process is used to remove the top of the first protective layer 400, thereby forming a Fig.11 The first protective layer 400 is shown to expose the upper surface of the internal conductive reinforcement element 300. It should be noted that removing the top of the first protective layer 400 provides a specific technical effect. In detail, the thermal expansion coefficient of the material of the first protective layer 400 is usually greatly different from the thermal expansion coefficient of other components, so an overly thick first protective layer 400 is likely to cause warping of the package structure. By removing the top of the first protective layer 400, the warping phenomenon of the package structure can be improved.

[0074] Next, the release film and the substrate S are peeled off to expose the first circuit layer 111. Fig.12 As shown, a solder ball 500 contacting the first wiring layer 111 is formed, thereby forming a package structure 10 .

[0075] The manufacturing method of the packaging structure 10' according to the second embodiment of the present invention is as follows: Figures 4 to 11 The cross-sectional diagrams of the various stages are shown. Figure 3 As shown, the electronic component 600 is disposed on the first protective layer 400, and the electronic component 600 is electrically connected to the top of the conductive connection member 320. Specifically, the second conductive pad 720 is bonded to the top of the conductive connection member 320 using the welding material 510. The electronic component 600 is electrically connected to the first conductive pad 710 through the wire 601, and the first conductive pad 710 is electrically connected to the second conductive pad 720 through the internal line. Therefore, the electronic component 600 is electrically connected to the top of the conductive connection member 320.

[0076] Next, the release film and the substrate S are peeled off to expose the first circuit layer 111. Then, solder balls 500 contacting the first circuit layer 111 are formed, thereby forming a Figure 3 The package structure 10 ′ is shown.

[0077] As can be seen from the above-mentioned embodiments of the invention, the packaging structure in some embodiments of the present invention has sufficient mechanical strength. Therefore, even if the thermal expansion coefficients of the various component materials in the packaging structure are very different, warping is not likely to occur. In addition, since the packaging structure is not likely to warp, it is suitable to set another packaging structure on this packaging structure to form a stacked packaging structure.

[0078] Although the present invention has been disclosed above with embodiments, other embodiments are also possible. Therefore, the spirit and scope of the claims are not limited to the description contained in the embodiments herein.

[0079] Anyone skilled in the art will appreciate that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the patent application.

Claims

1. A packaging structure, characterized in that: include: A circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; A chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer; as well as At least one internal conductive strengthening element is disposed on the line redistribution structure, wherein the internal conductive strengthening element comprises: A strengthening layer having a Young's modulus of 30 to 200 GPa, wherein the strengthening layer has through holes; A conductive connecting member is disposed in the through hole, wherein the top and bottom of the conductive connecting member are exposed outside the strengthening layer and are electrically connected to the second circuit layer; a first protective layer covering the sidewalls and a portion of the bottom surface of the opening of the chip and the internal conductive strengthening element, and filling the gap between the chip and the third circuit redistribution layer, and the gap between a portion of the bottom surface of the internal conductive strengthening element and the third circuit redistribution layer, wherein the first protective layer comprises a resin; and The two protective layers are respectively located on the upper surface and the lower surface of the strengthening layer, and the material of the two protective layers is solder-proof material.

2. The packaging structure according to claim 1, characterized in that: The strengthening layer material includes bismaleimide triazine resin, epoxy resin, glass or ceramic.

3. The packaging structure according to claim 1, characterized in that: The upper surface of the inner conductive strengthening element and the upper surface of the first protection layer are coplanar.

4. The packaging structure according to claim 1, characterized in that: It also includes a conductive element, which is disposed on the bottom of the conductive connecting element and is electrically connected to the second circuit layer.

5. The packaging structure according to claim 1, characterized in that: It further comprises an electronic element which is disposed on the first protection layer and electrically connected to the top of the conductive connecting member.

6. The packaging structure according to claim 5, characterized in that: Further including: A substrate structure is disposed between the first protection layer and the electronic component, and the electronic component is electrically connected to the top of the conductive connecting member through the substrate structure; as well as The second protective layer covers the electronic component.

7. A method for manufacturing a packaging structure, characterized in that: The following operations are included: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure comprises a first circuit layer and a second circuit layer disposed on the first circuit layer, and the first circuit layer is electrically connected to the second circuit layer; (ii) forming at least one internal conductive strengthening element on the line redistribution structure, wherein the internal conductive strengthening element comprises: A strengthening layer having a Young's modulus of 30 to 200 GPa, wherein the strengthening layer has through holes; Two protective layers, respectively located on the upper surface and the lower surface of the strengthening layer, the two protective layers are made of solder-resistant material; and A conductive connecting member is disposed in the through hole, wherein the top and bottom of the conductive connecting member are exposed outside the strengthening layer and are electrically connected to the second circuit layer; (iii) disposing a chip on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; and (iv) forming a first protective layer to cover the side walls and a portion of the bottom surface of the opening of the chip and the internal conductive reinforcement element, and to fill the gap between the chip and the third circuit redistribution layer, and the gap between a portion of the bottom surface of the internal conductive reinforcement element and the third circuit redistribution layer, wherein the first protective layer comprises a resin.

8. The method for manufacturing a packaging structure according to claim 7, characterized in that: Wherein operation (ii) comprises the following steps: (a) providing a substrate, wherein the substrate has a Young's modulus of 30 to 200 GPa; (b) performing a drilling process on the substrate to form the strengthening layer having the through hole; (c) forming the conductive connection member in the through hole to form an inner conductive strengthening element; and (d) Disposing the internal conductive reinforcement element on the line redistribution structure.

9. The method for manufacturing a packaging structure according to claim 7, wherein: Operation (ii) includes forming a conductive element at the bottom of the conductive connecting element and electrically connecting the second circuit layer.

10. The method for manufacturing a packaging structure according to claim 7, wherein: The method further comprises an operation (v) of disposing an electronic component on the first protection layer, wherein the electronic component is electrically connected to the top of the conductive connecting member.

11. The method for manufacturing a packaging structure according to claim 10, wherein: In operation (v), the electronic component is disposed on the substrate structure and covered by the second protection layer, and the electronic component is electrically connected to the top of the conductive connecting member through the substrate structure.

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