semiconductor devices

Abstract

A method comprising: forming in situ on a supporting substrate: a first metal layer; a light absorbing layer behind the first metal layer; a conductor pattern behind the light absorbing layer; and a semiconductor layer behind the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern, the semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light absorbing layer using the resist mask and the conductor pattern so as to selectively retain the light absorbing layer in an area occupied by at least one of the resist mask and the conductor pattern.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Some semiconductor materials are sensitive to white light, and the design of semiconductor devices including such materials may involve incorporating elements within the device to protect the semiconductor channel from the effects of white light.

[0003] An array of semiconductor devices can be defined by a stack of conductor, semiconductor, and insulator layers on a supporting substrate, and a technique for protecting a semiconductor channel from white light involves including a patterned metal layer within the stack between the supporting substrate and the semiconductor layer, the primary function of the patterned metal layer being to protect the semiconductor channel by reflecting white light incident on the supporting substrate from the opposite side of the stack of layers.

[0004] The inventors of the present application have conducted further research on protecting semiconductor channels from white light. Summary of the Invention

[0005] A method is thus provided, comprising: forming in situ on a supporting substrate: a first metal layer; a light absorbing layer behind the first metal layer; a conductor pattern behind the light absorbing layer; and a semiconductor layer behind the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern, the semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light absorbing layer using the resist mask and the conductor pattern so as to selectively retain the light absorbing layer in the area occupied by at least one of the resist mask and the conductor pattern.

[0006] According to one embodiment, the light absorbing layer exhibits a white light optical density of at least about 1 (in a direction substantially perpendicular to the plane of the support substrate) and a white light total reflectivity of no greater than about 10%.

[0007] According to one embodiment, the light absorbing layer comprises an insulator material, preferably having a sheet resistance greater than 1 MOhm / square.

[0008] According to one embodiment, the light absorbing layer is separated from the semiconductor layer by a distance of no more than about 500 nm (in a direction substantially perpendicular to the plane of the support substrate).

[0009] According to one embodiment, the light absorbing layer interfaces with the one or more semiconductor channels.

[0010] According to one embodiment, the first metal layer is a light-shielding metal pattern.

[0011] According to one embodiment, the one or more semiconductor devices form part of a control component half for a liquid crystal cell comprising liquid crystal material between the control component half and another half comprising a color filter array in a black matrix.

[0012] Also provided is a device comprising: a stack of layers defining one or more semiconductor devices; the stack comprising: a semiconductor layer defining one or more semiconductor channels of the one or more semiconductor devices; a first metal layer below the semiconductor layer and a second metal layer above the semiconductor layer; a conductor pattern between the first metal layer and the semiconductor layer; and a light absorption pattern between the first metal layer and the conductor pattern; the light absorption pattern having an edge aligned with an edge of the conductor pattern.

[0013] According to one embodiment, the light absorption pattern exhibits a white light optical density of at least about 1 (in a direction substantially perpendicular to the plane of the stack) and a total white light reflectance of no more than about 10%.

[0014] According to one embodiment, the light absorption pattern comprises an insulator material, preferably having a sheet resistance greater than 1 MOhm / square.

[0015] According to one embodiment, the light absorption pattern is separated from the semiconductor layer by a distance of no more than about 500 nm (in a direction substantially perpendicular to the plane of the stack).

[0016] According to one embodiment, the light absorption pattern interfaces with the one or more semiconductor channels.

[0017] According to one embodiment, the first metal layer includes a light-shielding metal pattern.

[0018] According to one embodiment, the one or more semiconductor devices form part of a control component half for a liquid crystal cell comprising liquid crystal material between the control component half and another half comprising a color filter array in a black matrix.

[0019] Also provided is a device comprising: a stack of layers defining one or more transistor devices; the stack comprising: a semiconductor layer defining one or more semiconductor channels of the one or more transistor devices; a metal layer on the semiconductor layer; and a light absorption pattern between the semiconductor layer and the metal layer.

[0020] According to one embodiment, the light absorption pattern exhibits a white light optical density of at least about 1 (in a direction substantially perpendicular to the plane of the stack) and a total white light reflectance of no more than about 10%.

[0021] According to one embodiment, the light absorption pattern comprises an insulator material, preferably having a sheet resistance greater than 1 MOhm / square.

[0022] According to an embodiment, the metal layer defines gate traces for the one or more transistor devices.

[0023] According to one embodiment, the one or more transistor devices form part of a control element half-cell for a liquid crystal cell comprising liquid crystal material between the control element half-cell and another half-cell comprising a color filter array in a black matrix.

[0024] Also provided is a device comprising: a stack of layers defining one or more semiconductor devices; wherein the stack comprises: a semiconductor layer defining one or more semiconductor channels of the one or more semiconductor devices; metal layers above and below the semiconductor layers; and one or more patterned light absorbing layers between the metal layers.

[0025] Also provided is a method comprising: forming in situ on a supporting substrate a stack of layers defining one or more semiconductor devices; wherein the stack comprises: a patterned semiconductor layer, the patterned semiconductor layer defining one or more semiconductor channels of the one or more semiconductor devices; metal layers above and below the semiconductor layer; and one or more patterned light absorbing layers between the metal layers; wherein the method comprises patterning at least one of the one or more patterned light absorbing layers using a resist mask, the resist mask also being used to pattern the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Example embodiments are described below in detail by way of example only with reference to the accompanying drawings, in which

[0027] Figures 1 to 11 An example technique according to a first embodiment is shown;

[0028] Figures 12 to 16 An example technique according to the second embodiment is shown; and Figure 17 An example application of a device manufactured using the techniques according to the first and second embodiments is shown. DETAILED DESCRIPTION

[0029] The following describes an example embodiment for fabricating an organic liquid crystal display (OLCD) device that includes an organic transistor device (such as an organic thin film transistor (OTFT) device) for a control component. The OTFT includes an organic semiconductor (such as an organic polymer or small molecule semiconductor) for the semiconductor channel. However, the technology described can also be applied to the fabrication of other types of devices that include photosensitive semiconductors, such as other types of display devices (e.g., electrophoretic display (EPD) devices) and non-display devices such as adaptive lenses and sensor devices.

[0030] First exemplary embodiment

[0031] Reference Figure 1 The description of the technology according to the first exemplary embodiment begins with a workpiece comprising a support substrate 2 (e.g., an optically neutral plastic support film, such as a triacetyl cellulose (TAC) film) and an initial set of layers formed in situ on the support substrate 2. The initial set of layers comprises, in order: (i) a planarization layer 4, such as a cross-linked organic polymer layer, for example, an epoxy polymer known as SU-8; (ii) a first metal pattern 6 (comprising a patterned metal layer or a sub-stack of patterned metal layers), the primary function of which is to protect the semiconductor channel by reflecting white light incident on the support substrate from the opposite side of the support substrate (the bottom side in the figure); (iii) another planarization layer 8, for example, having the same composition as the first planarization layer; (iv) a conductive metal oxide pattern 10 (e.g., indium tin oxide (ITO)), which provides an array of pixel electrodes for the device; (v) a second metal pattern 12 (comprising a patterned metal layer or a sub-stack of patterned metal layers), which defines at least a source conductor and a drain conductor of an array of thin film transistor (TFT) devices; and (vi) an unpatterned semiconductor layer 14 (e.g., an organic polymer semiconductor layer), which is a thin film transistor (TFT) device. The present invention relates to a thin film transistor (TFT) device that provides a semiconductor channel; (vii) an unpatterned gate dielectric layer 16 (e.g., a low-k, non-cross-linked organic polymer insulator layer, or a stack of, for example, a low-k, non-cross-linked organic polymer insulator sublayer and an overlying high-k organic polymer insulator (cross-linked or non-cross-linked) sublayer (k = dielectric constant)) interfaced with the semiconductor layer; (viii) an unpatterned conductive metal oxide layer 18 (e.g., indium tin oxide (ITO)) that provides a gate electrode for the thin film transistor (TFT) device (and, as further mentioned below, also serves as a dry etch stop layer in a later patterning process); (ix) an unpatterned layer of light absorbing material 20, whose primary function is to absorb any scattered white light that happens to propagate within the stack in a direction substantially parallel to the plane of the stack; and (x) an unpatterned photoresist layer 22.

[0032] refer to Figure 2A photoresist layer 22 is patterned by photolithography, as described below. The top surface of the workpiece is exposed to a radiation image (positive or negative, depending on the type of photoresist used) of the desired pattern in the photoresist layer. The radiation has a frequency that causes a change in the solubility of the photoresist material. The resulting latent solubility image is developed to produce a physical pattern 22a in the photoresist layer.

[0033] Reference Figure 3 The resulting workpiece is then subjected to a dry etching process (reactive ion etching (RIE) process), which etches the exposed portion of the cross-linked polymer absorber layer 20. The underlying metal oxide layer 18 is resistant to the dry etching process, and the etching stops at the metal oxide layer 18.

[0034] Reference Figure 4 The resulting workpiece is then subjected to a wet etching process that uses the photoresist pattern 22a as an etch mask to etch the ITO layer 18. The underlying gate dielectric layer 16 is resistant to the wet etching process; the wet etching stops at this layer 16. In one exemplary variation, the wet etching process is replaced by a dry etching process that uses a gas that generates a plasma species that is significantly more chemically reactive with the ITO layer 18 than with the underlying gate dielectric layer 16.

[0035] refer to Figure 5 , the workpiece is further dry-etched (RIE) without removing the photoresist pattern 22a, but an alternative option is to first remove the photoresist pattern 22a and rely on the patterned metal oxide layer 18a as an etching mask to pattern the organic dielectric layer 16 and the semiconductor layer 14 by dry etching. The second metal pattern (source-drain pattern) 12, the pixel electrode metal oxide pattern 10, and the upper planarization layer 8 are resistant to the dry etching, and the dry etching stops at these patterns / layers. Therefore, after patterning, the light absorbing material 20 remains at least in the region of the semiconductor channel.

[0036] Reference Figure 6 The photoresist pattern 22a is then removed, and an organic polymer insulator layer 24 (eg, a cross-linked polymer layer) is formed in situ on the working surface of the workpiece so as to completely cover the underlying pattern.

[0037] Reference Figure 7Another layer of conductive metal oxide (e.g., ITO) is formed in situ on the working surface of the workpiece and patterned using a patterned photoresist mask (not shown) and wet etching to provide a counter electrode 26 (COM electrode) for each pixel electrode. The underlying organic polymer insulator layer 24 is resistant to the wet etching, and the wet etching stops at the organic polymer insulator layer 24. The photoresist mask is then removed.

[0038] Reference Figure 8 A new layer of photoresist material 28 is formed in situ on the working surface of the workpiece and patterned to produce a photoresist mask for patterning the underlying insulator layer 24 and light absorbing layer 20 to produce at least interconnect vias (ICVs) down to the conductive metal oxide, gate electrode islands 18a. In this example, the patterning also produces ICVs outside the active display area down to the gate wiring conductor (not shown) defined by the second metal pattern 12.

[0039] Reference Figure 9 The workpiece is then dry-etched (RIE). The metal oxide islands 18a are resistant to dry etching, and the dry etching stops at these metal oxide islands 18a to leave an ICV down to the metal oxide gate electrode 18a of each TFT. The photoresist mask 28 is then removed.

[0040] Reference Figure 10 and 11 , a third metal pattern 32a is formed in situ on the upper surface of the workpiece to provide a trace for the gate electrode of the addressing TFT. A metal layer 32 (or a sub-stack of metal layers) is formed in situ on the working surface of the workpiece by, for example, a vapor deposition technique such as sputtering. The metal layer / sub-stack 32 contacts the metal oxide gate electrode 18a via an ICV through the insulator layer 24 and the light absorbing layer 20. The metal layer / sub-stack 32 also contacts the gate wiring conductor (not shown) via an additional ICV outside the active display area described above. A photoresist material layer ( Figure 10 ). The photoresist layer is then patterned to produce a photoresist mask 34 for patterning the metal layer 32; and the workpiece is subjected to a wet etching process. The wet etching process etches one or more metal layers 32 in the areas exposed by the photoresist mask. The organic polymer insulator 24 and the metal oxide common electrode pattern 18a are resistant to the wet etching process, and the wet etching stops at these layers. This patterning produces a metal oxide gate electrode 18a ( Figure 11 The photoresist mask is then removed.

[0041] In this example, the conductive traces (for gate electrodes) include an array of conductor lines, each connected to the gate electrode of a corresponding row of TFTs, each extending outside the active area occupied by the array of pixel electrodes, and each contacting a corresponding routing conductor (not shown) defined by the second metal pattern via a corresponding one of the above-mentioned ICVs outside the active area. The source / drain metal pattern also includes an array of source conductor lines, each providing a source electrode for a corresponding column of TFTs and extending outside the active area occupied by the array of pixel electrodes. Each TFT is associated with a corresponding, unique combination of source conductor lines and gate trace wires, whereby each pixel electrode can be addressed independently of all other pixel electrodes via the conductors outside the active area.

[0042] Second exemplary embodiment

[0043] Figures 12 to 16 A second example embodiment of the technology according to the present invention is shown.

[0044] Reference Figure 12 The description of this second exemplary embodiment begins with a workpiece comprising: a support substrate 2 (e.g., an optically neutral organic polymer film, such as a TAC film), and an initial set of layers formed in situ on the support substrate. The initial set of layers comprises, in order: (i) a planarization layer 4, such as a cross-linked organic polymer layer, for example, an epoxy polymer known as SU-8; (ii) a first metal pattern 6 (comprising a patterned metal layer or a sub-stack of patterned metal layers), the primary function of which is to protect the semiconductor channel by reflecting white light incident on the support substrate from the opposite side of the support substrate (the bottom side in the figure); (iii) another planarization layer 8, (e.g., having the same composition as the first planarization layer); (iv) an unpatterned layer of light absorbing material 50, the primary function of which is to absorb any scattered white light that happens to propagate within the stack in a direction substantially parallel to the plane of the stack; (v) an unpatterned insulator a material layer 52 (referred to herein as a back channel dielectric layer because it interfaces with the semiconductor channel), such as the same material layer as the planarization layer described above, or another organic polymer insulator material; (vi) a second metal pattern 12 (comprising a patterned metal layer or a substack of patterned metal layers) that defines at least a source conductor and a drain conductor for an array of thin film transistor (TFT) devices; (vii) an unpatterned semiconductor layer 14 (e.g., an organic polymer semiconductor layer) that provides a semiconductor channel for the thin film transistor (TFT) devices; and (viii) an unpatterned first gate dielectric layer 16 (e.g., an organic polymer insulator layer) that interfaces with the semiconductor layer.

[0045] Back channel dielectric layer 52 has a thickness of no greater than about 500 nm to position light absorbing layer 50 close to the semiconductor channel. Back channel dielectric layer 52 facilitates selection of light absorbing materials for light absorbing layer 50 without concern for conductivity or chemical compatibility with semiconductor material 14.

[0046] Reference Figure 13 A layer of photoresist material is formed in situ on the working surface of the workpiece above the first gate dielectric layer 16. The layer of photoresist material is exposed to an image (negative or positive, depending on the type of photoresist material used) of the desired pattern of the semiconductor and first gate dielectric layer using radiation of a frequency that causes a change in the solubility of the photoresist material. The resulting latent solubility image is developed to produce a physical pattern 70 in the photoresist layer.

[0047] Reference Figure 14 , and the resulting workpiece is then subjected to a dry etching (RIE) process. The second metal pattern 12 (defining the source and drain conductors) and the planarization layer 8 (e.g., SU-8) above are resistant to dry etching, and the dry etching is stopped at these layers. Therefore, the back channel dielectric layer 52a and the light absorbing layer 50a remain in all areas occupied by the patterned photoresist 70 and / or occupied by the second metal pattern 12. The first gate dielectric layer 16a and the semiconductor layer 14a remain only in those areas occupied by the patterned photoresist 70. Therefore, after patterning, the light absorbing material 50a remains at least in the area of ​​the semiconductor channel. The photoresist mask 70 is then removed.

[0048] Reference Figure 15 and 16A second gate dielectric layer 54 (e.g., a cross-linked organic polymer layer) is formed in situ on the workpiece surface. A metal layer or a sub-stack of metal layers 32 is then formed in situ on the workpiece above the second gate dielectric layer 54 and patterned by wet etching (using another patterned photoresist mask (not shown)) to produce a third metal pattern 32a that defines a gate conductor array for a display device. The second gate dielectric layer 54 is resistant to wet etching, and the wet etching stops at the second gate dielectric layer 54. The process continues in sequence by: forming an insulator (passivation) layer 56 (e.g., a cross-linked organic polymer layer) in situ on the workpiece; patterning the insulator layer 56 and the second gate dielectric layer 54 (by dry etching (RIE) using another patterned photoresist mask) to produce interconnect vias (ICVs) down to each drain conductor; forming a conductive metal oxide pattern 58 (e.g., an ITO pattern) in situ on the workpiece that defines an array of pixel electrodes, each pixel electrode contacting a corresponding drain conductor through a corresponding ICV; forming another insulator 60 (passivation) layer (e.g., a cross-linked organic polymer layer) in situ on the workpiece; and forming another conductive metal oxide pattern 62 in situ on the workpiece, located above the second insulating layer, which defines a common counter electrode (COM electrode) for each pixel electrode 58.

[0049] In this example, the gate metal pattern 32a defines an array of conductor lines that each provide a gate electrode for a corresponding row of TFTs and extend outside the active area occupied by the array of pixel electrodes 58. The source / drain metal pattern 12 defines an array of source conductor lines that each provide a source electrode for a corresponding column of TFTs and extend outside the active area occupied by the array of pixel electrodes. Each TFT is associated with a corresponding, unique combination of source conductor lines and gate trace wires, so that each pixel electrode can be addressed independently of all other pixel electrodes via the conductors outside the active area.

[0050] For both the first and second exemplary embodiments, the process may include additional steps such as forming an ordered array of spacing structures for the liquid crystal cells in situ on the workpiece; and thereafter forming a liquid crystal alignment layer in situ on the workpiece that provides a liquid crystal alignment surface to interface with the LC material of the liquid crystal cells.

[0051] Reference Figure 17 The resulting control component forms one half of a liquid crystal (LC) cell for a liquid crystal color display device. The other half of the LC cell comprises a supporting substrate 108 (e.g., an optically neutral organic polymer film such as TAC film) and a stack of layers 106 formed in situ on the supporting substrate. The stack of layers 106 defines a color filter array in a black matrix and a liquid crystal alignment surface that interfaces with the liquid crystal material 104. The two half cells are held together by an adhesive / sealant 100.

[0052] In the first and second exemplary embodiments, the light absorbing layers 20, 50 exhibit a white light optical density greater than about 1 in a direction perpendicular to the plane of the light absorbing layer. White light optical density is defined as (-log 10 T), where T is the white light transmittance in a direction perpendicular to the plane of the light absorbing layer 20, 50, and is itself defined as the proportion of white light that passes through the layer (i.e., (light intensity measured on the opposite side of the layer) ÷ (light intensity incident on the layer)). The light absorbing layer 20, 50 also exhibits a total reflectivity of less than about 10%. Total reflectivity is the sum of specular reflectivity and diffuse reflectivity. The total reflectivity of the light absorbing layer 20, 50 (as well as the specular and diffuse components of the total reflectivity) can be measured using an integrating sphere.

[0053] Optical densities greater than 1 and total reflectivity less than 10% can be achieved using, for example, a 500 nm (0.5 micron) layer of material for a black matrix of a color filter array for a color display device. For example, the material may comprise an epoxy acrylate polymer having carbon black dispersed therein.

[0054] According to some embodiments, the light absorbing layer 20, 50 includes a light absorbing layer having a strength greater than 1 MOhm / sq (ie, 1x10 6 Ω / sq) of thin film resistance of insulating materials.

[0055] In the first and second exemplary embodiments, only one light absorbing layer 20 , 50 is provided, but light absorbing layers may be provided above and below the semiconductor channel.

[0056] As mentioned above, while examples of techniques according to the present invention have been described in detail above with reference to specific process details, the techniques are more broadly applicable within the overall teachings of this application. Furthermore, and in accordance with the overall teachings of this application, techniques according to the present invention may include additional process steps not described above, and / or omit some of the process steps described above.

[0057] For example, as described above, the technology is also applicable to the manufacture of other types of display devices (e.g., EPD devices) and other non-display devices; and the manufacture of other devices may involve different structures in which light absorbing layers are incorporated. For example, the example technology of providing a patterned light absorbing layer between a semiconductor layer and an overlying metal layer (as in the first example embodiment) can also be applied to devices in which, for example, a single patterned metal layer provides the gate electrodes and gate traces of a TFT array.

[0058] In addition to any modifications explicitly mentioned above, it will be apparent to those skilled in the art that various other modifications of the described embodiments may be made within the scope of the invention.

[0059] The applicant hereby independently discloses each individual feature described herein and any combination of two or more such features, to the extent that such feature or combination can be implemented based on the overall content of this specification and in accordance with the common general knowledge of those skilled in the art, regardless of whether such feature or combination of features solves any problem disclosed herein, and without limiting the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features.

Claims

1. A method, characterized in that: include: forming in situ on a supporting substrate: a first metal layer; a light absorbing layer following the first metal layer; a conductor pattern behind the light absorbing layer; and a semiconductor layer behind the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern, the semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; as well as The light absorbing layer is patterned using the resist mask and the conductor pattern so as to selectively remain the light absorbing layer in a region occupied by at least one of the resist mask and the conductor pattern.

2. The method according to claim 1, wherein: The light absorbing layer exhibits a white light optical density of at least about 1 and a white light total reflectance of no greater than about 10% in a direction substantially perpendicular to the plane of the support substrate.

3. The method according to claim 1 or claim 2, characterized in that: The light absorbing layer includes an insulator material.

4. The method according to claim 3, wherein: The light absorbing layer includes an insulator material having a sheet resistance greater than 1 MOhm / square.

5. The method according to claim 1, wherein: The light absorbing layer is separated from the semiconductor layer by a distance of no more than about 500 nm in a direction substantially perpendicular to a plane of the supporting substrate.

6. The method according to claim 1, wherein: The light absorbing layer is interfaced to the one or more semiconductor channels.

7. The method according to claim 1, wherein: The first metal layer is a light-shielding metal pattern.

8. The method according to claim 1, wherein: The one or more semiconductor devices form part of a control component half for a liquid crystal cell comprising liquid crystal material between the control component half and another half comprising an array of color filters in a black matrix.

9. The method according to claim 1, wherein: Patterning the semiconductor layer and patterning the light absorbing layer include an etching process, the semiconductor layer and the light absorbing layer are not resistant to the etching process, and the resist mask and the conductor pattern are resistant to the etching process.

10. The method according to claim 1, wherein: The method includes forming a first gate dielectric layer over the semiconductor layer.

11. The method according to claim 10, characterized in that: The first gate dielectric layer is patterned using the resist mask.

12. The method according to claim 11, wherein: Patterning the first gate dielectric layer, patterning the semiconductor layer, and patterning the light absorbing layer includes an etching process, the first gate dielectric layer, the semiconductor layer, and the light absorbing layer are not resistant to the etching process, and the resist mask and the conductor pattern are resistant to the etching process.

13. The method according to claim 12, wherein: After patterning the first gate dielectric layer, the semiconductor layer, and the light absorbing layer, a second gate dielectric layer is formed.

14. The method according to claim 13, wherein: The method includes forming a metal pattern over the second gate dielectric layer, the metal pattern defining an array of gate conductors for the one or more semiconductor devices.

15. The method according to claim 1, wherein: The method includes forming a back channel dielectric layer after forming the light absorbing layer and before forming the conductor pattern, wherein the back channel dielectric layer is interfaced with the one or more semiconductor channels.

16. The method according to claim 15, characterized in that: The method includes patterning the back channel dielectric layer, wherein patterning the back channel dielectric layer, patterning the semiconductor layer, and patterning the light absorbing layer include an etching process, the semiconductor layer, the back channel dielectric layer, and the light absorbing layer are not resistant to the etching process, and the resist mask and the conductor pattern are resistant to the etching process.

17. The method according to claim 15, characterized in that: The method includes forming the first metal layer over a planarization layer, wherein the back channel dielectric layer includes a layer of a first metal, and the planarization layer includes a layer of the first metal.

18. The method according to claim 1, wherein: The light absorbing layer includes an organic polymer in which inorganic light absorbing particles are dispersed.

19. The method according to claim 18, wherein: The inorganic light absorbing particles include carbon black.

20. The method according to claim 1, wherein: The main function of the first metal layer is to protect the semiconductor channel from light incident on the support substrate from a side of the support substrate opposite to the first metal layer.

21. The method according to claim 1, wherein: The main function of the light absorbing layer is to absorb scattered light propagating in a direction substantially parallel to the light absorbing layer.

22. A device, characterized in that: include: a stack of layers defining one or more semiconductor devices; The stack includes: a semiconductor layer, which defines one or more semiconductor channels of the one or more semiconductor devices; a first metal layer below the semiconductor layer and a second metal layer above the semiconductor layer; a conductor pattern between the first metal layer and the semiconductor layer; and a light absorption pattern between the first metal layer and the conductor pattern; the light absorption pattern has an edge aligned with an edge of the conductor pattern.

23. The device according to claim 22, characterized in that: The light absorption pattern exhibits a white light optical density of at least about 1 in a direction substantially perpendicular to the plane of the stack, and a total white light reflectance of no more than about 10%.

24. The device according to claim 23, characterized in that: The light absorption pattern includes an insulator material.

25. The device according to claim 24, characterized in that: The light absorption pattern includes an insulator material having a sheet resistance greater than 1 MOhm / square.

26. The device according to claim 22, characterized in that: The light absorption pattern is separated from the semiconductor layer by a distance of no more than about 500 nm in a direction substantially perpendicular to a plane of the stack.

27. The device according to claim 22, characterized in that: The light absorption pattern is interfaced with the one or more semiconductor channels.

28. The device according to claim 22, characterized in that: The first metal layer includes a light-shielding metal pattern.

29. The device according to claim 22, characterized in that: The one or more semiconductor devices form part of a control component half for a liquid crystal cell comprising liquid crystal material between the control component half and another half comprising an array of color filters in a black matrix.

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