Switching Device and Memory Device

Abstract

The present invention discloses a switching device and a memory device. The switching device has a first electrode; a second electrode; and a switching layer located between the first electrode and the second electrode. The switching layer includes a composition of carbon C, arsenic As, selenium Se, and germanium Ge, and this composition is thermally stable up to a temperature exceeding 400 °C. This switching device is used in a 3D cross-point memory.

Description

Technical Field

[0001] The present invention relates to a switching device and a memory device, used in integrated circuits, including an integrated circuit memory device. Background Art

[0002] Switching devices have many applications, such as transistors and diodes in integrated circuits. The rise of new nonvolatile memory (NVM) technologies, such as phase change memory and resistive memory, has been motivated by exciting applications such as storage class memory, solid-state disk, embedded nonvolatile memory, and neuromorphic computing. Many of these applications are densely packed in vast "crosspoint" arrays, providing many gigabytes.

[0003] In this array, access to any small subset of arrays for accurate reading or low-power writing requires a strong nonlinear I-V characteristic, so that the current through the selected device greatly exceeds the residual leakage through the unselected device. This nonlinearity can be explicitly included by adding a discrete access device at each crosspoint, or implicitly included by using a nonvolatile memory device (NVM device) that also exhibits a highly nonlinear I-V characteristic.

[0004] Other types of switching devices based on ovonic materials are known as ovonic threshold switches, which are characterized by a large drop in resistance at the switching threshold voltage and recovery to a high resistance in the blocking state when the voltage drops below a holding threshold.

[0005] Switching devices have been used, for example, in various programmable resistance memory devices, including high-density arrays of multiple cells organized in a crosspoint architecture. Some crosspoint architectures use multiple memory cells, such as including a phase change memory element or other resistive memory elements in series with a bidirectional selector switch. Other architectures are used, including various two-dimensional and three-dimensional array structures, and switching devices can also be used to select memory elements in the array. In addition, bidirectional threshold switches have been proposed for various other uses, including so-called neuromorphic computing.

[0006] The thermal stability of materials used in integrated circuits can be an important characteristic. For example, in the back end of line (BEOL) of an integrated circuit, temperatures up to 400 °C can be generated, which can exceed the crystallization transition temperature or degrade the stability of the bidirectional material. In addition, in the components of the device, the integrated circuit can be exposed to high temperatures during solder bonding or other high-temperature component processes. In addition, the integrated circuit can be exposed to high temperatures during operation in the art. For example, the thermal stability of the GeTe6 material is low (<200 °C). For example, it is believed that due to serious phase separation being expected, tellurium (Te) crystallizes first above 200 °C, and then rhombohedral GeTe crystallizes at 300 °C. Therefore, unfortunately, it does not have the necessary thermal stability for BEOL CMOS integration.

[0007] It is desirable to provide switching devices with a relatively high threshold voltage, low leakage current, fast switching speed, and good thermal stability at the temperatures encountered during manufacturing and operation in the art. Summary of the Invention

[0008] A voltage sensitive switching device includes a first electrode; a second electrode; and a switching layer located between the first electrode and the second electrode. The switching layer includes a composition of carbon (C), arsenic (As), selenium (Se), and germanium (Ge), and this composition is stable at temperatures above 400°C. A class of compositions is used as a switching layer in an integrated circuit, where the amounts of carbon (C), arsenic (As), selenium (Se), and germanium (Ge) are combined, and the amounts of carbon (C), arsenic (As), selenium (Se), and germanium (Ge) and the thickness of the switching layer effectively give it a crystallization transition temperature above 400°C (measured for the purpose of illustration of the thermal cycling of a thin film). In some embodiments, the crystallization transition temperature is above 450°C. In some embodiments, the crystallization transition temperature is above 500°C.

[0009] A class of compositions includes arsenic (As), selenium (Se), germanium (Ge), and carbon (C) in the range of 10 at% to 30 at%. The materials described herein include a sub-class that includes carbon (C) in the range of 10 at% to 30 at%, arsenic (As) in the range of 20 at% to 35 at%, selenium (Se) in the range of 35 at% to 55 at%, and germanium (Ge) in the range of 8 at% to 25 at%. Among the members of such compositions, the amounts of C, As, Se, and Ge in a switching layer are combined, and the amounts of C, As, Se, and Ge and the thickness of the switching layer effectively give it high thermal stability and a high crystallization transition temperature.

[0010] During the operation of an access select switch, when a control circuit is for a threshold voltage, by applying a voltage to a selected switch to make the voltage above the switching layer in the selected switch higher than the threshold voltage, and by applying a voltage to an unselected switch to make the voltage above the switching layer in the unselected switch lower than the threshold voltage, the composition is effective for converting a threshold voltage.

[0011] A memory device includes a first electrode; a second electrode; a memory element; and a switching layer, such as the above-described switching layer, located between the first electrode and the second electrode and in series with the memory element. The memory device may include a barrier layer (also referred to as a buffer layer) located between the memory element and the switching layer. The memory device can be used as a 3D crosspoint memory on an integrated circuit device, which has a very high density.

[0012] In addition, the switching device can be used in various other types of devices.

[0013] By reading the following drawings, detailed description, and claims, other aspects and advantages of the present invention will become apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is a schematic cross-sectional view of a switching device including a switching layer of a composition including a CAsSeGe material.

[0015] Figure 1B is a schematic cross-sectional view of a switching device including a composition, the switching device being of the "mushroom unit" configuration described herein.

[0016] Figure 2 is a quaternary composition diagram showing a class of materials described herein.

[0017] Figure 3 is a graph of the resistance of Material A versus temperature, showing the crystallization transition temperature.

[0018] Figure 4 is a graph of the surface roughness of Material C versus temperature, showing the thermal stability.

[0019] Figure 5 is a graph of the cyclic applied voltage / induced current of an OTS switch including the materials described herein.

[0020] Figure 6 is a box plot of the OTS switch described herein, showing the transient threshold voltage above 3V.

[0021] Figure 7 is a graph of the levels of the turn-on current and turn-off current, showing the durability over 10 9 cycles.

[0022] Figure 8 is a schematic 3D perspective view of a memory cell in a cross-point memory device, the cross-point memory device including the switching device described herein.

[0023] Figure 9 is a schematic layer diagram of an alternating stacked structure of a cross-point memory device, the cross-point memory device including the switching device described herein.

[0024] Figure 10 is a schematic flow chart for manufacturing the switching device described herein.

[0025] Figure 11It is a schematic block diagram of an integrated circuit memory device including a 3D memory, and the 3D memory uses the switching device described herein.

[0026]

Symbol Explanation

[0027] 5: Region

[0028] 10: Switching layer

[0029] 11: First electrode

[0030] 12: Second electrode

[0031] 15: Barrier layer

[0032] 20: Switching layer

[0033] 21: First electrode

[0034] 22: Second electrode

[0035] 25: Barrier layer

[0036] 101: Bottom electrode layer

[0037] 102: Barrier layer

[0038] 103: OTS switching layer

[0039] 104: Barrier layer

[0040] 105: Memory material layer

[0041] 106: Top barrier layer

[0042] 110: First access line

[0043] 120: Second access line

[0044] 125: Memory cell

[0045] 160: Top electrode layer

[0046] 161: Bottom electrode layer

[0047] 162: Barrier layer

[0048] 163: OTS switching layer

[0049] 164: Barrier layer

[0050] 165: Memory material layer

[0051] 166: Barrier layer

[0052] 171, 172: Covering layer

[0053] 210, 212, 214, 216, 218: Steps

[0054] 300: Integrated circuit

[0055] 302: Array

[0056] 304: Column / layer decoder

[0057] 306: Word line

[0058] 308: Row / layer decoder

[0059] 310: Bit line

[0060] 312: Bus

[0061] 314: Square

[0062] 316: Bus

[0063] 318: Data input line

[0064] 320: Other circuits

[0065] 322: Data output line

[0066] 324: Controller

[0067] 326: Bias circuit voltage source and current source

[0068] 501: First cycle

[0069] Tx: Crystallization transition temperature

[0070] V1, V2: Voltages Detailed implementation manners

[0071] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0072] The detailed description of the embodiments of the present invention is provided with reference to Figures 1A to 11 being provided.

[0073] Figure 1A is a schematic diagram of a switching device, which includes a switching layer 10 of a carbon arsenic selenium germanium (CAsSeGe) material described herein. The switching device includes a first electrode 11, a second electrode 12, and a barrier layer 15 and a switching layer 10 connected in series between the first electrode and the second electrode. A voltage V1 can be applied to the first electrode 11, and a voltage V2 can be applied to the second electrode 12.

[0074] Figure 1BIt is a schematic diagram of a switching device with a "mushroom cell" structure. This switching device includes a first electrode 21 and a second electrode 22, as well as a barrier layer 25 and a switching layer 20 connected in series between the first electrode 21 and the second electrode 22. In this embodiment, the second electrode 22 is coupled to a conductor through a dielectric layer, and this conductor can be used to connect to a driver or other voltage sources for operating the switching device. In the "mushroom cell" structure, the second electrode 22 and the switching layer 20 have a contact area, which is quite smaller than the corresponding contact area of the first electrode 21 and the switching layer 20. This smaller contact area serves to concentrate the current passing through the switching layer in a smaller area, enabling lower current operation of the switching element.

[0075] For Figure 1A and Figure 1B the switching device, when the voltage (V1 - V2) across the switching layer between the first electrodes 11, 21 and the second electrodes 12, 22 exceeds the threshold voltage of the switching layer, then the switching device is turned on. When the voltage across the first electrodes 11, 21 and the second electrodes 12, 22 is lower than the holding threshold voltage of the switching layer, the switching device returns to the high-impedance off state. Figure 1A and Figure 1B The switching devices shown can have a highly nonlinear current-versus-voltage characteristic, making these switching devices suitable for use as switching elements in high-density memory devices and other settings.

[0076] The barrier layer 15 can provide one or more of resistance, adhesion, and diffusion barrier functions. The barrier layer 15 can have a conductive material layer with a thickness of about 5 to about 50 nanometers (nm), preferably about 20 nm. The barrier layer 15 can be a composition that includes carbon (including substantially pure carbon), or the composition is silicon and carbon on the top surface of a two-terminal switching material, or includes other materials. Other example materials for the barrier layer 15 can be a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN).In addition to metal nitrides, the barrier layer 15 may include materials such as carbon, doped polysilicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), or tantalum oxynitride (TaON).

[0077] In some embodiments, a second barrier layer may be disposed on a second surface (e.g., a bottom surface) of the two-terminal switching material, the second surface being opposite to the aforementioned first surface.

[0078] The switching layers 10, 20 are a two-terminal switch having a composition of carbon (C), arsenic (As), selenium (Se), and germanium (Ge), thermally stable to temperatures exceeding 400 °C. A class of compositions is used as a switching layer 10 in an integrated circuit, where the amounts of carbon (C), arsenic (As), selenium (Se), and germanium (Ge) are combined, and the amounts of carbon (C), arsenic (As), selenium (Se), and germanium (Ge) and the thickness of the switching layer 10 effectively result in a crystallization transition temperature exceeding 400 °C. In some embodiments, the crystallization transition temperature may exceed 450 °C. In some embodiments, the crystallization transition temperature may exceed 500 °C.

[0079] Figure 2 It is a pyramidal quaternary composition chart of materials C, As, Se, and Ge. In the chart, the concentrations of arsenic, selenium, and germanium can be represented by positions on the three axes at the bottom of the pyramid, with arsenic at the back in the chart. The concentration of carbon is represented by the vertical position of the pyramid.

[0080] This chart generally depicts a region 5 representing a class of carbon-arsenic-selenium-germanium materials that is stable at high temperatures and has a threshold voltage, a low off-state current, and switching endurance at a thickness below 100 nm. In some embodiments, region 5 preferably has switching endurance at a thickness below 50 nm. Among them, the thickness can be critical in the integrated circuit memory cells described herein.

[0081] Figure 2 Among them, materials A, B, C, and the material of arsenic selenide germanium (AsSeGe) are shown, and they have the compositions as shown in the following table.

[0082] C (at.%) As (at.%) Se (at.%) Ge (at.%) AsSeGe 0 26.3 49.6 24.1 A 28.3 20.2 39.4 12.1 B 19.5 27.2 37.0 16.3 C 14.5 20.8 47.1 8.6

[0083] Materials A and C in region 5 with a thickness of 30 nm are tested. As a switching layer, they show unexpectedly good performance and good thermal stability at temperatures exceeding 400 °C. The tests of materials A and C show a trend of increasing crystallization transition temperature and increasing carbon concentration, establishing the expectation that the materials in region 5 can have high thermal stability and high crystallization transition temperature.

[0084] For comparison, the arsenic selenide germanium (AsSeGe) material in the above table with a thickness of 30 nm has a threshold voltage Vth of about 4 volts (V) and a turn-off current (Ioff) of about 7 pA at 2 V. Material A with a thickness of 30 nm has a threshold voltage Vth of about 2.95 V and a turn-off current of about 2 nA at 2 V. Material C with a thickness of 30 nm has a threshold voltage Vth of about 2.6 V and a turn-off current of about 0.6 nA at 2 V. Therefore, at a thickness below 100 nm, and more preferably at a thickness below 50 nm for some embodiments, materials A and C have characteristics suitable for use as bidirectional threshold switches (OTS) devices and OTS switching elements in memory devices, showing an increasing threshold voltage and an increasing carbon concentration. Material B, which has characteristics between those of material A and material C, should therefore also be suitable for use as an OTS device and an OTS switching element in memory devices. The examples can be used as a switching layer with a thickness less than 50 nm, and the composition includes As, Se, Ge, and C. The amounts of As, Se, Ge, and C are effectively switched using an applied voltage pulse at a threshold voltage Vt < 4 V and a duration less than 5 ns.

[0085] One class of compositions includes arsenic (As), selenium (Se), germanium (Ge), and carbon (C). Carbon (C) is within the range of extrapolation of experimental results based on 10 at% to 30 at% of this composition and is stable at a surprisingly high temperature exceeding 400 °C. In some embodiments, multiple materials are combined, and the concentrations of these materials can effectively have a crystallization transition temperature exceeding 450 °C. In some embodiments, multiple materials are combined, and the concentrations of these materials can effectively have a crystallization transition temperature exceeding 500 °C.

[0086] Materials A, B, and C having an arsenic concentration between 20 and 21 at% are generally located in region 5 and are stable at surprisingly high and unpredictable temperatures above 400 °C. In some embodiments, the crystallization transition temperature can exceed 450 °C. In some embodiments, the crystallization transition temperature can exceed 500 °C

[0087] Materials located in region 5 generally include a class of compositions of carbon, arsenic, selenium, and germanium based on extrapolation of experimental results. Such compositions include carbon in the range of 10 at% to 30 at%, arsenic in the range of 20 at% to 35 at%, selenium in the range of 35 at% to 55 at%, and germanium in the range of 8 at% to 25 at%. Among the members of such compositions, C, As, Se, and Ge with a layer thickness of less than 50 nm can be combined into a switching layer, and the amounts of C, As, Se, and Ge effectively render this switching layer stable at surprisingly high and unpredictable temperatures above 400 °C. In some embodiments, the amounts of C, As, Se, and Ge effectively cause this switching layer to have a crystallization transition temperature above 450 °C. In some embodiments, the amounts of C, As, Se, and Ge effectively cause this switching layer to have a crystallization transition temperature above 500 °C. The relative concentrations of the multiple elements of a particular member of such compositions can be selected to effectively achieve one or more of the properties shown by the tests described herein, and such one or more properties include high thermal stability, high crystallization transition temperature, high threshold voltage, low off-state current, fast switching, and high endurance.

[0088] To test the thermal stability of Material A, a thin film of Material A was deposited on a substrate and subjected to increasing temperature. Visual inspection showed that the film did not appear to be damaged at temperatures above 450 °C, and that discoloration or roughness indicating thermal degradation occurred at approximately 550 °C. Even though the crystallization transition deduced from x-ray diffraction measurement did not seem to occur until about 500 °C, comparable testing of the ternary AsSeGe composition in the table above showed discoloration or roughness damage below 380 °C. Discoloration is believed to occur due to surface roughness caused by localized phase separation, delamination, or other physical changes in the material, indicating thermal degradation due to lack of thermal stability.

[0089] Figure 3 is a graph of the resistance of Material A versus temperature, showing very high resistance at low temperatures along the top row of samples, transitioning to low resistance at approximately 530 °C and remaining at low resistance when the material is cooled. This graph shows the crystallization transition temperature Tx of Material A above 500 °C.

[0090] Although not shown in Figure 3 Material C was also tested using a thin film on a substrate. No crystallization was observed when the temperature was ramped up above 530 °C. Additionally, no discoloration or thermal damage was seen in visual inspection.

[0091] Figure 4 is a graph of the temperature of Material C versus surface roughness, showing the thermal stability of the material for the latter process described above, exposing Material C to temperatures above 400 °C, above 450 °C, and above 500 °C or higher without changing the surface roughness, providing a substantial manufacturing margin for thermal stability.

[0092] Device performance was also tested on a cell, for example as shown in Figure 1BA 30-nm-thick layer of material C used, a tungsten bottom electrode, a carbon barrier layer on the OTS material, and a tungsten top electrode.

[0093] The IV graph of the force voltage / sense current for the cycles of the switch is shown in Figure 5 It. By sweeping the voltage from 0 V to 4 V and then from 4 V to 0 V and measuring the current I, this graph is generated. In the graph, a maximum value of 100 μA for compliance is set, so that even when the voltage in this region increases, the current is constant. The first cycle 501 is a forming cycle, in which the threshold voltage is relatively high. In subsequent cycles, the switch consistently switches at a threshold of approximately 2.6 V and a holding voltage Vh of approximately 1.4 V. Figure 5 In it, the first cycle 500 is the IV characteristic of the OTS material during formation. It is common that the current-voltage curve (I-V curve) of the forming process is different from the current-voltage curve after the forming process (the second cycle to the fifth cycle 501).

[0094] Figure 6 Is a box plot of 5-nsec switching pulses, showing successful switching of material C by approximately 3.2 volts within 5 nsec.

[0095] Figure 7 Is a graph showing durability, showing the levels of the on-current and off-current of material C, up to 10 9 cycles without breakdown.

[0096] The test data from material C implies that other combinations of materials A, B, CAsSeGe, as discussed above, and other materials in region 5 may have combinations of concentrations that effectively exhibit similar behavior of fast switching, good durability, and high crystallization temperature as discussed herein.

[0097] Figure 8Illustrate a memory cell 125 of an embodiment, including a multi-layer pillar disposed at the intersection of a first access line 110 and a second access line 120.

[0098] The pillar of this embodiment includes a bottom electrode layer 101 on the first access line 110, such as a metal, a metal nitride, a doped semiconductor, or the like.

[0099] A barrier layer 102 is disposed on the bottom electrode layer 101. In some embodiments, the barrier layer 102 includes a composition, such as carbon as described herein, or silicon and carbon. The barrier layer 102 can be, for example, 15 to 30 nm thick.

[0100] An OTS switching layer 103 is disposed above the barrier layer 102. The OTS switching layer 103 can include an OTS material, such as a material with thermal stability up to a temperature exceeding 400 °C, including materials such as those described above with reference to Figure 2 the materials of such materials as described above. The OTS switching layer can be, for example, a layer of CAsSeGe material 15 to 45 nm thick, more preferably less than 50 nm thick.

[0101] A barrier layer 104 is disposed above the OTS switching layer 103 and can be referred to as a capping layer of the OTS material. The barrier layer 104 is a barrier layer including a composition of carbon, or silicon and carbon as discussed herein. The barrier layer 104 can be, for example, 15 to 30 nm thick.

[0102] A memory material layer 105 is disposed on the barrier layer 104. The memory material may include a programmable resistance material. In embodiments of the technology, the memory material includes a phase change memory material, such as GST (e.g., Ge2Sb2Te5), silicon oxide doped GST, nitrogen-doped GST, silicon oxide doped GaSbGe, or other phase change memory materials. The memory material layer 105 may have a thickness selected according to the specific material used. For phase change materials, embodiments of the thickness range may be 5 to 50 nm thick. Some embodiments of memory materials that may be useful are disclosed in columns 11 to 13 of U.S. Patent Publication No. 5,687,112 invented by Ovshinsky et al., and these contents are incorporated herein by reference in their entirety.

[0103] The memory material layer 105 may include a chalcogenide alloy layer, using additives to modify conductivity, transition temperature, melting temperature, and other properties. Representative additives may include nitrogen (N), silicon (Si), oxygen (O), silicon oxide (SiO x ), silicon nitride (SiN), copper (Cu), silver (Ag), gold (Au), aluminum (Al), aluminum oxide (Al2O3), tantalum (Ta), tantalum oxide (TaO x ), tantalum nitride (TaN), titanium (Ti), and titanium oxide (TiO x ).

[0104] In some embodiments, other programmable resistance memory elements may be implemented, such as metal-oxide resistive memory, magnetic resistive memory, conducting-bridge resistive memory, or other types of memory devices.

[0105] The first access line (bit line) and the second access line (word line) may include various metals, metal-like materials, doped semiconductors, or combinations thereof. Embodiments of the first access line and the second access line may be implemented using one or more layers of material, such as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), tungsten silicide (WSi), titanium nitride / tungsten / titanium nitride (TiN / W / TiN), and other materials. For example, the thickness of the first access line and the second access line may range from 10 to 100 nm. In other embodiments, the first access line and the second access line may be very thin or very thick. The material selected for the second access line is preferably selected to be compatible with the memory material layer 105 and the top barrier layer 106. Similarly, the material selected for the first access line is preferably selected to be compatible with the bottom electrode layer 101 and the barrier layer 102.

[0106] In another embodiment, as Figure 3 shown, the bottom electrode has a smaller contact surface compared to the surface of the memory element, and this bottom electrode is sandwiched between the memory material layer 105 and the OTS switching layer 103, or between the memory material layer 105 and the top barrier layer 106. Therefore, an increased current density at the contact points in the memory element can be achieved.

[0107] A top barrier layer 106 is disposed on the memory material layer 105. In some embodiments, the top barrier layer 106 includes a composition comprising silicon and carbon as described herein. The top barrier layer 106 may be, for example, 15 to 30 nm thick.

[0108] In addition to the combination of silicon and carbon described herein, the exemplary materials for the first barrier layer 102, the second barrier layer 104, and the top barrier layer 106 may be metal nitrides, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), and tantalum aluminum nitride (TaAlN). In addition to metal nitrides, the first barrier layer 102 and the top barrier layer 106 may include a plurality of materials, such as carbon, doped polysilicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), or tantalum oxynitride (TaON).

[0109] The first access line (bit line) and the second access line (word line) may include various metals, metalloids, doped semiconductors, or combinations thereof. Embodiments of the first access line and the second access line may be implemented using one or more layers of material, such as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), tungsten silicide (WSi), titanium nitride / tungsten / titanium nitride (TiN / W / TiN), and other materials. For example, the thickness of the first access line and the second access line may range from 10 to 100 nm. In other embodiments, the first access line and the second access line may be very thin or very thick.

[0110] The first electrode and the dielectric layer are formed, and methods, materials, and processes disclosed in, for example, U.S. Patent No. 8,138,028, titled "Method for Manufacturing a Phase Change Memory Device with Pillar Bottom Electrode", may be used, which is incorporated herein by reference.

[0111] Alternatively, the switching devices may be organized in a cross-point architecture, described in, for example, "Self-Aligned, Programmable Phase change memory" of U.S. Patent No. 6,579,760, published on June 17, 2003, which is incorporated herein by reference. The first electrode may be an access line, such as a word line and / or a bit line. In this architecture, access devices are arranged between the switching devices and the access lines.

[0112] Figure 9 Illustrates an alternative stack including the materials of the CAsSeGe OTS layer described herein and a memory layer. Figure 9 A stack of material may be used in, for example, Figure 8 the cross-point structure shown. Figure 8 and Figure 9 Various material stacks of the embodiments shown may be used.

[0113] Figure 9 Among them, the stack includes a bottom electrode layer 161 located above the first access line (not shown), such as a metal, metal nitride, a doped semiconductor, or the like.

[0114] A barrier layer 162 is disposed over the bottom electrode layer 161. In some embodiments, the barrier layer 162 includes a composition of silicon and carbon as described herein. The barrier layer 162 can be, for example, 15 to 30 nm thick.

[0115] An OTS switching layer 163 is disposed over the barrier layer 162. The OTS switching layer 163 can include an OTS material, such as an OTS material having a thermal stability with a temperature up to over 400 °C, including materials of the above-described categories of materials with reference to Figure 2 The OTS switching layer can be, for example, a layer of CAsSeGe material that is 15 to 45 nm thick, and more preferably less than 50 nm thick.

[0116] A barrier layer 164 is disposed over the OTS switching layer 163 and can be referred to as a capping layer for the OTS material. The barrier layer 164 can include a composition of silicon and carbon as discussed herein. The barrier layer 164 can be, for example, 15 to 30 nm thick.

[0117] A memory material layer 165 is disposed above the barrier layer 164. The memory material can include a programmable resistive material as discussed with reference to Figure 8 A capping layer 172, including, for example, tungsten or another conductor, can be disposed between the memory material layer 165 and the barrier layer 164. In addition, a capping layer 171, including, for example, tungsten or other conductors, can be located above the memory material layer 165.

[0118] Figure 9 In the stack of, a barrier layer 166, including, for example, carbon and silicon, overlies the capping layer 171. A top electrode layer 160 is disposed above the barrier layer 166. In another embodiment, as Figure 3 shown, a bottom electrode having a contact surface smaller than the surface of the memory element is sandwiched between the memory material layer 165 and the OTS switching layer 163, or between the memory material layer 165 and the barrier layer 166. Thus, an increased current density at the contact points in the memory element can be achieved.

[0119] Figure 10 is a schematic flow chart of a process of a memory device including a CAsSeGe OTS material as described herein.

[0120] In step 210, a first electrode is formed using a patterning technique, such as those discussed in the references incorporated hereinabove, the first electrode including the above-described materials and having an optional barrier layer.

[0121] In step 212, a switching layer including a CAsSeGe OTS material, among other materials, is formed, for example, in a sputtering chamber of a sputtering system, which has a target composed of a selected material. In some embodiments, the CAsSeGe material is deposited using a target composed of a selected material while forming a combination of multiple elements, and the amount of this combination of multiple elements effectively stabilizes the switching layer at the high temperatures discussed herein.

[0122] In step 214, the deposition of a barrier layer including a composition of silicon and carbon as described above, for example, is formed so that the barrier layer acts as a barrier against oxidation of the switching layer. In a preferred embodiment, this composition is formed by in situ sputtering in the same sputtering chamber as the OTS material or by forming this composition without exposing the OTS material to an oxidizing atmosphere.

[0123] In step 216, a memory material is formed on the barrier layer. The memory material can be a programmable resistive material, such as the phase change material or other materials described above.

[0124] In step 218, a second electrode is formed. The second electrode can be formed by deposition and patterned etch, such as the patterned etch of a conductive material.

[0125] A device can be completed using back - end - of - line (BEOL) processing. The back - end - of - line processing is used to complete the semiconductor process steps of a chip, including some manufacturing technologies that expose materials to a temperature on the order of 400°C or more. The back - end - of - line processing can be a standard process known in the art, and the execution of the process depends on the configuration of the chip in which the switching device is implemented. Generally, the structures formed by the back - end - of - line processing can include contacts, inter - layer dielectrics, and various metal layers of the interconnection structure on the chip, including the circuitry that couples the switching device to the peripheral circuitry. Due to these processes, Figure 11 the control circuit and the bias circuit shown are formed on the device.

[0126] Figure 11Schematic block diagram of an integrated circuit 300 including a 3D array 302 of crosspoint memory cells, the integrated circuit 300 having a CAsSeGe switching layer (SSL switch) and a programmable resistance memory layer as described herein. A row / level decoder 304 having read, set, and reset modes is coupled and electrically connected to a plurality of word lines 306, the plurality of word lines 306 being arranged along a plurality of columns in a plurality of layers within the array 302. A column / level decoder 308 is electrically connected to a plurality of bit lines 310, the plurality of bit lines 310 being arranged along a plurality of rows in a plurality of layers within the array 302 to perform read, set, and reset on the memory cells in the array 302. An address is supplied on a bus 312 to the row / level decoder 304 and the column / level decoder 308. Sense circuitry (sense amplifier) and a data-in structure within a block 314 including voltage and / or current sources having read, set, and reset modes are coupled to the row / level decoder (bit line decoder) 308 via a bus 316. Data is supplied to the data-in structure within the block 314 via a data-in line 318 from an input / output port above the integrated circuit 300 or from other data sources internal or external to the integrated circuit 300. Other circuitry 320 may be included on the integrated circuit 300, such as a general purpose processor, special purpose application circuitry, or a combination of multiple modules providing system-on-a-chip functionality supported by the array 302. Data is supplied from the sense amplifier within the block 314 to an input / output port above the integrated circuit 300 or to other data destinations internal or external to the integrated circuit 300 via a data-out line 322.

[0127] The controller 324 implementing the use of a bias arrangement state machine in this embodiment controls the application of a voltage source and a current source 326 of a bias circuitry for the application of a bias arrangement, including reading, setting, resetting, and verifying the voltages and / or currents of word lines and bit lines. During a read operation or other operations for accessing a selected memory cell, by applying a voltage to the selected memory cell to make the voltage on the switch in the selected memory cell higher than a threshold value, and by applying a voltage to the unselected memory cells to make the voltage on the switches in the unselected memory cells lower than the threshold value, the controller includes control circuitry for the switching layer described herein according to the structure and composition of the switching layer. In addition, the voltage applied to the unselected cells during the read of the selected memory cell is set such that during the read operation for accessing the selected memory cell, the off-state current is preferably less than 2 nA or less than 1 nA according to the structure and composition of the switching layer.

[0128] The controller 324 can be implemented using special-purpose logic circuitry known in the art. In other embodiments, the controller 324 includes a general-purpose processor that can be implemented on the same integrated circuit to execute a computer program to control the operation of the device. In other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor can be used for the implementation of the controller 324.

[0129] The specific embodiments described above further elaborate on the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A switching device, comprising: A first electrode; A second electrode; And A switching layer located between the first electrode and the second electrode, the switching layer comprising a composition of arsenic (As), selenium (Se), germanium (Ge) and carbon (C), carbon (C) being in the range of 10 at% to 30 at% of the composition, the composition further comprising arsenic (As) in the range of 20 at% to 35 at%, selenium (Se) in the range of 35 at% to 55 at% and germanium (Ge) in the range of 8 at% to 25 at%.

2. The switching device according to claim 1, wherein the amounts of arsenic (As), selenium (Se), germanium (Ge) and carbon (C) comprised in the composition effectively render the composition stable at temperatures above 400 °C.

3. The switching device according to claim 1, wherein the switching layer has a thickness of less than 50 nm, and the amounts of arsenic (As), selenium (Se), germanium (Ge) and carbon (C) comprised in the composition effectively effect switching using an applied voltage pulse within a period of less than 5 nanoseconds (ns) at a threshold voltage Vt < 4V.

4. The switching device according to claim 1, wherein the switching layer has a thickness of less than 50 nm, and the amounts of arsenic (As), selenium (Se), germanium (Ge) and carbon (C) comprised in the composition effectively render the switching layer having a crystallization transition temperature above 400 °C.

5. The switching device according to claim 1, wherein the switching layer has a thickness of less than 50 nm, and the amounts of arsenic (As), selenium (Se), germanium (Ge) and carbon (C) comprised in the composition effectively render the switching layer having a crystallization transition temperature above 450 °C.

6. The switching device according to claim 1, wherein the switching layer is of a thickness less than 50 nm.

7. The switching device according to claim 1, wherein the switching layer has a thickness in the range of 15 to 45 nm.

8. A memory device, comprising: A first electrode; A second electrode; A memory element in contact with the first electrode; A switching layer connected in series with the memory element, the switching layer located between the first electrode and the second electrode, the switching layer comprising a composition of arsenic (As), selenium (Se), germanium (Ge) and carbon (C), carbon (C) being in the range of 10 at% to 30 at% of the composition; and A barrier layer located between the memory element and the switching layer, wherein the composition comprises arsenic (As) in the range of 20 at% to 35 at%, selenium (Se) in the range of 35 at% to 55 at% and germanium (Ge) in the range of 8 at% to 25 at%.

9. The memory device according to claim 8, wherein the switching layer has a thickness of less than 50 nm, and the amounts of arsenic (As), selenium (Se), germanium (Ge) and carbon (C) comprised in the composition effectively effect switching using an applied voltage pulse within a period of less than 5 nanoseconds (ns) at a threshold voltage Vt < 4V.

10. A switching device, comprising: A first electrode; a second electrode; and a memory element and a switching layer electrically connected in series between the first electrode and the second electrode, the switching layer including a composition of arsenic (As), selenium (Se), germanium (Ge), and carbon (C), the composition further including arsenic (As) in the range of 20 at% to 35 at%, selenium (Se) in the range of 35 at% to 55 at%, and germanium (Ge) in the range of 8 at% to 25 at%.

11. The switching device according to claim 10, wherein, The switching layer has a thickness of less than 50 nm, and the amounts of arsenic (As), selenium (Se), germanium (Ge), and carbon (C) included in the composition are effective to switch using an applied voltage pulse in a period of less than 5 nanoseconds (ns) with a threshold voltage Vt < 4V.

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