Substrate with embedded electronic components

Abstract

The present disclosure provides a substrate embedded with electronic components, the substrate embedded with electronic components comprising: a first core layer; a first through-portion penetrating the first core layer; a first electronic component disposed in the first through-portion; an encapsulant disposed in at least a portion of the first through-portion and covering at least a portion of the first electronic component; a second core layer disposed on the encapsulant; and a first through-via penetrating the second core layer, wherein the first through-via is connected to the first electronic component.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0168945 filed on December 17, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a substrate with embedded electronic components. Background Art

[0003] Recently, electronic devices such as mobile phones, tablet PCs, etc. are required to have miniaturized and slim sizes while maintaining high performance. Therefore, a technology for a substrate embedded with electronic components (such as passive elements, active elements, etc.) to be embedded in a printed circuit board has been developed.

[0004] Furthermore, in the case of such an electronic component embedded substrate, problems such as shortened life and performance degradation of the electronic component may occur due to heat generation of the embedded electronic component. Therefore, an embedded structure for dissipating heat from the electronic component embedded substrate is required. Summary of the invention

[0005] An aspect of the present disclosure is to provide an electronic component-embedded substrate having improved heat dissipation performance.

[0006] Another aspect of the present disclosure is to provide an electronic component embedded substrate utilizing an area other than an area where the electronic component is mounted in the substrate.

[0007] According to one aspect of the present disclosure, a substrate embedded with an electronic component includes: a first core layer; a first through-portion penetrating the first core layer; a first electronic component disposed in the first through-portion; an encapsulant disposed in at least a portion of the first through-portion and covering at least a portion of the first electronic component; a second core layer disposed on the encapsulant; and a first through-via penetrating the second core layer. The first through-via is connected to the first electronic component.

[0008] According to one aspect of the present disclosure, a substrate embedded with an electronic component includes: a core layer; a through-portion penetrating the core layer; an electronic component disposed in the through-portion; an encapsulant disposed in at least a portion of the through-portion and covering at least a portion of the electronic component; an accumulation layer disposed on an upper side of the encapsulant and including a metal layer connected to a pad of the electronic component; an insulating layer disposed on a lower side of the encapsulant opposite to the upper side of the encapsulant; a through-via penetrating the insulating layer; and a conductive structure embedded in the encapsulant and connecting the through-via and the electronic component to each other. The conductive structure and the metal layer are made of different materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic diagram illustrating an example of a block diagram of an electronic device system according to an example;

[0011] Figure 2 is a schematic perspective view showing an electronic device according to an example;

[0012] Figure 3 is a schematic cross-sectional view of a substrate with embedded electronic components according to an example;

[0013] Figure 4 is a schematic cross-sectional view of a substrate with embedded electronic components according to another example;

[0014] Figure 5 is a schematic cross-sectional view of a substrate with embedded electronic components according to another example;

[0015] Figure 6 is a schematic cross-sectional view of a substrate with embedded electronic components according to another example;

[0016] 7A to 9E is a schematic diagram showing a portion of a manufacturing process of a substrate embedded with electronic components according to an example; and

[0017] Fig.10 is a schematic cross-sectional view showing an example of a case in which a semiconductor package is mounted on an electronic component-embedded substrate according to an example. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes, sizes, etc. of elements may be exaggerated or simplified for clarity of description.

[0019] Electronic Devices

[0020] Figure 1 is a diagram illustrating an example of a block diagram of an electronic device system according to an example.

[0021] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically and / or electrically connected thereto. These components may be connected to other components to be described below via various signal lines 1090.

[0022] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0023] The network-related components 1030 may include components designated to operate according to protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols designated after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components designated to operate according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0024] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or the network-related components 1030.

[0025] The electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010, depending on the type of the electronic device 1000. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000, etc.

[0026] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0027] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0028] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically or electrically connected to the mainboard 1110 may be housed in the mainboard 1110. A portion of the electronic component 1120 may be a chip-related component (e.g., a semiconductor package 1121), but is not limited thereto. The semiconductor package 1121 may be a surface-mounted type, such as a semiconductor chip or a passive component on a package board of a multi-layer printed circuit board, but is not limited thereto. In addition, the electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0029] Substrate with embedded electronic components

[0030] Figure 3 is a schematic cross-sectional view of a substrate 100A in which electronic components are embedded according to an example.

[0031] Reference Figure 3According to the example, the substrate 100A embedded with electronic components may include: a first core layer 110; a first through-portion 100HA and a second through-portion 100HB formed in the first core layer 110; a first electronic component 120A and a second electronic component 120B, respectively disposed in the first through-portion 110HA and the second through-portion 110HB; an encapsulant 130, covering at least a portion of each of the first electronic component 120A and the second electronic component 120B, and filling at least a portion of each of the first through-portion 110HA and the second through-portion 110HB; a conductive via 133, penetrating at least a portion of the encapsulant 130, and connected to each of the first electronic component 120A and the second electronic component 120B; a conductive pattern 132, buried in the encapsulant 130 and connected to the conductive via 133; a second core layer 140, disposed on the encapsulant 130; a first through-portion 143A, penetrating the second core layer 140 and connecting to the first electronic component 120A; a second through via 143B, penetrating the second core layer 140 and connected to the second electronic component 120B; an insulating layer 150, disposed on the second core layer 140; a third through via 160, penetrating the first core layer 110, the encapsulant 130, the second core layer 140 and the insulating layer 150; a first build-up layer 210, disposed on the first core layer 110, and including one or more metal layers 212A to 212C connected to each of the first electronic component 120A, the second electronic component 120B and the third through via 160; a second build-up layer 220, disposed on the second core layer 140 and including one or more metal layers 222A to 222C connected to each of the first through via 143A, the second through via 143B and the third through via 160; a first passivation layer 310, disposed on the first build-up layer 210; and a second passivation layer 320, disposed on the second build-up layer 220.

[0032] In the case of a substrate with embedded electronic components, problems such as shortened life and performance degradation of the electronic components may occur due to heat generation of the embedded electronic components. When a portion of the inner area of ​​the substrate with embedded electronic components is used as a heat dissipation structure, it is feasible to provide a substrate with embedded electronic components having improved heat dissipation performance while maintaining the overall size of the substrate.

[0033] In the case of the electronic component embedded substrate 100A according to the example, each of the first electronic component 120A and the second electronic component 120B respectively disposed in the first through-portion 110HA and the second through-portion 110HB of the first core layer 110 can be connected to the through vias 143A and 143B penetrating the second core layer 140 through the conductive pattern 132.

[0034] Specifically, in the case of the electronic component-embedded substrate 100A according to the example, each of the first through-hole 143A and the second through-hole 143B can be connected to the corresponding electrode pads (pads, also referred to as "pads") 120AP and 120BP of the first electronic component 120A and the second electronic component 120B. However, the present disclosure is not limited thereto, but can be modified into electronic component-embedded substrates 100B to 100D according to another example.

[0035] The insulating layer 150 and the second build-up layer 220 may be further disposed on the second core layer 140. In this case, each of the first through via 143A and the second through via 143B may be connected to the metal vias 223A to 223C of the second build-up layer 220 and the metal layers 222A to 222C.

[0036] Therefore, the heat generated in each of the first electronic component 120A and the second electronic component 120B can be dissipated to the outside of the substrate through the conductive via 133, the conductive pattern 132, the first through via 143A or the second through via 143B, the metal vias 223A to 223C, and the metal layers 222A to 222C. Therefore, problems such as shortened life and performance degradation of electronic components caused by heat generation of embedded electronic components can be improved.

[0037] In addition, when it is required to provide a substrate with embedded electronic components including a core layer having a predetermined thickness or more, a partial area of ​​the core layer 140 (a portion of the core layer) can be used as an area for heat dissipation. Therefore, a substrate with embedded electronic components having improved heat dissipation performance while maintaining the overall size of the substrate can be provided.

[0038] Hereinafter, each configuration of the electronic component-embedded substrate 100A according to examples will be described in more detail.

[0039] The material of the first core layer 110 is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth or glass fabric (for example, a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used. The thickness of the first core layer 110 may be greater than the thickness of the insulating layer 150 and the thickness of each of the first accumulation layer 210 and the second accumulation layer 220.

[0040] Each of the first through-portion 110HA and the second through-portion 110HB may penetrate at least a portion of the first core layer 110. Although the drawings show a case where the first core layer 110 has two through-portions, the number of through-portions may be less than or greater than the number shown in the drawings. For example, the first core layer 110 may have only the first through-portion 110HA, or may also have a third through-portion. However, it is not limited thereto.

[0041] Each of the first electronic component 120A and the second electronic component 120B may be a passive component such as a multilayer ceramic capacitor (MLCC), a power inductor (PI), etc., or an active component such as an integrated circuit (IC) and a die.

[0042] The first electronic component 120A and the second electronic component 120B may include bodies 120AB and 120BB, respectively. In addition, the first electronic component 120A and the second electronic component 120B may include electrode pads 120AP and 120BP, respectively. Therefore, the first through-via 143A and the second through-via 143B may be connected to the bodies 120AB and 120BB and / or the electrode pads 120AP and 120BP of each of the first electronic component 120A and the second electronic component 120B, respectively.

[0043] In the drawings, two electronic components (first electronic component 120A and second electronic component 120B) are shown, but the number of embedded electronic components may be less than or greater than the number of embedded electronic components shown in the drawings. In addition, although it is shown that one electronic component is provided in each of the first through-portion 110HA and the second through-portion 110HB, the number of electronic components provided in one through-portion may be greater than or less than the number shown in the drawings. For example, a third electronic component may also be provided in the first through-portion 110HA. However, it is not limited thereto.

[0044] The material of the encapsulant 130 is not particularly limited, but any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth or glass fabric (e.g., prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0045] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as the formation material of the conductive via 133. The conductive via 133 may be completely filled with the conductive material, or the conductive material may be formed along the wall of the via hole. In addition, the shape of the conductive via 133 may be any shape known in the art, such as a conical shape, a cylindrical shape, etc.

[0046] As a formation material of the conductive pattern 132 , a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used.

[0047] The conductive vias 133 and the conductive pattern 132 may be connected to the first through via 143A and the second through via 143B. Therefore, heat generated in the first electronic component 120A and the second electronic component 120B may be dissipated to the outside of the substrate in which the electronic components are embedded through the conductive vias 133 and the conductive pattern 132 through the first through via 143A or the second through via 143B, respectively.

[0048] The material of the second core layer 140 is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth or glass fabric (for example, a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used. The thickness of the second core layer 140 may be greater than the thickness of the insulating layer 150 and the thickness of each of the first accumulation layer 210 and the second accumulation layer 220.

[0049] As a forming material of each of the first through-via 143A and the second through-via 143B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. Each of the first through-via 143A and the second through-via 143B may be completely filled with the conductive material, or the conductive material may be formed along the wall of the via hole. When each of the first through-via 143A and the second through-via 143B is formed so that the conductive material is formed along the wall of the via hole, the inner side of the wall of the via hole may be filled with an insulating material (not shown) or the like. In addition, the shape of each of the first through-via 143A and the second through-via 143B may be all shapes known in the art, such as a conical shape, a cylindrical shape, and the like.

[0050] The first through via 143A and the second through via 143B may penetrate the second core layer 140 and connect the conductive pattern 132 and the first to third metal layers 222A to 222C of the second build-up layer 220. Therefore, heat generated in the first electronic component 120A and the second electronic component 120B may be dissipated to the outside of the substrate in which the electronic components are embedded through the conductive via 133, the conductive pattern 132, the first through via 143A or the second through via 143B and the first to third metal layers 222A to 222C of the second build-up layer 220.

[0051] The material of the insulating layer 150 is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth or glass fabric (e.g., prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0052] A conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used as a forming material of the third through via 160. The through via 160 may be completely filled with the conductive material, or the conductive material may be formed along the wall of the via hole. As shown in the drawings, when the through via 160 is formed along the wall of the via hole, the inside of the wall of the via hole may be filled with an insulating material (not shown) or the like. In addition, the shape of the through via 160 may have all shapes in the art, such as a tapered shape, a cylindrical shape, and the like.

[0053] The through via 160 may penetrate the first core layer 110 , the encapsulant 130 , the second core layer 140 , and the insulating layer 150 , and may connect the first to third metal layers 212A to 212C of the first build-up layer 210 and the first to third metal layers 222A to 222C of the second build-up layer 220 to each other.

[0054] The first accumulation layer 210 may include: a first metal layer 212A, which is disposed on the encapsulant 130; a first metal via 213A, which penetrates a portion of the encapsulant 130 and connects the electronic components 120A and 120B and the first metal layer 212A; a first insulating layer 211A, which is disposed on the encapsulant 130 and covers the first metal layer 212A; a second metal layer 212B, which is disposed on the first insulating layer 211A; a second metal via 213B, which penetrates a portion of the first insulating layer 211A and connects the first metal layer 212A and the second metal layer 212B; a second insulating layer 211B, which is disposed on the first insulating layer 211A and covers the second metal layer 212B; a third metal layer 212C, which is disposed on the second insulating layer 211B; and a third metal via 213C, which penetrates a portion of the second insulating layer 211B and connects the second metal layer 212B and the third metal layer 212C.

[0055] However, the present disclosure is not limited thereto, but may be varied as much as possible within the scope of the creativity of those skilled in the art. That is, the number of insulating layers, metal layers, and metal vias included in the first accumulation layer 210 may be greater or less than the number of insulating layers, metal layers, and metal vias included in the first accumulation layer 210 shown in the drawings.

[0056] The material of each of the first insulating layer 211A to the second insulating layer 211B is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth or glass fabric (for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0057] The boundary between the first insulating layer 211A and the second insulating layer 211B may not be distinguishable depending on the material, process, etc. of each of the insulating layers. That is, during the lamination process, the first insulating layer 211A and the second insulating layer 211B may be integrated with each other, or the boundary surface therebetween may not be clear, making it difficult to visually determine the boundary therebetween in the structure of the complete substrate embedded with electronic components.

[0058] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as the formation materials of the first metal layer 212A to the third metal layer 212C. Each of the first metal layer 212A to the third metal layer 212C may perform various functions according to the design. For example, each of the first metal layer 212A to the third metal layer 212C may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern, etc. In addition, a via pad, a connection terminal pad, etc. may be included. In addition, the conductive structure embedded in the encapsulant and the metal layer in the accumulation layer can be made of different materials. For example, the conductive structure embedded in the encapsulant 130 (including the conductive via 133 and the conductive pattern 132) and the first metal layer 212A to the third metal layer 212C of the first accumulation layer 210 can be made of different materials.

[0059] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as the formation material of the first metal vias 213A to the third metal vias 213C. Each of the first metal vias 213A to the third metal vias 213C may be completely filled with a conductive material, or a conductive material may be formed along the wall of the via hole. In addition, the shapes of the first metal vias 213A to the third metal vias 213C may be all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0060] The second accumulation layer 220 may include: a first metal layer 222A, which is disposed on the insulating layer 150; a first metal via 223A, which penetrates the insulating layer 150 and connects the first through via 143A and the second through via 143B to the first metal layer 222A; a first insulating layer 221A, which is disposed on the insulating layer 150 and covers the first metal layer 222A; a second metal layer 222B, which is disposed on the first insulating layer 221A; a second metal via 223B, which penetrates a portion of the first insulating layer 221A and connects the first metal layer 222A and the second metal layer 222B; a second insulating layer 221B, which is disposed on the first insulating layer 221A and covers the second metal layer 222B; a third metal layer 222C, which is disposed on the second insulating layer 221B; and a third metal via 223C, which penetrates a portion of the second insulating layer 221B and connects the second metal layer 222B and the third metal layer 222C.

[0061] However, the present disclosure is not limited thereto, but may be varied as much as possible within the scope that can be implemented by those skilled in the art. That is, the number of insulating layers, metal layers, and metal vias included in the second build-up layer 220 may be greater or less than the number of insulating layers, metal layers, and metal vias included in the second build-up layer 220 shown in the drawings.

[0062] The material of each of the first insulating layer 221A to the second insulating layer 221B is not particularly limited, and any material can be used as long as it has insulating properties. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth or glass fabric (for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0063] The boundary between the first insulating layer 221A and the second insulating layer 221B may not be distinguishable depending on the material, process, etc. of each of the insulating layers. That is, during the lamination process, the first insulating layer 221A and the second insulating layer 221B may be integrated with each other, or the boundary surface therebetween may not be clear, making it difficult to visually determine the boundary therebetween with the naked eye in the structure of the complete substrate embedded with electronic components.

[0064] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as the formation materials of the first metal layer 222A to the third metal layer 222C. The first metal layer 222A to the third metal layer 222C may perform various functions according to the design. For example, each of the first metal layer 222A to the third metal layer 222C may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern, etc. In addition, a via pad, a connection terminal pad, etc. may be included.

[0065] Specifically, the first to third metal layers 222A to 222C may include metal patterns connected to the first through vias 143A and the second through vias 143B. Therefore, as described above, heat generated in the first electronic component 120A and the second electronic component 120B may be dissipated to the outside of the substrate through the conductive vias 133, the conductive patterns 132, the through vias 143A and 143B, the metal vias 223A to 223C, and the metal layers 222A to 222C.

[0066] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as the formation materials of the first metal vias 223A to the third metal vias 223C. The first metal vias 223A to the third metal vias 223C may perform various functions according to the design. Each of the first metal vias 223A to the third metal vias 223C may be completely filled with a conductive material, or a conductive material may be formed along the wall of the via hole. In addition, the shape of each of the first metal vias 223A to the third metal vias 223C may be all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0067] The first passivation layer 310 is an additional configuration for protecting the first accumulation layer 210 from external physical damage and / or chemical damage, etc. The first passivation layer 310 may have an opening for exposing at least a portion of the metal layer 212C of the first accumulation layer 210. The material of the first passivation layer 310 is not particularly limited. For example, a photosensitive insulating material such as a photosensitive insulating resin or a solder resist may be used, but is not limited thereto.

[0068] The second passivation layer 320 is an additional configuration for protecting the second build-up layer 220 from external physical damage and / or chemical damage, etc. The second passivation layer 320 may have an opening for exposing at least a portion of the metal layer 222C of the second build-up layer 220. The material of the second passivation layer 320 is not particularly limited. For example, a photosensitive insulating material such as a photosensitive insulating resin or a solder resist may be used, but is not limited thereto.

[0069] Figure 4 is a schematic cross-sectional view showing an electronic component-embedded substrate 100B according to another example.

[0070] Reference Figure 4 , the electronic component-embedded substrate 100B according to another example may include a metal pattern in which at least one metal layer among the first metal layer 222A to the third metal layer 222C of the second build-up layer 220 connects the first through via 143A and the second through via 143B in the electronic component-embedded substrate 100A according to the example. For example, as shown in the drawings, the first metal layer 222A may include a metal pattern connecting the first through via 143A and the second through via 143B, but is not limited thereto.

[0071] The other contents are substantially the same as those described in the electronic component-embedded substrate 100A according to the example, and thus a detailed description thereof will be omitted.

[0072] Figure 5 is a schematic cross-sectional view showing an electronic component-embedded substrate 100C according to another example.

[0073] Reference Figure 5 In the electronic component embedded substrate 100C according to another example, the first through-hole 143A and the second through-hole 143B may be respectively connected to the bodies 120AB and 120BB of the first electronic component 120A and the second electronic component 120B in the electronic component embedded substrate 100A according to the above example.

[0074] The other contents are substantially the same as those described in the electronic component-embedded substrate 100A according to the example, and thus a detailed description thereof will be omitted.

[0075] Figure 6 is a schematic cross-sectional view showing an electronic component-embedded substrate 100D according to another example.

[0076] Reference Figure 6 In the electronic component-embedded substrate 100D according to another example, the first through-hole 143A may be connected to the respective bodies 120AB and 120BB of the first electronic component 120A and the second electronic component 120B in the electronic component-embedded substrate 100A according to the above example. Therefore, heat generated in the plurality of electronic components 120A and 120B may be dissipated to the outside of the substrate through one through-hole 143A.

[0077] 7A to 9E is a diagram illustrating a portion of a manufacturing process of an electronic component-embedded substrate 100A according to an example.

[0078] Reference Fig. 7A , a first through portion 110HA and a second through portion 110HB penetrating the first core layer 110 are respectively formed, and then an adhesive film 410 is attached to one side of the first core layer 110 .

[0079] The formation of each of the first through-portion 110HA and the second through-portion 110HB may be performed by a sandblasting method using abrasive particles, a dry etching method using plasma, etc. However, the present disclosure is not limited thereto, and each of the first through-portion 110HA and the second through-portion 110HB may be formed by using mechanical drilling, laser drilling, etc. When the first through-portion 110HA and the second through-portion 110HB are formed using mechanical drilling, laser drilling, etc., a desmear treatment such as a permanganate method may be performed to remove resin smears in the first through-portion 110HA and the second through-portion 110HB.

[0080] The adhesive film 410 may be used as long as the first core layer 110 can be fixed, and as a non-limiting example, a known tape or the like may be used. Examples of the known tape may be a heat-treatment curable adhesive tape having weakened adhesive force by heat treatment, an ultraviolet curable adhesive tape having weakened adhesive force by ultraviolet irradiation, or the like.

[0081] Reference Figure 7B , the first electronic component 120A and the second electronic component 120B may be respectively disposed in the first through-portion 110HA and the second through-portion 110HB, and then the first electronic component 120A and the second electronic component 120B may be encapsulated using an encapsulant 130A.

[0082] The first electronic component 120A and the second electronic component 120B may be arranged so that the first electronic component 120A and the second electronic component 120B are attached to the adhesive film 410 in the first through-portion 110HA and the second through-portion 110HB, respectively. Therefore, one surface of the first core layer 110 and one surface of each of the first electronic component 120A and the second electronic component 120B may be substantially located on the same plane. That is, one surface of the first core layer 110 and one surface of each of the first electronic component 120A and the second electronic component 120B may be coplanar. In this case, in each of the first through-portion 110HA and the second through-portion 110HB, each of the first electronic component 120A and the second electronic component 120B may be arranged to be spaced apart from the first core layer 110 by a predetermined distance.

[0083] The encapsulant 130A may cover at least a portion of each of the first electronic component 120A and the second electronic component 120B, and may fill at least a portion of the space in each of the first through-portion 110HA and the second through-portion 110HB. The encapsulant 130A may be formed by a known method, for example, the encapsulant 130A may be formed by laminating a precursor and then curing. Alternatively, the encapsulant 130A may be formed by coating the encapsulant 130A on the adhesive film 410 to encapsulate the first electronic component 120A and the second electronic component 120B and then curing. The first electronic component 120A and the second electronic component 120B may be fixed by curing.

[0084] Reference Figure 7C , a via hole 133H penetrating a portion of the encapsulant 130A and exposing the electrode pad 120AP of the first electronic component 120A and the electrode pad 120BP of the second electronic component 120B may be formed. In addition, the adhesive film 410 may be peeled off.

[0085] The via hole 133H may be formed using photolithography, mechanical drilling, laser drilling, or the like.

[0086] The peeling method of the adhesive film 410 is not particularly limited, but can be performed by a known method. For example, when a heat-treatment curable adhesive tape having a weakened adhesive force by heat treatment, an ultraviolet curable adhesive tape having a weakened adhesive force by ultraviolet irradiation, or the like is used, the peeling method of the adhesive film 410 can be performed after weakening the adhesive force by heat-treating the adhesive film 410, or after weakening the adhesive force by irradiating ultraviolet rays to the adhesive film 410.

[0087] Reference Fig.7D , a conductive paste 420 may be disposed in the via hole 133H.

[0088] As the conductive paste 420, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The conductive paste 420 may be arranged to protrude further than the upper surface of the via hole 133H. Therefore, as described later, the conductive paste may flow into the through-portion 130BH of the encapsulant 130B that has been formed. The conductive paste 420 arranged in the via hole 133H may form a conductive via 133, and the conductive paste 420 arranged in the through-portion 130BH of the encapsulant 130B may form a conductive pattern 132.

[0089] Reference Fig. 8A , the second core layer 140 may be prepared first, and then the first through portion 143AH and the second through portion 143BH penetrating the second core layer 140 may be formed.

[0090] Each of the first through-portion 143AH and the second through-portion 143BH may be formed by photolithography, mechanical drilling, laser drilling, etc. When the first through-portion 143AH and the second through-portion 143BH are formed by using mechanical drilling, laser drilling, etc., a desmear treatment such as a permanganate method may be performed to remove resin smears in the first through-portion 143AH and the second through-portion 143BH. However, the present disclosure is not limited thereto, and if necessary, the formation of each of the first through-portion 143AH and the second through-portion 143BH may be performed by a sandblasting method using abrasive particles, a dry etching method using plasma, etc.

[0091] Reference Figure 8B , a plating process may be performed in each of the first through-portion 143AH and the second through-portion 143BH to form the first through-hole 143A and the second through-hole 143B. Electroplating or electroless plating (specifically, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), etc.) may be used as the plating process, but is not limited thereto.

[0092] Each of the first through-hole 143AH and the second through-hole 143BH may be completely filled with a conductive material, or may be formed along the wall of the via hole. When each of the first through-hole 143AH and the second through-hole 143BH is formed so that a conductive material is formed along the wall of the via hole, the inner side of the wall of the via hole may be filled with an insulating material (not shown).

[0093] Reference Fig.9A and Fig. 9B , sequentially stacking metal plate 440, encapsulant 130C, 7A to 7C The structure including the first core layer 110, the electronic components 120A and 120B, the encapsulant 130A and the conductive paste 420 is formed by the process, the encapsulant 130B having the through portion 130BH therein, and the conductive paste 420 is formed by the process. FIG. 8A to FIG. 8B The structure including the second core layer 140 and the through vias 143A and 143B, the insulating layer 150 and the metal plate 430 is formed by the process.

[0094] In this case, the forming materials of the encapsulants 130A, 130B, and 130C and the insulating layer 150 may be in an uncured state or a semi-cured state. Therefore, the boundaries between the encapsulants 130A, 130B, and 130C after lamination may not be distinguished depending on the material, process, etc. of each insulating layer. That is, the forming materials of the encapsulants 130A, 130B, and 130C may be integrated with each other during the lamination process, or the boundary surface between them may not be clear, making it difficult to visually determine the boundaries between them with the naked eye in the structure of the complete substrate embedded with electronic components. For example, in Figure 3 , the encapsulants 130A, 130B, and 130C are shown as one encapsulant 130 integrated with each other and they have no boundary surfaces. Figure 3 Unlike shown in FIG. 1 , the encapsulant 130 may include two or more layers separated from each other.

[0095] In addition, the conductive paste 420 may flow into the through-portion 130BH formed in the encapsulant 130B. Fig. 9B As shown in , a conductive via 133 and a conductive pattern 132 may be formed. That is, the conductive paste 420 disposed in the via hole 133H may form the conductive via 133, and the conductive paste 420 disposed in the through portion 130BH of the encapsulant 130B may form the conductive pattern 132. Therefore, the conductive pattern 132 and the conductive via 133 made of the same material may be a conductive structure for connecting the through via 143A or 143B to the electronic component 120A or 120B.

[0096] Reference Fig. 9C, the metal plates 440 and 430 may be removed by a known etching method or the like, and the third through portion 160H may be formed.

[0097] The third through-portions 160H may be formed by photolithography, mechanical drilling, laser drilling, etc. When the third through-portions 160H are formed by using mechanical drilling and / or laser drilling, a desmear treatment such as a permanganate method may be performed to remove resin smears in the third through-portions 160H. However, the present disclosure is not limited thereto, and if necessary, the formation of each of the third through-portions 160H may be performed by a sandblasting method using abrasive particles, a dry etching method using plasma, etc.

[0098] Reference Fig.9D , a plating process may be performed in the third through portion 160H to form the third through via 160 .

[0099] As the plating process, electroplating or electroless plating (specifically, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), etc.) may be used, but is not limited thereto.

[0100] The third through via 160 may be formed by filling with a conductive material, or a conductive material may be formed along a wall of the via hole. When the third through via 160 is formed such that a conductive material is formed along a wall of the via hole, the inside of the via hole may be filled with an insulating material (not shown).

[0101] Reference Fig.9E , the first accumulation layer 210 and the second accumulation layer 220 may be formed on both surfaces of the substrate.

[0102] In the case of the first accumulation layer 210, first, a metal via 213A penetrating the encapsulant 130 may be formed. In addition, a first metal layer 212A may be formed on the encapsulant 130. Next, a first insulating layer 211A covering the first metal layer 212A may be formed on the encapsulant 130. Thereafter, a second metal via 213B penetrating the first insulating layer 211A may be formed. In addition, a second metal layer 212B may be formed on the first insulating layer 211A. Next, a second insulating layer 211B covering the second metal layer 212B may be formed on the first insulating layer 211A. Thereafter, a third metal via 213C penetrating the second insulating layer 211B may be formed. In addition, a third metal layer 212C may be formed on the second insulating layer 211B.

[0103] The first metal via 213A to the third metal via 213C and the first metal layer 212A to the third metal layer 212C can be formed by the following steps: forming a via hole in the encapsulant 130 or in the first insulating layer 211A to the second insulating layer 211B using photolithography, mechanical drilling, laser drilling, etc., and then patterning the first insulating layer 211A to the second insulating layer 211B by a dry film, etc., and filling the via hole and the patterned space by a plating process, etc.

[0104] The first to second insulating layers 211A and 211B may be formed by laminating precursors by a known lamination method and then curing the precursors, or by coating a precursor material by a known coating method and then curing it.

[0105] In the case of the second accumulation layer 220, a first metal via 223A penetrating the insulating layer 150 may be formed. In addition, a first metal layer 222A may be formed on the insulating layer. Next, a first insulating layer 221A covering the first metal layer 222A may be formed on the insulating layer 150. Thereafter, a second metal via 223B penetrating the first insulating layer 221A may be formed. In addition, a second metal layer 222B may be formed on the first insulating layer 221A. Next, a second insulating layer 221B covering the second metal layer 222B may be formed on the first insulating layer 221A. Thereafter, a third metal via 223C penetrating the second insulating layer 221B may be formed. In addition, a third metal layer 222C may be formed on the second insulating layer 221B. These formation methods are the same as the formation method of the first accumulation layer 210.

[0106] If necessary, the first passivation layer 310 and the second passivation layer 320 may be respectively formed on the first accumulation layer 210 and the second accumulation layer 220. Each of the first passivation layer 310 and the second passivation layer 320 may be formed by laminating a precursor of each of the first passivation layer 310 and the second passivation layer 320 and then curing them, or by coating a forming material of each of the first passivation layer 310 and the second passivation layer 320 and then curing them. An opening (not marked) may be formed so that at least a portion of the metal layer 212C of the first accumulation layer 210 and at least a portion of the metal layer 222C of the second accumulation layer 220 are exposed.

[0107] The manufacturing process of the electronic component-embedded substrate 100A according to the example may be changed within the range that can be implemented by those skilled in the art. For example, the material, manufacturing sequence and / or manufacturing method of each configuration may be changed.

[0108] Fig.10 is a schematic cross-sectional view of an example in which a semiconductor package 510 is mounted on an electronic component-embedded substrate 100A according to an example.

[0109] Reference Fig.10 , the semiconductor package 510 may be mounted on the first build-up layer 210 through the connection terminal 520. Therefore, the semiconductor chip in the semiconductor package 510 may be electrically connected to the electronic component-embedded substrate 100A according to an example.

[0110] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" by means of an adhesive layer or the like. In addition, the term "electrical connection" may include both a case where an element is "physically connected" and a case where an element is "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one element from another, and may not limit the order and / or importance or other aspects of the elements. In some cases, without departing from the scope of rights of example embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0111] In the example embodiments, the term "example embodiment" may not refer to one and the same example embodiment, but may be provided to describe and emphasize different unique features of each example embodiment. The example embodiments set forth above may be implemented without excluding the possibility of combination with features of other example embodiments. For example, unless otherwise indicated, even if a feature described in one example embodiment is not described in other example embodiments, the feature may also be understood to be relevant to other example embodiments.

[0112] The terms used in the exemplary embodiments are only used to describe the exemplary embodiments and are not intended to limit the present disclosure. Unless otherwise specified, singular terms include plural forms.

[0113] As described above, as one of the various effects of the present disclosure, it is possible to provide an electronic component-embedded substrate having improved heat dissipation performance.

[0114] As another one of the various effects of the present disclosure, it is possible to provide an electronic component-embedded substrate utilizing an area other than an area in which the electronic component is mounted in the substrate.

[0115] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A substrate embedded with electronic components, comprising: The first core layer; A first through portion, penetrating the first core layer; A first electronic component is disposed in the first through-portion; an encapsulant disposed in at least a portion of the first through-portion and covering at least a portion of the first electronic component; a metal layer disposed on an upper side of the encapsulant and connected to the first electronic component; a metal via extending through at least a portion of the encapsulant and connecting the metal layer to the first electronic component; a second core layer disposed on a lower side of the encapsulant opposite the upper side of the encapsulant; as well as A first through hole penetrates the second core layer, Wherein, the first through via is connected to the first electronic component.

2. The substrate with embedded electronic components according to claim 1, further comprising: a first conductive via extending through at least a portion of the encapsulant and connected to the first electronic component; as well as a first conductive pattern, buried in the encapsulant and connected to the first conductive via, Wherein, the first electronic component is connected to the first through-via through the first conductive via and the first conductive pattern.

3. The electronic component embedded substrate according to claim 1, wherein: The first electronic component includes a first body and a first electrode pad, and The first through via is connected to the first body of the first electronic component.

4. The electronic component embedded substrate according to claim 1, wherein: The first electronic component includes a first body and a first electrode pad, and The first through via is connected to the first electrode pad of the first electronic component.

5. The substrate embedded with electronic components according to claim 1, further comprising: a second through portion, penetrating the first core layer and arranged to be spaced apart from the first through portion; A second electronic component is disposed in the second through portion; as well as A second through hole penetrates the second core layer, wherein the encapsulant is disposed in at least a portion of the second through-portion and covers at least a portion of the second electronic component, and The second through via is connected to the second electronic component.

6. The substrate embedded with electronic components according to claim 5, further comprising: The first build-up layer is disposed on the second core layer and includes a first metal layer.

7. The electronic component embedded substrate according to claim 6, wherein: The first electronic component includes a first body and a first electrode pad, and The second electronic component includes a second body and a second electrode pad.

8. The electronic component embedded substrate according to claim 7, wherein: The first through via and the second through via are connected to the first electrode pad of the first electronic component and the second electrode pad of the second electronic component, respectively.

9. The electronic component embedded substrate according to claim 8, wherein: The first metal layer includes: a first metal pattern connected to the first through via; and a second metal pattern connected to the second through via.

10. The electronic component embedded substrate according to claim 8, wherein: The first metal layer includes a first metal pattern connecting the first through via and the second through via.

11. The electronic component embedded substrate according to claim 7, wherein: The first through via and the second through via are connected to the first body of the first electronic component and the second body of the second electronic component, respectively.

12. The electronic component embedded substrate according to claim 11, wherein: The first metal layer includes: a first metal pattern connected to the first through via; and a second metal pattern connected to the second through via.

13. The substrate with embedded electronic components according to claim 1, further comprising: a second through portion, penetrating the first core layer and arranged to be spaced apart from the first through portion; as well as A second electronic component is disposed in the second through-portion, wherein the encapsulant is disposed in at least a portion of the second through-portion and covers at least a portion of the second electronic component, and The first through via is connected to a body of the second electronic component.

14. The substrate with embedded electronic components according to claim 13, further comprising: A first build-up layer is disposed on the second core layer and includes a first metal layer connected to the first through via.

15. The substrate with embedded electronic components according to claim 14, further comprising: The second build-up layer is disposed on the first core layer and includes the metal layer.

16. The substrate with embedded electronic components according to claim 15, further comprising: A third through hole penetrates the first core layer, the encapsulant and the second core layer, The third through via connects the first metal layer and the metal layer.

17. The electronic component embedded substrate according to claim 15, wherein: A thickness of each of the first core layer and the second core layer is greater than a thickness of each of the first build-up layer and the second build-up layer.

18. A substrate embedded with electronic components, comprising: Core layer; A through portion, penetrating through the core layer; An electronic component is disposed in the through-portion; an encapsulant disposed in at least a portion of the through-portion and covering at least a portion of the electronic component; a build-up layer disposed on an upper side of the encapsulant and comprising a metal layer connected to a pad of the electronic component through a metal via extending through at least a portion of the encapsulant; an insulating layer disposed on a lower side of the encapsulant opposite to the upper side of the encapsulant; A through hole penetrates the insulating layer; as well as a conductive structure embedded in the encapsulant and connecting the through via and the electronic component to each other, Wherein, the conductive structure and the metal layer are made of different materials.

19. The electronic component embedded substrate according to claim 18, wherein: The conductive structure is connected to the body of the electronic component.

20. The electronic component embedded substrate according to claim 18, wherein: The conductive structure is connected to the pad of the electronic component.

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