Fpga logic cell with improved support for counters

Abstract

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the maximum number of functions that the logic cell can compute for K inputs, and where the logic cell can be configured to implement one bit of a counter in parallel with K-1 any independent functions of the K inputs.

Description

BACKGROUND

[0001] The present invention relates to logic circuits for use in user programmable circuits such as field programmable gate arrays (FPGA). More particularly, the present invention relates to logic cells for use in such programmable integrated circuits, the logic cells having improved support for counters.

[0002] As is well known in the art, FPGAs are composed of logic cells connected by a programmable routing network. The value of any logic cell output connected to the programmable routing network can be transmitted through the network to any logic cell input connected to the network. Common types of logic cells include K-input look-up tables (LUTs) and additional logic functions such as multiplexers and carry chains. The value of K can range from 2 to 10 or greater; the most common values in practice are 3, 4, and 6. Figure 1 An existing logic cell 10 (as used in Microsemi The logic cell has a 4-input LUT formed from two 3-input LUTs 14a and 14b and a 2-input multiplexer 16, shown within dashed line 12. The Inl input of the 4-input LUT 12 at reference numeral 18 is connected to the select input of the multiplexer 16, and the In2, In3, and In4 inputs of the 4-input LUT 12 at reference numerals 20, 22, and 24 are presented to both 3-input LUTs 14a and 14b, respectively. Configuration bits represented by squares 26 are used to define the function of 3-input LUT 14a, and configuration bits represented by squares 28 are used to define the function of 3-input LUT 14b.

[0003] The carry chain implementation shown within dashed line 30 includes an additional three multiplexers. A 4-input multiplexer 32 has data inputs connected to the respective outputs of 3-input LUTs 14a and 14b as well as to constant logic 0 and constant logic 1, and produces an output G. Configuration bits represented by square 34 are used to select which of the inputs of 4-input multiplexer 32 will be passed to the output at G.

[0004] A 3-input multiplexer 36 has data inputs connected to the output of multiplexer 16 as well as to constant logic 0 and constant logic 1, and produces an output P. Configuration bits represented by square 38 are used to select which of the inputs of the third multiplexer 36 will be passed to the output at P.

[0005] The carry-output multiplexer 40 has a data input, the carry input CI 42, connected to logic unit 10, and a data input, the output G, connected to 4-input multiplexer 32. The output of the carry-output multiplexer 40 is connected to the carry output CO 44 of logic unit 10. The select input of the carry-output multiplexer 40 is connected to the output P of 3-input multiplexer 36.

[0006] XOR gate 46 has a first input that is connected to the output of 4-input LUT 12 at the output of multiplexer 16, and this first input also forms the main output Y 48 of logic unit 10. The second input of XOR gate 46 is connected to the carry input CI 42 of logic unit 10. The output of XOR gate 46 is the sum output S 50 of logic unit 10.

[0007] The In1, In2, In3, and In4 inputs (18, 20, 22, and 24) and the Y and S outputs (48 and 50, respectively) are connected to a programmable routing network in the integrated circuit, as shown in the attached reference numeral 52. The carry input CI 42 is directly driven by the carry output of the previous logic unit 10 in the carry chain; these are not connected to the programmable routing network.

[0008] Existing LUT-based FPGA logic units such as Figure 1 The logic unit 10 can implement one bit of an incrementing counter or a decrementing counter, or one bit of an accumulator. This is in Figure 2 The diagram shows a block diagram of an N-bit counter implemented using N logic units labeled 10-0, 10-1, and 10-(N-1) and D-flip-flops 54-0, 54-1, and 54(N-1). However, because a first multiplexer 16 is required in each of the logic units 10-0, 10-1, and 10-(N-1) to drive a 3-input multiplexer 36 and an XOR gate 46 for implementing the counter function, none of the logic units 10-0, 10-1, and 10-(N-1) can use the 4-input LUT 12 for any other purpose when implementing the counter, although they are not used for implementing the counter.

[0009] A key characteristic of FPGA logic units is the number of their inputs and outputs that must be connected to a programmable routing network. For example, Figure 3A The existing logic unit 60 shown is manufactured by Xilinx, Inc. of San Jose, California. Used in the 4FPGA series. Figure 3A Some components of logic unit 60 are related to Figure 1 The logic unit 10 shares the same characteristics, and will be... Figure 3A Used to specify Figure 1to those of the same elements in the other figures.

[0010] Logic cell 60 includes a 4-input LUT portion 62 having inputs Inl, In2, In3, In4 identified at reference numerals 18, 20, 22, and 24, respectively. Small square 64 indicates configuration bits used to define a function of the Inl, In2, In3, In4 LUT inputs that LUT 62 will perform. The output of LUT 62 forms the Y output 66 of logic cell 60.

[0011] The carry chain segment of logic cell 60 is identified within dashed line 68. Carry chain 68 includes a 6-input multiplexer 70. The first input of 6-input multiplexer 70 is driven by a 2-input AND gate 72 driven by the Inl and In2 inputs (22 and 24) to LUT 62. The next two inputs to 6-input multiplexer 70 are driven directly by the Inl and In2 inputs (22 and 24) to LUT 62. The fourth input to 6-input multiplexer 70 is driven by input X at reference numeral 74. The remaining two inputs to 6-input multiplexer 70 are driven by constant values of logic 0 and logic 1. Small square 76 indicates configuration bits used to select which of the inputs of 6-input multiplexer 68 will be passed to its output.

[0012] The output of 6-input multiplexer 70 is coupled to one input of 2-input carry-out multiplexer 40. The other input of carry-out multiplexer 40 is driven by the output of 2-input multiplexer 78, one input of which is coupled to the CO output of the lower order logic cell on line 80. The other input to multiplexer 78 is driven by X input on line 82 as shown in dashed line, as this connection is made only in alternate (e.g., odd or even) instances of logic cell 60.

[0013] The connections to LUT inputs Inl, In2, In3, In4 (18, 20, 22, and 24) and input X (74) are from programmable routing network 52. The additional connections from programmable routing network 52 to carry-in at 74 via input X and from carry-out 44 to programmable routing network 52 are shown by dashed lines. Figure 3A As can be seen, logic cell 60 adds additional connections from programmable routing network 52 to carry-in via input X at 74 and adds additional connections from carry-out 44 to programmable routing network 52. The connections to LUT inputs Inl, In2, In3, In4 (18, 20, 22, and 24) and input X (74) are from programmable routing network 52. The additional connections from programmable routing network 52 to carry-in at 74 via input X and from carry-out 44 to programmable routing network 52 are shown by dashed lines. Figure 1 Like logic cell 10 of FIG. 1, logic cell 60 is based on a 4-input LUT 62, but implements carry chain 66 differently. While Figure 1 Logic cell 10 of FIG. 1 has 4 inputs and 2 outputs connected to programmable routing network 52, logic cell 60 has 5 inputs and 2 outputs connected to programmable routing network 52. Figure 3AThe logic cell 60 has 5 such inputs and 3 such outputs. These additional connections between the logic cell 60 and the programmable routing network 52 can provide additional flexibility, but also significantly increase the complexity of the programmable routing network 52 and thus increase the cost.

[0014] Another important characteristic of FPGA logic cells is the number K of inputs to the LUT. Some existing FPGAs use 4-input LUT cells (K = 4), such as the Xilinx®Virtex®series 7 logic cell 10 shown in Figure 1 and Figure 3A As shown for the logic cell 10 and the logic cell 60, this is generally best for low-cost, low-power FPGAs. Other existing FPGAs use splittable 6-input LUTs (K = 6). These FPGAs can implement a more diverse set of functions, but consume more area and more power. A recent study of the tradeoffs related to the number of LUT inputs can be found in “Improving FPGA Performance with a S44 LUT Structure,” 2018, in the ACM / SIGDA International Symposium on Field-Programmable Gate Arrays Conference Proceedings, 2018.

[0015] Figure 3B One existing example of a 6-input LUT logic cell is shown in FIG. 1. This is a block diagram of a logic cell 90 that includes a splittable 6-input LUT shown in dashed lines 92. This logic cell is equivalent to the Xilinx®Virtex®series 7 logic cell manufactured by Xilinx, Inc. of San Jose, California.

[0016] The 6-input LUT 92 is formed from two 5-input LUTs 94a and 94b. As in the logic cell 10 of FIG. 1, the small squares 96 and 98 represent configuration bits used to define the functions of the LUTs 94a and 94b, respectively. Figure 1 As in the logic cell 10 of FIG. 1, the small squares 96 and 98 represent configuration bits used to define the functions of the LUTs 94a and 94b, respectively.

[0017] The multiplexer 110 has the respective outputs of the LUTs 94a and 94b, labeled F0 and Fl, respectively, as its data inputs. The select input of the multiplexer 110 at reference numeral 112 is connected to the Inl input of the logic cell 90 and serves as the sixth input to the 6-input LUT 92. The output of the multiplexer 110 is connected to the output Y of the logic cell 60, as shown at reference numeral 48.

[0018] The carry logic of the logic cell 90 is shown within the dashed line 114 and is formed by two multiplexers 36 and 40 and an XOR gate 46. The multiplexer 36 (G multiplexer) has a first data input connected to the F0 output of the LUT 94a, a second data input connected to the F1 output of the LUT 94b, and a third input connected to a constant low logic level. The small square 38 represents a configuration bit used to route one of the inputs of the multiplexer 36 to its output.

[0019] The second multiplexer 40 is a carry-out multiplexer having one of its data inputs connected to the output G of the multiplexer 36 and the other of its data inputs connected to the carry-in (CI) input of the logic cell identified at reference numeral 42. Its select input is connected to the output of the multiplexer 110. The output of the carry-out multiplexer 40 is connected to the CO output of the logic cell 90 as shown at reference numeral 44.

[0020] The XOR gate 46 has a first input connected to the carry-in input 42 of the logic cell 90 and a second input connected to the output of the multiplexer 110. The output of the XOR gate 46 is connected to the sum (S) output of the logic cell 90 as shown at reference numeral 50.

[0021] The logic cell 90 has a first output Y shown at reference numeral 48 representing the output of the six-input LUT 92 and a second output Yl shown at reference numeral 116 connected to the F0 output of the 5-input LUT 94a. Figure 3B The six-input LUT 92 in the logic cell 90 is referred to as "splittable" in that the 5-input LUT 94a and the 5-input LUT 94b can be used independently since the direct outputs Y 48 and Yl 116 are available from both 5-input LUTs (through the multiplexer 110, the output Yl 116 is obtained from the 5-input LUT 94a and the output Y 48 is obtained from the 5-input LUT 94b).

[0022] The logic cell 90 is in Figure 3BAs shown in the figure, the logic cell is configured to implement a one-bit counter and any independent function of four inputs. The In2 input 100 is used as a counter input. The lower 5-input LUT 94b is configured so that at its output Fl = In2. The Inl input 112 is connected to a logic 1 level, so at reference numeral 48, the Y output of the logic cell 90 is Y = In2. The sum output at reference numeral 50 is S = EXOR(In2, CI). The output G of the multiplexer 36 is configured to pass a low logic level 0, so that the carry output CO of the logic cell 90 at reference numeral 44 is CO = AND(In2, CI). The Yl output 116 of the logic cell 90 is still available to generate any function of the remaining four inputs from the 5-input LUT 94a, In3, In4, In5, and In6. Because Figure 3B The configuration shown requires the Inl and In2 LUT inputs to be used for the counter function, so these inputs are not available for any independent LUT function, effectively reducing the LUT to a 4-input LUT (94a), the output of which is available at Yl.

[0023] Some designs programmed into FPGAs require a large number of incrementing or decrementing counters. In particular, for such designs, it would be beneficial if Figure 1 It would be beneficial if a 4-input LUT cell could implement a counter while leaving the LUT available for other purposes. It would also be beneficial if a 6-input LUT cell could implement a counter while leaving more than four of the inputs of the LUT available for use.

[0024] In addition, binary neural networks are an increasingly important application. Binary neural networks often require implementation of a function known as "population count" or "pop count". This function represents the number of true Boolean inputs in a set of M Boolean inputs as a log2(M)-bit binary output value. Pop counters are typically implemented using compressors and accumulators (which allow the value to be computed over multiple clock cycles).

[0025] A compressor is a series of logic circuits that takes multiple binary-valued inputs and produces their sum as a single binary-valued output. For example, the well-known full adder can also be referred to as a 3:2 compressor; it takes three one-bit inputs and produces a single two-bit output. In some cases, compressors can be organized in a chain similar to a carry chain, where each compressor receives one or more additional inputs from a previous compressor in the chain and generates the same number of additional outputs to the next compressor in the chain. For more details on compressors, see Gajski, "Parallel Compressors", IEEE Transactions on Computers, vol. C-29, no. 5, May 1980. With prior logic cells such as Figure 1two logic cells to implement each 3:2 compressor: one logic cell to produce each of the two outputs. The 3:2 compressor can be implemented in a single logic cell of Figure 3A and Figure 3B a logic cell of Figure 3A The logic cell 60 of Figure 3B The logic cell 90 of consumes both more area and more power, and has additional connections to the programmable routing network for the CO outputs.

[0026] It would be advantageous to improve the efficiency of implementing counters and compressors in 4-input LUT logic cells such as Figure 1 without increasing the number of inputs and outputs connected to the programmable routing network (making the programmable routing network more complex and more costly) or increasing the number of LUT inputs K (which would significantly increase the area and power consumption of the logic cell). Such an efficiency improvement would enable users to pack more logic into an FPGA chip with the same number of cells, and possibly make it clock faster. SUMMARY

[0027] According to one aspect of the invention, a logic cell for a programmable logic integrated circuit is presented, where K is the maximum number of inputs that the logic cell can compute any function of, and the logic cell can be configured to implement one bit of a counter in parallel with any independent function of K-1 inputs.

[0028] According to one aspect of the invention, the counter can be an incrementing counter or a decrementing counter.

[0029] According to one aspect of the invention, the logic cell can be further configured to implement one bit of a dual-input adder in parallel with any independent function of K inputs.

[0030] According to one aspect of the invention, the logic cell can be further configured to implement one bit of a dual-input adder in parallel with any independent function of K inputs.

[0031] According to one aspect of the invention, a logic cell can be further configured to implement one bit of a two-input adder, and the logic cell has K function inputs to be used to compute a function; a counter input to receive a current state of a counter bit; a carry-in input; a carry-out output; a primary output at which an output of the K-input function is available; a sum output at which an output of one of the counter bit and an output of the one-bit adder is available; a K-input LUT whose inputs are driven by the K function inputs and whose output drives the primary output; and a carry circuit coupled to the carry-in input and the counter input and driving the carry-out output and the sum output. The carry circuit can invert or not invert the count input.

[0032] According to two particular aspects of the invention, K = 4 and K = 6.

[0033] According to one aspect of the invention, a logic cell for a programmable logic integrated circuit has only 4 inputs connected to a programmable routing network, the logic cell has only two outputs connected to the programmable routing network, the logic cell has a carry-in input, the logic cell can be configured in a first way such that a value of the carry-in input appears at one of the outputs and, in parallel, any function of the 4 inputs appears at the other output, and the logic cell can be configured in a second way to implement one bit of a two-input adder in which a sum bit appears at one of the two outputs.

[0034] According to one aspect of the invention, a logic cell can be used to implement a chain of 4:2 compressors, where each 4:2 compressor in the chain of 4:2 compressors can be implemented in 2 instances of the logic cell.

[0035] According to one aspect of the invention, a logic cell for a programmable logic integrated circuit includes a carry-in input; a 2-input carry-out multiplexer that produces a carry-out output signal; a 2-input XOR gate having a first input and a second input, the first input driven by the carry-in input that does not drive the programmable routing network, the second input driven by a signal that also does not drive the programmable routing network; a multiplexer that produces a signal P that drives a select input of the carry-out multiplexer and one input of the XOR gate.

[0036] According to one aspect of the present application, a logic cell for a programmable logic integrated circuit includes K data inputs; a primary output; a carry-in input; a carry-out output; a counter input; a sum output; a K-input look-up table (LUT) having K LUT inputs each connected to a different one of the K data inputs and a LUT output connected directly to the primary output, the K-input LUT including a first (K-l)-input look-up table LUT and a second (K-l)-input LUT, both of which share the second through Kth inputs to the K-input LUT in common, each of the first (K-l)-input LUT and the second (K-l)-input LUT having an output; a first multiplexer having a first input coupled to the output of the first (K-l)-input LUT, a second data input coupled to the output of the second (K-l)-input LUT, and a select input coupled to the first input of the K-input LUT, the first multiplexer having an output forming the LUT output connected directly to the primary output.

[0037] According to one aspect of the present application, the logic cell has a carry circuit including: a second multiplexer having a first data input coupled to the output of one of the first (K-l)-input LUT and the second (K-l)-input LUT, a second data input coupled to a logic low constant voltage, a select input coupled to a configuration circuit of the logic cell, and a data output; a third multiplexer having a first data input coupled to the counter input of the logic cell, a second data input coupled to the LUT output, a third data input coupled to a logic low constant voltage, a select input coupled to the configuration circuit of the logic cell, and a data output; a carry-out multiplexer having a first data input coupled to the data output of the second multiplexer, a second data input coupled to the carry-in input of the logic cell, a select input coupled to the data output of the third multiplexer, and a data output coupled to the carry-out output of the logic cell; and an exclusive OR gate having a first input coupled to the carry-in input of the logic cell, a second input coupled to the data output of the third multiplexer, and an output coupled to the sum output of the logic cell. The carry circuit can further include a fourth multiplexer coupled between the counter input of the logic cell and the first data input of the third multiplexer, the fourth multiplexer having a first data input and a second data input which is an inverted data input, the first data input and the second data input coupled together to the counter input of the logic cell, the fourth multiplexer having a select input coupled to the configuration circuit of the logic cell, and an output coupled to the first data input of the third multiplexer.

[0038] According to one aspect of the present application, at least one of the second multiplexer and the third multiplexer has a data input coupled to a logic high constant voltage.

[0039] According to one aspect of the present application, the second multiplexer has a data input coupled to an output of the first (K-l)-input LUT, and a data input coupled to an output of the second (K-l)-input LUT. BRIEF DESCRIPTION OF DRAWINGS

[0040] The present application will be explained in more detail with reference to the various aspects and the accompanying drawings, in which:

[0041] Figure 1 is a block diagram of a prior art logic cell;

[0042] Figure 2 is a block diagram of an incrementing counter using one Figure 1 prior art logic cell per bit;

[0043] Figure 3A is a diagram of a prior art logic cell including a 4-input LUT and additional connections to the programmable routing network for a carry-in and a carry-out;

[0044] Figure 3B is a block diagram of a prior art logic cell including a splittable K-input LUT and capable of simultaneously implementing an incrementing counter and any (K-2)-input function (where K = 6);

[0045] Figure 4 is a block diagram of a logic cell according to one aspect of the present application;

[0046] Figure 5 is a block diagram of an incrementing counter using one Figure 4 logic cell per bit according to one aspect of the present application;

[0047] Figure 6 is a block diagram of a logic cell supporting both an incrementing counter function and a decrementing counter function according to one aspect of the present application;

[0048] Figure 7 is a block diagram of a decrementing counter using one Figure 6 logic cell per bit according to one aspect of the present application;

[0049] Figure 8 is a block diagram of an accumulator having L-bit inputs and N-bit outputs using one Figure 4 logic cell per output bit according to one aspect of the present application;

[0050] Figure 9A is a block diagram of a logic cell usingFigure 4 a detailed view of a 3:2 compressor implemented using logic similar to the logic of

[0051] Figure 9B a 3:2 compressor implemented using logic similar to the logic of Figure 4 a detailed view of a 3:2 compressor implemented using logic similar to the logic of

[0052] Figure 10A a functional block diagram of a 4:2 compressor;

[0053] Figure 10B a 4:2 compressor implemented using logic similar to the logic of Figure 4 a block diagram of a 4:2 compressor implemented using logic similar to the logic of

[0054] Figure 11 a block diagram of a 2-input adder implemented using logic similar to the logic of Figure 4 a block diagram of a 2-input adder implemented using logic similar to the logic of DETAILED DESCRIPTION

[0055] Those of ordinary skill in the art will realize that the following description is illustrative only and is not intended to be in any way limiting. Other aspects will readily occur to those skilled in the art.

[0056] The present invention improves the efficiency of existing LUT-based FPGA logic cells in implementing incrementing counters, decrementing counters, and pop counters. When implementing each of these functions, some of the K-input LUTs in some of the logic cells remain available to generate any function of the K inputs to those LUTs.

[0057] According to one aspect of the present invention, Figure 4 An exemplary LUT-based logic cell 120 that allows for improved efficiency of incrementing counters and pop counters is shown in FIG. 1 1 1, to which attention will now be directed. Figure 4 Some elements of the logic cell 120 of FIG. 1 1 1 are common to the logic cells shown in the previous figures, and will be referred to using the same reference numerals used to designate those same elements in the previous figures. Figure 4

[0058] Figure 4 ​The logic unit 120 includes a K-input LUT formed by a first (K-1)-input LUT 124a and a second (K-1)-input LUT 124b, shown within dashed line 122. Small squares 126 and 128 represent the configuration inputs for defining the functions of LUT 124a and LUT 124b, respectively. LUT 124a and LUT 124b share the K-1 function inputs (In2, In3…In… shown at reference numerals 130, 132 and 134, respectively). K The first (2-input) multiplexer 136 has a first data input coupled to the output F0 of the first (K-1)-input LUT 124a, a second data input coupled to the output F1 of the second (K-1)-input LUT 124b, and a selection input of the function input In1 coupled to the K-input LUT 122 at reference numeral 138. The data output of the first multiplexer 136 is used as the output of the K-input LUT 122 and is directly connected to the primary output (Y) of the logic unit 120, the main output of which is shown at reference numeral 48. In a specific embodiment of the invention, K = 4.

[0059] Figure 4 The logic unit 120 also includes a carry input CI 42, a counter input QI 140, a carry output CO 44, and a sum output S 50. Figure 4 The carry circuit 142 in the logic unit includes Figure 4 The second multiplexer, shown as a 4-input multiplexer 32, has a first data input coupled to the F0 output of a first 3-input LUT 124a; a second data input coupled to the F1 output of a second 3-input LUT 124b; a third data input coupled to a logic high constant voltage; a fourth data input coupled to a logic low constant voltage; a selection input shown as a small square 34, coupled to a configuration circuit for multiplexer 32, for selecting which input of the second carry multiplexer 32 will be passed to its data output; and a data output represented as G. The third multiplexer... Figure 4 The middle is shown as Figure 4a first data input coupled to a counter input QI 140 of the logic unit 120; a second data input coupled to an output of the K-input LUT 122 at the first multiplexer 136; a third data input coupled to a logic high constant voltage; a fourth data input coupled to a logic low constant voltage; a select input, shown as a small square 38, coupled to a configuration circuit for the third multiplexer 36 for selecting which of the inputs of the third multiplexer 36 will pass to its data output; and a data output, denoted P. In Figure 4 Figure 4 The carry-out multiplexer of the 2-input multiplexer 40 in the carry circuit 142 of the logic unit 110 has a first data input coupled to the data output G of the second multiplexer 32; a second data input coupled to the carry-in CI 42 of the logic unit 120; a select input coupled to the P data output of the third multiplexer 36; and a data output coupled to the carry-out CO 44 of the logic unit 120. Figure 4 The XOR gate 46 in the carry circuit 142 of the logic unit 120 has a first input coupled to the carry-in CI 42 of the logic unit 120, a second input coupled to the data output P of the third multiplexer 36, and an output coupled to the sum output S 50 of the logic unit 120.

[0060] In some implementations of the invention, either the F0 or F1 input from the LUT 124a and LUT 124b or the logic high constant voltage input can be omitted from the second multiplexer 32 and / or the logic high constant voltage input can be omitted from the third multiplexer 36.

[0061] Figure 1 The logic unit 120 shown in accordance with aspects of the invention differs in structure from the existing logic unit in Figure 4 by the use of a second 4-input multiplexer 36 to drive the generation of the XOR gate 46 that produces the sum output S 50, and the addition of the QI counter input 140 to the logic unit 120, as shown in Figure 4 .

[0062] Broadly speaking, Figure 4 The logic unit 120 has K function inputs, one QI input, and one carry-in input. Figure 2 The specific example shown includes K function inputs, Inl 138, In2 130, IN3 132, through In K ​134. To implement a logic cell with a larger K value, additional function inputs can be added, each driving both LUT 124a and LUT 124b. The primary output Y 48 of logic cell 120 presents the value of any function of the K function inputs. A second output (carry-out CO 44) presents the value present on carry-in CI 42 or present on the output from the second multiplexer 32, as selected by the output of the third multiplexer 36. Inputs Inl, In2, In3... In K and outputs S and Y are connected to the programmable routing network. QI inputs can be driven by flip-flops associated with the logic cell, as described above with respect to Figure 5 , but need not be driven by the programmable routing network. The carry-out CO of one cell directly drives the carry-in CI of the next cell in the carry chain, and neither CI nor CO need be connected to the programmable routing network.

[0063] Figure 4 is a block diagram showing how an incrementing counter can be implemented using logic cell 120. Figure 5 Figure 5 An N-bit incrementing counter 160 is shown formed from (N-l) logic cells 120-0, 120-1, and 120-(N-l). As shown in Figure 4 Figure 4 The second multiplexer 32 in each of Figure 4 is set so that its output G is the value logical 0, and multiplexer 36 is set so that its output P is the value at the QI 140 input of the logic cell 120. The carry-in CI input 42 of the logic cell 120 representing the least significant bit is set to logical 1, and the carry-in CI input 42 of each of the successive higher significant bits is connected to the carry-out CO 44 of the adjacent lower significant bit logic cell 120. Data flip-flops 162-0 through 162-(N-l) each have their data input connected to the S output (138 in Figure 4 ) of the logic cell 120 included in their respective counter stage. The Q output of flip-flops 162-0 through 162-(N-l) are each connected to the QI input (140 in Figure 5 ) of the logic cell included in their respective counter stage.

[0064] As shown in Figure 5 none of the LUT inputs (shown as Inl, In2, In3... In K ) or Y outputs of all of the logic cells (120-0, 120-1, and 120-(N-l)) are used to perform the counter function, so each cell can be used to generate K inputs Figure 6 ​​In1, In2, In3...In in K ) of any function. This is not possible using existing logic cells.

[0065] Referring now to Figure 4 , a block diagram illustrates Figure 6 a variant of the logic cell of Figure 4 The logic cell 170 of Figure 4 includes many of the same elements as the logic cell 120 of Figure 4 The elements common to both figures will be denoted using the same reference numerals as employed in Figure 6 The elements common to the logic cell 170 and the logic cell 120 of

[0066] Figure 4 The difference between the logic cell 170 of Figure 6 and the logic cell 120 of Figure 6 The logic cell 170 of The logic cell 170 of

[0067] The fourth multiplexer 172 selectively inverts the value present at the QI input 134 configured by the configuration bits 174. Thus, Figure 4 The logic cell 170 of Figure 7 employs the fourth multiplexer 172 as a programmable inverter to support both the incrementing counter function and the decrementing counter function by setting the configuration bits at reference numeral 174 to pass either the non-inverted or inverted QI input at reference numeral 140. As in the case of the logic cell of

[0068] Figure 6 is a block diagram illustrating the logic cell of Figure 7 for implementing a decrementing counter. Figure 5 An N-bit counter 180 using (N-1) logic cells is illustrated. The carry-in CI input having the least significant bit is set to a logic 0 (rather than set to a logic 1 as in the counter illustrated in Figure 7 As illustrated in Figure 6 Figure 6The output of the second multiplexer 32 is set to pass the logic 1 value, and the output P of the third multiplexer 36 is set to pass the value inverted by the fourth multiplexer 172. Figure 7 The value at input QI 140 of logic unit 170. Similarly... Figure 5 As shown, all LUT inputs of all logic units (0, 1, and N-1) can be used to generate any function with K inputs simultaneously with the operation of an increment or decrement counter function.

[0069] One of the attractive features of this invention is that when both the incrementing counter and the decrementing counter are implemented, as... Figure 7 and Figure 8 As shown, the entire K-input LUT portion 112 used by each logic unit 120 and 170 retains any function that can be used to generate all LUT inputs. This feature is impossible to achieve using existing logic units, which is a significant advantage of the logic units of the present invention, as fewer logic units can be used to implement the user design compared to the prior art.

[0070] Figure 4 It shows Figure 6 and Figure 4 Further explanation of the flexibility of logic units 120 and 170 is provided in the block diagram, which illustrates how they can be used as follows: Figure 8 The logic units of those logic units implement the accumulator. Figure 8 An accumulator with L-bit inputs and N-bit outputs is shown. The N-bit accumulator 190 employs N logic cells, shown as 120-0 to 120-N, connected as illustrated. The CI input of logic cell 120-0 is connected to a constant logic low "0" level. The CO output of each logic cell is connected to the CI input of the next logic cell in the accumulator.

[0071] Each logic cell 120-0 to 120-(N-1) is associated with a data flip-flop 192-0 to 192-(N-1), respectively. The S-output of each logic cell is coupled to the D-input of its associated data flip-flop. The Q-output of each data flip-flop 192-L to 192-(N-1) is coupled to the Q-input of its associated logic cell.

[0072] The In1 inputs of logic units 120-0 to 120-(L-1) are coupled to the Q outputs of their associated data flip-flops. The In2 inputs of logic units 120-0 to 120-(L-1) are coupled to the individual bits of the L-bit inputs of accumulator 190. Figure 8 The diagram shows the configuration of each logical unit in the accumulator.

[0073] When implementing an accumulator, the entire LUT portion of the logic cell in the most significant bit of the implementation accumulator 190 remains fully available for other purposes, such as Figure 8 As can be seen from Figure 4 inspection, the LUT function of logic cells 120-L through 120-(N-1) remains available for use concurrently with the operations of the accumulator 190. While the above has been described with respect to logic cells 120, those skilled in the art will recognize that this is equally applicable to logic cells 170.

[0074] Figure 6 Another example of the flexibility of the logic cells 120 and 170 of Figure 9A is shown in Figure 3A The logic cells of the present invention have the ability to pass the value of the CI input to the S output and to the programmable routing network by setting P=0, while leaving the LUT available to implement any independent function of K inputs in parallel. In contrast to Figure 1 existing cells, no additional, expensive connections between the CI or CO and the programmable routing network are required. This ability can, for example, allow more efficient implementation of compressors. Implementing a 3:2 compressor with Figure 9A an existing logic cell of the prior art would consume two cells entirely. Figure 9A The way in which the logic cells 120 or 170 can implement a 3:2 compressor using only portions of two logic cells is shown. Those of ordinary skill in the art will recognize that Figure 1 the logic cell 120-1 still has its available Inl, In2, In3, and In4 inputs and Y and CO outputs available, and its sufficient available internal logic is also available as a first logic cell of an additional 3:2 compressor, or as an independent K-input function. In this way, an M compressor can be implemented in M+1 logic cells, as compared to 2M of the existing cells of the prior art using Figure 9B Thus, the increased cost of a 3:2 compressor is only one logic cell. More details of this implementation are shown in Figure 10A , specifically showing an implementation with logic cells 120, it will be understood that a similar implementation can be performed with logic cells 170.

[0075] Figure 10B and Figure 4 shows yet another example of the flexibility of the logic cells 120 and 170 of Figure 6 or Figure 10A . Figure 10A is a block diagram of a 4:2 compressor 210 formed from two full adders 212 as shown. Figure 10BThe function of the 4:2 compressor is defined in terms of a well-known full adder cell 212. The compressor 210 is fed from any inputs designated as inputs T, U, V, W, and X. The input T will be driven by the output N of the previous compressor in the chain. Figure 10A is a block diagram showing how only two logic cells 120-0 and 120-1 are needed to implement the 4:2 compressor 210 of Figure 10A and includes a table showing the configuration of the logic cells 120-0 and 120-1 implementing the function. Figure 10B The top full adder 212 is implemented in logic cell 1 of Figure 10B The lower full adder 212 is implemented in logic cell 0, including the generation of signal M, which then passes from the CI input through logic cell 1 to the S output. As Figure 1 shown, the 4:2 compressor can be implemented using two of the logic cells 120 of the present invention, while at least three of the prior art logic cells shown in Figure 11 would be needed to implement the function. While the above has been described with respect to the logic cells 120, those skilled in the art will recognize that this is equally applicable to the logic cells 170.

[0076] Referring now to Figure 4 , a block diagram shows a two-input N-bit adder 220 implemented in accordance with one aspect of the present invention using the logic cells 120 of Figure 11 The N-bit adder 220 employs N+1 logic cells 120-0 through 120-N connected as shown. The CI input of logic cell 120-0 is connected to a constant logic low "0" level. The CO output of each logic cell 120 is connected to the CI input of the next logic cell 120 in the adder 220.

[0077] The Inl and In2 inputs of logic cells 120-0 through 120-(N-1) are coupled to the N operand inputs U[0] through U[N-1] and V[0] through V[N-1] of the adder 220, respectively. The S output of each logic cell 120-0 through 120-N forms the sum output of each of the N+1 output bits of the adder. Figure 9A The configuration of each of the logic cells 120 in the adder 220 is shown in Logic cell 120-N only needs to pass its carry-in (CI) input to its sum (S) output and to the programmable routing network. Advantageously, this makes its LUT available to implement any uncorrelated function of K inputs in parallel. While the above has been described with respect to the logic cells 120, those skilled in the art will recognize that this is equally applicable to the logic cells 170.

[0078] While aspects and applications of the present application have been shown and described with the above-mentioned details, it will be apparent to those skilled in the art that numerous modifications can be made without departing from the inventive concept here presented. For example, Figure 9B , Figure 10B and Figure 4 the ability shown by ​ is dependent only on the aspect of the present application that uses P instead of Y to drive the XOR gate, and thus can be implemented in alternative embodiments that do not include the addition of the QI input shown by ​ . Accordingly, the present application is not limited except as by the substance of the appended claims.

Claims

1. A logic cell for a programmable logic integrated circuit, comprising: K function inputs; a counter input, the counter input receiving a current state of a counter bit; a carry-in input; a carry-out output; a primary output; a sum output; a first (K-1)-input LUT and a second (K-1)-input LUT, both of which share in common the second through Kth function inputs of the K function inputs, each of the first (K-1)-input LUT and the second (K-1)-input LUT having an output; a first multiplexer having a first input coupled to the output of the first (K-1)-input LUT, a second data input coupled to the output of the second (K-1)-input LUT, a select input coupled to a first input of the K function inputs, and an output directly connected to the primary output; a second multiplexer having a first data input coupled to the output of the first (K-1)-input LUT, a second data input coupled to the output of the second (K-1)-input LUT, a select input coupled to a configuration circuit of the logic cell, and an output; a third multiplexer having a first data input coupled to the counter input, a second data input coupled to the output of the first multiplexer, and an output coupled to the sum output; a carry-out multiplexer having a first data input coupled to the carry-in input, a second data input coupled to the output of the second multiplexer, a select input coupled to the output of the third multiplexer, and an output coupled to the carry-out output.

2. The logic cell of claim 1, wherein the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K inputs.

3. The logic cell of claim 2, wherein the logic cell is further configurable to implement one bit of a two-input adder.

4. The logic cell of claim 2, wherein the counter is one of an incrementing counter and a decrementing counter.

5. The logic cell of claim 1, wherein the second multiplexer includes a third data input coupled to a logic low constant voltage and a fourth data input coupled to a logic high constant voltage.

6. The logic cell of claim 1, wherein the third multiplexer includes a third data input coupled to a logic low constant voltage and a fourth data input coupled to a logic high constant voltage.

7. The logic cell of claim 2, including an exclusive OR gate having an input coupled to the carry-in input, an input coupled to the output of the third multiplexer, and an output coupled to the sum output.

8. The logic cell of claim 1 or 2, wherein K = 4.

9. The logic cell of claim 1 or 2, wherein K = 6.

10. The logic cell of claim 1, wherein: the logic cell can be used to implement a chain of 4:2 compressors, wherein each 4:2 compressor in the chain of 4:2 compressors can be implemented in 2 instances of the logic cell.

11. A logic cell for a programmable logic integrated circuit, comprising: K function inputs; a primary output; a carry-in input; a carry-out output; a counter input; a sum output; a K-input lookup table (LUT) coupled to the K function inputs, the K-input LUT comprising: a first (K-l)-input LUT and a second (K-l)-input LUT that collectively share a second through Kth function input of the K function inputs, each of the first (K-l)-input LUT and the second (K-l)-input LUT having an output; a first multiplexer having a first input coupled to the output of the first (K-l)-input LUT, a second data input coupled to the output of the second (K-l)-input LUT, a select input coupled to a first function input of the K function inputs, and an output directly connected to the primary output; and a second multiplexer having a first data input coupled to the output of the first (K-l)-input LUT, a second data input coupled to the output of the second (K-l)-input LUT, a third data input coupled to a logic low constant voltage, a fourth data input coupled to a logic high constant voltage, a select input coupled to a configuration circuit of the logic cell, and an output; a third multiplexer having a first data input coupled to the counter input, a second data input coupled to the output of the first multiplexer, a third data input coupled to a logic low constant voltage, a fourth data input coupled to a logic high constant voltage, a select input coupled to a configuration circuit of the logic cell, and an output; a carry-out multiplexer having a first data input coupled to the carry-in input of the logic cell, a second data input coupled to the output of the second multiplexer, a select input coupled to the output of the third multiplexer, and an output coupled to the carry-out output of the logic cell; and an XOR gate having a first input coupled to the carry-in input of the logic cell, a second input coupled to the output of the third multiplexer, and an output coupled to the sum output of the logic cell.

12. The logic cell of claim 11, further comprising: a fourth multiplexer coupled between the counter input of the logic cell and the first data input of the third multiplexer, the fourth multiplexer having a first data input and a second data input, the second data input being an inverted data input, the first data input and the second data input together coupled to the counter input of the logic cell, the fourth multiplexer having a select input coupled to configuration circuitry of the logic cell, and an output coupled to the first data input of the third multiplexer.

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