Method for forming material film, integrated circuit device, and method for manufacturing the same

Abstract

The present application provides a method for forming a material film, an integrated circuit device, and a method for manufacturing an integrated circuit device. In order to manufacture an integrated circuit (IC) device, a lower structure having a stepped structure defining a groove is prepared. A material film is formed inside the groove. In order to form the material film, a first precursor including a first central element and a first ligand having a first size is supplied to the lower structure to form a first chemical adsorption layer of the first precursor on the lower structure. A second precursor including a second central element and a second ligand having a second size smaller than the first size is supplied to the resulting structure including the first chemical adsorption layer to form a second chemical adsorption layer of the second precursor on the lower structure. A reaction gas is supplied to the first chemical adsorption layer and the second chemical adsorption layer.

Description

[0001] This application claims the benefit of and priority to Korean Patent Application No. 10-2019-0171894 filed on December 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a method for forming a material film, an integrated circuit (IC) device, and a method for manufacturing an IC device. More specifically, it relates to a method for forming a material film using an atomic layer deposition (ALD) process, an IC device including a material film obtained using the method, and a method for manufacturing an IC device. Background Art

[0003] As electronic devices become highly integrated and shrink, the aspect ratio of patterns included in the electronic devices is gradually increasing. Therefore, there is a need for a deposition technology that provides good gap filling characteristics even in narrow and deep spaces with a high aspect ratio. Specifically, in order to perform an atomic layer deposition (ALD) process for forming a material film on a three-dimensional (3D) structure including deep and narrow trenches to fill the trenches, it is useful to develop a deposition technology that can form a material film inside the trenches without causing gaps or voids. Summary of the Invention

[0004] Various aspects of the inventive concept provide a method of forming a material film, by which a material film without gaps or voids can be formed on a three-dimensional (3D) structure including deep and narrow trenches to fill the trenches.

[0005] Aspects of the inventive concepts also provide a method of fabricating an integrated circuit (IC) device, the method including a process of forming a material film on a 3D structure including a deep and narrow trench to fill the trench without forming seams or voids in the material film.

[0006] Furthermore, aspects of the inventive concept provide a method of manufacturing an IC device including a material film that can fill deep and narrow trenches formed in a 3D structure without gaps or voids and provide excellent electrical characteristics.

[0007] According to one aspect of the inventive concept, a method for forming a material film is provided. The method includes the following steps: supplying a first precursor comprising a first central element and a first ligand having a first size onto a lower structure, thereby forming a first chemisorption layer of the first precursor on the lower structure. Supplying a second precursor comprising a second central element and a second ligand having a second size onto the resulting structure in which the first chemisorption layer is formed, thereby forming a second chemisorption layer of the second precursor on the lower structure. The second size is smaller than the first size. Reactive gas is supplied to the first and second chemisorption layers to remove the first and second ligands from the lower structure, thereby forming a material film comprising the first and second central elements.

[0008] According to another aspect of the inventive concept, a method for manufacturing an IC device is provided. The method includes preparing a lower structure having a stepped structure defining a groove. A material film is formed inside the groove. The formation of the material film includes performing at least one atomic layer deposition (ALD) cycle. The ALD cycle includes the following steps: a first process of supplying a first precursor including a first central element and a first ligand having a first size into the groove, and forming a first chemical adsorption layer of the first precursor inside the groove; a second process of supplying a second precursor including a second central element and a second ligand having a second size smaller than the first size into the groove in which the first chemical adsorption layer is formed, and forming a second chemical adsorption layer of the second precursor inside the groove; and a third process of forming an atomic-scale material film including the first central element and the second central element inside the groove by supplying a reaction gas to the first chemical adsorption layer and the second chemical adsorption layer.

[0009] According to another aspect of the inventive concept, a method for manufacturing an IC device is provided. The method includes forming a trench defining an active area in a substrate. A silicon oxide film is formed within the trench. The formation of the silicon oxide film includes performing at least one ALD cycle. The ALD cycle includes the following steps: a first process of supplying a first precursor including a first silicon (Si) central element and a first ligand having a first size into the trench, and forming a first chemical adsorption layer of the first precursor within the trench; a second process of supplying a second precursor including a second silicon central element and a second ligand having a second size smaller than the first size into the trench in which the first chemical adsorption layer is formed, and forming a second chemical adsorption layer of the second precursor within the trench; and a third process of forming an atomic-scale silicon oxide film within the trench by supplying an oxidizing gas to the first and second chemical adsorption layers.

[0010] According to another aspect of the inventive concept, an IC device formed using the method for manufacturing an IC device according to one aspect of the inventive concept is provided. The IC device includes a material film filling a trench, and the material film includes a silicon oxide film. An upper portion of the silicon oxide film, relatively close to an entrance of the trench, includes a first content of carbon atoms. A lower portion of the silicon oxide film, relatively close to a bottom surface of the trench, includes a second content of carbon atoms lower than the first content.

[0011] According to another aspect of the inventive concept, an IC device manufactured using the method for manufacturing an IC device according to another aspect of the inventive concept is provided. The IC device includes a silicon oxide film filling a trench. The silicon oxide film has a carbon atom content of less than 3 atomic percent (at%). An upper portion of the silicon oxide film relatively close to the entrance of the trench includes a first content of carbon atoms selected within a range of greater than 0 at% and less than 3 at%. A lower portion of the silicon oxide film relatively close to the bottom surface of the trench includes a second content of carbon atoms selected within a range of greater than or equal to 0 at% and less than 3 at%, and the second content is lower than the first content. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a flow chart of a method for forming a material film according to an embodiment;

[0014] Figures 2A to 2E is a cross-sectional view showing a process sequence of a method for forming a material film according to an embodiment;

[0015] Figure 3 is a flow chart of a method for forming a material film according to an embodiment;

[0016] Figure 4 is a flow chart of a method for forming a material film according to an embodiment;

[0017] Figure 5 is a flow chart of a method for forming a material film according to an embodiment;

[0018] Figure 6 is a plan view of a schematic configuration of an integrated circuit (IC) device according to an embodiment;

[0019] Figure 7 is a schematic plan layout diagram of main components of a memory cell array region according to an embodiment;

[0020] Figures 8A to 8C is a cross-sectional view of main components of an IC device according to an embodiment;

[0021] Figure 9A and Figure 9Bis a cross-sectional view of major components of an IC device according to an embodiment; and

[0022] 10A to 10F 1 is a cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. In the accompanying drawings, the same reference numerals are used to represent the same or similar elements, and their repeated description will be omitted.

[0024] Figure 1 is a flowchart of a method of forming a material film according to an embodiment. Figures 2A to 2E is a cross-sectional view of a process sequence of a method for forming a material film according to an embodiment. Figure 1 and Figures 2A to 2E Methods of forming a material film according to these embodiments are described. In this embodiment, a method of manufacturing a material film using an atomic layer deposition (ALD) process will be exemplarily described.

[0025] Reference Figure 1 and Figure 2A In process P12, a first precursor P1 may be supplied onto the lower structure 110 in the reaction space, and thus a first chemical adsorption layer AL1 of the first precursor P1 may be formed on the lower structure 110. The first precursor P1 may include a first central element and a first ligand having a first size.

[0026] A stepped structure defining the trench TR may be formed in an upper portion of the lower structure 110. The lower structure 110 may include or may be a semiconductor element, a compound semiconductor, or an insulating material. In example embodiments, the lower structure 110 may include a conductive region (e.g., a doped well or doped structure), an interconnection layer, a contact plug, and a transistor, and may further include an insulating film configured to insulate the conductive region, the interconnection layer, the contact plug, and the transistor from one another.

[0027] The first size of the first ligand of the first precursor P1 may be larger than the second size of the second ligand of the second precursor P2, which will be referred to below. Figure 1 Process P14 and Figure 2B In an exemplary embodiment, the size of the first precursor P1 may be larger than the size of the second precursor P2, which will be referred to below. Figure 1 Process P14 and Figure 2B As used herein, the size of a ligand or precursor refers to the volume of space occupied by the ligand or precursor. In example embodiments, the molecular weight of the first precursor P1 may be greater than the molecular weight of the second precursor P2.

[0028] In example embodiments, the first ligand of the first precursor P1 may include at least one selected from an aromatic functional group, an alkoxy functional group, a thiol functional group, and a bulky organic functional group. Because the first precursor P1 includes a first ligand having a relatively large size, the first precursor P1 may have a low adsorption density due to steric hindrance. Therefore, even after the first precursor P1 is adsorbed on the exposed surface of the lower structure 110, empty areas on which the first precursor P1 is not adsorbed may remain in and on the exposed surface of the lower structure 110. In addition, the first precursor P1 may have relatively low fluidity, so the first precursor P1 may have difficulty reaching the deep area or bottom surface of the trench TR and may be mainly adsorbed on the top surface of the lower structure 110 and the upper sidewall of the trench TR near the entrance side of the trench TR. For example, in some embodiments, 80% or more of the first precursor P1 is adsorbed on the top surface of the lower structure 110 and the upper half of the sidewalls of the trench TR. Since the first precursor P1 is mainly adsorbed on the inlet side of the trench TR, the first precursor P1 can prevent the Figure 1 Process P14 and Figure 2B The second precursor P2 described is adsorbed on the inlet side of the trench TR and induces the second precursor P2 to be preferentially adsorbed on the deep region or bottom surface of the trench TR. Figure 1 Process P14 and Figure 2B The second precursor P2 is described in detail.

[0029] Reference Figure 1 and Figure 2B In process P14 , a second precursor P2 may be supplied onto the resulting structure including the first chemical adsorption layer AL1 , and thus, a second chemical adsorption layer AL2 of the second precursor P2 may be formed on the lower structure 110 .

[0030] In some embodiments, the second precursor P2 may include a second central element and a second ligand or may be formed of a second central element and a second ligand, and the second central element of the second precursor P2 may include the same element as the first central element of the first precursor P1 or may be formed of the same element as the first central element of the first precursor P1. The second ligand included in the second precursor P2 may have a structure different from the first ligand of the first precursor P1. The second size of the second ligand may be smaller than the first size of the first ligand. In example embodiments, the first precursor P1 may have a size larger than that of the second precursor P2. In example embodiments, the molecular weight of the first precursor P1 may be greater than the molecular weight of the second precursor P2. In some other embodiments, the second central element of the second precursor P2 may include an element different from the first central element of the first precursor P1.

[0031] The second precursor P2 may have a higher reactivity than the first precursor P1. Therefore, the deposition rate of a material film formed using the second precursor P2 may be higher than the deposition rate of a material film formed using the first precursor P1. A second chemical adsorption layer AL2 of the second precursor P2 may be formed in an exposed surface area of ​​the lower structure 110 that is exposed by the first chemical adsorption layer AL1 of the first precursor P1. First and second chemical adsorption layers AL1 and AL2 obtained from first and second precursors P1 and P2 having different structures may be formed on the lower structure 110.

[0032] Since the first precursor P1 is mainly adsorbed on the inlet side of the trench TR when the first precursor P1 is supplied to the lower structure 110, a large amount of the second precursor P2 having a relatively small size can enter the trench TR. The first precursor P1 adsorbed on the inlet side of the trench TR can induce the second precursor P2 to be adsorbed on the deep area or bottom surface of the trench TR more preferentially than on the inlet side of the trench TR.

[0033] A first chemical adsorption layer AL1 of the first precursor P1 having a relatively low adsorption density can be formed on the top surface of the lower structure 110 and the inlet side of the trench TR, while a second chemical adsorption layer AL2 of the second precursor P2 having a relatively high adsorption density can be formed on the deep region or bottom surface of the trench TR. Therefore, a material film can be deposited on the top surface of the lower structure 110 and the inlet side of the trench TR at a relatively low deposition rate, while a material film can be deposited on the deep region of the trench TR at a relatively high deposition rate. Therefore, the interior of the trench TR can be filled with a high-purity material film without causing voids.

[0034] In example embodiments, the first central element of the first precursor P1 may include the same element as the second central element of the second precursor P2. The first central element and the second central element may include or may be silicon (Si), boron (B), or a metal. The metal that may be included in the first central element and the second central element or that may form the first central element and the second central element may be selected from zirconium (Zr), lithium (Li), beryllium (Be), sodium (Na), magnesium (Mg), aluminum (Al), potassium (K), calcium (Ca), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), rubidium (Rb), strontium (Sr), yttrium (Y), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver ( The present invention also includes, but is not limited to, tungsten (W), iridium (Ir), chrysene (Cyb), thorium (Cy), thallium (Cy), thulium (Tm), ytterbium (Yb), lutetium (Lu), uranium (UR), tungsten (W), chrysene (Re), sulphur (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lead (Pb), bismuth (Bi), polonium (Po), radium (Ra), and actinium (Ac).

[0035] When each of the first central element of the first precursor P1 and the second central element of the second precursor P2 is silicon (Si), the first ligand of the first precursor P1 may include an aromatic functional group, an alkoxy functional group, a thiol functional group or a large organic functional group, and the second ligand of the second precursor P2 may not include any one of the aromatic functional group, the alkoxy functional group, the thiol functional group and the large organic functional group, or may not include any aromatic functional group, the alkoxy functional group, the thiol functional group or the large organic functional group.

[0036] Examples of the first precursor P1 having the first ligand including an aromatic functional group may include 5-(bicycloheptenyl)methyldimethoxysilane (BMDS), 5-(bicycloheptenyl)triethoxysilane (BTS), and 5-(bicycloheptenyl)diethoxysilaneacetylene (BDS), but are not limited thereto.

[0037] Examples of the first precursor P1 having a first ligand including an alkoxy functional group may include trimethylmethoxysilane (CH3-O-Si-(CH3)3, abbreviated as TMMS), dimethyldimethoxysilane ((CH3)2-Si-(OCH3)2, abbreviated as DMDMS), methyltrimethoxysilane ((CH3-O-)3-Si-CH3, abbreviated as MTMS), phenyltrimethoxysilane (C6H5-Si-(OCH3)3, abbreviated as PTMOS), vinyldiethoxysilane, vinyldimethoxysilane, vinyltrimethoxysilane, vinyltriethoxysilane, vinylmethyldimethoxysilane and vinylmethyldiethoxysilane, but are not limited thereto.

[0038] Examples of the first precursor P1 having the first ligand including a thiol functional group may include (3-mercaptopropyl)trimethoxysilane, (3-mercaptopropyl)triethoxysilane, and (3-mercaptopropyl)methyldimethoxysilane.

[0039] Large organic functional groups can include -Si-(CH2) n-Si- group (herein, n is an integer ranging from 1 to 5). For example, the first precursor P1 having a first ligand including a large organic functional group can be selected from a precursor containing a -Si-CH2-Si- group and a precursor containing a -Si-(CH2)2-Si- group. Examples of the precursor containing a -Si-CH2-Si- group can include (EtO)3Si-CH2-Si(OEt)2H, Me(EtO)2Si-CH2-Si(OEt)2H, Me(EtO)2Si-CH2-Si(OEt)2H, Me(EtO)2Si-CH2-Si(OEt)HMe, Me2(EtO)Si-CH2-Si(OEt)2H, (EtO)Me2Si-CH2-Si(OMe)2H, Me2(EtO)Si-CH2 -Si(OEt)HMe, (EtO)3Si-CH2-Si(OEt)HMe, (EtO)3Si-CH2-Si(OMe)HMe, Me(MeO)2Si-CH2-Si(OMe )2H, Me(MeO)2Si-CH2-Si(OMe)HMe, Me2(MeO)Si-CH2-Si(OMe)2H and Me2(EtO)Si-CH2-Si(OMe)HMe. Examples of precursors containing -Si-(CH2)2-Si- groups may include (EtO)3Si-CH2CH2-Si(OEt)2H, Me(EtO)2Si-CH2CH2-Si(OEt)2H, Me(EtO)2Si-CH2CH2-Si(OEt)2H, Me(EtO)2Si-CH2CH2-Si(OEt)HMe, Me2(EtO)Si-CH2CH2-Si(OEt)2H, (EtO)Me2Si-CH2CH2-Si(OMe)2H, Me2(EtO)Si-CH2C H2-Si(OEt)HMe, (EtO)3Si-CH2CH2-Si(OEt)HMe, (EtO)3Si-CH2CH2-Si(OMe)HMe, Me(MeO)2Si-CH2CH2-Si(OMe)2H, Me(MeO)2Si-CH2CH2-Si(OMe)HMe, Me2(MeO)Si-CH2CH2-Si(OMe)2H, Me2(EtO)Si-CH2CH2-Si(OMe)HMe. As used herein, the abbreviation "Me" refers to a methyl group and the abbreviation "Et" refers to an ethyl group.

[0040] In example embodiments, the second precursor P2 may include silane (SiH 4 ), disilane (Si 2 H 6 ), halogenated silane, organic silane, or organic aminosilane, but is not limited thereto.

[0041] The halogenated silane may be selected from monofluorosilane (SiFH3), difluorosilane (SiF2H2), trifluorosilane (SiF3H), tetrafluorosilane (SiF4), monofluorodisilane (Si2FH5), difluorodisilane (Si2F2H4), trifluorodisilane (Si2F3H3), tetrafluorodisilane (Si2F4H2), pentafluorodisilane (Si2F5H), hexafluorodisilane (Si2F6), monochlorosilane (SiClH3), dichlorosilane (SiCl2H2), trichlorosilane (SiCl3H), tetrachlorosilane (SiCl4), monochlorodisilane (Si2ClH5), dichlorodisilane (Si2Cl2H4), trichlorodisilane (Si2Cl3H3), tetrachlorodisilane (Si2Cl4H2), pentachlorodisilane (Si2Cl5H), hexachlorodisilane (Si2Cl6) , monobromosilane (SiBrH3), dibromosilane (SiBr2H2), tribromosilane (SiBr3H), tetrabromosilane (SiBr4), monobromodisilane (Si2BrH5), dibromodisilane (Si2Br2H4), tribromodisilane (Si2Br3H3), tetrabromodisilane (Si2Br4H2), pentabromodisilane (Si2Br5H), hexabromodisilane (Si2Br6), monoiodosilane (SiIH3), diiodosilane (SiI2H2), triiodosilane (SiI3H), tetraiodosilane (SiI4), monoiododisilane (Si2IH5), diiododisilane (Si2I2H4), triiododisilane (Si2I3H3), tetraiododisilane (Si2I4H2), pentaiododisilane (Si2I5H) and hexaiododisilane (Si2I6), but are not limited to these.

[0042] The organosilane may be selected from diethylsilane (Et2SiH2) and tetraethyl orthosilicate (Si(OCH2CH3)4, TEOS), but is not limited thereto.

[0043] The organic aminosilane may include diisopropylaminosilane (H3Si(N(i-Prop)2)), bis(tert-butylamino)silane ((C4H9(H)N)2SiH2), tetrakis(dimethylamino)silane (Si(NMe2)4), tetrakis(ethylmethylamino)silane (Si(NEtMe)4), tetrakis(diethylamino)silane (Si(NEt2)4), tris(dimethylamino)silane (HSi(NMe2)3), tris(ethylmethylamino)silane (HSi(NEt 2)3), but are not limited thereto. As used herein, the abbreviation "Me" refers to a methyl group, the abbreviation "Et" refers to an ethyl group, and the abbreviation "i-Prop" refers to an isopropyl group.

[0044] In other example embodiments, the first precursor P1 and the second precursor P2 may be different precursors selected from all the silicon precursors described above. Here, the size of the first precursor P1 may be larger than the size of the second precursor P2. In example embodiments, the size of the first precursor P1 may be larger than the size of the second precursor P2, and the molecular weight of the first precursor P1 may be greater than the molecular weight of the second precursor P2.

[0045] exist Figure 1 During the supply of the first precursor P1 onto the lower structure 110 in the process P12 and / or during Figure 1 During the supply of the second precursor P2 onto the lower structure 110 in process P14, the interior of the reaction space may be maintained at a temperature of about 100° C. to about 600° C. The first precursor P1 may be supplied onto the lower structure 110 in a vaporized state. The second precursor P2 may be supplied after the supply and adsorption of the first precursor P1 are completed, and the second precursor P2 may also be supplied onto the lower structure 110 in a vaporized state. After the first precursor P1 and the second precursor P2 are supplied onto the lower structure 110, the first chemical adsorption layer AL1 of the first precursor P1, the second chemical adsorption layer AL2 of the second precursor P2, and the physical adsorption layer of each of the first precursor P1 and the second precursor P2 may remain on the inner wall of the trench TR and the top surface of the lower structure 110.

[0046] exist Figure 1In process P16, a purge gas is supplied into the reaction space to remove unnecessary materials from the lower structure 110. In this case, the physically adsorbed layer of each of the first precursor P1 and the second precursor P2 remaining on the lower structure 110 can also be removed due to the purge gas. For example, an inert gas such as argon (Ar), helium (He), and neon (Ne) or nitrogen (N2) can be used as the purge gas. During the supply of the purge gas into the reaction space, the interior of the reaction space can be maintained at a temperature of about 100° C. to about 600° C.

[0047] exist Figure 1 In the process P18, the reaction gas is supplied to the first chemical adsorption layer AL1 and the second chemical adsorption layer AL2 formed. Figure 2B Thus, the first ligand of the first precursor P1 and the second ligand of the second precursor P2 may be removed from the lower structure 110, and an atomic-scale material film including the first central element and the second central element may be formed.

[0048] The reaction gas may include, for example, an oxidizing gas or a reducing gas.

[0049] In example embodiments, the oxidizing gas may include O2, O3, H2O, NO, NO2, N2O, CO2, H2O2, HCOOH, CH3COOH, (CH3CO)2O, plasma O2, remote plasma O2, plasma N2O, plasma H2O, or a combination thereof, but is not limited thereto.

[0050] In example embodiments, the reducing gas may include H2, NH3, GeH4, hydrazine (N2H4), a hydrazine derivative, or a combination thereof, but is not limited thereto. The hydrazine derivative may include C1 to C10 alkyl hydrazine, dialkyl hydrazine, or a combination thereof, but is not limited thereto.

[0051] In other example embodiments, the reaction gas may include a nitrogen-containing gas. The nitrogen-containing gas may include an organic amine compound (such as monoalkylamine, dialkylamine, trialkylamine, and alkylenediamine), hydrazine, ammonia, or a combination thereof.

[0052] In an exemplary embodiment, when the Figure 1 In process P18, when a reaction gas is supplied onto the lower structure 110, the supply of an oxidizing gas as the reaction gas may include sequentially supplying a plurality of oxidizing gases having different oxidizing powers. In an exemplary embodiment, the plurality of oxidizing gases may include different oxidizing gases selected from the oxidizing gases exemplarily described above. The sequential supply of the plurality of oxidizing gases may include performing an additional purge process after supplying a first oxidizing gas having a first oxidizing power onto the lower structure 110 and before supplying a second oxidizing gas having a second oxidizing power onto the lower structure 110.

[0053] exist Figure 1 In process P20, the Figure 1 In a manner similar to that described in process P16, a purge gas may be supplied to the reaction space to remove unnecessary byproducts from the atomic-level material film. During the supply of the purge gas to the reaction space, the interior of the reaction space may be maintained at a temperature of approximately 100° C. to approximately 600° C.

[0054] exist Figure 1 In the process P22, it can be determined whether the material film has been formed on the lower structure 110 to the desired target thickness, and the process including Figure 1 The deposition cycles of processes P12 to P20 are repeated until the desired target thickness is obtained.

[0055] Reference Figure 2C , which can be repeated multiple times including Figure 1 The ALD cycle of processes P12 to P20 is performed, and thus, an initial material film P112 can be obtained on the lower structure 110.

[0056] When multiple repetitions include Figure 1 During the ALD cycles of processes P12 to P20, due to the steric hindrance effect provided by the first precursor P1, the atomic-scale material film can be preferentially deposited in the relatively deep portion of the trench TR rather than at the entrance side of the trench TR. Therefore, the deposition rate of the atomic-scale material film on the bottom surface of the trench TR can be higher than the deposition rate of the atomic-scale material film on the entrance side of the trench TR. As a result, a bottom-up filling method can be performed, and thus, the initial material film P112 can be formed to a greater thickness on the bottom surface of the trench TR than on the top surface of the lower structure 110.

[0057] Reference Figure 2D , can be compared with the reference Figure 2A and Figure 2B The method described is similar to Figure 2C The processes P12 and P14 are sequentially performed on the resultant structure, and thus, a first chemical adsorption layer AL1 and a second chemical adsorption layer AL2 may be formed on the initial material film P112 .

[0058] Reference Figure 2E , you can repeat Figure 2D The resulting structure performs Figure 1 The process of processes P16 to P20 and the process of determining whether the material film has been formed on the lower structure 110 to the desired target thickness according to process P22 are performed until the material film 112 having the desired target thickness is obtained. When it is determined in process P22 that the material film 112 having the target thickness is obtained in process P22, the reference process is terminated. Figure 1 The ALD process is described.

[0059] When based on Figure 1 and Figures 2A to 2E When forming the material film 112 by the method shown in , the number of ALD cycles performed can be adjusted to control the thickness of the material film 112. Figure 1 and Figure 2E When forming the material film 112 by the method shown in FIG. , energy (eg, plasma, light, and voltage) may be applied. The time point for applying the energy may be selected differently. For example, Figure 1 Energy (e.g., plasma, light, and voltage) is applied at the time point when the first precursor P1 is introduced into the reaction space in process P12, at the time point when the second precursor P2 is introduced into the reaction space in process P14, at the time point when the reaction gas is introduced into the reaction space in process P18, or between the respective time points. Figure 1 When the first precursor P1 is introduced into the reaction space in process P12 and when Figure 1 When the second precursor P2 is introduced into the reaction space in process P14 , various types of material films can be formed by appropriately selecting another precursor supplied together with the first precursor P1 or the second precursor P2 , a reaction gas, and reaction conditions.

[0060] In example embodiments, other precursors that may be supplied with the first precursor P1 or the second precursor P2 may include silicon (Si), carbon (C), or a metal. Other precursors may include at least one ligand selected from hydride, hydroxide, halide, azide, alkyl, alkenyl, cycloalkyl, allyl, alkynyl, amino, dialkylaminoalkyl, monoalkylamino, dialkylamino, diamino, di(silyl-alkyl)amino, di(alkyl-silyl)amino, disilylamino, alkoxy, alkoxyalkyl, hydrazide, phosphide, nitrile, dialkylaminoalkoxy, alkoxyalkyldialkylamino, siloxy, diketo, cyclopentadienyl, silyl, pyrazol, guanidine, phosphoguanidine, amidine, phosphoamidinium, ketimino, diketimino, and carbonyl.

[0061] You can use the reference Figure 1 and Figures 2A to 2E The material film obtained by the method of the described embodiment may include or may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride oxycarbon film, a metal oxide film, or a metal nitride film, but is not limited thereto.

[0062] The material film manufactured using the method according to the embodiment can be used for various purposes. For example, the material film can be used for device isolation films and insulating films of semiconductor devices, dielectric films included in capacitors, gate dielectric films of transistors, conductive barrier films for interconnects, resistor films, magnetic films, barrier metal films for liquid crystals, components for thin-film solar cells, components for semiconductor devices, or nanostructures, but is not limited to the examples described above.

[0063] In reference Figure 1 and Figures 2A to 2E In the method for forming a material film according to the described embodiment, after obtaining the material film 112 having a target thickness, a process of annealing the material film 112 can be performed. The annealing of the material film 112 can be performed at a temperature higher than the process temperature applied to the processes P12 to P20. For example, the annealing process can be performed at a temperature selected within the range of about 500°C to about 1150°C. For example, in one embodiment, a process temperature having a value from 100°C to 600°C is used in the processes P12 to P20, and a temperature having a value from 500°C to 1150°C (which is higher than the process temperature) is used for annealing. In an example embodiment, the annealing process can be performed in a nitrogen atmosphere. By performing the annealing process described above, the material film 112 can be densified and impurities can be removed from the material film 112, and therefore, the film characteristics of the material film 112 can be improved. For example, when using the method according to reference Figure 1 and Figures 2A to 2E When the silicon oxide film is formed by the method of the described embodiment, the silicon oxide film can be densified due to the annealing process, thereby increasing the density of the silicon oxide film.

[0064] According to the reference Figure 1 and Figures 2A to 2E The method of forming the material film 112 described, after forming the first chemical adsorption layer AL1 including the first precursor P1 of the first ligand having a relatively large size on the lower structure 110, the second chemical adsorption layer AL2 including the second precursor P2 of the second ligand having a relatively small size can be formed in the empty space exposed by the first chemical adsorption layer AL1, and the reaction gas can be supplied to the first chemical adsorption layer AL1 and the second chemical adsorption layer AL2 to form an atomic-level material film. Therefore, the deposition rate of the material film can be relatively low on the top surface of the lower structure 110 and the inlet side of the trench TR (for example, at a height above a specific threshold height), and relatively high on the deep area of ​​the trench TR (for example, at a height below a specific threshold height). The threshold height can be, for example, a certain amount of the total height of the trench TR (for example, 1 / 4 of the height, 1 / 3 of the height, or 1 / 2 of the height). Therefore, the interior of the trench TR can be filled with a high-purity material film 112 without gaps or voids. In addition, according to reference Figure 1 and Figures 2A to 2EThe method of forming the material film 112 described above does not require performing a separate etching process for each ALD cycle or using a separate inhibitor to reduce the deposition rate of the material film 112 formed on the top surface of the lower structure 110 and the entrance side of the trench TR. Therefore, it is possible to fundamentally prevent problems (such as the possibility of contamination caused by etching byproducts that may be generated during the etching process, or the adverse effects of residual components of the inhibitor on electrical characteristics). Therefore, a deep and narrow trench TR can be formed in the lower structure 110 using a relatively simple process and filled with a material film 112 that does not have gaps or voids. In addition, because the material film 112 filling the trench TR has a high purity, an IC device using the material film 112 can exhibit excellent electrical characteristics.

[0065] Figure 3 is a flow chart of a method for forming a material film according to an embodiment. Figure 3 The method of forming a silicon oxide film using an ALD process is described. The method of forming a material film according to this embodiment can be compared with the method of forming a silicon oxide film using an ALD process. Figure 1 and Figures 2A to 2E The described method of forming the material film is substantially the same. In the present embodiment, each of the central element of the first precursor P1 and the central element of the second precursor P2 includes a silicon atom.

[0066] Reference Figure 3 and Figure 2A In process P32 , a first precursor P1 having a Si central element and a first ligand is supplied onto the lower structure 110 in the reaction space to form a first chemical adsorption layer AL1 of the first precursor P1 on the lower structure 110 .

[0067] Reference Figure 3 and Figure 2B In process P34 , a second precursor P2 including a Si central element and a second ligand is supplied onto the lower structure 110 to form a second chemical adsorption layer AL2 of the second precursor P2 .

[0068] The detailed description of the first ligand of the first precursor P1 and the second ligand of the second precursor P2 can be found in reference Figure 1 The first ligand and the second ligand described in processes P12 and P14 are the same.

[0069] exist Figure 3 In the process P36, with reference to Figure 1 In the same manner as described in process P16 , a purge gas is supplied into the reaction space to remove unnecessary materials from the lower structure 110 .

[0070] exist Figure 3 In the process P38, with reference to Figure 1In a manner similar to that described in process P18, an oxidizing gas is supplied to the first chemical adsorption layer AL1 and the second chemical adsorption layer AL2 formed therein. Figure 2B Thus, the first ligand of the first precursor P1 and the second ligand of the second precursor P2 can be removed from the lower structure 110, and an atomic-level silicon oxide film including a Si central element is formed.

[0071] exist Figure 3 In the process P40, the Figure 1 In a manner similar to that described in process P20, a purge gas is supplied into the reaction space, and thus, unnecessary by-products can be removed from the atomic-level silicon oxide film including the Si central element.

[0072] exist Figure 3 In the process P42, it is determined whether the silicon oxide film has been formed to the target thickness on the lower structure 110, and the process may be repeated including Figure 3 The ALD process from P32 to P40 is cycled until the silicon oxide film reaches the target thickness. Figure 3 The use of silicon described in can also occur in e.g. Figure 4 and Figure 5 Or in the embodiments described later in the following drawings.

[0073] Figure 4 is a flowchart of a method of forming a material film according to an embodiment.

[0074] exist Figure 4 The method for forming a material film shown in FIG. Figure 1 and Figures 2A to 2E The method of forming the material film described is essentially the same. However, in Figure 4 In the method of forming a material film shown in , after unnecessary byproducts are removed from the atomic-level material film by supplying a purge gas according to process P20 , the resulting structure including the atomic-level material film is treated using hydrogen plasma in process P52 .

[0075] Due to the hydrogen plasma treatment, unnecessary impurities that may remain in the atomic-level material film can be removed from the atomic-level material film. For example, because the first precursor P1 includes first ligands having a relatively large size, impurities derived from the first ligands may remain in the atomic-level material film and are effectively removed due to the hydrogen plasma treatment. Therefore, it is possible to remove the impurities by using Figure 4 The method shown in is used to form a material film to further improve the purity of the material film. Figure 4 (and the following Figure 5) shows that the hydrogen plasma treatment of process P52 occurs before the step of determining whether the material film has the target thickness (process P52), but in some embodiments, this step can be performed after process P22 so that this step only occurs once between the beginning and the end of the entire process.

[0076] Figure 5 is a flowchart of a method of forming a material film according to an embodiment.

[0077] exist Figure 5 The method for forming a material film shown in FIG. Figure 1 and Figures 2A to 2E The method of forming the material film described is essentially the same. However, in Figure 5 In the method of forming a material film shown in FIG, the resulting structure obtained after performing the ALD cycle including processes P12 to P20 multiple times can be treated with hydrogen plasma in process P64. Figure 1 and Figures 2A to 2E Let's understand the detailed description of processes P12 to P20.

[0078] exist Figure 5 In process P62, the number of times the ALD cycle including processes P12 to P20 is repeated may be confirmed. When the number of times the ALD cycle is repeated reaches a predetermined set value N (here, N is an integer greater than or equal to 2), hydrogen plasma treatment may be performed according to process P64. In an example embodiment, the predetermined set value N may be selected within a range of 2 to 10. Due to the hydrogen plasma treatment, unnecessary impurities that may remain in the plurality of atomic-level material films may be removed.

[0079] exist Figure 5 In process P22, it is determined whether a desired material film has been formed to a target thickness on the lower structure 110, and processes P12 to P20, P62, and P64 may be repeated until the material film obtains the target thickness.

[0080] According to the reference Figures 1 to 5 In the method of forming a material film according to the embodiment described, the groove (refer to Figure 2E The interior of the trench TR) can be filled with a high-purity material film 112 without gaps or voids. In addition, the formation of the material film 112 may not involve an additional etching process for each cycle of the ALD process, or may not use an additional inhibitor to reduce the deposition rate at the top surface of the lower structure 110 and the entrance side of the trench TR. Therefore, it may be possible to fundamentally prevent problems (such as the possibility of contamination due to the use of an etching process or an inhibitor, or the adverse effects of the etching process or the inhibitor on electrical characteristics). Therefore, in accordance with the reference Figures 1 to 5In the method of forming the material film of the described embodiment, a deep and narrow trench TR can be formed in the lower structure 110, and the trench TR can be easily filled with the material film 112 without gaps or voids using a relatively simple process. In addition, because the trench TR is filled with the material film 112 having high purity, an IC device using the material film 112 can exhibit excellent electrical characteristics.

[0081] Figure 6 is a plan view of a schematic configuration of an integrated circuit (IC) device 200 according to an embodiment.

[0082] Reference Figure 6 The IC device 200 may include a substrate 210 , the substrate 210 including a first region RA1 , a second region RA2 , and an interface region IF. The second region RA2 surrounds the first region RA1 , and the interface region IF is between the first region RA1 and the second region RA2 .

[0083] The substrate 210 may include, for example, a semiconductor element (e.g., silicon (Si) and germanium (Ge)) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), or may be formed of, for example, a semiconductor element (e.g., silicon (Si) and germanium (Ge)) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate 210 may include a conductive region, for example, a doped well or a doped structure.

[0084] The first region RA1 may include a memory cell region of the IC device 200. In example embodiments, the first region RA1 may be a memory cell region of a dynamic random access memory (DRAM). The first region RA1 may include a unit memory cell having a transistor and a capacitor or a unit memory cell having a switching element and a variable resistor.

[0085] The second area RA2 may be a core area or a peripheral circuit area (hereinafter, inclusively referred to as a "peripheral circuit area"). Peripheral circuits required to drive the memory cells located in the first area RA1 may be arranged in the second area RA2. In an example embodiment, the second area RA2 may include a row decoder, a sense amplifier, a column decoder, a self-refresh control circuit, a command decoder, a mode register configuration / extended mode register configuration (MRS / EMRS) circuit, an address buffer, a data input / output (I / O) circuit, a clock circuit configured to generate a clock signal, and a power supply circuit configured to receive an externally applied power supply voltage and generate or divide an internal voltage.

[0086] A plurality of conductive wires and an insulating structure may be arranged in the interface region IF. The plurality of conductive wires may be installed to enable electrical connection between the first region RA1 and the second region RA2, and the insulating structure may be provided to enable insulation between the first region RA1 and the second region RA2.

[0087] Figure 7 is a schematic plan layout diagram of main components of the memory cell array area MCA of the IC device 200 according to the embodiment. Figure 7 The memory cell array area MCA shown in FIG may be included in Figure 6 In the first area RA1 shown in .

[0088] Reference Figure 7 , the memory cell array area MCA may include a plurality of active areas A1. Each of the plurality of active areas A1 may be arranged to have a major axis in a diagonal direction (Q direction) relative to a first direction (X direction) and a second direction (Y direction). Some of the plurality of active areas A1 may be arranged in a line in the first direction (X direction). Some other active areas A1 in the plurality of active areas A1 may be arranged in a line in a second direction (Y direction) intersecting the first direction (X direction).

[0089] A plurality of word lines WL may intersect with a plurality of active areas A1 and extend parallel to each other along a first direction (X direction). A plurality of bit lines BL may extend parallel to each other along a second direction (Y direction) on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of active areas A1 through direct contacts DC (e.g., vertical direct contacts or pillars extending in a vertical direction (Z direction) that contact the corresponding bit lines BL and the active areas A1). It should be noted that the term "contact" as used in this specification as a verb refers to direct connection (i.e., touching).

[0090] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of buried contacts BC may be arranged in a line in each of a first direction (X direction) and a second direction (Y direction). A plurality of bonding pads LP may be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of bonding pads LP may connect lower electrodes (not shown) of capacitors formed on the plurality of bit lines BL to the active area A1. Each of the plurality of bonding pads LP may partially overlap with the buried contact BC.

[0091] Figures 8A to 8C as well as Figure 9A and Figure 9B is a cross-sectional view of major components of an IC device 200 according to an embodiment.

[0092] More specifically, Figure 8A It is along Figure 7A cross-sectional view of some components taken along line AA'. Figure 8B It is along Figure 7 A cross-sectional view of some components taken along line BB'. Figure 8C It is along Figure 7 A cross-sectional view of some components taken along line CC'. Figure 9A and Figure 9B 2 is a cross-sectional view of the cross-sectional structure of each partial region of the memory cell array region MCA, the interface region IF, and the peripheral circuit region PERI of the IC device 200. Figure 9A and Figure 9B In the embodiment, the memory cell array region MCA and the peripheral circuit region PERI may correspond to Figure 6 The first and second regions RA1 and RA2 are shown in FIG, and the interface region IF may be a region between the memory cell array region MCA and the peripheral circuit region PERI. Figure 9A Shown along Figure 7 Some components in the local area intercepted by the line AA' and the interface area IF and the peripheral circuit area PERI adjacent to the local area. Figure 9B Shown along Figure 7 Some components in the local area intercepted by the line CC' and the interface area IF and the peripheral circuit area PERI adjacent to the local area.

[0093] Reference Figures 8A to 8C as well as Figure 9A and Figure 9B In the IC device 200, a device isolation trench T1 may be formed in the memory cell array area MCA of the substrate 210, and an interface trench T2 may be formed in the interface area IF of the substrate 210. A device isolation film 212 may be formed on the substrate 210 to fill the device isolation trench T1 and the interface trench T2. The device isolation film 212 filling the device isolation trench T1 in the memory cell array area MCA may define a plurality of active areas A1 in the memory cell array area MCA, while the device isolation film 212 filling the interface trench T2 in the interface area IF may define an active area A2 in the peripheral circuit area PERI.

[0094] The device isolation film 212 may include a silicon oxide film. In example embodiments, the device isolation film 212 may include a silicon oxide film, which may be formed using a reference Figures 1 to 5 The described method of forming a material film may be formed by making various modifications and changes within the scope of the inventive concept.

[0095] The device isolation film 212 may not include impurities that adversely affect electrical characteristics. For example, the device isolation film 212 may include a silicon oxide film having an allowable carbon atom content of less than about 3 atomic percent (at%) (e.g., from 0% to just below 3% or between 0% and just below 3%). The carbon atoms included in the device isolation film 212 at the allowable content may be derived from the Figure 1 The first ligand of the first precursor P1 used in process P12 and the Figure 1 The second ligand of the second precursor P2 used in process P14.

[0096] Specifically, the first ligand of the first precursor P1 may contain a greater number of carbon atoms than the second ligand of the second precursor P2. Figure 2B As described, during the formation of the device isolation film 212, the first chemical adsorption layer AL1 of the first precursor P1 can be primarily formed on the inlet side of each of the device isolation trench T1 and the interface trench T2, and the second chemical adsorption layer AL2 of the second precursor P2 can be primarily formed in the deep region or near the bottom surface of each of the device isolation trench T1 and the interface trench T2. Therefore, the carbon content of the upper portion 212U of the device isolation film 212 filling the device isolation trench T1 and the interface trench T2 can be higher than the carbon content of the lower portion 212L thereof within an allowable range. The upper portion 212U of the device isolation film 212 can be a portion of the device isolation film 212 relatively close to the inlet of each of the device isolation trench T1 and the interface trench T2, that is, a portion of the device isolation film 212 relatively close to the top surface 210T of the substrate 210. The lower portion 212L of the device isolation film 212 can be a portion of the device isolation film 212 relatively close to the bottom surface of each of the device isolation trench T1 and the interface trench T2.

[0097] In an example embodiment, the upper portion 212U of the device isolation film 212 may include a first content of carbon atoms selected within a range greater than 0 at % and less than approximately 3 at %. The lower portion 212L of the device isolation film 212 may include a second content of carbon atoms selected within a range greater than or equal to 0 at % and less than approximately 3 at %, and the second content may be lower than the first content. Terms such as "about" or "approximately" may reflect an amount, size, orientation, or layout that varies only in a small relative manner and / or in a manner that does not significantly change the operation, function, or structure of certain elements. For example, a range from "about 0.1 to about 1" may include ranges such as 0%-5% deviations around 0.1 and 0% to 5% deviations around 1, especially where such deviations maintain the same effect as the listed range.

[0098] The memory cell array area MCA may include a plurality of gate trenches GT, which intersect the plurality of active regions A1 and the device isolation film 212 and extend in a first direction (X direction). A gate dielectric film 220, a conductive line 230, and an insulating cap pattern 270 may be formed inside each of the plurality of gate trenches GT. The gate dielectric film 220 may cover the inner wall of the gate trench GT, the conductive line 230 may partially fill the gate trench GT on the gate dielectric film 220, and the insulating cap pattern 270 may cover the conductive line 230. The conductive line 230 may constitute Figure 7 The word line WL shown in .

[0099] At the bottom surface of the gate trench GT, the level of the portion of the gate trench GT where the active area A1 of the substrate 210 is exposed (e.g., the vertical level measured from the bottom of the substrate 210) (e.g., the vertical level of the topmost surface of the active area A1) may be higher than the level of the portion of the gate trench GT where the device isolation film 212 is exposed (e.g., the vertical level measured from the bottom of the substrate 210) (e.g., the vertical level of the topmost surface of the device isolation film 212). The bottom surface of the conductive line 230 may have a rough shape corresponding to the contour of the bottom surface of the gate trench GT. As used herein, the term "level" may refer to a height in the vertical direction (Z direction).

[0100] The gate dielectric film 220 may cover the inner surface of the gate trench GT and may contact the plurality of active regions A1 and the device isolation film 212. The gate dielectric film 220 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a higher dielectric constant than the silicon oxide film. The high-k dielectric film may have a dielectric constant of about 10 to about 25. For example, the high-k dielectric film may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2, but is not limited thereto.

[0101] Each of the conductive line 230 and the insulating cap pattern 270 may have a sidewall facing the active area A1. The conductive line 230 may include a metal, a metal nitride, a metal carbide, or a combination thereof. In example embodiments, the conductive line 230 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. The insulating cap pattern 270 may include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a combination thereof. Source and drain regions SD may be formed on opposite sides of the conductive line 230 in the plurality of active areas A1, respectively.

[0102] 10A to 10F is a cross-sectional view of a process sequence of a method for manufacturing an IC device according to an embodiment. 10A to 10F Describing the manufacturing process according to example embodiments Figures 8A to 8C as well as Figure 9A and Figure 9B The method of the IC device 200 shown in FIG.

[0103] Reference Figure 10A , preparing a substrate 210 including a memory cell array area MCA, an interface area IF and a peripheral circuit area PERI.

[0104] A mask pattern M1 is formed on the substrate 210, and the substrate 210 can be etched using the mask pattern M1 as an etching mask, thereby forming a device isolation trench T1 in the memory cell array region MCA and an interface trench T2 in the interface region IF. Due to the device isolation trench T1 and the interface trench T2, a plurality of active areas A1 can be defined in the memory cell array region MCA, and an active area A2 can be defined in the peripheral circuit region PERI.

[0105] The mask pattern M1 may be formed to cover a portion of the memory cell array area MCA, a portion of the interface area IF, and the peripheral circuit area PERI. The mask pattern M1 may include a hard mask including an oxide film, polysilicon, or a combination thereof.

[0106] An anisotropic dry etching process may be performed on the substrate 210 to form the device isolation trench T1 and the interface trench T2. When the substrate 210 includes silicon (Si), the anisotropic etching process may be performed using an inductively coupled plasma (ICP) etching apparatus. In an exemplary embodiment, during the anisotropic etching process, a cycle process of repeating an oxidation process for oxidizing the exposed surface of the substrate 210 and an etching process for partially removing the substrate 210 is performed multiple times.

[0107] Reference Figure 10B ,from Figure 10A The mask pattern M1 is removed from the resulting structure, and a device isolation film 212 is formed to fill the device isolation trench T1 and the interface trench T2. Figures 1 to 5 The described method of forming a material film or any one method selected from methods variously modified and changed within the scope of the inventive concept is used to form the device isolation film 212. The device isolation film 212 may include a silicon oxide film.

[0108] Device isolation film 212 may include a portion filling device isolation trench T1, a portion filling interface trench T2, and a portion covering top surface 210T of substrate 210. Because device isolation film 212 is formed using a material film forming method according to the inventive concept, even when device isolation film 212 is formed to simultaneously fill a narrow and deep trench structure (e.g., device isolation trench T1 formed in memory cell array area MCA) and a trench structure having a relatively large width (e.g., interface trench T2) (e.g., two different trenches having two different width-to-depth aspect ratios), the portion of device isolation film 212 filling device isolation trench T1 and the portion of device isolation film 212 filling interface trench T2 can both comprise high-quality insulating films without seams or voids. When device isolation film 212 comprises a silicon oxide film, the portion of device isolation film 212 filling device isolation trench T1 and the portion filling interface trench T2 can comprise high-purity silicon oxide films and provide excellent electrical characteristics.

[0109] The portion of the device isolation film 212 remaining on the top surface 210T of the substrate 210 may protect the surface of the substrate 210 during a subsequent ion implantation process for implanting impurity ions into the substrate 210 or a subsequent etching process.

[0110] Reference Figure 10C A portion of the substrate 210 and a portion of the device isolation film 212 are removed (eg, etched) using the mask pattern M2 as an etching mask, thereby forming a gate trench GT crossing the plurality of active regions A1 and the device isolation film 212 and extending in a first direction (X direction).

[0111] To form the gate trench GT, a portion of each of the substrate 210 and the device isolation film 212 may be etched under a condition where the etching rate of the substrate 210 is substantially equal to the etching rate of the device isolation film 212. Subsequently, an etching process may be performed under a condition where the etching rate of the device isolation film 212 is higher than the etching rate of the substrate 210, so that the top surface of each of the plurality of active regions A1 exposed at the bottom surface of the gate trench GT may be at a higher level than the top surface of the device isolation film 212 exposed at the bottom surface of the gate trench GT. The mask pattern M2 may include an oxide film, an amorphous carbon layer (ACL), a silicon oxynitride film, or a combination thereof.

[0112] Reference Figure 10D ,exist Figure 10C A gate dielectric film 220 is formed on the resulting structure to conformally cover the inner wall of the gate trench GT. The gate dielectric film 220 may be formed using an ALD process.

[0113] Reference Figure 10EA conductive layer (not shown) may be formed on the gate dielectric film 220 to fill the gate trench GT. Thereafter, the conductive layer may be etched back to leave the conductive line 230 partially filling the gate trench GT. While the conductive layer is being etched back to form the conductive line 230, a portion of the mask pattern M2 may be consumed to reduce the thickness of the mask pattern M2.

[0114] The conductive layer may have a structure in which a metal-containing liner and a metal film are sequentially stacked. The metal-containing liner may contact the gate dielectric film 220. The metal film may be spaced apart from the gate dielectric film 220 and surrounded by the metal-containing liner. In example embodiments, the metal-containing liner may include titanium nitride (TiN), and the metal film may include tungsten (W), but the inventive concept is not limited thereto.

[0115] Reference Figure 10F , the inner space of the gate trench GT remaining on the conductive line 230 is filled with the insulating cap pattern 270. Thereafter, the mask pattern M2 remaining on the substrate 210 is removed, and a portion of the device isolation film 212 covering the top surface 210T of the substrate 210 may be removed to expose the top surface 210T of the substrate 210.

[0116] According to the reference 10A to 10F In the method for manufacturing the IC device 200 described herein, when the device isolation film 212 is formed to simultaneously fill a narrow and deep trench structure (e.g., the device isolation trench T1 formed in the memory cell array region MCA) and a trench structure having a relatively large width (e.g., the interface trench T2), the device isolation trench T1 and the interface trench T2 can be filled with the high-purity device isolation film 212 without causing seams or voids. Furthermore, the device isolation trench T1 formed in the memory cell array region MCA can have different widths in the lateral direction (e.g., the X direction or the Y direction). When the device isolation film 212 is formed to fill the device isolation trenches T1 having different widths, regardless of the different widths of the device isolation trenches T1, the interior of the device isolation trench T1 can be filled with the high-purity device isolation film 212 without causing seams or voids.

[0117] In addition, according to the reference 10A to 10FThe method of manufacturing the IC device 200 described above can eliminate the need to perform a separate etching process for each ALD cycle or use a separate inhibitor to reduce the deposition rate of the device isolation film 212 formed on the inlet side of each of the device isolation trench T1 and the interface trench T2. Therefore, it is possible to fundamentally prevent problems such as the possibility of contamination due to the etching process or the use of an inhibitor, or the adverse effects of the etching process or the inhibitor on electrical characteristics. Therefore, the device isolation trench T1 and the interface trench T2 having different widths can be filled with the device isolation film 212 using a relatively simple process without causing gaps or voids. In addition, because the insulating film included in the device isolation film 212 has a high purity, the electrical characteristics of the IC device 200 can be improved.

[0118] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for forming a material film, the method comprising the following steps: supplying a first precursor including a first central element and a first ligand having a first size onto the lower structure formed with the groove, and forming a first chemical adsorption layer of the first precursor on the lower structure; supplying a second precursor including a second central element and a second ligand having a second size onto the resulting structure in which the first chemisorption layer is formed, and forming a second chemisorption layer of the second precursor on the lower structure, wherein the second size is smaller than the first size; and forming a material film including a first central element and a second central element by supplying a reaction gas to the first chemical adsorption layer and the second chemical adsorption layer to remove the first ligand and the second ligand from the underlying structure, Wherein, each of the first central element and the second central element is silicon, boron or metal.

2. The method according to claim 1, wherein The first molecular weight of the first precursor is greater than the second molecular weight of the second precursor.

3. The method according to claim 1, wherein The first ligand includes an aromatic functional group, an alkoxy functional group, a thiol functional group or a -Si-(CH2) n -Si- group, wherein n is an integer ranging from 1 to 5.

4. The method according to claim 1, wherein The reaction gas includes an oxidizing gas or a reducing gas. The method according to claim 1 , further comprising treating the material film using hydrogen plasma.

6. The method according to claim 1, wherein The material film is part of an integrated circuit device, and the method is a method of forming an integrated circuit device including a lower structure having a stepped structure defining a trench, wherein a material film is formed inside the trench, and The forming of the material film includes performing an atomic layer deposition cycle at least once.

7. A method for manufacturing an integrated circuit device, the method comprising the steps of: preparing a lower structure having a stepped structure defining a groove; as well as A material film is formed inside the trench, The forming of the material film includes performing at least one atomic layer deposition cycle, wherein the atomic layer deposition cycle includes the following steps: In a first process, a first precursor including a first central element and a first ligand having a first size is supplied into the trench, and a first chemical adsorption layer of the first precursor is formed inside the trench; a second process of supplying a second precursor including a second central element and a second ligand having a second size into the trench in which the first chemisorption layer is formed, and forming a second chemisorption layer of the second precursor inside the trench, wherein the second size is smaller than the first size; and In a third process, a reaction gas is supplied to the first chemical adsorption layer and the second chemical adsorption layer to form an atomic-scale material film including the first central element and the second central element inside the trench.

8. The method according to claim 7, wherein: The atomic layer deposition cycle further includes a fourth process of treating the atomic-level material film using hydrogen plasma after performing the third process.

9. The method according to claim 7, wherein: The forming of the material film further includes treating the material film at the atomic level using hydrogen plasma after performing the atomic layer deposition cycles multiple times.

10. The method according to claim 7, wherein: The material film is a silicon oxide film, and Each of the first central element and the second central element is a silicon atom.

11. The method according to claim 7, wherein: The material film is a silicon oxide film, The first ligand includes an aromatic functional group, an alkoxy functional group, a thiol functional group or a -Si-(CH2) n -Si- group, and The second ligand does not include an aromatic functional group, an alkoxy functional group, a thiol functional group or a -Si-(CH2) n -Si- group, Here, n is an integer ranging from 1 to 5.

12. The method according to claim 7, wherein: The material film is a silicon oxide film, and The second precursor includes a silane, a disilane, a halosilane, an organosilane, or an organoaminosilane.

13. An integrated circuit device manufactured using the method according to claim 7, in, The material film includes a silicon oxide film, wherein an upper portion of the silicon oxide film relatively close to an entrance of the trench includes a first content of carbon atoms, and A lower portion of the silicon oxide film relatively close to a bottom surface of the trench includes a second content of carbon atoms lower than the first content.

14. A method for manufacturing an integrated circuit device, the method comprising the steps of: forming a trench in a substrate defining an active area; as well as A silicon oxide film is formed inside the trench. The forming of the silicon oxide film includes performing at least one atomic layer deposition cycle, wherein the atomic layer deposition cycle includes the following steps: In a first process, a first precursor including a first silicon central element and a first ligand having a first size is supplied into the trench, and a first chemical adsorption layer of the first precursor is formed inside the trench; a second process of supplying a second precursor including a second silicon central element and a second ligand having a second size into the trench in which the first chemical adsorption layer is formed, and forming a second chemical adsorption layer of the second precursor inside the trench, wherein the second size is smaller than the first size; and In the third process, an atomic silicon oxide film is formed inside the trench by supplying an oxidizing gas to the first chemical adsorption layer and the second chemical adsorption layer.

15. The method according to claim 14, wherein The first ligand includes an aromatic functional group, an alkoxy functional group, a thiol functional group or a -Si-(CH2) n -Si- group, and The second ligand does not include an aromatic functional group, an alkoxy functional group, a thiol functional group or a -Si-(CH2) n -Si- group, Here, n is an integer ranging from 1 to 5.

16. The method according to claim 14, wherein The first molecular weight of the first precursor is greater than the second molecular weight of the second precursor.

17. The method according to claim 14, wherein: The oxidizing gas includes O2, O3, H2O, NO, NO2, N2O, CO2, H2O2, HCOOH, CH3COOH, (CH3CO)2O, plasma O2, remote plasma O2, plasma N2O, plasma H2O, or a combination thereof.

18. The method according to claim 14, wherein The atomic layer deposition cycle further includes a fourth process of treating the atomic silicon oxide film using hydrogen plasma after performing the third process.

19. The method according to claim 14, wherein The formation of the silicon oxide film further includes treating the atomic silicon oxide film using hydrogen plasma after performing the atomic layer deposition cycles multiple times.

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