Integrated circuit manufacturing processes using buffer layers as a stop for chemical mechanical polishing of coupling dielectric oxide layers.

Abstract

This disclosure relates to an integrated circuit manufacturing process using a buffer layer as a stop for chemical mechanical polishing of a coupled dielectric oxide layer. A first dielectric layer made of a first dielectric material is deposited on a semiconductor substrate. A buffer layer is then deposited on the upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is conformally deposited on the buffer layer and fills the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove the overlying portion of the second dielectric layer, wherein the buffer layer serves as a polishing stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallized dielectric layer having a substantially flat upper surface.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 950316, filed December 19, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to the fabrication of integrated circuits, and more particularly to chemical mechanical polishing (CMP) of coupling dielectric oxide layers to form a pre-metallized dielectric (PMD) layer having a flat top surface. Background Technology

[0004] refer to Figure 1A In the field of integrated circuit manufacturing, it is known that depositing a layer 10 of dielectric material (e.g., oxide) on a semiconductor (e.g., silicon) substrate 12 has formed integrated circuit devices such as transistors 14 within the semiconductor substrate 12. The deposition of layer 10 is conformal, therefore, due to the presence of the underlying integrated circuit device structure, the upper (top) surface 16 of layer 10 will not be flat. Layer 10 is used in the formation of a pre-metallized dielectric (PMD) layer for integrated circuits. The flatness of the upper (top) surface of the PMD layer is crucial for subsequent steps in the manufacturing process. To achieve flatness, chemical mechanical polishing (CMP) is typically performed on layer 10 to provide the desired degree of flatness to the upper surface 16', the result of which is as follows: Figure 1B As shown in the image.

[0005] In some integrated circuits, the PMD layer is formed from a coupling dielectric oxide layer. To achieve this structure, trenches 20 are formed in the planarization layer 10. Trenches 20 can have any suitable depth and, in a typical embodiment, extend downwards to the upper surface of the semiconductor substrate 12, such as... Figure 1C As shown in the diagram. Then, on top of layer 10 and filling the trench 20, layer 22 of a dielectric material (e.g., an oxide, but different from the oxide of layer 10) is deposited. The deposition of layer 22 is conformal, so the upper (top) surface 26 of layer 22 will not be flat due to the presence of the underlying layer 10 and the trench 20. See also Figure 1DLayers 10 and 22 are used in the formation of a pre-metallized dielectric (PMD) layer for an integrated circuit with a coupled dielectric oxide configuration. The flatness of the upper (top) surface of the PMD layer is crucial for subsequent steps in the fabrication process. To achieve flatness, chemical mechanical polishing (CMP) is performed on layer 22, where CMP ideally stops on layer 10 to form a flat top surface for the PMD layer. However, CMP becomes unstable when it reaches the vertically extending interface 28 of the coupled dielectric between layers 10 and 22 at trench 20. This occurs because layers 10 and 22 are made of different oxide materials with significantly different polishing rates. For example, if the oxide material used for layer 10 is tetraethyl borophosphosilicate orthosilicate (BPTEOS) and the oxide material used for layer 22 is tetraethyl orthosilicate (TEOS), the polishing rate of layer 10 can be almost twice that of layer 22. As a result, as Figure 1E As shown, there is a non-negligible difference in thickness between the portion of the PMD layer formed by layer 10 and the portion of the PMD layer formed by layer 22, wherein there is an overall non-flat top surface 26', and there may also be non-uniformity 26" (possibly with depressions 27) regarding the flatness of the top surface of the portion of the PMD layer formed by layer 10.

[0006] Therefore, there is a need in the art for a manufacturing process relating to the fabrication of a PMD layer formed from a coupling dielectric oxide layer, which can achieve a flat top surface after CMP. Summary of the Invention

[0007] In one embodiment, a method includes: depositing a first dielectric layer made of a first dielectric material; depositing a buffer layer on an upper surface of the first dielectric layer; opening a trench extending through the buffer layer and the first dielectric layer; conformally depositing a second dielectric layer made of a second dielectric material on the buffer layer and filling the trench; performing chemical mechanical polishing on the second dielectric layer, wherein the chemical mechanical polishing uses the buffer layer as a polishing stop; and removing the buffer layer such that the first dielectric layer and the second dielectric material filling the trench form a pre-metallized dielectric layer having a substantially flat upper surface.

[0008] A buffer layer protects the first dielectric material from erosion by chemical mechanical polishing, thereby supporting the surface flatness of the vertically extended interface of the pre-metallized dielectric layer across the coupled dielectric structure, which is formed by the first dielectric layer and a second dielectric material filling the trench.

[0009] The method further includes: forming a first metal contact that extends through a second dielectric material in a trench to an upper surface of an underlying semiconductor substrate; and forming a second metal contact that extends through the first dielectric material to an integrated circuit device supported by the underlying semiconductor substrate.

[0010] The method also includes forming a hole that extends through a second dielectric material in a trench to the upper surface of an underlying semiconductor substrate to expose a microelectromechanical system (MEMS) device. Attached Figure Description

[0011] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, in which:

[0012] Figures 1A-1E The illustration shows a prior art process for forming a pre-metallized dielectric (PMD) layer;

[0013] Figures 2A-2H The diagram illustrates the process for forming a pre-metallized dielectric (PMD) layer, which includes a coupling dielectric oxide layer.

[0014] Figure 3 The illustration shows additional steps in the process of forming a hole that extends through the PMD layer to expose the underlying substrate and microelectromechanical systems (MEMS) device. Detailed Implementation

[0015] Now for reference Figures 2A-2H , Figures 2A-2H The diagram illustrates the process for forming a pre-metallized dielectric (PMD) layer that includes a coupling dielectric oxide layer.

[0016] A semiconductor (e.g., silicon) substrate 112 supports an integrated circuit device such as a transistor 114. An undoped silicon glass (USG) layer 120 is deposited over the circuit device and substrate 112 and planarized using chemical mechanical polishing (CMP). A first dielectric oxide material layer 122 is deposited over layer 120 and planarized using CMP to provide a flat top surface 126. In one embodiment, the first dielectric oxide material is tetraethyl borophosphosilicate orthosilicate (BPTEOS). See also Figure 2A .

[0017] Next, a buffer material layer 130 is deposited on the flat top surface 126 of layer 122. The material used for buffer layer 130 should exhibit a significant selectivity difference to the slurry used during chemical mechanical polishing. In one embodiment, the buffer material used for layer 130 may include silicon nitride (SiN). Alternatively, the buffer layer may include silicon carbonitride (SiCN) or hydrogen-containing silicon carbon oxide (SiCOH). Further, a metal and / or metal nitride barrier layer material may be used for buffer layer 130. Examples include a titanium / titanium nitride barrier or a tantalum / tantalum nitride barrier. A photolithographically patterned mask 132 is then formed on the top surface of layer 130. Mask 132 has mask openings 134. See also Figure 2B .

[0018] Then, an etching process is performed through mask opening 132 to open trenches 140 in layers 120, 122, and 130. For example, in a plane parallel to the top surface of the substrate, trenches 140 may have dimensions defined by a width in the range of hundreds of micrometers (e.g., approximately 100 μm) and a length in the range of tens of millimeters (e.g., approximately 20 mm). In a preferred embodiment, trenches 140 extend completely through layers 120, 122, and 130 to reach the upper surface of the semiconductor substrate 112. Figure 2C The results are shown in the diagram. For example, the etching process can be performed in multiple etching steps, including: a first etching to remove a portion of layer 130; a second step to remove layers 120 and 122; and a third etching to then remove the structure (not shown) located between the bottom of layer 120 and the top surface of semiconductor substrate 112. The first etching may in this case include an etching customized to penetrate buffer layer 130; the second etching may in this case include an etching customized to remove material from layers 120 and 122; and the third etching may in this case include an etching customized to remove the underlying structure. Appropriate cleaning operations may be performed after each etching. It will also be understood that the second and third etchings may use the remaining portion of buffer layer 130 as a hard mask, in which case the mask 132 may be stripped during cleaning performed after the first etching.

[0019] Then, a layer 144 of a second dielectric oxide material (different from the first dielectric oxide material) is deposited on top of the buffer layer 130, and the trench 140 is filled. The deposition of layer 144 is conformal, so the upper (top) surface 146 of layer 144 will be uneven due to the presence of the underlying layer and the trench 140. In one embodiment, the second dielectric oxide material is tetraethyl orthosilicate (TEOS). See also Figure 2D .

[0020] In one embodiment, the first and second dielectric oxide materials are different forms of silicon oxide. For example, the two silicon oxides can be doped differently, including the possibility that one is doped and the other is undoped. The selection of the dielectric oxide material can, for example, depend on the dielectric properties of the material, based on the use of the material at a specific location on the substrate 112.

[0021] Layers 120, 122, and 144 are used in the formation of the pre-metallized dielectric (PMD) layer for the integrated circuit. The planarity of the upper (top) surface of the PMD layer is crucial for subsequent steps in the manufacturing process. To achieve planarity, chemical mechanical polishing (CMP) is performed on layer 144, with the CMP stopping at buffer 130. Figure 2E The results are shown in the figure, where the upper surface of layer 144 in trench 140 is generally coplanar with the upper surface of layer 122. It will be noted that at trench 140, at and / or near the vertical extension interface 150 of the coupling dielectric between layers 120 / 122 and layer 144, there is some inhomogeneity (such as depressions) in the second dielectric material, but the buffer layer 130 has successfully suppressed the erosion of the first dielectric material at the interface 150, thus maintaining the possibility of achieving a flat upper surface.

[0022] Then, the buffer layer 130 is removed. For example, a dry etching process selectively etching the material of the buffer layer 130 can be used. After etching, appropriate cleaning operations can be performed. Figure 2F The results are shown in the figure. Advantageously, removing the buffer layer 130 after CMP completion allows for a flat surface of the PMD layer without introducing additional film layers into the final layer stack for the fabricated integrated circuit.

[0023] It will be noted that the portions having layers 120 / 122 and the remaining portions of layer 144 filling the grooves 140 exhibit substantially uniform thickness. For example, in embodiments of the aforementioned process, this is different from not using the buffer layer 130 (see...). Figure 1E Around ) (with approximately) Compared to a difference of approximately 5.5% standard deviation, the PMD layer exhibits a difference in thickness between the portion containing layers 120 / 122 and the remaining portion of layer 144. to Differences (with) (Approximately 1.4% standard deviation).

[0024] If the remaining inhomogeneity at and / or near the vertically extended interface 150° is acceptable, the process for forming the PMD layer is complete. Alternatively, further over-polishing is performed to complete the planarization of the top surface of the PMD layer, wherein... Figure 2G The results are shown in the figure.

[0025] Then, in a manner well known to those skilled in the art, subsequent front-end processing (FEOL) for forming metal contacts in the PMD layer to reach the integrated circuit device is performed. As an example, Figure 2H The formation of a metal contact 160 is shown, extending through a portion of layer 144 in trench 140 to contact the substrate 112. The formation of a metal contact 162 is also shown, extending through portions of layers 120 and 122 outside trench 140 to contact the source (S), drain (D), and gate (G) of transistor 114. The contact metal can be made of, for example, tungsten, and, where necessary, the contact can further include a suitable lining material.

[0026] Then, in a manner well known to those skilled in the art, conventional back-end processing (BEOL) for forming a metallization layer is performed on top of the PMD layer.

[0027] In some embodiments, further processing may include opening an aperture 200 that extends through a portion of layer 144 in trench 140 to reach substrate 112. This aperture 200 is used to expose integrated circuit device 114' to the external environment. This is useful in applications where integrated circuit device 114' is a microelectromechanical system (MEMS) device operating as a fluid flow device (e.g., for use in printed applications) or as a sensing device (e.g., for use in gas detectors). See also Figure 3 .

[0028] The hole 200 is formed using an etching process controlled by a mask. In a plane parallel to the upper surface of the substrate, the hole 200 will have dimensions defined by a width and length smaller than the width and length of the trench 140. Therefore, in a preferred embodiment, the second dielectric oxide material for layer 144 in the trench 140 will completely surround the hole 200. For example, the etching process can be performed in a single etching step to remove a portion of the material remaining in layer 144 in the trench 140. The etching is tailored to remove material from layer 144. Appropriate cleaning operations can be performed after etching.

[0029] Although the invention has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions are intended to be illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention upon studying the drawings, the disclosure, and the appended claims.

Claims

1. A method for manufacturing an integrated circuit, comprising: Deposit a first dielectric layer made of a first dielectric material; A buffer layer is deposited on the upper surface of the first dielectric layer; A trench is opened, the trench extending through the buffer layer and the first dielectric layer; A second dielectric layer made of a second dielectric material is deposited on the buffer layer in a conformal manner, and the trench is filled; Perform chemical mechanical polishing on the second dielectric layer, wherein the chemical mechanical polishing uses the buffer layer as a polishing stop, such that the upper surface of the second dielectric layer in the trench is generally coplanar with the upper surface of the first dielectric layer; as well as The buffer layer is removed, such that the first dielectric layer and the second dielectric material filling the trench form a pre-metallized dielectric layer having a substantially flat upper surface.

2. The manufacturing method of claim 1, wherein opening the trench includes performing an etching process.

3. The manufacturing method according to claim 2, wherein the etching process comprises: Etching used to penetrate the buffer layer; as well as Etching used to remove a portion of the first dielectric material.

4. The manufacturing method of claim 3, wherein the etching for penetrating the buffer layer uses a mask deposited on the buffer layer, and wherein the etching for removing the portion of the first dielectric material uses the buffer layer as a mask.

5. The manufacturing method of claim 1 further includes performing over-polishing after removing the buffer layer to improve the planarization of the upper surface of the pre-metallized dielectric layer.

6. The manufacturing method according to claim 1 further includes forming a metal contact portion that extends through the second dielectric material in the trench to the upper surface of the underlying semiconductor substrate.

7. The manufacturing method of claim 1 further comprises forming a metal contact portion that extends through the first dielectric material and into an integrated circuit device supported by an underlying semiconductor substrate.

8. The manufacturing method according to claim 7, wherein the integrated circuit device is a transistor.

9. The manufacturing method according to claim 1, wherein the buffer layer is made of a material selected from the group consisting of silicon nitride (SiN), silicon carbonitride (SiCN), and hydrogen-containing silicon carbon oxide (SiCOH).

10. The manufacturing method according to claim 1, wherein the buffer layer is made of a metal nitride material selected from the group consisting of tantalum nitride and titanium nitride.

11. The manufacturing method according to claim 1, wherein the buffer layer is made of a material selected from the group consisting of tantalum and titanium.

12. The manufacturing method according to claim 1, wherein the first dielectric material is a first form of tetraethyl orthosilicate (TEOS), and the second dielectric material is a second form of tetraethyl orthosilicate (TEOS).

13. The manufacturing method according to claim 12, wherein the first form is tetraethyl borophosphosilicate orthosilicate (BPTEOS), and wherein the second form is tetraethyl orthosilicate (TEOS).

14. The manufacturing method according to claim 1, wherein the first dielectric material is a first form of silicon oxide, and the second dielectric material is a second form of silicon oxide, the second form being different from the first form.

15. The manufacturing method according to claim 1, wherein the second dielectric material filling the trench and the first dielectric material of the first dielectric layer form a contact interface of the coupling dielectric of the pre-metallized dielectric layer at the sidewall of the trench.

16. The manufacturing method of claim 15, wherein during the chemical mechanical polishing, the buffer layer inhibits erosion of the first dielectric material at the contact interface.

17. The manufacturing method of claim 1, further comprising forming a hole that extends through the second dielectric material filling the trench to the upper surface of the underlying semiconductor substrate.

18. The manufacturing method of claim 17, wherein forming the hole includes performing an etching process.

19. The manufacturing method of claim 17, wherein the hole exposes a microelectromechanical system (MEMS) device supported by the underlying semiconductor substrate.

20. The manufacturing method according to claim 19, wherein the MEMS device is a sensor.

21. The manufacturing method according to claim 19, wherein the MEMS device is a fluid flow device.

22. The manufacturing method of claim 17, wherein the remaining portion of the second dielectric material after the hole is formed completely surrounds the hole.

23. The manufacturing method of claim 1, wherein depositing the first dielectric layer comprises depositing the first dielectric layer on a silicon glass layer, the silicon glass layer covering electronic circuitry formed on an upper surface of a semiconductor substrate; and wherein opening the trench comprises opening the trench to extend through the buffer layer, the first dielectric layer and the silicon glass layer to reach the upper surface of the semiconductor substrate.

24. The manufacturing method of claim 23, wherein opening the trench includes performing an etching process.

25. The manufacturing method according to claim 24, wherein the etching process comprises: Etching used to penetrate the buffer layer; Etching used to remove a portion of the first dielectric material; as well as Etching used to remove a portion of the silicon glass layer.

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