Substrate with embedded electronic components

Abstract

The present invention provides a substrate embedded with electronic components, the substrate embedded with electronic components comprising: a core structure, comprising a first insulator and a core wiring layer, and the core structure has a cavity and has a barrier layer set as a bottom surface; an electronic component, set in the cavity and attached to the barrier layer; and a build-up structure, comprising a second insulator and a build-up wiring layer, the second insulator covers at least a portion of each of the core structure and the electronic component and fills at least a portion of the cavity, wherein the barrier layer has a first region and a second region, in the first region a portion of a surface of the barrier layer is exposed from the first insulator, in the second region the other portion of a surface of the barrier layer is covered by the first insulator, and the surface roughness of a surface of the barrier layer in the first region is greater than the surface roughness of a surface of the barrier layer in the second region.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0171093 filed on December 19, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a substrate with embedded electronic components. Background Art

[0003] Due to the high densification, miniaturization and slimming of circuits, various characteristics need to be improved. For this reason, technologies for embedding active components and / or passive components in printed circuit boards (PCBs) have been actively studied. Technologies that can ensure the reliability of the corresponding structures are being actively studied. On the other hand, since the substrate in which the components are embedded generally has a chip (die) with a low coefficient of thermal expansion inserted into an organic composite material with a high coefficient of thermal expansion (CTE), etc., various reliability problems may occur due to differences in the coefficients of thermal expansion. For example, interface delamination may occur between heterogeneous materials due to warping of the substrate, and the above-mentioned interface delamination may occur even after thermal cycling or humidity testing. Summary of the invention

[0004] An aspect of the present disclosure may provide an electronic component-embedded substrate having improved bonding reliability between heterogeneous materials.

[0005] Another aspect of the present disclosure may provide a substrate embedded with electronic components that may be modularized and miniaturized in the form of a system-in-package (SiP).

[0006] One of several solutions proposed in the present disclosure may be to additionally form fine roughness on the exposed surface of the barrier layer provided for forming the cavity.

[0007] According to one aspect of the present disclosure, a substrate embedded with an electronic component may include: a core structure including a first insulator and a plurality of core wiring layers, the plurality of core wiring layers are respectively arranged on the first insulator or in the first insulator, and the core structure has a cavity passing through at least a portion of the first insulator in the thickness direction of the first insulator, and the core structure has a barrier layer arranged as the bottom surface of the cavity; an electronic component is arranged in the cavity and attached to the barrier layer; and a build-up structure including a second insulator and one or more build-up wiring layers, the second insulator covers at least a portion of each of the core structure and the electronic component and is arranged in at least a portion of the cavity, and the one or more build-up wiring layers are all arranged on the second insulator or in the second insulator. The barrier layer may have a first region and a second region, in which a portion of one surface of the barrier layer is exposed from the first insulator through the cavity, in which the other portion of the one surface of the barrier layer is covered by the first insulator, and the surface roughness of the one surface of the barrier layer in the first region may be greater than the surface roughness of the one surface of the barrier layer in the second region.

[0008] According to another aspect of the present disclosure, a substrate embedded with an electronic component may include: a core structure including a first insulator and a plurality of core wiring layers, the plurality of core wiring layers are respectively arranged on the first insulator or in the first insulator, and the core structure has a cavity passing through at least a portion of the first insulator in the thickness direction of the first insulator, and the core structure has a barrier layer arranged as the bottom surface of the cavity; an electronic component, arranged in the cavity and attached to the barrier layer; and a buildup structure including a second insulator and one or more buildup wiring layers, the second insulator covers at least a portion of each of the core structure and the electronic component and is arranged in at least a portion of the cavity, and the one or more buildup wiring layers are all arranged on the second insulator or in the second insulator. A portion of one surface of the barrier layer in an area exposed from the first insulator through the cavity may have a first concave-convex portion and a second concave-convex portion, the second concave-convex portion being formed on the first concave-convex portion and having a concave-convex height difference smaller than the concave-convex height difference of the first concave-convex portion.

[0009] According to another aspect of the present disclosure, a substrate embedded with an electronic component may include: a core structure including a first insulator and a plurality of core wiring layers, the plurality of core wiring layers being respectively arranged on the first insulator or in the first insulator, and the core structure having a cavity passing through at least a portion of the first insulator in the thickness direction of the first insulator, and the core structure having a barrier layer arranged as the bottom surface of the cavity; an electronic component arranged in the cavity and attached to the barrier layer; and a buildup structure including a second insulator and one or more buildup wiring layers, the second insulator covering at least a portion of each of the core structure and the electronic component and arranged in at least a portion of the cavity, the one or more buildup wiring layers being arranged on the second insulator or in the second insulator. A portion of one surface of the barrier layer in an area exposed from the first insulator through the cavity may have a centerline average roughness Ra of 0.6 μm to 1.2 μm and / or a ten-point average roughness Rz of 7 μm to 13 μm.

[0010] Other solutions among the several solutions proposed in the present disclosure may consist in introducing a modular structure by providing surface mount components on a substrate embedded with electronic components.

[0011] For example, one or more surface mount components may be mounted on the electronic component-embedded substrate according to the above-described examples through electrically connected metal bumps, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0014] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0015] Figure 3 is a schematic cross-sectional view showing an example of a substrate in which electronic components are embedded;

[0016] Figure 4 is along Figure 3 A schematic cross-sectional plan view of a substrate embedded with electronic components taken along line II';

[0017] Figure 5 yes Figure 3 A schematic enlarged cross-sectional view of an R region of a substrate with electronic components embedded therein;

[0018] Figure 6 Observed through electron microscopy Figure 5 A schematic surface photograph of region A;

[0019] Figure 7 Observed through electron microscopy Figure 5 A schematic surface photograph of region B of FIG. 1 ; and

[0020] Figures 8 to 14 It shows the manufacturing Figure 3 Schematic process diagram of an example of a substrate with embedded electronic components. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0023] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically and / or electrically connected thereto. These components may be connected to other components to be described below via various signal lines 1090.

[0024] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0025] The network-related components 1030 may include components operating based on protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution Data Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating based on various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 .

[0026] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, and may also include passive components in the form of chip components for various other purposes, etc. In addition, the other components 1040 may be combined with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0027] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the mainboard 1010. Examples of other electronic components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, and the like. However, the other electronic components are not limited thereto, and may further include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disc (CD), a digital versatile disc (DVD), and the like. In addition, depending on the type of the electronic device 1000, other electronic components for various purposes may be included.

[0028] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0029] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0030] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the electronic components 1120 may be the above-mentioned chip-related components, for example, a semiconductor package 1121, but are not limited thereto. The semiconductor package 1121 may have a form in which an electronic component is embedded in a multi-layer printed circuit board and / or a form in which an electronic component is surface-mounted on a multi-layer printed circuit board, but are not limited thereto. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0031] Figure 3 is a schematic cross-sectional view showing an example of a substrate in which electronic components are embedded.

[0032] Figure 4 is along Figure 3 Schematic cross-sectional plan view of a substrate embedded with electronic components taken along line II'.

[0033] Figure 5 yes Figure 3 Schematic enlarged cross-sectional view of the R region of a substrate in which electronic components are embedded.

[0034] Figure 6 Observed through electron microscopy Figure 5 Schematic surface photograph of area A.

[0035] Figure 7 Observed through electron microscopy Figure 5 Schematic surface photograph of region B.

[0036] Reference Figures 3 to 7, according to the example, the substrate 100 embedded with electronic components may include a core structure 110, an electronic component 120 and a build-up structure 160, and may further include a first passivation layer 170 and a second passivation layer 180. The core structure 110 may include first insulators 111a, 111b and 111c and a plurality of core wiring layers 112a, 112b, 112c and 112d, and the plurality of core wiring layers 112a, 112b, 112c and 112d are respectively disposed on the first insulators 111a, 111b and 111c or in the first insulators 111a, 111b and 111c. The core structure 110 may have a cavity 110H, and the cavity 110H passes through at least a portion (e.g., 111a and 111c) of the first insulators 111a, 111b and 111c in a thickness direction. The barrier layer 115 may be provided as the bottom surface of the cavity 110H. The electronic component 120 may be disposed in the cavity 110H and attached to the barrier layer 115. The barrier layer 115 may have a central region in which a portion of the upper surface of the barrier layer 115 is exposed from the first insulators 111a, 111b, and 111c through the cavity 110H, and an edge region in which the other portion of the upper surface of the barrier layer 115 is covered by the first insulators 111a, 111b, and 111c. In this case, the surface roughness of the upper surface of the barrier layer 115 in the central region may be greater than the surface roughness of the upper surface of the barrier layer 115 in the edge region. Here, the surface roughness may be a centerline average roughness Ra and / or a ten-point average roughness Rz.

[0037] In addition, as described above, a technology for embedding active components and / or passive components in a substrate is recently required. In the structure of such a substrate embedded with electronic components, warpage control may be relatively easy in a symmetrical structure compared with an asymmetric structure. However, an asymmetric structure is required to fully ensure the thickness of the electronic component while eliminating unnecessary layers. In addition, in order to embed and bury the electronic component in the substrate of the asymmetric structure, a cavity in the form of a blind cavity needs to be formed. In order to form such a cavity, laser processing or sandblasting may be considered. In this case, a barrier layer formed by a metal material may be used to adjust the processing depth. After forming the cavity, the electronic component may be attached to the barrier layer using an adhesive or the like. However, after laser processing or sandblasting, the exposed surface of the barrier layer may be difficult to have fine roughness due to processing. Therefore, the adhesion between the heterogeneous material of the adhesive containing the resin and the barrier layer containing the metal may be low. As a result, interface delamination may easily occur between the barrier layer and the adhesive. For example, interface delamination may occur due to the warping of the substrate, and interface delamination may occur even after thermal cycling or moisture absorption testing. That is, reliability problems may occur.

[0038] On the other hand, in the electronic component-embedded substrate 100 according to the example, fine roughness is additionally formed in the central region of the upper surface of the barrier layer 115 (which provides the bottom surface for forming the cavity 110H) exposed by the cavity 110H. Therefore, the portion of the upper surface of the barrier layer 115 in the exposed central region may have a surface roughness different from the surface roughness of the portion of the upper surface of the barrier layer 115 in the buried edge region. For example, the surface roughness of the upper surface of the barrier layer 115 in the central region (e.g., centerline average roughness Ra) may be greater than the surface roughness of the upper surface of the barrier layer 115 in the edge region (e.g., centerline average roughness Ra). For another example, the surface roughness of the upper surface of the barrier layer 115 in the central region (e.g., ten-point average roughness Rz) may be greater than the surface roughness of the upper surface of the barrier layer 115 in the edge region (e.g., ten-point average roughness Rz). By having such a relative size of the surface roughness of the upper surface of the barrier layer 115 in the exposed area, the mechanical bonding force can be improved by increasing the surface area or anchoring effect. As a result, the adhesion between the adhesive 125 and the heterogeneous material of the barrier layer 115 can be improved. Therefore, reliability issues such as interface delamination can be solved.

[0039] In addition, the portion of the upper surface of the barrier layer 115 in the central region exposed from the first insulator 111a, 111b and 111c through the cavity 110H may have a first concavoconvex portion and a second concavoconvex portion, the first concavoconvex portion having a first height difference h1, and the second concavoconvex portion formed on the first concavoconvex portion and having a second height difference h2. Although briefly shown in the drawings, the first height difference h1 and the second height difference h2 refer to the average value of the height difference of each concavoconvex. For example, the central region of the upper surface of the barrier layer 115 exposed by laser processing or sandblasting may basically have a first concavoconvex portion in an embossed form. In addition, a second concavoconvex portion in a fine roughness form may be further formed on the first concavoconvex portion by surface polishing, etc. In this case, the surface area can be increased by the first concavoconvex portion in an embossed form to improve the adhesion to the adhesive 125, and the second concavoconvex portion in a fine roughness form can be provided to further improve the adhesion to the adhesive 125, etc. Furthermore, since the second concavo-convex portion having a fine roughness form is formed on the first concavo-convex portion in a relief form, a relative difference in surface roughness between an exposed central region of the upper surface of the barrier layer 115 and a buried edge region of the upper surface of the barrier layer 115 can be more effectively achieved. Therefore, reliability issues such as interface delamination can be more effectively resolved.

[0040] In addition, the portion of the edge area of ​​the upper surface of the barrier layer 115 embedded in the first insulator 111a, 111b and 111c may have a third concavoconvex portion, and the third concavoconvex portion has a third height difference h3. Although briefly shown in the drawings, the third height difference h3 refers to the average value of the height difference of the concavoconvex portion. In this case, the first height difference h1 of the above-mentioned first concavoconvex portion may be greater than the third height difference h3 of the third concavoconvex portion, and the second height difference h2 of the above-mentioned second concavoconvex portion may be greater than the third height difference h3 of the third concavoconvex portion. By achieving such relative sizes, the adhesion between the barrier layer 115 and the adhesive 125 can be more effectively improved, and reliability issues such as interface delamination can be more effectively solved.

[0041] In addition, the thickness of the barrier layer 115 in the central region having the exposed upper surface may be thinner than the thickness of the barrier layer 115 in the edge region having the buried upper surface. For example, the central region of the barrier layer 115 may be partially removed in the process for forming the cavity 110H and the process for forming the fine roughness, and thus may have such a thickness relationship.

[0042] Hereinafter, respective components included in the electronic component embedded substrate 100 according to an example will be described in more detail with reference to the accompanying drawings.

[0043] The core structure 110 may include: a first core insulation layer 111a; a first core wiring layer 112a and a barrier layer 115, both of which are arranged on the lower surface of the first core insulation layer 111a; a second core wiring layer 112b, arranged on the upper surface of the first core insulation layer 111a; the second core insulation layer 111b, arranged on the lower surface of the first core insulation layer 111a and covering at least a portion of each of the first core wiring layer 112a and the barrier layer 115; a third core wiring layer 112c, arranged on the lower surface of the second core insulation layer 111b; the third core insulation layer 111c, arranged on the upper surface of the first core insulation layer 111a and covering at least a portion of the second core wiring layer 112b; and a fourth core wiring layer 112d, arranged on the upper surface of the third core insulation layer 111c. The core structure 110 may also include: a first core via layer 113a, which passes through the first core insulation layer 111a and connects the first core wiring layer 112a and the second core wiring layer 112b to each other; a second core via layer 113b, which passes through the second core insulation layer 111b and connects the first core wiring layer 112a and the third core wiring layer 112c to each other; and a third core via layer 113c, which passes through the third core insulation layer 111c and connects the second core wiring layer 112b and the fourth core wiring layer 112d to each other.

[0044] The core structure 110 can further improve the rigidity of the substrate 100 embedded with the electronic component according to the specific material, and is used to ensure the uniformity of the thickness of the first buildup insulating layer 130. In addition, the core structure 110 may include a first core wiring layer 112a, a second core wiring layer 112b, a third core wiring layer 112c, and a fourth core wiring layer 112d, as well as a first core via layer 113a, a second core via layer 113b, and a third core via layer 113c, and various circuits can be designed, and upper and lower electrical connection paths can also be provided. In addition, the core structure 110 may include a third core wiring layer 112c disposed below the back side of the electronic component 120, so that a back wiring layer can be easily provided. The core structure 110 can be constructed using more layers than those shown in the drawings. In addition, the number of the core wiring layers 112a, 112b, 112c, and 112d of the core structure 110 may be greater than the number of the buildup wiring layers 132, 142, and 152 of the buildup structure 160.

[0045] The core structure 110 may have a cavity 110H. The barrier layer 115 may be provided as the bottom surface of the cavity 110H. The cavity 110H may have the form of a blind cavity that passes through the first core insulation layer 111a and the third core insulation layer 111c but not through the second core insulation layer 111b. The cavity 110H may have a tapered profile in which the width of the cross section narrows from the upper side to the lower side, but is not limited thereto.

[0046] An insulating material may be used as the material of the first core insulating layer 111a. In this case, as the insulating material, an insulating material of a copper clad laminate (CCL) may be used. Insulating materials may be used as the materials of the second core insulating layer 111b and the third core insulating layer 111c, respectively. In this case, as the insulating material, an insulating material of resin coated copper (RCC) may be used. However, the materials of the first core insulating layer, the second core insulating layer, and the third core insulating layer are not limited thereto, and thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or resins (e.g., prepregs, etc.) impregnated into core materials such as glass fibers together with inorganic fillers may be used as the materials of each of the first core insulating layer 111a, the second core insulating layer 111b, and the third core insulating layer 111c. When a material having high rigidity (such as a prepreg containing glass fibers, etc.) is used, it may be more effective in warpage control. The second core insulating layer 111b and the third core insulating layer 111c may include the same kind of material. The first core insulation layer 111 a may have a thickness greater than that of the second core insulation layer 111 b and the third core insulation layer 111 c .

[0047] The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may perform various functions according to the design. For example, the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, and the like, such as a data signal pattern, and the like. Each of these patterns may have a line form, a surface form, or a pad form. The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d can be formed by a plating process such as an additive process (AP), a semi-additive process (SAP), a modified semi-additive process (MSAP) or a sealing hole (TT), and therefore can include a seed layer (no electroplating layer) and an electroplating layer formed based on the seed layer. The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d may further include a copper foil layer as the lowermost layer. In addition, the first core wiring layer 112a and the second core wiring layer 112b can be formed based on CCL, and therefore can have a copper foil layer as the lowermost layer.

[0048] The first core via layer 113a, the second core via layer 113b and the third core via layer 113c may respectively pass through the first core insulation layer 111a, the second core insulation layer 111b and the third core insulation layer 111c, and vertically connect the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c and the fourth core wiring layer 112d. The first core via layer 113a, the second core via layer 113b and the third core via layer 113c may also include metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. According to the design, the first core via layer 113a, the second core via layer 113b and the third core via layer 113c may respectively include signal connection vias, ground connection vias and power connection vias. The connection vias of each of the first core via layer 113a, the second core via layer 113b, and the third core via layer 113c can be completely filled with a metal material, or can also be formed along the wall surface of the via hole using a metal material. The first core via layer 113a may have an hourglass shape or a cylindrical shape. The second core via layer 113b and the third core via layer 113c may have a profile that tapers in opposite directions (e.g., a tapered profile), and the first core via layer 113a is between the two. The first core via layer 113a, the second core via layer 113b, and the third core via layer 113c may also be formed by a plating process (e.g., AP, SAP, MSAP, TT, etc.), and therefore may include a seed layer (no electroplating layer) and an electroplating layer formed based on the seed layer. In addition, the first core via layer 113a may be formed based on CCL, and therefore may have a copper foil layer as the bottom layer. The connection vias of the first core via layer 113a may be seamlessly integrated with the pad pattern of the first core wiring layer 112a and the pad pattern of the second core wiring layer 112b. The connection vias of the second core via layer 113b and the third core via layer 113c may be seamlessly integrated with the pad pattern of the third core wiring layer 112c and the pad pattern of the fourth core wiring layer 112d, respectively.

[0049] The barrier layer 115 may be disposed on the lower surface of the first core insulating layer 111a and covered by the second core insulating layer 111b. The barrier layer 115 may be formed by a plating process (e.g., a process such as AP, SAP, MSAP, or TT) the same as the plating process of the first core wiring layer 112a, and thus may include a seed layer (electroless plating layer) and an electroplating layer formed based on the seed layer. The barrier layer 115 may further include a copper foil layer as the lowermost layer. The barrier layer 115 may be formed simultaneously with the first core wiring layer 112a by the same plating process, and thus may be disposed at the same height as the first core wiring layer 112a. The barrier layer 115 may include the same metal material as the first core wiring layer 112a, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The barrier layer 115 may have a planar shape. For example, in a plane, the barrier layer 115 may have a rectangular shape or a square shape in which a central region is exposed and an edge region is buried, but is not limited thereto.

[0050] The barrier layer 115 may have a central region exposed from the first core insulating layer 111a through the cavity 110H, and an edge region surrounding the central region and covered by the first core insulating layer 111a. The upper surface of the barrier layer 115 may have a relative surface roughness as described above in the central region and the edge region. On the other hand, the surface roughness can be compared by measuring the fine roughness of each surface. For example, the upper surface of the barrier layer 115 may have a center line average roughness Ra of 0.6μm to 1.2μm in the central region, and may have a center line average roughness Ra of 0.1μm to 0.4μm in the edge region. In addition, the upper surface of the barrier layer 115 may have a ten-point average roughness Rz of 7μm to 13μm in the central region, and may have a ten-point average roughness Rz of 0.9μm to 3μm in the edge region. The upper surface of the barrier layer 115 may have a first concavoconvex portion in the form of relief as described above and a second concavoconvex portion in the form of fine roughness formed on the first concavoconvex portion in the central region, and may have a third concavoconvex portion in the form of fine roughness as described above in the edge region. The first height difference h1 of the first concavoconvex portion, the second height difference h2 of the second concavoconvex portion, and the third height difference h3 of the third concavoconvex portion may be relatively smaller in this order. If necessary, the lower surface of the barrier layer 115 may also have fine roughness.

[0051] The electronic component 120 may be disposed in the cavity 110H. The back of the electronic component 120 may be attached to the barrier layer 115 by a known adhesive 125, which includes a resin such as an adhesive component of an epoxy resin, for example, a chip attachment film (DAF). The electronic component 120 may be an integrated circuit (IC) provided by integrating hundreds to millions or more components in a single chip. For example, the electronic component 120 may be a processor chip (more specifically, an application processor (AP)), such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc., but is not limited thereto. For example, the electronic component 120 may also be a memory (such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.), or a logic chip (such as an analog-to-digital converter, an application-specific IC (ASIC), etc.). In addition, the electronic component 120 may be a passive component in the form of a chip.

[0052] The electronic component 120 may be formed based on an active wafer. The base material of the main body of the electronic component 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed on the main body. The connection pad 120P may be disposed on the effective surface of the main body (i.e., the surface opposite to the back of the electronic component 120). The connection pad 120P may electrically connect the electronic component 120 to other components. The material of the connection pad 120P may be a conductive material such as copper (Cu), aluminum (Al), etc., without particular limitation. A passivation film covering at least a portion of the connection pad 120P and exposing at least a portion of the connection pad 120P may be disposed on the effective surface of the main body. The passivation film may be an oxide film or a nitride film, or a double layer of an oxide film and a nitride film. An insulating layer, etc. may be further disposed at a desired position. The electronic component 120 may be a bare chip, but is not limited thereto, and may be a packaged chip with a redistribution area.

[0053] The stacking structure 160 may include a second insulator 130, 140 and 150 and one or more stacking wiring layers 132, 142 and 152, wherein the second insulator 130, 140 and 150 covers at least a portion of each of the core structure 110 and the electronic component 120 and is arranged in at least a portion of the cavity 110H, and the one or more stacking wiring layers 132, 142 and 152 are all arranged on the second insulator 130, 140 and 150 or in the second insulator 130, 140 and 150. Specifically, the stacking structure 160 may include: a first stacking insulating layer 130, covering at least a portion of each of the core structure 110 and the electronic component 120 and filling at least a portion of the cavity 110H; a first stacking wiring layer 132, disposed on the first stacking insulating layer 130; a second stacking insulating layer 140, disposed on the first stacking insulating layer 130 and covering at least a portion of the first stacking wiring layer 132; a second stacking wiring layer 142, disposed on the second stacking insulating layer 140; a third stacking insulating layer 150, disposed on the second stacking insulating layer 140 and covering at least a portion of the second stacking wiring layer 142; and a third stacking wiring layer 152, disposed on the third stacking insulating layer 150. The stacking structure 160 may further include: a first stacking via layer 133, which passes through the first stacking insulating layer 130 and connects the first stacking wiring layer 132 to the connection pad 120P and the fourth core wiring layer 112d; a second stacking via layer 143, which passes through the second stacking insulating layer 140 and connects the first stacking wiring layer 132 and the second stacking wiring layer 142 to each other; and a third stacking via layer 153, which passes through the third stacking insulating layer 150 and connects the second stacking wiring layer 142 and the third stacking wiring layer 152 to each other.

[0054] The stacking structure 160 may allow for more wiring designs in the upward direction. The stacking structure 160 may include a first stacking wiring layer 132, a second stacking wiring layer 142, and a third stacking wiring layer 152, as well as a first stacking via layer 133, a second stacking via layer 143, and a third stacking via layer 153, and various circuits may be designed, and upper and lower electrical connection paths may also be provided. The stacking structure 160 may be constructed using more layers than those shown in the drawings. However, the stacking structure 160 is not limited thereto, but may be constructed using fewer layers than those shown in the drawings.

[0055] The first stacked insulating layer 130, the second stacked insulating layer 140, and the third stacked insulating layer 150 may be sequentially laminated on the core structure 110 and the electronic component 120. The first stacked insulating layer 130 may cover at least a portion of each of the core structure 110 and the electronic component 120. In addition, the first stacked insulating layer 130 may fill at least a portion of the cavity 110H. The material of each of the first stacked insulating layer 130, the second stacked insulating layer 140, and the third stacked insulating layer 150 is not particularly limited. For example, an insulating material may be used as the material of the first stacked insulating layer 130, the second stacked insulating layer 140, and the third stacked insulating layer 150. In this case, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a resin in which a thermosetting resin and a thermoplastic resin are mixed with an inorganic filler (for example, ABF (Ajinomoto Build-up Film), etc.) may be used as the insulating material. The first stacked insulating layer 130, the second stacked insulating layer 140, and the third stacked insulating layer 150 may include the same kind of material. Since the first, second, and third buildup insulating layers 130, 140, and 150 are integrated after curing, it may be difficult to distinguish their own boundaries.

[0056] The first buildup wiring layer 132, the second buildup wiring layer 142, and the third buildup wiring layer 152 may each include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first buildup wiring layer 132, the second buildup wiring layer 142, and the third buildup wiring layer 152 may also perform various functions according to the design. For example, the first buildup wiring layer 132, the second buildup wiring layer 142, and the third buildup wiring layer 152 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, and the like, such as a data signal pattern. Each of these patterns may be in a line form, a surface form, or a pad form. The first buildup wiring layer 132, the second buildup wiring layer 142, and the third buildup wiring layer 152 may also be formed by a plating process (e.g., AP, SAP, MSAP, TT, etc.), and may include a seed layer (electroless plating layer) and an electroplating layer formed based on the seed layer. The first buildup wiring layer 132, the second buildup wiring layer 142, and the third buildup wiring layer 152 may further include a copper foil layer as the lowermost layer.

[0057] The first stacked via layer 133, the second stacked via layer 143, and the third stacked via layer 153 pass through the first stacked insulating layer 130, the second stacked insulating layer 140, and the third stacked insulating layer 150, respectively. The first stacked via layer 133 can connect the first stacked wiring layer 132 to the connection pad 120P of the electronic component 120. In addition, the first stacked via layer 133 can connect the first stacked wiring layer 132 to the fourth core wiring layer 112d. The second stacked via layer 143 and the third stacked via layer 153 can vertically connect the first stacked wiring layer 132, the second stacked wiring layer 142, and the third stacked wiring layer 152 to each other. The first stacked via layer 133, the second stacked via layer 143, and the third stacked via layer 153 may also include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. According to the design, the first stacked via layer 133, the second stacked via layer 143 and the third stacked via layer 153 may also include signal connection vias, ground connection vias and power connection vias. The first stacked via layer 133, the second stacked via layer 143 and the third stacked via layer 153 may be completely filled with a metal material, or may be formed along the wall surface of the via hole using a metal material. The first stacked via layer 133, the second stacked via layer 143 and the third stacked via layer 153 may have a profile (e.g., a tapered profile) that tapers along the same direction. For example, in cross section, the upper width of the first stacked via layer 133, the second stacked via layer 143 and the third stacked via layer 153 may be greater than the lower width. For example, each of the first stacked via layer 133, the second stacked via layer 143 and the third stacked via layer 153 may have a tapered profile in which the width of the cross section narrows in the direction from the stacked structure 160 toward the core structure 110. The first stacked via layer 133, the second stacked via layer 143, and the third stacked via layer 153 may also be formed by a plating process (e.g., AP, SAP, MSAP, TT, etc.), and may include a seed layer (electroplating-free layer) and an electroplating layer formed based on the seed layer. The connection vias of the first stacked via layer 133, the second stacked via layer 143, and the third stacked via layer 153 may be integrated with the pad pattern of the first stacked wiring layer 132, the pad pattern of the second stacked wiring layer 142, and the pad pattern of the third stacked wiring layer 152 without borders, respectively.

[0058] The first passivation layer 170 can protect the third core wiring layer 112c from external physical damage or chemical damage. The first passivation layer 170 may be disposed on the lower surface of the second core insulating layer 111b to cover at least a portion of the third core wiring layer 112c, and have a plurality of first openings that expose at least a portion of the third core wiring layer 112c, respectively. The material of the first passivation layer 170 is not particularly limited. For example, an insulating material can be used as the material of the first passivation layer 170. In this case, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a resin in which a thermosetting resin and a thermoplastic resin are mixed with an inorganic filler (e.g., ABF, etc.) can be used as an insulating material. However, the material of the first passivation layer 170 is not limited, and a photosensitive insulating material such as a solder resist (SR) can be used.

[0059] The second passivation layer 180 can protect the third buildup wiring layer 152 from external physical damage or chemical damage. The second passivation layer 180 can be disposed on the upper surface of the third buildup insulating layer 150 to cover at least a portion of the third buildup wiring layer 152, and have a plurality of second openings that expose at least a portion of the third buildup wiring layer 152, respectively. The material of the second passivation layer 180 is not particularly limited. For example, an insulating material can be used as the material of the second passivation layer 180. In this case, the above-mentioned ABF, SR, etc. can be used as the insulating material. If necessary, the second passivation layer 180 may include a material of a different type from the first passivation layer 170. For example, the second passivation layer 180 may have a smaller coefficient of thermal expansion (CTE). Thus, the deviation of the coefficient of thermal expansion of the upper and lower portions of the substrate can be further improved.

[0060] The first electrically connected metal bumps 190 may be respectively disposed on the first openings of the first passivation layer 170. The first electrically connected metal bumps 190 may be connected to the exposed third core wiring layer 112c. The first electrically connected metal bumps 190 may physically connect and / or electrically connect the substrate 100 embedded with electronic components to the outside. For example, the substrate 100 embedded with electronic components may be mounted on a main board of an electronic device or another ball grid array (BGA) substrate through the first electrically connected metal bumps 190. Each of the first electrically connected metal bumps 190 may be formed using tin (Sn) or an alloy containing tin (Sn) (e.g., solder, etc.). However, this is merely an example, and the material of each of the first electrically connected metal bumps 190 is not particularly limited thereto. Each of the first electrically connected metal bumps 190 may be a pad, a solder ball, a pin, etc. The first electrically connected metal bumps 190 may be formed as a multilayer or a single layer. When the first electrically connected metal bumps 190 are formed as a multilayer, the first electrically connected metal bumps 190 may include a copper (Cu) column and solder. When the first electrically connected metal bump 190 is formed as a single layer, the first electrically connected metal bump 190 may include tin-silver solder or copper (Cu). However, this is merely an example, and the first electrically connected metal bump 190 is not limited thereto. The number, spacing, arrangement form, etc. of the first electrically connected metal bump 190 are not particularly limited, and may be modified according to design details. If necessary, an under-bump metal (UBM) may be provided on each of the plurality of first openings, and the first electrically connected metal bump 190 may be connected to the under-bump metal.

[0061] The surface mount component 210 may be further disposed on the second passivation layer 180. The surface mount component 210 may be disposed on the second passivation layer 180 in a surface mounted form through the second electrical connection metal bump 220. The surface mount component 210 may be an active component and / or a passive component. Examples of active components may include ICs described above with respect to the electronic component 120, etc. Examples of passive components may include chip capacitors such as multilayer ceramic capacitors (MLCCs), chip inductors such as power inductors (PIs), etc. The second electrical connection metal bump 220 may include tin (Sn) or an alloy containing tin (Sn), for example, solder, etc. The second electrical connection metal bumps 220 may be respectively disposed on a plurality of second openings of the second passivation layer 180, and may all be connected to the exposed third buildup wiring layer 152. If necessary, a molding material covering the surface mount component 210 may be further disposed on the second passivation layer 180. The molding material may be a known epoxy molding compound (EMC), but is not limited thereto. When the surface mount component 210 is further provided, the electronic component embedded substrate 100 may be implemented as a SiP.

[0062] In addition, the electronic component embedded substrate 100 according to the example may have a plurality of cavities 110H. In this case, the above-mentioned barrier layer 115 may be applied to each cavity 110H. The same or different electronic components may be disposed in each cavity 110H.

[0063] Figures 8 to 14 It shows the manufacturing Figure 3 Schematic process diagram of an example of a substrate with embedded electronic components.

[0064] Reference Figure 8 , first, a CCL or the like used as the first core insulating layer 111a is prepared. The CCL may be formed by laminating copper foil m1 on the upper and lower surfaces of the insulating material. Next, a via hole 113ah may be formed in the CCL using a mechanical drill or the like. Next, a first core wiring layer 112a and a second core wiring layer 112b and a first core via layer 113a may be formed by a plating process. In addition, a barrier layer 115 may be formed. In one example, the barrier layer 115 and the first core wiring layer 112a may be formed by the same process using the same material, but the present disclosure is not limited thereto.

[0065] Reference Fig. 9 , Next, the second core insulation layer 111b and the third core insulation layer 111c may be formed by laminating a prepreg on the upper and lower sides of the first core insulation layer 111a using RCC or the like. RCC may be formed by laminating a copper foil m2 on an insulating material. In addition, via holes 113bh and 113ch may be formed by laser processing or the like. Next, the third core wiring layer 112c and the fourth core wiring layer 112d and the second core via layer 113b and the third core via layer 113c may be formed by a plating process. Next, a separation carrier film 310 may be attached to the lower side of the core structure 110 manufactured by a series of processes, and a first passivation layer 170 such as ABF may be interposed between the separation carrier film 310 and the core structure 110.

[0066] Reference Fig.10 , next, the patterned dry film 320 may be attached to the upper side of the core structure 110, and the cavity 110H having a depth to the barrier layer 115 may be formed by removing the core insulating layer by metal etching and sandblasting. In this case, the first concavoconvex portion in the above-mentioned relief form may be formed on the surface of the barrier layer 115. Next, fine roughness may be additionally formed on the surface of the barrier layer 115. A mechanical polishing or chemical polishing method may be used as a method for forming fine roughness. Examples of mechanical polishing may include buff polishing, jet polishing, etc., and examples of chemical polishing may include soft etching, but are not limited thereto. Thus, a second concavoconvex portion in the form of fine roughness may be formed on the first concavoconvex portion in the relief form. Subsequently, the dry film 320 may be removed.

[0067] Reference Fig.11 Next, the electronic component 120 may be attached to the barrier layer 115 in the cavity 110H in a face-up manner using an adhesive 125. Next, a first build-up insulating layer 130 may be formed using an ABF laminate or the like.

[0068] Reference Fig.12 Next, the via hole 133h may be formed by laser processing, etc. Next, the first buildup wiring layer 132 and the first buildup via layer 133 may be formed by a plating process.

[0069] Reference Fig.13 Next, a second stacking insulating layer 140, a second stacking wiring layer 142, and a second stacking via layer 143 may be formed in a similar manner. Next, a third stacking insulating layer 150, a third stacking wiring layer 152, and a third stacking via layer 153 may be formed in a similar manner. The stacking structure 160 may be formed by a series of processes.

[0070] Reference Fig.14 , Next, a second passivation layer 180 may be formed on the upper side of the buildup structure 160 by laminating ABF or coating and curing SR. Next, the separation carrier film 310 may be separated. If necessary, a first opening and a second opening may be formed in the first passivation layer 170 and the second passivation layer 180, respectively. In addition, if necessary, a first electrical connection metal bump 190 and a second electrical connection metal bump 220 may be formed to mount the surface mount component 210.

[0071] The electronic component-embedded substrate 100 according to the above example may be manufactured through a series of processes, and other details are the same as above, so a detailed description thereof will be omitted.

[0072] Here, for convenience, with respect to the drawings, the side, side surface, etc. are used to indicate the left-right direction or the surface in that direction; for convenience, with respect to the drawings, the upper side, upper part, upper surface, etc. are used to indicate the upward direction or the surface in that direction; and for convenience, with respect to the drawings, the lower side, lower part, lower surface, etc. are used to indicate the downward direction or the surface in that direction. In addition, the phrase "located on the side, upper side, upper part, lower side or lower part" has been used as a concept including the case where the target component is positioned in the corresponding direction but does not directly contact the reference component and the case where the target component directly contacts the reference component in the corresponding direction. However, these directions are defined for the convenience of interpretation, and the claims are not specifically limited to the directions defined as above, and the concepts of the upper part and the lower part may be changed at any time.

[0073] The meaning of "connection" of a component in the present disclosure to another component includes an indirect connection through an adhesive layer and a direct connection between two components. In addition, "electrical connection" means a concept including physical connection and physical disconnection. It is understood that when an element is referred to using "first" and "second", the element is not limited thereto. They can only be used for the purpose of distinguishing an element from other elements, and the order or importance of the elements may not be limited. In some cases, without departing from the scope of the present disclosure, the first component may be named as the second component, and similarly, the second component may also be named as the first component.

[0074] The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by combining with each other in whole or in part. For example, unless a contrary or contradictory description is provided herein, even if an element described in a particular exemplary embodiment is not described in another exemplary embodiment, the element can still be understood as a description related to another exemplary embodiment.

[0075] The terms used herein are used only to describe exemplary embodiments rather than to limit the present disclosure. In this case, unless the context otherwise explains, the singular form includes the plural form.

[0076] As described above, according to exemplary embodiments in the present disclosure, an electronic component-embedded substrate having improved bonding reliability between heterogeneous materials may be provided.

[0077] Furthermore, a substrate embedded with electronic components that can be modularized and miniaturized in the form of a SiP can be provided.

[0078] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present invention as defined by the appended claims.

Claims

1. A substrate embedded with electronic components, comprising: A core structure comprising a first insulator and a plurality of core wiring layers, the plurality of core wiring layers being respectively disposed on or in the first insulator, and the core structure having a cavity penetrating at least a portion of the first insulator in a thickness direction of the first insulator, and the core structure having a barrier layer disposed as a bottom surface of the cavity; an electronic component disposed in the cavity and attached to the barrier layer; as well as a build-up structure including a second insulator covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, and one or more build-up wiring layers each disposed on or in the second insulator, The barrier layer has a first region and a second region, in which a portion of one surface of the barrier layer is exposed from the first insulator through the cavity, and in the second region, the other portion of the one surface of the barrier layer is covered by the first insulator, The surface roughness of the one surface of the barrier layer in the first region is greater than the surface roughness of the one surface of the barrier layer in the second region, The portion of the one surface of the barrier layer in the first region has a first concavo-convex portion and a second concavo-convex portion, the second concavo-convex portion being provided on the first concavo-convex portion and having a concavo-convex height difference smaller than that of the first concavo-convex portion, and The height difference of the concave and convex portions refers to the average value of the height differences of the concave and convex portions.

2. The electronic component embedded substrate according to claim 1, wherein: A centerline average roughness of the one surface of the barrier layer in the first region is greater than a centerline average roughness of the one surface of the barrier layer in the second region.

3. The electronic component embedded substrate according to claim 2, wherein: The one surface of the barrier layer has a centerline average roughness of 0.6 μm to 1.2 μm in the first region, and has a centerline average roughness of 0.1 μm to 0.4 μm in the second region.

4. The electronic component embedded substrate according to claim 1, wherein: A ten-point average roughness of the one surface of the barrier layer in the first region is greater than a ten-point average roughness of the one surface of the barrier layer in the second region.

5. The electronic component embedded substrate according to claim 4, wherein: The one surface of the barrier layer has a ten-point average roughness of 7 μm to 13 μm in the first region, and has a ten-point average roughness of 0.9 μm to 3 μm in the second region.

6. The electronic component embedded substrate according to claim 1, wherein: The thickness of the barrier layer in the first region is thinner than the thickness of the barrier layer in the second region.

7. The electronic component embedded substrate according to claim 1, wherein: The barrier layer is disposed at the same height as one core wiring layer among the plurality of core wiring layers.

8. The electronic component embedded substrate according to claim 1, wherein: The electronic component has a first surface on which connection pads are disposed and a second surface opposite to the first surface, and The second surface is attached to the barrier layer by a die attach film.

9. The electronic component embedded substrate according to claim 8, wherein: The core structure includes: a first core insulation layer; a first core wiring layer and the barrier layer, both of which are arranged on one surface of the first core insulation layer; a second core wiring layer, which is arranged on the other surface of the first core insulation layer; a second core insulation layer, which is arranged on the one surface of the first core insulation layer and covers at least a portion of each of the first core wiring layer and the barrier layer; a third core insulation layer, which is arranged on the other surface of the first core insulation layer and covers at least a portion of the second core wiring layer; a third core wiring layer, which is arranged on the second core insulation layer; a fourth core wiring layer, which is arranged on the third core insulation layer; a first core via layer, which passes through the first core insulation layer and connects the first core wiring layer and the second core wiring layer to each other; a second core via layer, which passes through the second core insulation layer and connects the first core wiring layer and the third core wiring layer to each other; and a third core via layer, which passes through the third core insulation layer and connects the second core wiring layer and the fourth core wiring layer to each other, The first insulator includes the first core insulation layer, the second core insulation layer and the third core insulation layer, The plurality of core wiring layers include the first core wiring layer, the second core wiring layer, the third core wiring layer, and the fourth core wiring layer, The first core insulation layer has a thickness greater than a thickness of each of the second core insulation layer and the third core insulation layer, and The second core via layer and the third core via layer have profiles tapered in opposite directions.

10. The electronic component embedded substrate according to claim 9, wherein: The build-up structure includes: a first build-up insulating layer covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity; a first build-up wiring layer disposed on the first build-up insulating layer; and a first build-up via layer passing through the first build-up insulating layer and connecting the first build-up wiring layer to the connection pad and the fourth core wiring layer, respectively. The second insulator includes the first buildup insulating layer, The one or more build-up wiring layers include the first build-up wiring layer, and The first buildup via layer has a tapered profile in which a width of a cross section becomes narrower in a direction from the buildup structure toward the core structure.

11. The electronic component embedded substrate according to claim 10, wherein: The buildup structure further includes: a second buildup insulating layer disposed on the first buildup insulating layer and covering at least a portion of the first buildup wiring layer; a second buildup wiring layer disposed on the second buildup insulating layer; and a second buildup via layer passing through the second buildup insulating layer and connecting the first buildup wiring layer and the second buildup wiring layer to each other. The second insulator further includes the second buildup insulating layer, The one or more build-up wiring layers further include the second build-up wiring layer, and The second buildup via layer has a tapered profile in which a width of a cross section becomes narrower in the direction from the buildup structure toward the core structure.

12. The substrate with embedded electronic components according to claim 1, further comprising: a first passivation layer disposed on an opposite side of the core structure on which the buildup structure is disposed and having a plurality of first openings, the plurality of first openings respectively exposing at least a portion of one of the plurality of core wiring layers; as well as A plurality of first electrical connection metal bumps are respectively disposed on the plurality of first openings and are all connected to the exposed portion of the one core wiring layer.

13. The substrate embedded with electronic components according to claim 12, further comprising: a second passivation layer disposed on an opposite side of the buildup structure to the side on which the core structure is disposed and having a plurality of second openings that respectively expose at least a portion of one of the one or more buildup wiring layers; a plurality of second electrical connection metal bumps, respectively disposed on the plurality of second openings and each connected to the exposed portion of the one build-up wiring layer; as well as One or more surface mount components are mounted on the second passivation layer via the plurality of second electrical connection metal bumps.

14. A substrate embedded with electronic components, comprising: A core structure comprising a first insulator and a plurality of core wiring layers, the plurality of core wiring layers being respectively disposed on or in the first insulator, and the core structure having a cavity penetrating at least a portion of the first insulator in a thickness direction of the first insulator, and the core structure having a barrier layer disposed as a bottom surface of the cavity; an electronic component disposed in the cavity and attached to the barrier layer; as well as a build-up structure including a second insulator covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, and one or more build-up wiring layers each disposed on or in the second insulator, wherein a portion of one surface of the barrier layer in a region exposed from the first insulator through the cavity has a first concavo-convex portion and a second concavo-convex portion, the second concavo-convex portion being disposed on the first concavo-convex portion and having a concavo-convex height difference smaller than that of the first concavo-convex portion, At least a portion of the one surface of the barrier layer is buried in the first insulator, the portion of the one surface of the barrier layer buried in the first insulator has a third concavo-convex portion, and the first concavo-convex portion has a concavo-convex height difference greater than that of the third concavo-convex portion, and The height difference of the concave and convex portions refers to the average value of the height differences of the concave and convex portions.

15. The electronic component embedded substrate according to claim 14, wherein: A thickness of a portion of the one surface of the barrier layer in a region exposed from the first insulator through the cavity is thinner than a thickness of a portion of the one surface of the barrier layer buried in the first insulator.

16. The electronic component embedded substrate according to claim 14, wherein: The second concavo-convex portion has a concavo-convex height difference greater than a concavo-convex height difference of the third concavo-convex portion.

17. A substrate embedded with electronic components, comprising: A core structure comprising a first insulator and a plurality of core wiring layers, the plurality of core wiring layers being respectively disposed on or in the first insulator, and the core structure having a cavity penetrating at least a portion of the first insulator in a thickness direction of the first insulator, and the core structure having a barrier layer disposed as a bottom surface of the cavity; an electronic component disposed in the cavity and attached to the barrier layer; as well as a build-up structure including a second insulator covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, and one or more build-up wiring layers each disposed on or in the second insulator, wherein a portion of one surface of the barrier layer in the first region exposed from the first insulator through the cavity has a centerline average roughness of 0.6 μm to 1.2 μm and / or a ten-point average roughness of 7 μm to 13 μm, wherein the portion of the one surface of the barrier layer in the first region exposed from the first insulator through the cavity has a first concavo-convex portion and a second concavo-convex portion, the second concavo-convex portion being disposed on the first concavo-convex portion and having a concavo-convex height difference smaller than that of the first concavo-convex portion, and The height difference of the concave and convex portions refers to the average value of the height differences of the concave and convex portions.

18. The electronic component embedded substrate according to claim 17, wherein: The centerline average roughness of the portion of the one surface of the barrier layer in the second region covered by the first insulator is smaller than the centerline average roughness of the portion of the one surface of the barrier layer in the first region exposed from the first insulator through the cavity, and / or The ten-point average roughness of the portion of the one surface of the barrier layer in the second region covered by the first insulator is smaller than the ten-point average roughness of the portion of the one surface of the barrier layer in the first region exposed from the first insulator through the cavity.

19. The electronic component embedded substrate according to claim 18, wherein: The portion of the one surface of the barrier layer in the second region covered by the first insulator has a center line average roughness of 0.1 μm to 0.4 μm and / or a ten-point average roughness of 0.9 μm to 3 μm.

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