Vertical memory device

Abstract

A vertical memory device is disclosed. The vertical memory device includes gate electrodes, a channel, a first conductive through via, and an insulating structure. The gate electrodes are spaced apart from each other on a substrate along a first direction substantially perpendicular to an upper surface of the substrate, and can be stacked in a staircase shape. The channel extends through the gate electrodes along the first direction. The first conductive through via extends through and electrically connects with a conductive pad of a first one of the gate electrodes. The first conductive through via extends through a second one of the gate electrodes under the first one of the gate electrodes. The insulating structure is formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

Description

[0001] Priority is claimed to Korean Patent Application No. 10-2019-0171208, filed on December 19, 2019, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a vertical memory device. Background Technology

[0003] In VNAND flash memory devices, the contact plugs of the corresponding gate electrodes in the pad region of the contact substrate can sometimes make contact with the underlying gate electrodes through a hole. This can lead to an electrical short circuit between the gate electrode and the corresponding(s) underlying gate electrodes(s). Therefore, a method is needed to prevent such electrical short circuits. Summary of the Invention

[0004] Embodiments of the inventive concept provide a vertical memory device with improved electrical characteristics.

[0005] Embodiments of the inventive concept provide a vertical memory device. The vertical memory device may include a gate electrode, a channel, a first conductive through-via, and an insulating structure. The gate electrodes may be spaced apart from each other on a substrate along a first direction substantially perpendicular to the upper surface of the substrate, and may be stacked in a stepped shape. The channel may extend through the gate electrode along the first direction. The first conductive through-via may extend through and be electrically connected to a conductive pad of a first gate electrode among the gate electrodes. The first conductive through-via may extend through a second gate electrode disposed below the first gate electrode among the gate electrodes. The insulating structure may be formed between the sidewalls of the first conductive through-via and each of the second gate electrodes facing the first conductive through-via, and electrically insulate the first conductive through-via from each of the second gate electrodes.

[0006] Embodiments of the inventive concept also provide a vertical memory device. The vertical memory device may include a gate electrode, a channel, and first to third conductive through-vias. The gate electrodes may be spaced apart from each other in a first region and a second region of a substrate along a first direction substantially perpendicular to the upper surface of the substrate. The substrate includes a first region, a second region, and a third region, and the gate electrodes may have a stepped shape in the second region of the substrate. The channel may extend through the gate electrodes in the first region of the substrate along the first direction. The first conductive through-via may extend through some of the gate electrodes in the second region of the substrate, the first conductive through-via being electrically connected to the uppermost horizontal first gate electrode among the gate electrodes, and the first conductive through-via may be electrically insulated from a second gate electrode below the first gate electrode among the gate electrodes. A second conductive through-via may be formed at the same level as the first conductive through-via in a third region of the substrate. A third conductive through-via may be formed at the same level as the first conductive through-via in the first region of the substrate, and may extend through and be electrically insulated from the gate electrode. The first to third conductive through-vias may have the same width. Each of the first to third conductive through-holes may include a vertical portion and a ramp portion, the vertical portion extending along a first direction, and the ramp portion having a width that gradually increases from the bottom of the ramp portion toward the top of the ramp portion.

[0007] Embodiments of the inventive concept further provide a vertical memory device. The vertical memory device may include gate electrodes, channels, and a first conductive through-via. The gate electrodes may be spaced apart from each other on a substrate along a first direction substantially perpendicular to the upper surface of the substrate, and may be stacked in a stepped shape. The channels may extend through the gate electrodes along the first direction. The first conductive through-via may extend on the substrate through some of the gate electrodes, and may extend through and be electrically connected to a conductive pad of the uppermost horizontal first gate electrode among the gate electrodes. The first conductive through-via may be electrically insulated from a second gate electrode below the first gate electrode among the gate electrodes. The first conductive through-via may include a vertical portion, a protruding portion, and a ramp portion, the vertical portion extending along the first direction, the protruding portion protruding from the vertical portion in a horizontal direction substantially parallel to the upper surface of the substrate, and the ramp portion located on the vertical portion, having a width that gradually increases from the bottom of the ramp portion towards the top of the ramp portion.

[0008] Embodiments of the inventive concept further provide a vertical memory device. The vertical memory device may include: a transistor located on a substrate; a lower wiring located on the substrate and electrically connected to the transistor; a common source plate (CSP) located on the lower wiring; a channel connection pattern and a support layer sequentially stacked on the CSP; gate electrodes spaced apart from each other on the substrate along a first direction substantially perpendicular to the upper surface of the substrate and stacked in a stepped shape on the substrate; channels electrically connected to each other via the channel connection pattern, each of the channels potentially extending along the first direction on the CSP through the gate electrode, the support layer, and the channel connection pattern; a first conductive through-via to a third conductive through-via; and an insulating structure. The first conductive through-via can extend on the substrate through some of the gate electrodes, is electrically connected to the uppermost horizontal first gate electrode among the gate electrodes, and is electrically insulated from a second gate electrode below the first gate electrode among the gate electrodes. The second conductive through-via can be formed at the same level as the first conductive through-via, may not extend through the gate electrode, and can be electrically connected to one of the lower wirings. A third conductive through-via can be formed at the same level as the first conductive through-via, and can extend through the gate electrode, channel connection pattern, support layer, and CSP to electrically connect to another in the underlying wiring. An insulating structure can be formed between the sidewalls of each of the first conductive through-vias and the second gate electrodes to electrically insulate the first conductive through-vias from each of the second gate electrodes, and can be formed between the sidewalls of each of the third conductive through-vias to electrically insulate the third conductive through-vias from each of the gate electrodes.

[0009] In a vertical memory device according to an example embodiment, a first conductive through-via electrically connected to a corresponding gate electrode in the gate electrode on a pad region of the substrate can extend through other gate electrodes below the corresponding gate electrode in the gate electrode, but can be electrically insulated from other gate electrodes in the gate electrode by insulating patterns and spacers. Therefore, the first conductive through-via can be formed using the same process used to form the second and third conductive through-vias respectively in the cell region and peripheral circuit region of the substrate, simplifying the overall process. Furthermore, the first conductive through-via can receive electrical signals from the bottom wiring, eliminating the need to form top wiring to apply electrical signals to the first conductive through-via, thus increasing the layout freedom of the top wiring.

[0010] Furthermore, the first conductive through-via can support the molded part during the formation of the gate electrode. Therefore, if only the first conductive through-via is formed in each of the conductive pads, there is no need to form additional dummy channels to support the molded part. Thus, since it is not necessary to maintain the distance between the first conductive through-via and the dummy channels, the first conductive through-via can have a relatively large size, thereby increasing the layout freedom of the first conductive through-via. Attached Figure Description

[0011] Figure 1 A plan view is shown illustrating a method for manufacturing a vertical memory device according to an example embodiment of the inventive concept.

[0012] Figure 2 It shows along Figure 1 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0013] Figure 3 It shows along Figure 1 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device.

[0014] Figure 4 It shows along Figure 1 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device.

[0015] Figure 5 It shows along Figure 1 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device.

[0016] Figure 6 A plan view is shown that further describes the method of manufacturing a vertical memory device.

[0017] Figure 7 It shows along Figure 6 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0018] Figure 8 A plan view is shown that further describes the method of manufacturing a vertical memory device.

[0019] Figure 9 It shows along Figure 8 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0020] Figure 10 It shows Figure 9 An enlarged sectional view of region X.

[0021] Figure 11 It shows along Figure 8 The section view taken by line B-B' describes a method for manufacturing a vertical memory device.

[0022] Figure 12 It shows along Figure 8 The section view taken by line B-B' further describes the method of manufacturing a vertical memory device.

[0023] Figure 13 It shows along Figure 8 The section view taken by line B-B' further describes the method of manufacturing a vertical memory device.

[0024] Figure 14 It shows along Figure 8 The section view taken by line B-B' further describes the method of manufacturing a vertical memory device.

[0025] Figure 15 A plan view is shown that further describes the method of manufacturing a vertical memory device.

[0026] Figure 16 It shows along Figure 15 The figure shows a cross-sectional view taken along line C-C', depicting a method for manufacturing a vertical memory device.

[0027] Figure 17 It shows along Figure 15 The cross-sectional view taken by line C-C' further describes the method of manufacturing a vertical memory device.

[0028] Figure 18 It shows along Figure 15 The cross-sectional view taken by line C-C' further describes the method of manufacturing a vertical memory device.

[0029] Figure 19 It shows along Figure 15 The cross-sectional view taken by line C-C' further describes the method of manufacturing a vertical memory device.

[0030] Figure 20 It shows along Figure 15 The section view taken by line B-B' describes a method for manufacturing a vertical memory device.

[0031] Figure 21 It shows along Figure 15 The cross-sectional view taken by line C-C' further describes the method of manufacturing a vertical memory device.

[0032] Figure 22 A plan view is shown that further describes the method of manufacturing a vertical memory device.

[0033] Figure 23It shows along Figure 22 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0034] Figure 24 It shows Figure 23 An enlarged sectional view of region X.

[0035] Figure 25 It shows along Figure 22 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device.

[0036] Figure 26 It shows Figure 25 An enlarged sectional view of region X.

[0037] Figure 27 It shows along Figure 22 The section view taken by line B-B' describes a method for manufacturing a vertical memory device.

[0038] Figure 28 It shows along Figure 22 The section view taken by line B-B' further describes the method of manufacturing a vertical memory device.

[0039] Figure 29 A plan view is shown that further describes the method of manufacturing a vertical memory device.

[0040] Figure 30 It shows along Figure 29 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0041] Figure 31 It shows Figure 30 An enlarged sectional view of region X.

[0042] Figure 32 It shows along Figure 29 The section view taken by line B-B' describes a method for manufacturing a vertical memory device.

[0043] Figure 33 It shows along Figure 29 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device.

[0044] Figure 34 A plan view is shown illustrating a method for manufacturing a vertical memory device according to an example embodiment of the inventive concept.

[0045] Figure 35 It shows along Figure 34 The region X intercepted by line A-A' (refer to) Figure 30 An enlarged sectional view of ( ).

[0046] Figure 36 It shows along Figure 34 The line D-D' in the figure is a cross-sectional view describing a method for manufacturing a vertical memory device.

[0047] Figure 37 It shows along Figure 34 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0048] Figure 38 It shows along Figure 34 The cross-sectional view taken by line A-A' in the figure describes a method for manufacturing a vertical memory device.

[0049] Figure 39 It shows along Figure 34 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device.

[0050] Figure 40 It shows along Figure 34 The cross-sectional view taken by line A-A' further describes the method of manufacturing a vertical memory device. Detailed Implementation

[0051] The following description, with reference to the accompanying drawings, will depict an exemplary embodiment of a vertical memory device and a method of manufacturing a vertical memory device according to the inventive concept. It should be understood that although the terms "first," "second," and / or "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0052] In the following description (rather than necessarily in the claims), a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In an example embodiment, the second direction and the third direction may be substantially perpendicular to each other.

[0053] Figures 1 to 33 These are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment. Specifically, Figure 1 , Figure 6 , Figure 8 , Figure 15 , Figure 22 and Figure 29 It's a floor plan. Figures 2 to 5 , Figure 7 , Figures 9 to 14 , Figures 16 to 21 , Figures 23 to 28 and Figures 30 to 33 It is a sectional view.

[0054] Figures 2 to 5 , Figure 7 , Figure 9 , Figure 23 , Figure 25 , Figure 30 and Figure 33 These are sectional views taken along line A-A' of the corresponding plan view. Figures 11 to 14 , Figure 20 , Figures 27 to 28 and Figure 32 These are sectional views taken along line B-B' of the corresponding plan view. Figures 16 to 19 and Figure 21 These are sectional views taken along line C-C' of the corresponding plan view. Figure 10 , Figure 24 , Figure 26 and Figure 31 They are Figure 9 , Figure 23 , Figure 25 and Figure 30 An enlarged sectional view of region X.

[0055] Reference Figure 1 and Figure 2 A lower circuit pattern can be formed on the substrate 100, and a first insulating interlayer 160 and a second insulating interlayer 230 can be sequentially formed on the substrate 100 to cover the lower circuit pattern.

[0056] The substrate 100 may include group IV semiconductor materials (such as silicon, germanium, silicon-germanium, etc.) or group III-V compounds (such as GaP, GaAs, GaSb, etc.). In an example embodiment, the substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0057] The substrate 100 may include a field region on which an isolation pattern 110 is formed and an active region 105 on which no isolation pattern is formed. The isolation pattern 110 may be formed by, for example, a shallow trench isolation (STI) process and may include oxides such as silicon oxide.

[0058] In an example embodiment, substrate 100 may include first regions to third regions I, II, and III. First region I may be a cell array region in which memory cells are formed, second region II may be an extension region or pad region at least partially surrounding first region I in which upper contact plugs for transmitting electrical signals to memory cells are formed, and third region III may be a peripheral circuit region at least partially surrounding second region II in which some conductive through-vias for transmitting electrical signals to a lower circuit pattern are formed. First region I and second region II may form cell regions, thus the peripheral circuit region may at least partially surround the cell regions. Figure 1 and Figure 2 A portion of each of the first to third regions I, II and III of the substrate is shown.

[0059] In an example embodiment, the vertical memory device may have a peripheral upper cell (COP) structure. That is, the lower circuit pattern may be formed on the substrate 100, and the memory cells, upper contact plugs, and conductive through vias may be formed on the lower circuit pattern.

[0060] The lower circuit pattern may include transistors, lower contact plugs, lower wiring, lower vias, etc. In an example embodiment, a first transistor, a second transistor, and a third transistor may be formed. The first transistor includes a first lower gate structure 152 located on the substrate 100 and a first impurity region 102 located above the active region 105 adjacent to the first lower gate structure 152. The second transistor includes a second lower gate structure 154 located on the substrate 100 and a second impurity region 104 located above the active region 105 adjacent to the second lower gate structure 154. The third transistor includes a third lower gate structure 156 located on the substrate 100 and a third impurity region 106 located above the active region 105 adjacent to the third lower gate structure 156.

[0061] exist Figure 2 In this embodiment, the first to third transistors are formed on the first region I and the second region II of the substrate 100. However, the inventive concept is not limited thereto, and additional transistors may be further formed on the third region III of the substrate 100.

[0062] The first lower gate structure 152 may include a first lower gate insulating pattern 122, a first lower gate electrode 132, and a first lower gate mask 142 sequentially stacked on the substrate 100; the second lower gate structure 154 may include a second lower gate insulating pattern 124, a second lower gate electrode 134, and a second lower gate mask 144 sequentially stacked on the substrate 100; and the third lower gate structure 156 may include a third lower gate insulating pattern 126, a third lower gate electrode 136, and a third lower gate mask 146 sequentially stacked on the substrate 100.

[0063] A first insulating interlayer 160 may be formed on the substrate 100 to cover the first transistor, the second transistor and the third transistor, and a first lower contact plug to a third lower contact plug 172, 174 and 176 may be formed through the first insulating interlayer 160 to contact the first impurity region to the third impurity region 102, 104 and 106 respectively.

[0064] First lower wirings to third lower wirings 182, 184, and 186 can be formed on the first insulating interlayer 160 to contact first lower contact plugs to third lower contact plugs 172, 174, and 176, respectively. First lower vias 192, fourth lower wirings 202, fourth lower vias 212, and seventh lower wirings 222 can be sequentially stacked on the first lower wiring 182; second lower vias 194, fifth lower wirings 204, fifth lower vias 214, and eighth lower wirings 224 can be sequentially stacked on the second lower wiring 184; and third lower vias 196, sixth lower wirings 206, sixth lower vias 216, and ninth lower wirings 226 can be sequentially stacked on the third lower wiring 186.

[0065] The first lower contact plugs to the third lower contact plugs 172, 174 and 176, the first lower vias to the sixth lower vias 192, 194, 196, 212, 214 and 216, and the first lower wiring to the ninth lower wiring 182, 184, 186, 202, 204, 206, 222, 224 and 226 may include conductive materials, such as metals, metal nitrides, metal silicides, doped polysilicon or other conductive materials.

[0066] A second insulating layer 230 can be formed on the first insulating layer 160 to cover the first to ninth lower wirings 182, 184, 186, 202, 204, 206, 222, 224 and 226, and the first to sixth lower vias 192, 194, 196, 212, 214 and 216. The second insulating layer 230 and the first insulating layer 160 can form a lower insulating layer structure, and in some cases can include a single layer, because the first insulating layer 160 and the second insulating layer 230 can include the same material, such as silicon oxide merged together.

[0067] The first to third lower gate structures 152, 154 and 156, the first to third lower contact plugs 172, 174 and 176, the first to sixth lower vias 192, 194, 196, 212, 214 and 216, and the first to ninth lower wirings 182, 184, 186, 202, 204, 206, 222, 224 and 226 can be formed by patterning or damascene processes.

[0068] Reference Figure 3 A common source plate (CSP) 240, a third insulating layer pattern 250, and a fourth insulating layer pattern 253 can be formed on the second insulating layer 230.

[0069] CSP 240 can be formed on the second insulating interlayer 230 and can be patterned to remain only on the first region I and the second region II of the substrate 100. Alternatively, CSP 240 can be patterned to not retain the formation of the first conductive through-hole 622 and the third conductive through-hole 626 (see reference 1). Figures 29 to 32 The first through hole 422 and the third through hole 426 (refer to) Figures 8 to 11 In other words, CSP 240 can include openings above the first region I and the second region II.

[0070] The third insulating layer pattern 250 and the fourth insulating layer pattern 253 can be formed by forming the third insulating layer on the second insulating layer 230 (including in the opening in the CSP 240) and planarizing the third insulating layer until the upper surface of the CSP 240 is exposed. Therefore, the third insulating layer pattern 250 can be formed on the third region III of the substrate 100, and the fourth insulating layer pattern 253 can be formed in the opening of the CSP 240 on the first region I and the second region II of the substrate 100.

[0071] CSP 240 may include polycrystalline silicon doped with n-type impurities, and the third insulating interlayer pattern 250 and the fourth insulating interlayer pattern 253 may include oxides, such as silicon oxide.

[0072] The sacrificial layer structure 290 and the support layer 300 can be sequentially formed on the CSP 240, the third insulating interlayer pattern 250, and the fourth insulating interlayer pattern 253.

[0073] The sacrificial layer structure 290 may include first to third sacrificial layers 260, 270 and 280 stacked in sequence. The first sacrificial layer 260 and the third sacrificial layer 280 may include oxides such as silicon oxide, and the second sacrificial layer 270 may include nitrides such as silicon nitride.

[0074] The support layer 300 may include a material that is etch-selective relative to the first to third sacrificial layers 260, 270, and 280, such as undoped polysilicon or polysilicon doped with n-type impurities. A portion of the support layer 300 may extend through the sacrificial layer structure 290 to contact the upper surface of the CSP 240, the upper surface of which may be formed with a support pattern (not shown).

[0075] The first insulating layer 310 and the fourth sacrificial layer 320 can be stacked alternately and repeatedly on the support layer 300. Therefore, a molded layer comprising a plurality of first insulating layers 310 and a plurality of fourth sacrificial layers 320 stacked alternately and repeatedly in a first direction can be formed. The first insulating layer 310 may comprise an oxide such as silicon oxide, and the fourth sacrificial layer 320 may comprise a material having etch selectivity relative to the first insulating layer 310, such as a nitride (e.g., silicon nitride).

[0076] Reference Figure 4 An etch stop layer 330 can be formed on the uppermost first insulating layer 310 of the first insulating layer 310. A photoresist pattern (not shown) can be formed on the etch stop layer 330, partially covering it. The photoresist pattern can be used as an etch mask to etch the etch stop layer 330, the uppermost first insulating layer 310 of the first insulating layer 310, and the uppermost fourth sacrificial layer 320 below the uppermost first insulating layer 310 of the fourth sacrificial layer 320. Therefore, a portion of the first insulating layer 310 directly below the uppermost fourth sacrificial layer 320 of the fourth sacrificial layer 320 can be exposed.

[0077] After performing a trimming process to reduce the area of ​​the photoresist pattern by a given ratio, an etching process can be performed, such that the reduced photoresist pattern can be used as an etching mask to etch the etch stop layer 330, the uppermost first insulating layer 310 of the first insulating layers 310, the uppermost fourth sacrificial layer 320 of the fourth sacrificial layers 320, an exposed first insulating layer 310 of the first insulating layers 310, and a fourth sacrificial layer 320 below the exposed first insulating layer 310. By repeatedly performing the trimming and etching processes, a molded part comprising multiple stepped layers can be formed, the multiple stepped layers including fourth sacrificial layers 320 and first insulating layers 310 that are sequentially stacked and have a stepped shape.

[0078] In the following text, each of the "step layers" can be considered to include not only the exposed portion but also the portion of the step layer covered by the step layer above it, and therefore can refer to the entire portion of the fourth sacrificial layer 320 and the entire portion of the first insulating layer 310 at each level. The exposed portion of a step layer not covered by the step layer above it can be referred to as a "step". In the example embodiment, the steps can be arranged along a second direction and can also be arranged along a third direction.

[0079] The molding part can be formed on the support layer 300 in the first region I and the second region II of the substrate 100, and the upper surface of the edge of the support layer 300 is not covered by the molding part, but is exposed. Steps in the molding part can be formed in the second region II of the substrate 100.

[0080] Reference Figure 5 The thickness of each of the fourth sacrificial layers 320 at its end in the second direction can be increased to form an insulating pad layer 322.

[0081] In one embodiment, an insulating pad 322 can be formed by removing the ends of the first insulating layer 310 included in each step layer that are not covered by the upper step layer in the second direction to expose the ends of the fourth sacrificial layer 320 in the second direction in each step layer. Thereafter, the pad can be formed on the etch stop layer 330, the molding, the support layer 300, and the third insulating interlayer pattern 250. Subsequently, portions of the pad on the sidewalls of the molding, the upper surface of the etch stop layer 330, the upper surface of the support layer 300, and the upper surface of the third insulating interlayer pattern 250 can be removed. The pad may comprise a material substantially the same as that of the fourth sacrificial layer 320 and can therefore be incorporated into the fourth sacrificial layer 320 to form the insulating pad 322. The end of each of the fourth sacrificial layers 320 in the second direction where the insulating pad 322 is formed may have a thickness greater than the thickness of the other portions of the fourth sacrificial layer 320.

[0082] A fifth insulating interlayer 340 can be formed on the third insulating interlayer pattern 250 and the support layer 300 to cover the molded part, the exposed upper surface of the etch stop layer 330, the exposed upper surface of the support layer 300, the exposed upper surface of the third insulating interlayer pattern 250, and the sidewalls of the sacrificial layer structure 290. The fifth insulating interlayer 340 can be planarized until the upper surface of the uppermost of the first insulating layers 310 is exposed. Therefore, the etch stop layer 330 can be removed, and the sidewalls of the molded part can be covered by the fifth insulating interlayer 340. The fifth insulating interlayer 340 may include oxides, such as silicon oxide.

[0083] A sixth insulating layer 350 may be formed on the upper surface of the molded part and on the upper surface of the fifth insulating layer 340. The sixth insulating layer 350 may include oxides, such as silicon oxide.

[0084] Reference Figure 6 and Figure 7After forming an etching mask (not shown) on the upper surface of the sixth insulating interlayer 350, the sixth insulating interlayer 350, the first insulating layer 310, the fourth sacrificial layer 320, the support layer 300 and the sacrificial layer structure 290 can be etched using the etching mask to form a channel hole 360 ​​through the upper surface of the exposed CSP 240 in the first region I of the substrate 100.

[0085] In an example embodiment, the plurality of channel holes 360 may be formed to be spaced apart from each other in each of the second and third directions.

[0086] After removing the etch mask, a charge storage structure layer and a channel layer can be formed on the sidewalls of the channel hole 360, the upper surface of the CSP 240, and the upper surface of the sixth insulating interlayer 350. A first fill layer can be formed on the channel layer to fill the channel hole 360. The first fill layer, channel layer, and charge storage structure layer can be planarized until the upper surface of the sixth insulating interlayer 350 is exposed to form a charge storage structure 370, a channel 380, and a first fill pattern 390 sequentially stacked in each channel hole 360.

[0087] In an example embodiment, the charge storage structure 370 may include a tunnel insulating pattern, a charge storage pattern, and a first barrier pattern sequentially stacked from the outer wall of the channel 380 in a horizontal direction substantially parallel to the upper surface of the substrate 100. The tunnel insulating pattern may include an oxide such as silicon oxide, the charge storage pattern may include a nitride such as silicon nitride, and the first barrier pattern may include an oxide such as silicon oxide.

[0088] The upper portion of the first pillar structure, including the charge storage structure 370, the channel 380, and the first fill pattern 390, which are sequentially stacked in each channel via 360, can be removed to form a first trench, and a first cap pattern 400 can be formed to fill the first trench. The first cap pattern 400 may include, for example, polysilicon doped with n-type impurities.

[0089] An etching mask (not shown) may be formed on the upper surface of the sixth insulating interlayer 350, and the etching mask may be used to etch the sixth insulating interlayer 350, the upper first insulating layer 310 of the first insulating layer 310, and the upper fourth sacrificial layer 320 of the fourth sacrificial layer 320 to form a first opening therethrough, which may extend in a second direction. A first dividing pattern 405 may be formed in the first opening.

[0090] In an example embodiment, the first separating pattern 405 may extend through the upper portion of some channels 380. Additionally, the first separating pattern 405 may extend through the sixth insulating interlayer 350, the fourth sacrificial layers 320 at two levels above, and the first insulating layers 310 at two levels above, and partially through one of the first insulating layers 310 at a third level from above. The first separating pattern 405 may extend along a second direction on the first region I and the second region II of the substrate 100, and may extend through the stepped layers at the two levels above in the molding. Therefore, the fourth sacrificial layers 320 at the corresponding two levels above may be separated by the first separating pattern 405 in a third direction.

[0091] Reference Figures 8 to 11 A seventh insulating layer 410 can be formed on the sixth insulating layer 350, the first cover pattern 400, and the first separator pattern 405. An etching mask can be used to etch the fifth to seventh insulating layers 340, 350, and 410, the molded part, the support layer 300, the sacrificial layer structure 290, the third insulating layer pattern 250, the fourth insulating layer pattern 253, and the upper portion of the second insulating layer 230 to form first to third through-holes 422, 424, and 426, respectively exposing the upper surfaces of the seventh to ninth lower wirings 222, 224, and 226.

[0092] In an exemplary embodiment, the first through-hole 422 may extend through the fourth sacrificial layer 320 in the molded part. Specifically, the first through-hole 422 may extend through the insulating pad 322 of the uppermost fourth sacrificial layer 320 among the fourth sacrificial layers 320 through which the first through-hole 422 extends. In an exemplary embodiment, the first through-hole to the third through-holes 422, 424 and 426 may have the same diameter.

[0093] The first through-hole 422 may extend through the insulating pad 322 corresponding to one of the fourth sacrificial layers 320, and the insulating pad 322 may have a smaller area than the area in which the second through-hole 424 and the third through-hole 426 may be formed. Therefore, if other structures, such as dummy channels, are formed in the insulating pad 322, the first through-hole 422 must be spaced apart from the dummy channels and thus have a relatively small diameter. However, in the example embodiment, only the first through-hole 422 is formed in the insulating pad 322, and other structures, such as dummy channels, are not formed in the insulating pad 322; therefore, the first through-hole 422 can have a relatively large diameter, for example, a diameter substantially equal to the diameters of the second through-hole 424 and the third through-hole 426.

[0094] The first through-hole 422 and the third through-hole 426 may extend through the fourth insulating interlayer pattern 253, and the second through-hole 424 may extend through the third insulating interlayer pattern 250. The seventh insulating interlayer 410 may include an oxide such as silicon oxide.

[0095] The fourth sacrificial layer 320 exposed by the first via 422 and the third via 426 can be partially removed, for example, by a wet etching process to form the first gap 430. In an example embodiment, the insulating pad layer 322, which is thicker than other portions of the fourth sacrificial layer 320, can be etched at a relatively fast rate, so that a second gap 440 can be formed in the insulating pad layer 322 to have a depth in the horizontal direction greater than the depth of the first gap 430. The width of the second gap 440 in the first direction can be greater than the width of the first gap 430 in the first direction.

[0096] Alternatively, the second sacrificial layer 270, which includes a material substantially the same as or similar to that of the fourth sacrificial layer 320, may be partially removed to form the third gap 435.

[0097] Reference Figure 12 A first spacer layer 450 may be formed on the sidewalls of the first through holes to the third through holes 422, 424, and 426, the upper surfaces of the seventh to ninth lower wirings 222, 224, and 226 exposed by the first through holes to the third through holes 422, 424, and 426 respectively, the inner walls of the first gaps to the third gaps 430, 440, and 435, and the upper surface of the seventh insulating interlayer 410. A second insulating layer may be formed on the first spacer layer 450 to fill the first gap 430 and the third gap 435, and at least partially fill the second gap 440 and the first through holes to the third through holes 422, 424, and 426.

[0098] The second insulating layer may include an oxide such as silicon oxide, and the first spacer layer 450 may include a material that is etch-selective relative to the second insulating layer. The first spacer layer 450 may include a nitride such as silicon nitride.

[0099] The second insulating layer can be partially removed by, for example, a wet etching process, so that a portion of the second insulating layer in the second gap 440 can be completely removed. The second gap 440 has a relatively large width in the first direction, and a second insulating pattern 460 can be formed in each of the first gap 430 and the third gap 435, each of the first gap 430 and the third gap 435 has a relatively small width in the first direction.

[0100] During the wet etching process, the first insulating layer 310 of the molded part can be protected by a first spacer layer 450, which includes a material having etch selectivity relative to the first insulating layer 310 and the second insulating pattern 460.

[0101] Reference Figure 13 A second fill layer can be formed on the first spacer layer 450 and the second insulating pattern 460 to fill the second gap 440 and at least partially fill the first vias to the third vias 422, 424 and 426. The second fill layer can then be partially removed by, for example, a wet etching process. The second fill layer may include a nitride, such as silicon nitride.

[0102] A second filling pattern 480 can be formed in the second gap 440 to partially fill the second gap 440 using a wet etching process. In an example embodiment, the first distance D1 in the horizontal direction from the sidewall of the first through-hole 422 to the sidewall of the second filling pattern 480 can be equal to or less than the second distance D2 in the horizontal direction from the sidewall of the first through-hole 422 to the sidewall of the fourth sacrificial layer 320 facing the second insulating pattern 460.

[0103] The first spacer layer 450, which includes a material substantially the same as or similar to that of the second filler layer, can be partially removed. Specifically, portions of the first spacer layer 450 on the sidewalls of the first through-holes to the third through-holes 422, 424, and 426, and on the upper surface of the seventh insulating interlayer 410, can be removed. Thus, a first spacer 455 can be formed covering the lower and upper surfaces of the second insulating pattern 460 and the sidewalls of the second insulating pattern 460 facing the fourth sacrificial layer 320, and a second spacer 457 can be formed covering the lower and upper surfaces of the second filler pattern 480 and the sidewalls of the second filler pattern 480 facing the insulating pad layer 322.

[0104] Reference Figure 14 A third spacer layer may be formed on the sidewalls of the first through-holes to the third through-holes 422, 424, and 426, the upper surfaces of the seventh lower wiring to the ninth lower wiring 222, 224, and 226, the upper surface of the seventh insulating interlayer 410, and the sidewalls of the second insulating pattern 460, the second filling pattern 480, the sidewalls of the first spacer 455, and the sidewalls of the second spacer 457. A fifth sacrificial layer may be formed on the third spacer layer to fill the first through-holes to the third through-holes 422, 424, and 426, and the fifth sacrificial layer and the third spacer layer may be planarized until the upper surface of the seventh insulating interlayer 410 is exposed.

[0105] Therefore, a third spacer 490 can be formed on the sidewalls of the first through holes to the third through holes 422, 424 and 426, the upper surface of the seventh lower wiring to the ninth lower wiring 222, 224 and 226, and the sidewalls of the second insulating pattern 460, the second filling pattern 480, the sidewalls of the first spacer 455 and the sidewalls of the second spacer 457. Furthermore, the fifth to seventh sacrificial patterns 502, 504 and 506 (see reference) can be formed in the remaining portions of the first through holes to the third through holes 422, 424 and 426. Figure 15 ).

[0106] The third spacer 490 may include a material that is etch-selective relative to the fourth sacrificial layer 320, such as an oxide (e.g., silicon oxide), and the fifth to seventh sacrificial patterns 502, 504 and 506 may include, for example, polysilicon.

[0107] Reference Figure 15 and Figure 16 An eighth insulating layer 510 can be formed on the seventh insulating layer 410, the fifth to seventh sacrificial patterns 502, 504 and 506, and the third spacer 490. A second opening 520 penetrating the fifth to eighth insulating layers 340, 350, 410 and 510, and the molded part can be formed on the first region I and the second region II of the substrate 100 by an etching process using an etching mask. The eighth insulating layer 510 may include an oxide such as silicon oxide.

[0108] An etching process can be performed until the second opening 520 exposes the upper surface of the support layer 300, and further, the second opening 520 can extend through the upper part of the support layer 300. With the formation of the second opening 520, the first insulating layer 310 and the fourth sacrificial layer 320 of the molded part can be exposed.

[0109] In an example embodiment, the second opening 520 may extend along a second direction on the first region I and the second region II of the substrate 100, and a plurality of second openings 520 may be formed to be spaced apart from each other along a third direction. With the formation of the second openings 520, the first insulating layer 310 may be divided into a plurality of first insulating patterns 315 each extending in the second direction, and the fourth sacrificial layer 320 may be divided into a plurality of fourth sacrificial patterns 325 each extending in the second direction. The insulating pad layer 322 at the end of the fourth sacrificial layer 320 in the second direction may be transformed into an insulating pad 327.

[0110] A fourth spacer layer can be formed on the sidewalls and bottom of the second opening 520 and on the upper surface of the eighth insulating interlayer 510. The fourth spacer layer can be anisotropically etched to remove a portion of the fourth spacer layer at the bottom of the second opening 520. Therefore, a fourth spacer 530 can be formed on the sidewalls of the second opening 520, and the upper surface of the support layer 300 can be partially exposed.

[0111] The exposed portion of the support layer 300 and a portion of the sacrificial layer structure 290 beneath the support layer 300 can be removed to widen the second opening 520 downwards. Therefore, the second opening 520 can expose the upper surface of the CSP 240 and can further extend through the upper portion of the CSP 240.

[0112] In an example embodiment, the fourth spacer 530 may include, for example, undoped polycrystalline silicon or undoped amorphous silicon.

[0113] When the sacrificial layer structure 290 is partially removed, the sidewall of the second opening 520 is covered by the fourth spacer 530, so the first insulating pattern 315 and the fourth sacrificial pattern 325 of the molded part are not removed.

[0114] Reference Figure 17 The sacrificial layer structure 290 can be removed through the second opening 520 by, for example, a wet etching process, thus forming the fourth gap 540. The wet etching process can be performed using, for example, hydrofluoric acid and / or phosphoric acid.

[0115] With the formation of the fourth gap 540, the lower surface of the support layer 300 and the upper surface of the CSP 240 can be exposed. Additionally, a portion of the sidewall of the charge storage structure 370 can be exposed, and the exposed portion of the sidewall of the charge storage structure 370 can be removed during a wet etching process to expose a portion of the outer sidewall of the channel 380. Therefore, the charge storage structure 370 can be divided into an upper portion extending through the molding to cover the upper part of the outer sidewall of the channel 380 and a lower portion covering the bottom surface of the channel 380 on the CSP 240.

[0116] When the fourth gap 540 is formed by a wet etching process, the molded part does not fall off because it includes the first pillar structure of the channel 380, the support layer 300 and the support pattern, as well as the fifth sacrificial pattern 502 and the seventh sacrificial pattern 506.

[0117] Reference Figure 18 The fourth spacer 530 can be removed, and a channel connection layer can be formed on the sidewall of the second opening 520 and in the fourth gap 540. Then, a portion of the channel connection layer in the second opening 520 can be removed by an etching process to form a channel connection pattern 550 in the fourth gap 540.

[0118] As the channel connection pattern 550 is formed, the channels 380 between adjacent second openings 520 in the third direction can be connected to each other.

[0119] The channel connection pattern 550 may include amorphous silicon doped with n-type impurities, which can be crystallized by heat generated during deposition processes used for other structures to be converted into polycrystalline silicon doped with n-type impurities. Air gaps 555 may be formed in the channel connection pattern 550.

[0120] Reference Figure 19 and Figure 20 The fourth sacrificial pattern 325 exposed by the second opening 520 can be removed to form a fifth gap between adjacent first insulating patterns 315 in the first direction. The outer wall of the charge storage structure 370 can be partially exposed by the fifth gap.

[0121] When the fourth sacrificial pattern 325 is removed, the second spacer 457 and the second filling pattern 480, which are made of materials substantially the same or similar to those of the fourth sacrificial pattern 325, as well as the sidewalls of the first spacer 455 facing each of the fourth sacrificial patterns 325, can also be removed, so that the first spacer 455 can remain only on the lower and upper surfaces of the second insulating pattern 460.

[0122] As the fifth gap is formed, the outer wall of the third spacer 490, the outer wall of the second insulating pattern 460, and the end of the first spacer 455 adjacent to the outer wall of the second insulating pattern 460 can be exposed.

[0123] In an example embodiment, the fourth sacrificial pattern 325 can be removed by a wet etching process using phosphoric acid or sulfuric acid.

[0124] When the fourth sacrificial pattern 325 is removed to form the fifth gap, the fifth sacrificial pattern 502 and the seventh sacrificial pattern 506 have already been formed on the first region I and the second region II of the substrate 100, so the molded part including the first insulating pattern 315 will not fall off even if the dummy channel is not formed.

[0125] A second barrier layer can be formed on the exposed outer wall of the charge storage structure 370, the exposed outer wall of the third spacer 490, the exposed outer wall of the second insulating pattern 460, the exposed end of the first spacer 455, the inner wall of the fifth gap, the surface of the first insulating pattern 315, the sidewall of the support layer 300, the sidewall of the channel connection pattern 550, the upper surface of the CSP 240, and the upper surface of the eighth insulating interlayer 510. A gate electrode layer can then be formed on the second barrier layer.

[0126] The second barrier layer may include a metal oxide, such as aluminum oxide. The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked in sequence. The gate barrier layer may include a metal nitride, and the gate conductive layer may include a metal.

[0127] The gate electrode layer can be partially removed to form a gate electrode in each of the fifth gaps. In an example embodiment, the gate electrode layer can be partially removed by a wet etching process.

[0128] In an example embodiment, the gate electrode may extend in a second direction, and multiple gate electrodes may be stacked along a first direction to form a gate electrode structure. The gate electrode structure may have a stepped shape with gate electrodes serving as step layers, and the steps in each step layer that are not stacked by the upper step layers (i.e., the ends in each step layer in the second direction) may be referred to as conductive pads. A molded part including a first insulating pattern 315 and a fourth sacrificial pattern 325 can be converted into a molded part including the first insulating pattern 315 and the gate electrode.

[0129] In an example embodiment, multiple gate electrode structures may be formed to be spaced apart from each other in a third direction through a second opening 520. The gate electrode structures may include a first gate electrode 572, a second gate electrode 574, and a third gate electrode 576 sequentially stacked in a first direction. In an example embodiment, the first gate electrode 572 may be formed at the lowest horizontal level and may serve as a ground select line (GSL). The third gate electrode 576 may be formed at the highest horizontal level and at a second horizontal level from above, and may serve as a string select line (SSL). The second gate electrode 574 may be formed at multiple horizontal levels between the first gate electrode 572 and the third gate electrode 576, and may serve as a word line. The conductive pads of the first to third gate electrodes 572, 574, and 576 may be referred to as first conductive pads to third conductive pads 573, 575, and 577, respectively (see reference). Figure 22 ).

[0130] Reference Figure 21 A second separator layer can be formed on the second barrier layer to fill the second opening 520, and the second separator layer and the second barrier layer can be planarized until the upper surface of the eighth insulating interlayer 510 is exposed to form a second separator pattern 580 and a second barrier pattern 560, respectively (see also...). Figure 19 and Figure 20 The second dividing pattern 580 may divide each of the first gate electrode to the third gate electrode 572, 574 and 576 in a third-order upward direction, and may include oxides such as silicon oxide.

[0131] Reference Figures 22 to 24A fourth through-hole can be formed through the fifth to eighth insulating interlayers 340, 350, 410 and 510, the support layer 300 and the channel connection pattern 550 to expose the upper surface of the CSP 240. A fifth spacer 590 can be formed on the sidewall of the fourth through-hole, and a first upper contact plug 595 can be formed to fill the fourth through-hole.

[0132] The fifth spacer 590 may include an insulating material such as an oxide or nitride, and the first upper contact plug 595 may include a metal, a metal nitride, a metal silicide, or doped polysilicon.

[0133] Reference Figures 25 to 27 A ninth insulating layer 600 can be formed on the eighth insulating layer 510, the first upper contact plug 595, and the fifth spacer 590. Then, fifth through-holes to seventh through-holes 612, 614, and 616 through the seventh to ninth insulating layers 410, 510, and 600 can be formed by an etching process using an etching mask to expose fifth to seventh sacrificial patterns 502, 504, and 506, respectively.

[0134] The third spacer 490 can also be exposed through the fifth through holes to the seventh through holes 612, 614 and 616. The fifth through holes to the seventh through holes 612, 614 and 616 can extend through the sixth insulating interlayer to the ninth insulating interlayer 350, 410, 510 and 600, or extend through the eighth insulating interlayer 510 and the ninth insulating interlayer 600.

[0135] In the example embodiment, due to the characteristics of the etching process, each of the fifth through holes 612, 614 and 616 can have a width that gradually decreases from its top to its bottom.

[0136] The exposed fifth to seventh sacrificial patterns 502, 504 and 506 can be removed by, for example, wet etching, so that the first to third vias 422, 424 and 426 can be re-formed under the fifth to seventh vias 612, 614 and 616 respectively to connect thereto, and the second gap 440 can be re-formed.

[0137] Reference Figure 28 The third spacer 490 can be removed, and portions of the second blocking pattern 560 on the sidewalls of the conductive pads 573, 575, and 577 of the first to third gate electrodes 572, 574, and 576 can also be removed. Therefore, the upper surfaces of the seventh to ninth lower wirings 222, 224, and 226, as well as the sidewalls of the conductive pads 573, 575, and 577 of the first to third gate electrodes 572, 574, and 576, can be exposed.

[0138] In an example embodiment, the portion of the second blocking pattern 560 and the third spacer 490 can be removed by a wet etching process.

[0139] Reference Figures 29 to 32 The first conductive through-hole to the third conductive through-hole 622, 624 and 626 can be formed in the first through-hole to the third through-hole 422, 424 and 426 and the fifth through-hole to the seventh through-hole 612, 614 and 616.

[0140] The first conductive through-hole 622 can fill the first through-hole 422 and the fifth through-hole 612 to contact the upper surface of the seventh lower wiring 222. The second conductive through-hole 624 can fill the second through-hole 424 and the sixth through-hole 614 to contact the upper surface of the eighth lower wiring 224. The third conductive through-hole 626 can fill the third through-hole 426 and the seventh through-hole 616 to contact the upper surface of the ninth lower wiring 226.

[0141] In an example embodiment, the first conductive through-hole 622 may extend through the gate electrodes 572, 574, and 576 (or some of the gate electrodes). The first conductive through-hole 622 may directly contact and electrically connect to one of the conductive pads 573, 575, and 577, which is included in the uppermost gate electrode among the multiple gate electrodes 572, 574, and 576, and may be electrically insulated from the other gate electrodes among the multiple gate electrodes 572, 574, and 576 by the second insulating pattern 460 and the first spacer 455.

[0142] Each of the first conductive through-hole 622 and the third conductive through-hole 626 may extend through the fourth insulating interlayer pattern 253 in the CSP 240 and may be electrically insulated from the CSP 240.

[0143] In an example embodiment, each of the first conductive through-hole to the third conductive through-hole 622, 624 and 626 may include a lower portion having a constant width in a first direction and an upper portion having a width that gradually increases from its bottom to its top in the first direction.

[0144] Reference Figure 33A tenth insulating layer 630 may be formed on the ninth insulating layer 600 and the first conductive through-holes to the third conductive through-holes 622, 624, and 626. A first upper through-hole 644 may be formed extending through the tenth insulating layer 630 to contact the upper surface of the second conductive through-hole 624. A second upper through-hole 648 may be formed extending through the seventh insulating layer to the tenth insulating layers 410, 510, 600, and 630 to contact the upper surface of the first cover pattern 400. A third upper through-hole 649 may be formed through the ninth insulating layer 600 and the tenth insulating layer 630 to contact the upper surface of the first upper contact plug 595.

[0145] An eleventh insulating layer 650 may be formed on the tenth insulating layer 630 and on the first to third upper vias 644, 648 and 649. First to third upper wirings 664, 668 and 669 may be formed through the eleventh insulating layer 650 to contact the upper surfaces of the first to third upper vias 644, 648 and 649, respectively.

[0146] In the example embodiment, the second upper wiring 668 may extend upward in a third direction, and multiple second upper wirings 668 may be formed to be spaced apart from each other in a second direction. Each of the second upper wirings 668 may be electrically connected to the channel 380 via the second upper via 648 and the first cover pattern 400, and may be used as a bit line.

[0147] The tenth insulating interlayer 630 and the eleventh insulating interlayer 650 may include oxides, such as silicon oxide. The first upper vias to the third upper vias 644, 648 and 649 and the first upper wirings to the third upper wirings 664, 668 and 669 may include, for example, metals, metal nitrides, metal silicides, doped polysilicon or other suitable materials.

[0148] As shown above, each of the first conductive through-vias 622 electrically connected to a corresponding gate electrode among gate electrodes 572, 574, and 576 can be formed on the second region II of the substrate 100. Each of the first conductive through-vias 622 can extend through the conductive pad of the corresponding gate electrode among gate electrodes 572, 574, and 576, and can also extend through the other gate electrodes among gate electrodes 572, 574, and 576, but can be electrically insulated from the other gate electrodes among gate electrodes 572, 574, and 576 by the second insulating pattern 460 and the first spacer 455. Therefore, when forming the first conductive through-vias 622, in order to electrically connect only to the corresponding gate electrode among gate electrodes 572, 574, and 576, it is not necessary to prevent breakdown phenomena in which each of the first conductive through-vias 622 extends through the other gate electrodes among gate electrodes 572, 574, and 576 to be electrically connected thereto, thus the formation of the first conductive through-vias 622 can be easier.

[0149] The first conductive through-via 622 can extend not only through the gate electrodes 572, 574, and 576, but also through the upper part of the support layer 300, the channel connection pattern 550, the CSP 240, and the second insulating interlayer 230 to contact the seventh lower wiring 222. Therefore, the first conductive through-via 622 can be formed using the same process used to form the second conductive through-via 624 and the third conductive through-via 626 respectively, which contact the eighth lower wiring 224 and the ninth lower wiring 226 on the third region III and the first region I of the substrate 100, simplifying the overall process. Furthermore, electrical signals can be applied to the first conductive through-via 622 through the seventh lower wiring 222, thus eliminating the need to form an upper wiring for applying electrical signals to the first conductive through-via 622, increasing the layout freedom of the upper wiring.

[0150] Furthermore, before removing the fourth sacrificial pattern 325 to form the fifth gap and the gate electrodes 572, 574, and 576 filling the fifth gap, a first conductive through-hole 622 and a third conductive through-hole 626 can be formed on the first region I and the second region II of the substrate 100. This ensures that the molded part will not fall off even if a dummy channel for supporting the molded part during the formation of the fifth gap is not formed, because the first conductive through-hole 622 and the third conductive through-hole 626 support the molded part. Therefore, in each of the conductive pads 573, 575, and 577, only the first conductive through-hole 622 can be formed without forming a dummy channel. Thus, the first conductive through-hole 622 does not need to have a small size to maintain a distance from the dummy channel, which increases the layout freedom of the first conductive through-hole 622.

[0151] Vertical memory devices manufactured using the above process can have the following structural characteristics.

[0152] A vertical memory device may include: transistors located on first to third regions I, II, and III of a substrate 100; seventh to ninth lower wirings 222, 224, and 226 electrically connected to the transistors; a CSP 240 located on the first region I and second region II of the substrate 100 above the seventh to ninth lower wirings 222, 224, and 226; a channel connection pattern 550 and a support layer 300 sequentially stacked on the CSP 240; gate electrodes 572, 574, and 576, each of which may extend in a second direction, spaced apart from each other in a first direction on the support layer 300 on the first region I and second region II of the substrate 100, and having a stepped shape on the second region II of the substrate 100; and channels 380, each of which may extend on the CSP on the first region I of the substrate 100. A first conductive through-hole 622 extends along a first direction through gate electrodes 572, 574, and 576, support layer 300, and channel connection pattern 550, and is electrically connected to each other through channel connection pattern 550; a first conductive through-hole 622 extends through the gate electrodes in gate electrodes 572, 574, and 576, channel connection pattern 550, support layer 300, and CSP240 to be electrically connected to the seventh lower wiring 222, but is only electrically connected to the uppermost gate electrode among gate electrodes 572, 574, and 576. It is electrically insulated from the other gate electrodes in gate electrodes 572, 574, and 576; the second conductive through-via 624 is located at the same level as the first conductive through-via 622 and does not extend through gate electrodes 572, 574, and 576, and is electrically connected to the eighth lower wiring 224; the third conductive through-via 626 is located at the same level as the first conductive through-via 622 and extends through gate electrodes 572, 574, and 576, the channel connection pattern 550, the support layer 300, and the CSP. 240 is electrically connected to the ninth lower wiring 226 and electrically insulated from gate electrodes 572, 574 and 576; (a plurality of) insulating structures are located between the first conductive through-via 622 and the sidewalls of the other gate electrodes 572, 574 and 576 except for the sidewall of the uppermost gate electrode among gate electrodes 572, 574 and 576, and between the third conductive through-via 626 and the sidewalls of gate electrodes 572, 574 and 576; and bit lines 668, each of which may extend in a third direction on the channel 380 to be electrically connected to the channel 380, and spaced apart from each other in a second direction.

[0153] In an example embodiment, the first conductive through-via to the third conductive through-via 622, 624, and 626 may have the same shape, size, and height. That is, each of the first conductive through-via to the third conductive through-via 622, 624, and 626 may include a vertical portion extending in a first direction and a ramp portion having a width that gradually increases from its bottom to its top in the vertical portion. The vertical portion of each of the first conductive through-via to the third conductive through-via 622, 624, and 626 may have sidewalls substantially perpendicular to the upper surface of the substrate 100, and the ramp portion of each of the first conductive through-via to the third conductive through-via 622, 624, and 626 may have sidewalls inclined relative to the upper surface of the substrate 100. However, due to the characteristics of the etching process, even the sidewalls of the vertical portions may be inclined (e.g., slightly inclined), although the slope of the sidewalls of the vertical portions may be greater than the slope of the sidewalls of the ramp portions.

[0154] For example, besides such as Figure 31 and Figure 32 In addition to the vertical portion 622a and the ramp portion 622c shown, the first conductive through-hole 622 may also include a protrusion 622b that projects horizontally from the vertical portion 622a. In an example embodiment, the protrusion 622b of the first conductive through-hole 622 may contact and be electrically connected to a conductive pad 575 of the uppermost gate electrode through which the first conductive through-hole 622 extends, the conductive pad 575 being formed at its end in the second direction to have a thickness greater than the thickness of the other portions of the uppermost gate electrode through which the first conductive through-hole 622 extends.

[0155] In such Figure 32 In the example embodiment shown, the insulating structures may include a second insulating pattern 460 and a first spacer 455 covering the lower and upper surfaces of the second insulating pattern 460. In the example embodiment, a third distance D3 from the sidewall of the vertical portion 622a of the first conductive through-hole 622 to the sidewall of the conductive pad 575 of the uppermost gate electrode among gate electrodes 572, 574, and 576 facing the protrusion 622b of the first conductive through-hole 622 may be equal to or less than a fourth distance D4 from the sidewall of the vertical portion 622a of the first conductive through-hole 622 to the sidewall of the other gate electrodes under the uppermost gate electrode among gate electrodes 572, 574, and 576. In the example embodiment, the insulating structures may also be formed between the sidewall of the first conductive through-hole 622 and the channel connection pattern 550 to electrically insulate each other.

[0156] In such Figure 32 In the example embodiment shown, the second blocking pattern 560 may cover the lower and upper surfaces and a portion of the sidewalls of each of the gate electrodes 572, 574, and 576, and may not be formed on the sidewall of the protrusion 622b of the conductive pad of the uppermost gate electrode of the gate electrodes 572, 574, and 576 facing the first conductive through-hole 622. That is, the second blocking pattern 560 may be formed on the sidewalls of the sidewalls of the insulating structures on the vertical portions 622a of the other gate electrodes of the gate electrodes 572, 574, and 576 facing the first conductive through-hole 622.

[0157] In such Figure 33 In the example embodiment shown, the fourth insulating interlayer pattern 253 may be formed between each of the first conductive through-hole 622 and the third conductive through-hole 626 and the CSP 240, and may be electrically insulated from each other.

[0158] In an example embodiment, a first upper wiring 664 may be formed on a second conductive through-via 624 to be electrically connected to the second conductive through-via 624; however, upper wiring may be formed on each of the first conductive through-via 622 and the third conductive through-via 626 and electrically connected to each of the first conductive through-via 622 and the third conductive through-via 626.

[0159] Figures 34 to 36 These are plan views and cross-sectional views illustrating a vertical memory device according to an example embodiment. Specifically, Figure 34 It's a floor plan. Figure 35 It is along Figure 34 The region X in the sectional view intercepted by line A-A' (refer to) Figure 30 Enlarged sectional view of ) Figure 36 It is along Figure 34 A cross-sectional view taken along line D-D'. Aside from some components, this vertical memory device can be used with... Figures 29 to 33 The vertical memory devices are substantially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated descriptions are omitted below.

[0160] Reference Figures 34 to 36 The vertical memory device may include a second pillar structure extending through a portion of a fifth insulating interlayer 340, a first insulating pattern 315, gate electrodes 572, 574, and 576, a support layer 300, and a channel connection pattern 550 to contact a portion of a CSP 240 on a second region II of the substrate 100. Additionally, a second cover pattern 403 is included, extending through a portion of the fifth insulating interlayer 340 and a sixth insulating interlayer 350 on the second pillar structure.

[0161] The second pillar structure may include dummy charge storage structures 375, dummy channels 385, and first dummy filling patterns 395 sequentially stacked corresponding to the charge storage structure 370, channel 380, and first filling pattern 390 of the first pillar structure. The dummy charge storage structure 375 may include dummy tunnel insulating patterns, dummy charge storage patterns, and first dummy blocking patterns sequentially stacked in the horizontal direction from the outer sidewall of the dummy channel 385. The dummy tunnel insulating pattern may include oxides such as silicon oxide, the dummy charge storage pattern may include nitrides such as silicon nitride, and the first dummy blocking pattern may include oxides such as silicon oxide.

[0162] In an example embodiment, the second pillar structure may be formed at the boundary region between the upper and lower steps of the molded part. That is, the second pillar structure may contact the end of a corresponding conductive pad or multiple conductive pads 573, 575, and 577 of one or more gate electrodes 572, 574, and 576 in the second direction, and may extend through the other conductive pads of the gate electrodes 572, 574, and 576. In an example embodiment, the plurality of second pillar structures may be spaced apart from each other, with a corresponding first conductive through-hole 622 of the first conductive through-hole 622 located at the center therebetween, and as... Figure 34 As shown, the second pillar structures are arranged at the four vertices, and a corresponding first conductive through-hole 622 is located at the center. However, the inventive concept is not limited to the arrangement of the second pillar structures at the four vertices as described.

[0163] The second column structure, including the dummy channel 385, can be formed using the same process as the first column structure, including the channel 380. Therefore, when the reference is executed... Figure 19 and Figure 20 When the process shown (i.e., the process for forming the fifth gap by removing the fourth sacrificial pattern 325) is employed, the second pillar structure, together with the fifth sacrificial pattern 502 and the seventh sacrificial pattern 506, can prevent the molded part from falling off. However, since the fifth sacrificial pattern 502 and the seventh sacrificial pattern 506 have already been formed, a minimum number of second pillar structures, including the dummy channel 385, can be formed to increase the layout freedom of the first conductive through-hole 622.

[0164] Figure 37 This is a cross-sectional view illustrating a vertical memory device according to an example embodiment. Except for some components, this vertical memory device can be... Figures 29 to 33 The vertical memory devices are substantially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated descriptions are omitted below.

[0165] Reference Figure 37For example, some of the fourth sacrificial patterns 325, including nitrides such as silicon nitride, are not replaced by gate electrodes 572, 574, and 576, but remain on the first region I of the substrate 100. Furthermore, the third conductive through-hole 626 may extend through the fourth sacrificial pattern 325 instead of the gate electrodes 572, 574, and 576. Therefore, the fourth sacrificial pattern 325 may be positioned between the sidewall of the third conductive through-hole 626 and the sidewall of each of the gate electrodes 572, 574, and 576.

[0166] The first spacer 455 can cover not only the lower and upper surfaces of the second insulating pattern 460, but also the sidewall of the second insulating pattern 460 facing the fourth sacrificial pattern 325.

[0167] In reference Figure 19 and Figure 20 During the illustrated process (i.e., the process for removing the fourth sacrificial pattern 325 through the second opening 520), a portion of the fourth sacrificial pattern 325 in the central region between adjacent second openings 520 in the third direction may not be removed but retained, and a portion may be formed in the central region. Figure 37 The third conductive through-hole 626 is shown.

[0168] Figures 38 to 40 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment. The method may include... Figures 1 to 33 The processes are basically the same or similar, so their repeated descriptions are omitted below.

[0169] Reference Figure 38 It can execute with Figures 1 to 3 The processes are basically the same or similar.

[0170] However, CSP 240 can be formed on the entire portion of the first region I and the second region II of the substrate 100, and the fourth insulating interlayer pattern 253 is not formed.

[0171] Reference Figure 39 It can execute with Figures 4 to 11 The processes are basically the same or similar.

[0172] However, each of the first through holes to the third through holes 422, 424 and 426 can expose the upper surface of the CSP 240 through a first etching process, and the exposed portion of the CSP 240 can be removed through a second etching process to expose the upper surface of the second insulating interlayer 230, such that the sidewalls of the CSP 240 can be exposed by each of the first through holes to the third through holes 422, 424 and 426.

[0173] The exposed sidewalls of the first through-holes 422, 424 and 426 can be oxidized to form a third insulating pattern 245 comprising silicon oxide. A fourth insulating pattern 305 can be formed on each of the exposed sidewalls of the support layer 300 of the first through-holes 422, 424 and 426.

[0174] Reference Figure 40 The first through-hole to the third through-hole 422, 424 and 426 can be enlarged downwards to expose the upper surfaces of the seventh to the ninth lower wirings 222, 224 and 226 respectively, and can perform operations with... Figures 12 to 33 The processes are basically the same or similar to those used to manufacture vertical memory devices.

[0175] Therefore, each of the first to third conductive through-vias 622, 624, and 626 can be electrically insulated from the CSP 240 by a third insulating pattern 245 formed by oxidizing the sidewalls of the CSP 240, rather than by a fourth insulating interlayer pattern 253 formed by patterning the CSP 240. When the support layer 300 comprises, for example, polysilicon doped with n-type impurities, the support layer 300 can also be electrically insulated from each of the first to third conductive through-vias 622, 624, and 626 by a fourth insulating pattern 305.

[0176] As described above, although the inventive concept has been described with reference to exemplary embodiments, it should be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A vertical memory device, the vertical memory device comprising: Gate electrodes are spaced apart from each other on a substrate along a first direction perpendicular to the upper surface of the substrate, and the gate electrodes are stacked in a stepped shape. The channel extends through the gate electrode in a first direction; A first conductive through-hole extends through the conductive pad of the first gate electrode in the gate electrode and is electrically connected to the conductive pad. The first conductive through-hole extends through the second gate electrode disposed under the first gate electrode in the gate electrode. as well as An insulating structure is located between the sidewalls of the first conductive through-via and each of the second gate electrodes facing the first conductive through-via, the insulating structure electrically insulating the first conductive through-via from each of the second gate electrodes. Each of the insulating structures includes: an insulating pattern; and a spacer covering the lower and upper surfaces of the insulating pattern. Wherein, the distance between the sidewalls of each of the first conductive through-hole and the second gate electrode facing the first conductive through-hole in a second direction parallel to the upper surface of the substrate is greater than the width of the spacer in the second direction.

2. The vertical memory device according to claim 1, wherein, The first conductive through-hole includes: The vertical portion extends along the first direction; and The protruding part protrudes from the vertical part in the second direction, and The protruding portion contacts the sidewall of the conductive pad of the first gate electrode.

3. The vertical memory device according to claim 2, wherein, The first conductive through-hole also includes a ramp portion located on the vertical portion, the ramp portion having a width that gradually increases from the bottom of the ramp portion toward the top of the ramp portion.

4. The vertical memory device according to claim 2, wherein, The distance from the sidewall of the vertical portion of the first conductive through-hole to the sidewall of the conductive pad of the first gate electrode facing the protruding portion of the first conductive through-hole is equal to or less than the distance from the sidewall of the vertical portion of the first conductive through-hole to the sidewall of each of the second gate electrodes facing the first conductive through-hole.

5. The vertical memory device according to claim 1, wherein, The insulating pattern comprises oxides, and the spacers comprise nitrides.

6. The vertical memory device of claim 1, further comprising a blocking pattern covering the lower and upper surfaces of each of the gate electrodes. in, The blocking pattern is not formed on the sidewall of the conductive pad of the first gate electrode facing the first conductive through-via, but is formed on the sidewall of each of the second gate electrodes facing the first conductive through-via.

7. The vertical memory device according to claim 1, wherein, Each of the gate electrodes extends in the second direction, and The conductive pads are formed at the ends of each of the gate electrodes in the second direction and have a thickness in the first direction that is greater than the thickness of the other portions of each of the gate electrodes.

8. The vertical memory device according to claim 1, further comprising: Below is the circuit pattern; An insulating interlayer is located on the substrate, covering the circuit pattern underneath; as well as The common source plate is located on the insulating interlayer. The gate electrode is formed on the common source plate.

9. The vertical memory device according to claim 8, wherein, The first conductive through-hole extends through the upper part of the common source plate and the insulating interlayer, and is electrically connected to the lower circuit pattern.

10. The vertical memory device of claim 9, further comprising an insulating pattern located between the first conductive through-via and the common source plate, the insulating pattern electrically insulating the first conductive through-via from the common source plate and comprising an oxide.

11. The vertical memory device of claim 8, further comprising a second conductive through-via at the same level as the first conductive through-via, the second conductive through-via not extending through the common source plate and the gate electrode, and the second conductive through-via extending through the upper portion of the insulating interlayer to be electrically connected to the lower circuit pattern.

12. The vertical memory device of claim 11, further comprising a third conductive through-via at the same level as the first conductive through-via, the third conductive through-via extending through the upper portion of the gate electrode, the common source plate and the insulating interlayer to be electrically connected to the lower circuit pattern.

13. The vertical memory device according to claim 12, wherein, A second insulating structure is formed between the sidewall of the third conductive through-via and the sidewall of each of the gate electrodes facing the third conductive through-via, the second insulating structure electrically insulating the third conductive through-via from each of the gate electrodes.

14. The vertical memory device of claim 12, further comprising silicon nitride located between the sidewall of the third conductive through-via and the sidewall of each of the gate electrodes facing the third conductive through-via.

15. The vertical memory device of claim 12, further comprising an upper wiring located on and electrically connected to the second conductive through-via. in, No additional top wiring is formed on each of the first conductive through-via and the third conductive through-via, and the top wiring is configured to apply an electrical signal to each of the first conductive through-via and the third conductive through-via.

16. A vertical memory device, the vertical memory device comprising: The gate electrode is spaced apart from each other in a first region and a second region of the substrate along a first direction. The substrate includes a first region, a second region and a third region. The first direction is perpendicular to the upper surface of the substrate, and the gate electrode has a stepped shape in the second region of the substrate. A channel extends through a gate electrode in a first direction over a first region of the substrate; A first conductive through-via extends through some of the gate electrodes in a second region of the substrate. The first conductive through-via is electrically connected to the uppermost horizontal first gate electrode among the gate electrodes and is electrically insulated from a second gate electrode disposed below the first gate electrode among the gate electrodes via an insulating structure. The second conductive through-hole is at the same level as the first conductive through-hole in the third region of the substrate; as well as A third conductive through-via is located at the same level as the first conductive through-via in a first region of the substrate. The third conductive through-via extends through the gate electrode and is electrically insulated from the gate electrode via an insulating structure. The first conductive through-hole to the third conductive through-hole have the same width. Each of the first to third conductive through-holes includes a vertical portion and a ramp portion, the vertical portion extending along a first direction, and the ramp portion having a width that gradually increases from the bottom of the ramp portion toward the top of the ramp portion. The insulating structure is located between the sidewalls of the first conductive through-via and each of the second gate electrodes facing the first conductive through-via, and between the sidewalls of the third conductive through-via and each of the gate electrodes facing the third conductive through-via. Each of the insulating structures includes: an insulating pattern; and a spacer covering the lower and upper surfaces of the insulating pattern. Wherein, the distance between the sidewalls of each of the first conductive through-hole and the second gate electrode facing the first conductive through-hole in a second direction parallel to the upper surface of the substrate is greater than the width of the spacer in the second direction.

17. The vertical memory device of claim 16, further comprising an upper wiring located on the second conductive through-via, the upper wiring being electrically connected to the second conductive through-via. in, No additional top wiring is formed on each of the first conductive through-via and the third conductive through-via, and the top wiring is configured to apply an electrical signal to each of the first conductive through-via and the third conductive through-via.

18. The vertical memory device of claim 16, further comprising: Below is the circuit pattern; An insulating interlayer is located on the substrate, covering the circuit pattern underneath; as well as The common source plate is located on the insulating interlayer. The gate electrode is formed on the common source plate.

19. A vertical memory device, the vertical memory device comprising: Transistors are located on a substrate; The bottom wiring is located on the substrate and is electrically connected to the transistor. The common source plate is located on the lower wiring. The channel connecting pattern and the support layer are sequentially stacked on the common source plate; Gate electrodes are spaced apart from each other on a substrate along a first direction perpendicular to the upper surface of the substrate, and the gate electrodes are stacked in a stepped shape on the substrate. The channels are electrically connected to each other via a channel connection pattern, each of which extends along a first direction on the common source plate through the gate electrode, the support layer and the channel connection pattern. A first conductive through-via extends on the substrate through some of the gate electrodes, the first conductive through-via is electrically connected to the uppermost horizontal first gate electrode among the gate electrodes, and the first conductive through-via is electrically insulated from a second gate electrode among the gate electrodes disposed below the first gate electrode. The second conductive through-via is at the same level as the first conductive through-via, the second conductive through-via does not extend through the gate electrode, and the second conductive through-via is electrically connected to one of the lower wirings; The third conductive through-via is at the same level as the first conductive through-via. The third conductive through-via extends through the gate electrode, the channel connection pattern, the support layer and the common source plate and is electrically connected to another line in the lower wiring. as well as An insulating structure is located between the sidewalls of each of the first conductive through-vias and the second gate electrodes facing the first conductive through-vias to electrically insulate the first conductive through-vias from each of the second gate electrodes, and is located between the sidewalls of each of the third conductive through-vias and the third conductive through-vias facing the third conductive through-vias to electrically insulate the third conductive through-vias from each of the gate electrodes. Each of the insulating structures includes: an insulating pattern; and a spacer covering the lower and upper surfaces of the insulating pattern. Wherein, the distance between the sidewalls of each of the first conductive through-hole and the second gate electrode facing the first conductive through-hole in a second direction parallel to the upper surface of the substrate is greater than the width of the spacer in the second direction.

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