Chip testing method and device

Abstract

The present application provides a chip testing method and device, which are applied to a test server, the test server is externally connected to a network device, and the network device includes an NP chip. The method is: obtain a configuration file; initialize the NP chip according to the configuration file; load the firmware to the NP chip after the initialization is completed; after the firmware is loaded, establish a communication connection with the PCIE server; obtain a test case suite from the PCIE server, and load the obtained test case suite on the NP chip, the test case suite includes multiple test cases; send a message injection instruction to the network tester, so that the network tester sends the test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite; monitor and process the NP chip, and if it is detected that an exception occurs when the NP chip processes the test message based on the test case suite, the exception details of the message processing are written into the log file.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip testing method and device. Background Art

[0002] When testing a network processor (NP) chip, it generally involves the configuration combination of multiple modules, such as Figure 1 As shown, the platform device where the NP chip is located, the network tester, the PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) server and the serial port enable device, the test process generally includes environment preparation, device startup, serial port enable and configuration delivery, etc. The platform device where the NP chip is located runs the script to prepare the test environment, device occupancy and load the specified firmware version, and then inputs the command through the remote serial port to wait for the configuration to be delivered; then the configuration of the test case is obtained through the PCIE server connected to the NP chip, and the forwarding platform (Data Platform, DP) program is run after the NP chip configuration is completed, and the specified message is configured through the network tester to input the chip port, so as to realize the NP chip based on the test case to look up the table and forward the input message, thereby realizing the test of the NP chip.

[0003] However, when the prior art tests NP chips, the test process varies with the network device (platform device) where the NP chip is located, and the test process is not universal; moreover, the test results depend on the analysis of the network tester, and only return whether the message forwarding table lookup is successful after the test is completed. When the forwarding table lookup is unsuccessful, it is impossible to determine whether it is caused by a problem in a certain step or module itself, which is not conducive to tracking and locating the problem when the test fails. In addition, the existing network tester can only realize the stress test of the traffic of a single test case by continuously injecting messages, but cannot perform stress loading test verification for all test cases.

[0004] Therefore, how to provide a test flow that can implement sequential testing and verification of multiple test cases is one of the technical issues worth considering. Summary of the invention

[0005] In view of this, the present application provides a chip testing method and device to implement sequential testing and verification of multiple test cases.

[0006] Specifically, the present application is implemented through the following technical solutions:

[0007] According to a first aspect of the present application, a chip testing method is provided for use in a testing server, wherein the testing server is externally connected to a network device, and the network device includes a network processor NP chip; the method includes:

[0008] Get the configuration file;

[0009] Initializing the NP chip according to the configuration file;

[0010] After the initialization is completed, the firmware is loaded into the NP chip;

[0011] After the firmware is loaded, establish a communication connection with the PCIE server;

[0012] Acquire a test case suite from the PCIE server, and load the acquired test case suite on the NP chip, wherein the test case suite includes a plurality of test cases;

[0013] Sending a message injection instruction to a network tester, so that the network tester sends a test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite;

[0014] The NP chip is monitored and processed. If it is monitored that an exception occurs when the NP chip processes the test message based on the test case suite, the exception details of the message processing are written into a log file.

[0015] According to a second aspect of the present application, a chip testing device is provided, which is applied to a testing server, wherein the testing server is externally connected to a network device, and the network device includes a network processor NP chip; the device includes:

[0016] A first acquisition module, used to acquire a configuration file;

[0017] An initialization module, used to initialize the NP chip according to the configuration file;

[0018] A first loading module, used for loading firmware into the NP chip after initialization is completed;

[0019] A connection establishment module is used to establish a communication connection with the PCIE server after the firmware is loaded;

[0020] A second acquisition module is used to acquire a test case suite from the PCIE server;

[0021] A second loading module, configured to load the acquired test case suite onto the NP chip, wherein the test case suite includes a plurality of test cases;

[0022] A first sending module, configured to send a message injection instruction to a network tester, so that the network tester sends a test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite;

[0023] A monitoring module, used for monitoring the NP chip;

[0024] The exception handling module is used to write the exception details of the message processing into a log file if the monitoring module detects that an exception occurs when the NP chip processes the test message based on the test case suite.

[0025] According to the third aspect of the present application, an electronic device is provided, including a processor and a machine-readable storage medium, the machine-readable storage medium storing a computer program that can be executed by the processor, and the processor is prompted by the computer program to execute the method provided in the first aspect of the embodiment of the present application.

[0026] According to the fourth aspect of the present application, a machine-readable storage medium is provided, which stores a computer program. When called and executed by a processor, the computer program prompts the processor to execute the method provided in the first aspect of the embodiment of the present application.

[0027] Beneficial effects of the embodiments of the present application:

[0028] By obtaining and loading the test case suite, not only can multiple test cases be run in sequence, but the processing stability of the NP chip can also be tested. In addition, when an exception is detected in the NP chip test, by writing the exception details into a log file, it is convenient for R&D personnel to locate the location of the exception in a timely manner based on the log file, thereby realizing the tracking and location of the exception when the test occurs, thereby solving the problem in the prior art that the step where the exception occurs cannot be located. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of chip testing provided by the prior art;

[0030] Figure 2 is a flow chart of a chip testing method provided in an embodiment of the present application;

[0031] Figure 3 This is an application scenario architecture diagram of the chip testing method provided in the embodiment of the present application;

[0032] Figure 4 is a block diagram of a chip testing device provided in an embodiment of the present application;

[0033] Figure 5 It is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0035] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more corresponding listed items.

[0036] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0037] The chip testing method provided in this application is described in detail below.

[0038] See also Figure 2 , Figure 2 This is a flowchart of a chip testing method provided by the present application. The method can be applied to a test server. The test server is connected to an external network device. The network device includes a network processor NP chip. Figure 3 As shown, when the test server executes the above chip testing method, the following steps may be included:

[0039] S201. Obtain a configuration file.

[0040] In this step, the test server pre-stores a configuration file required for testing the NP. When the test server needs to test the NP chip, the configuration file can be obtained locally from the test server.

[0041] S202: Initialize the NP chip according to the configuration file.

[0042] In this step, after obtaining the configuration file, the test server can initialize the NP chip in the network device connected to it based on the configuration file. The initialization configuration of the NP chip includes test environment preparation and chip enablement, etc. By initializing the NP chip, a test environment can be provided for the test of the NP chip.

[0043] Optionally, the configuration file in this embodiment includes the device identification and variable parameters of the network device where the NP chip is located; step S202 can be implemented according to the following process: based on the variable parameters, the NP chip is initialized using the chip test script corresponding to the device identification.

[0044] Specifically, in practical applications, NP chips can be applied to different network devices, such as router devices, business simulation platforms (EMUs), and field programmable gate array (FPGA) platforms, etc. When NP chips are applied to different network devices, the chip test scripts and initialization parameters used are also different. Therefore, in order to achieve the versatility of the test process, the present application adds a device identifier and variable parameters to the configuration file, so that after obtaining the configuration file, the device identifier of the network device where the NP chip currently to be tested is located can be parsed from the configuration file, and the variable parameters required for the initialization of the NP chip can then be called. The chip test script corresponding to the parsed device identifier can then be used as the input parameter of the chip test script, and then the chip test script initializes the NP chip. Thus, the portability of NP chip testing is achieved.

[0045] It should be noted that there is at least one variable parameter in the configuration file, and generally there are multiple. The variable parameters are the parameters required for the NP chip to be initialized. For example, when the network device where the NP chip is located is a high-end router device, the variable parameters may include but are not limited to: the actual slot number of the device line card, the terminal number corresponding to the master serial port number, the master serial port number, the master IP, the port number of the device connection, etc. When the network device where the NP chip is located is an EMU platform and an FPGA platform, its variable parameters may include but are not limited to: pal server name, pal server password, PCIE management port IP, PCIE management port username, PCIE management port password, remote IP of the device corresponding to the serial port, etc.

[0046] Optionally, the chip testing method provided in this embodiment further includes: if an exception occurs when the NP chip is initialized, writing the exception details of the initialization exception into the log file.

[0047] Specifically, when the NP chip is initialized, there may be an initialization exception. In order to facilitate the location of the exception when the abnormal situation occurs, the present embodiment proposes to integrate the initialization monitoring function in the chip test script. When the chip test script executes the initialization process, the execution state of the initialization can be monitored. If an abnormality is detected during the initialization process, the abnormal details of the initialization abnormality are written into the log file. Optionally, the test process can be terminated by interruption to indicate that the test cannot be performed, and the above-mentioned abnormal details are written into a pre-established log file by redirection. That is, the address information of the log file will be obtained in advance, and then redirected to the log file corresponding to the address information, and then the abnormal details are written into the log file. In this way, the R&D personnel can locate the location where the abnormality occurs as soon as possible based on the log file, and realize the tracking and location of the abnormality when the test occurs abnormally, thereby solving the problem that the steps of the abnormality cannot be located in the prior art.

[0048] S203: Loading firmware to the NP chip after initialization is completed.

[0049] In this step, when the NP chip is initialized, the firmware can be loaded into the NP chip. Specifically, the firmware version of the firmware to be loaded will be obtained, and then the corresponding firmware will be loaded based on the firmware version. The firmware version is the version number of the released firmware, which includes updates to the application part and the baseband part. The so-called firmware refers to the program written into the EROM or EPROM (programmable read-only memory), which is commonly understood as "cured software." To put it more simply, firmware is the program code that is cured inside the integrated circuit, which is responsible for controlling and coordinating the functions of the integrated circuit. Therefore,

[0050] Optionally, after the firmware is loaded, a management port reset instruction is sent to the PCIE server, so that the PCIE server performs a reset operation on the PCIE management port therein after receiving the reset instruction.

[0051] S204: After the firmware is loaded, a communication connection with the PCIE server is established.

[0052] In this step, when the firmware is loaded, the test case can be obtained to complete the test of the NP chip, and the test case is in the PCIE server, so it is necessary to establish a communication connection between the test server and the PCIE server directly connected to the NP chip. Specifically, the PCIE server directly connected to the NP chip can be logged in through the Secure Shell Protocol (SSH), and when the login is successful, it indicates that the communication connection between the test server and the PCIE server is established. Specifically, an agent is set on the PCIE server. After logging in to the PCIE server through SSH, the interactive command can be entered through the expect tool to enable the agent in the PCIE server, thereby establishing a connection channel with the PCIE server, providing a bridge for obtaining test cases.

[0053] Optionally, the chip testing method provided in this embodiment further includes: if an exception occurs when establishing a communication connection with the PCIE server, writing the exception details of establishing the connection into the log file.

[0054] Specifically, when establishing a connection with a PCIE server, the connection establishment may fail due to some factors. In order to monitor whether the above-mentioned process of establishing a connection is successful, the present application adds a monitoring function of the communication connection establishment process in the chip test script, and then when trying to establish a communication connection with the PCIE server, the above-mentioned monitoring function is started to monitor whether the communication connection between the PCIE server can be successfully established. When the establishment is successful, the subsequent test process is executed; when the communication connection fails to be established, it indicates that the current test process cannot proceed, and the abnormal details of the connection establishment are written into the above-mentioned log file, and the abnormal details of the abnormal connection establishment can be written at the position corresponding to the current pointer of the log file. Specifically, when the communication connection establishment fails, the test process can be terminated by interruption, and then the abnormal details of the connection establishment are written into the above-mentioned log file by redirection. Thus, the R&D personnel can locate the location where the abnormality occurs as soon as possible based on the log file, and realize the tracking and positioning of the abnormality when the test occurs abnormally, thereby solving the problem that the steps of the abnormality cannot be located in the prior art.

[0055] S205: Acquire a test case suite from the PCIE server, and load the acquired test case suite onto the NP chip, wherein the test case suite includes a plurality of test cases.

[0056] In this step, after establishing a communication connection with the PCIE server, a test case suite can be obtained from the PCIE server based on the communication connection. Specifically, in order to achieve the purpose of testing the NP chip based on multiple test cases, the present application proposes to configure multiple test cases on the PCIE server and integrate them into a test case suite, and then obtain the test case suite from the PCIE server and load the obtained test case suite into the NP chip for use in subsequent testing of the NP chip. In this way, the sequential running of multiple test cases is achieved, thereby solving the problem of low test efficiency caused by only being able to run one test case alone in the prior art. In addition, by running the test case suite, the present application can not only test the forwarding performance of the NP chip when the message pressure is injected into the NP chip, but also test the stability of the NP chip itself.

[0057] S206: Send a message injection instruction to the network tester, so that the network tester sends the test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite.

[0058] Specifically, after the currently acquired test case suite is successfully loaded into the NP chip, the test server can send a message injection instruction to the network tester. After the network tester receives the message injection instruction, it can send the test message to the NP chip. After receiving the test message, the NP chip can perform corresponding processing actions based on the test case in the test case suite. If the test case in the test case suite is a forwarding table entry, after the NP chip receives the test message, it can parse the IP address from the test message, and then search in the forwarding table entry based on the IP address to find the outbound port and next hop information of the test message. If the search is successful, the test message can be forwarded based on the found information.

[0059] S207: Monitor the NP chip. If it is detected that an exception occurs when the NP chip processes the test message based on the test case suite, write the exception details of the message processing into a log file.

[0060] In this step, in order to monitor whether there is an abnormality when the NP chip is tested based on the test case suite, the present application proposes to add a monitoring function for the NP chip in the chip test script. In this way, if it is monitored that the processing of the test message by the NP chip is consistent with the processing of the test case in the test case suite, it indicates that there is no abnormality in the NP chip test, and the subsequent operation can be performed on the message according to the next test case. If it is monitored that the NP chip is interrupted when processing the message based on the current test case, it indicates that the NP chip processing is abnormal, and the abnormal details of the message processing can be written into the above-mentioned log file. Specifically, taking the performance query as an example, when the NP chip finds the egress port and destination information of the test message by searching the forwarding performance, and then forwards the test message according to the egress port and destination information, the status of the egress port can be monitored based on this. If the test message is forwarded successfully according to the egress port, it indicates that the NP chip can forward the message, that is, there is no abnormality in the forwarding message of the NP chip, and the forwarding function test of the NP chip is successful. If the NP chip fails to complete the forwarding operation of the test message, it indicates that an exception occurs during the test of the NP chip. The test process can be terminated by interruption, and then the exception details when the message processing exception occurs are written into the above-mentioned log file by redirection. Specifically, when writing the log file, the exception details when the message processing exception occurs are written starting from the position pointed to by the current pointer of the log file. In this way, the R&D personnel can locate the location where the exception occurs as soon as possible based on the log file, and realize the tracking and positioning of the exception when the test exception occurs, thereby solving the problem that the step where the exception occurs cannot be located in the prior art.

[0061] Optionally, the PCIE server in this embodiment may include multiple test case suites; the chip testing method provided in this embodiment also includes: when it is monitored that no abnormality occurs when the NP chip processes the test message based on the current test case suite, continuing to execute the step of obtaining the test case suite from the PCIE server.

[0062] Specifically, a plurality of test case suites may be configured in the PCIE server, and when the test case suites are loaded to the NP chip, they are loaded one by one. Therefore, when it is detected that the NP chip processes the test message based on the current test case suite without exception, the test server may obtain the next test case suite from the PCIE server, that is, continue to execute the step of obtaining the test case suite from the PCIE server, and then execute steps S206 to S207 again for the next test case suite obtained. In this way, by looping and nesting the test case suites, the stability of the NP chip message processing can be tested.

[0063] Optionally, based on any of the above embodiments, the chip testing method provided in this embodiment further includes: sending a serial port enable instruction to the NP chip to enable the serial port of the NP chip; if an exception occurs when the serial port is enabled, the exception details of the serial port enablement are written into the log file.

[0064] Specifically, the test server can connect to the serial port of the chip through telnet, so as to enable the serial port to work. In this way, the relevant functions of the serial port can be tested, such as the function of issuing commands through the serial port, or the function of waiting for table items and other configurations to be issued; and if an exception occurs during the serial port enabling process, the exception details of the serial port enabling can be written into the above-mentioned log file. Specifically, when an exception occurs during the serial port enabling process, the test can be terminated by interruption, and then the exception details of the serial port enabling can be written into the above-mentioned log file by redirection. Specifically, the above-mentioned exception details can be written starting from the current pointer of the log file. In this way, the R&D personnel can locate the location where the exception occurs as soon as possible based on the log file, and realize the tracking and positioning of the exception when the test occurs, thereby solving the problem that the steps where the exception occurs cannot be located in the prior art.

[0065] In the chip testing method provided in the present application, by obtaining and loading a test case suite, not only the sequential (continuous) running of multiple test cases is realized, but also the processing stability of the NP chip is tested; in addition, when an abnormality is detected in the NP chip test, by writing the abnormality details into a log file, it is convenient for R&D personnel to locate the location where the abnormality occurs in a timely manner based on the log file, thereby realizing the tracking and location of the abnormality when the test occurs, thereby solving the problem in the prior art that the step where the abnormality occurs cannot be located.

[0066] Based on the same inventive concept, the present application also provides a chip testing device corresponding to the above chip testing method. The implementation of the chip testing device can refer to the above description of the chip testing method, which will not be discussed here one by one.

[0067] See also Figure 4 , Figure 4 A chip detection device provided by an exemplary embodiment of the present application is applied to a test server, wherein the test server is externally connected to a network device, and the network device includes a network processor NP chip; the device includes:

[0068] A first acquisition module 401 is used to acquire a configuration file;

[0069] Initialization module 402, used to initialize the NP chip according to the configuration file;

[0070] A first loading module 403, used to load firmware into the NP chip after initialization is completed;

[0071] A connection establishing module 404 is used to establish a communication connection with a PCIE server after the firmware is loaded;

[0072] A second acquisition module 405 is used to acquire a test case suite from the PCIE server;

[0073] A second loading module 406, configured to load the acquired test case suite onto the NP chip, wherein the test case suite includes a plurality of test cases;

[0074] A first sending module 407 is used to send a message injection instruction to the network tester, so that the network tester sends the test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite;

[0075] A monitoring module 408, used for monitoring the NP chip;

[0076] The exception handling module 409 is configured to write the exception details of the message processing into a log file if the monitoring module 408 detects that an exception occurs when the NP chip processes the test message based on the test case suite.

[0077] Optionally, the configuration file in this embodiment includes the device identification and variable parameters of the network device where the NP chip is located;

[0078] The initialization module 402 is specifically configured to initialize the NP chip based on the variable parameters and using the chip test script corresponding to the device identifier.

[0079] Optionally, the exception handling module 409 is further configured to write the exception details of the initialization exception into the log file if an exception occurs when the NP chip is initialized.

[0080] Optionally, the exception handling module 409 is further configured to write the exception details of establishing the connection into the log file if an exception occurs when establishing the communication connection with the PCIE server.

[0081] Optionally, the chip testing device provided in this embodiment further includes:

[0082] A second sending module (not shown in the figure), used for sending a serial port enabling instruction to the NP chip to enable the serial port of the NP chip;

[0083] The exception handling module 409 is also used to write the exception details of the serial port enabling into the log file if an exception occurs when the serial port is enabled.

[0084] Optionally, the PCIE server provided in this embodiment includes multiple test case suites;

[0085] The monitoring module 408 is further configured to trigger the second acquisition module 405 to continue to execute the step of acquiring the test case suite from the PCIE server when it is detected that the NP chip processes the test message based on the current test case suite without any abnormality.

[0086] In the chip testing device provided in the present application, by acquiring and loading a test case suite, not only the sequential running of multiple test cases is realized, but also the processing stability of the NP chip is tested; in addition, when an abnormality is detected in the NP chip test, by writing the abnormality details into a log file, it is convenient for R&D personnel to locate the location where the abnormality occurs in a timely manner based on the log file, thereby realizing the tracking and location of the abnormality when the test occurs, thereby solving the problem in the prior art that the step where the abnormality occurs cannot be located.

[0087] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which can be the above-mentioned test server, such as Figure 5 As shown, the electronic device includes a processor 501 and a machine-readable storage medium 502, the machine-readable storage medium 502 stores a computer program that can be executed by the processor 501, and the processor 501 is prompted by the computer program to execute the chip testing method provided in any embodiment of the present application.

[0088] The computer-readable storage medium may include a RAM (Random Access Memory), a DDR SRAM (Double Data Rate Synchronous Dynamic Random Access Memory), or a NVM (Non-volatile Memory), such as at least one disk storage. Optionally, the computer-readable storage medium may also be at least one storage device located away from the processor.

[0089] The above-mentioned processor can be a general-purpose processor, including a CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0090] In addition, an embodiment of the present application provides a machine-readable storage medium, which stores a computer program. When called and executed by a processor, the computer program prompts the processor to execute the chip testing method provided by any embodiment of the present application.

[0091] As for the electronic device and machine-readable storage medium embodiments, since the method contents involved are basically similar to the aforementioned method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0092] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0093] The implementation process of the functions and effects of each unit / module in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0094] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can refer to the partial description of the method embodiments. The device embodiments described above are merely schematic, wherein the units / modules described as separate components may or may not be physically separated, and the components displayed as units / modules may or may not be physical units / modules, that is, they may be located in one place, or they may be distributed on multiple network units / modules. Some or all of the units / modules may be selected according to actual needs to achieve the purpose of the present application. A person of ordinary skill in the art can understand and implement it without creative work.

[0095] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip testing method, characterized in that: Applied in a test server, the test server is externally connected to a network device, and the network device includes a network processor NP chip; the method includes: Obtain a configuration file, where the configuration file is a file required for testing the NP chip; Initializing the NP chip according to the configuration file; After initialization is completed, the firmware is loaded into the NP chip; After the firmware is loaded, establish a communication connection with the PCIE server; Acquire a test case suite from the PCIE server, and load the acquired test case suite on the NP chip, wherein the test case suite includes a plurality of test cases; Sending a message injection instruction to a network tester, so that the network tester sends a test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite; The NP chip is monitored and processed. If it is monitored that an exception occurs when the NP chip processes the test message based on the test case suite, the exception details of the message processing are written into a log file.

2. The method according to claim 1, characterized in that The configuration file includes the device identification and variable parameters of the network device where the NP chip is located; Initializing the NP chip according to the configuration file includes: Based on the variable parameters, the NP chip is initialized using a chip test script corresponding to the device identifier.

3. The method according to claim 1, characterized in that Also includes: If an exception occurs when the NP chip is initialized, the exception details of the initialization exception are written into the log file.

4. The method according to claim 1, characterized in that: If an exception occurs when establishing a communication connection with the PCIE server, the exception details of establishing the connection are written into the log file.

5. The method according to claim 1, characterized in that Also includes: Sending a serial port enable instruction to the NP chip to enable the serial port of the NP chip; If an exception occurs when the serial port is enabled, the exception details of the serial port enabling are written into the log file.

6. The method according to claim 1, characterized in that The PCIE server includes a plurality of test case suites; The method further comprises: When it is monitored that the NP chip processes the test message based on the current test case suite without any abnormality, the step of obtaining the test case suite from the PCIE server is continued.

7. A chip testing device, characterized in that: Applied in a test server, the test server is externally connected to a network device, the network device includes a network processor NP chip; the device includes: A first acquisition module is used to acquire a configuration file, where the configuration file is a file required for testing the NP chip; An initialization module, used to initialize the NP chip according to the configuration file; A first loading module, used for loading firmware into the NP chip after initialization is completed; A connection establishment module is used to establish a communication connection with the PCIE server after the firmware is loaded; A second acquisition module is used to acquire a test case suite from the PCIE server; A second loading module, configured to load the acquired test case suite onto the NP chip, wherein the test case suite includes a plurality of test cases; A first sending module, configured to send a message injection instruction to a network tester, so that the network tester sends a test message to the NP chip, and the NP chip processes the test message accordingly based on the test case suite; A monitoring module, used for monitoring the NP chip; The exception handling module is used to write the exception details of the message processing into a log file if the monitoring module detects that an exception occurs when the NP chip processes the test message based on the test case suite.

8. The device according to claim 7, characterized in that The configuration file includes the device identification and variable parameters of the network device where the NP chip is located; The initialization module is specifically used to initialize the NP chip based on the variable parameters and using the chip test script corresponding to the device identifier.

9. The device according to claim 7, characterized in that The exception handling module is further configured to write the exception details of the initialization exception into the log file if an exception occurs when the NP chip is initialized.

10. The device according to claim 7, characterized in that The exception handling module is further configured to write the exception details of establishing the connection into the log file if an exception occurs when establishing the communication connection with the PCIE server.

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