A method for forming a NAND flash memory and a NAND flash memory

Abstract

The present invention discloses a method for forming a NAND flash memory, comprising providing a semiconductor substrate, the semiconductor substrate having a floating gate oxide material layer and a floating gate material layer located on the floating gate oxide material layer; forming a groove penetrating the floating gate material layer, the floating gate oxide material layer and a part of the semiconductor substrate, and forming the floating gate material layer into a floating gate layer, and forming the floating gate oxide material layer into a floating gate oxide layer; forming a protective layer on the inner wall of the groove, the protective layer covering the semiconductor substrate and the floating gate film and exposing the floating gate oxide film; transversely etching part of the floating gate oxide film to expose the bottom corner of the floating gate film facing the groove and the top corner of the semiconductor substrate facing the groove; after transversely etching part of the floating gate oxide film, rounding the bottom corner of the exposed floating gate film and the top corner of the exposed semiconductor substrate to improve the performance of the NAND flash memory. The present invention also provides a NAND flash memory with better performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a NAND flash memory and a NAND flash memory. Background Art

[0002] As the size of NAND flash memory devices becomes smaller and smaller, the isolation layer of the active area of ​​many devices or flash memories has been manufactured using a shallow trench isolation (STI) process.

[0003] In the STI process, it is usually necessary to first form trenches on the substrate to separate components, then fill the trenches with dielectric materials using chemical vapor deposition (CVD), and after sidewall oxidation and dielectric material filling, perform planarization using chemical mechanical polishing (CMP).

[0004] For example, the formation process of NAND (NAND flash memory device) in the prior art is as follows Figures 1 to 4 Specifically, Figure 1 As shown, a semiconductor substrate 1 is first provided, and a floating gate oxide material layer 20 and a floating gate material layer 30 are sequentially formed on the semiconductor substrate 1, and a mask material layer 50 is formed on the floating gate material layer 30; then, as shown in FIG. Figure 2 As shown, the mask material layer 50 and the floating gate material layer 30 are etched and stopped at the floating gate oxide material layer 20; then the floating gate oxide material layer 20 and the semiconductor substrate 1 are further etched to form a Figure 3 The trench 7 shown in FIG. 1 forms a mask layer 51, a floating gate film 31 and a floating gate oxide film 21 at the same time; finally, Figure 4 As shown, an isolation structure 6 is formed in the trench 7 formed by etching and CMP is performed to finally form a NAND flash memory. The finally formed NAND flash memory includes a semiconductor substrate 1, a floating gate layer 32 located on the semiconductor substrate, and a floating gate oxide layer 22 located between the semiconductor substrate 1 and the floating gate layer 32.

[0005] However, the existing NAND flash memory has the following problems in its internal structure: Figure 3 and Figure 4 The sharp angle Z shown may result in poor performance of NAND flash memory. Summary of the invention

[0006] The purpose of the present invention is to solve the problem of poor performance of NAND flash memory in the prior art due to the sharp corners of the bottom edge of the floating gate layer facing the groove and the top edge of the semiconductor substrate facing the groove. The present invention provides a method for forming a NAND flash memory and a NAND flash memory, which can improve the performance of the NAND flash memory.

[0007] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a NAND flash memory, comprising:

[0008] Providing a semiconductor substrate, wherein the semiconductor substrate has a floating gate oxide material layer and a floating gate material layer located on the floating gate oxide material layer;

[0009] Forming a groove penetrating the floating gate material layer, the floating gate oxide material layer and a portion of the semiconductor substrate, and forming the floating gate material layer into a floating gate film, and forming the floating gate oxide material layer into a floating gate oxide film;

[0010] forming a protective layer on the inner wall of the trench, wherein the protective layer covers the semiconductor substrate and the floating gate layer and exposes the floating gate oxide film;

[0011] Laterally etching a portion of the floating gate oxide film to expose a bottom corner of the floating gate film toward the trench and a top corner of the semiconductor substrate toward the trench;

[0012] After a portion of the floating gate oxide film is laterally etched, the exposed bottom corners of the floating gate film and the exposed top corners of the semiconductor substrate are rounded.

[0013] Preferably, in the rounding process, part of the material at the bottom corner of the floating gate film and part of the material at the top corner of the semiconductor substrate are removed.

[0014] Preferably, the rounding process comprises an isotropic etching process.

[0015] Preferably, the rounding treatment includes a wet etching process, and the etching solution used in the wet etching process is a hydrofluoric acid solution.

[0016] Preferably, after the rounding treatment, the bottom corners of the floating gate film facing the trench are rounded, and the top corners of the semiconductor substrate facing the trench are rounded.

[0017] Preferably, the etching amount of the floating gate oxide film in the laterally etched portion is 30 angstroms to 50 angstroms.

[0018] Preferably, after the smoothing process is performed, the method further comprises:

[0019] removing the protective layer;

[0020] After removing the protection layer, an isolation structure is formed in the trench.

[0021] Preferably, the method for forming the protection layer comprises: performing nitridation treatment on the material of the floating gate film on the inner wall of the trench and the material of the semiconductor substrate.

[0022] Preferably, before forming the floating gate film and the floating gate oxide film, a mask material layer is provided on the surface of the floating gate material layer; during the process of forming the groove, the groove penetrates the mask material layer and causes the mask material layer to form a mask layer.

[0023] Preferably, the material of the protective layer includes silicon nitride.

[0024] Preferably, the thickness of the protective layer is 20 angstroms to 50 angstroms.

[0025] Preferably, before forming the groove, the semiconductor substrate includes a first well region and a second well region located on the first well region and adjacent to the first well region, and the conductivity type of the first well region is opposite to the conductivity type of the second well region; after forming the groove, the groove penetrates the second well region and extends into part of the first well region.

[0026] Preferably, it also includes: after forming the isolation structure, forming a control gate structure across the floating gate film and the isolation structure on the semiconductor substrate; etching and removing the floating gate film and the floating gate oxide film on the side of the control gate structure, so that the floating gate film forms a floating gate layer, and the floating gate oxide film forms a floating gate oxide layer.

[0027] An embodiment of the present invention further provides a NAND flash memory, comprising:

[0028] Semiconductor substrate;

[0029] a floating gate film located on the semiconductor substrate;

[0030] A floating gate oxide film located between the semiconductor substrate and the floating gate film;

[0031] A trench located in a portion of the semiconductor substrate, wherein the trench extends between adjacent floating gate oxide films and between adjacent floating gate films, and the floating gate oxide film is recessed relative to the sidewall of the floating gate film toward the sidewall of the trench;

[0032] The floating gate film has a rounded bottom corner toward the trench, and the semiconductor substrate has a rounded top corner toward the trench.

[0033] Preferably, a bottom corner of the floating gate film facing the trench is rounded, and a top corner of the semiconductor substrate facing the trench is rounded.

[0034] Preferably, a dimension of the floating gate oxide film recessed toward the sidewall of the trench relative to the sidewall of the floating gate film is 30 angstroms to 50 angstroms.

[0035] Preferably, the semiconductor substrate includes a first well region and a second well region located on and adjacent to the first well region, the conductivity type of the first well region and the conductivity type of the second well region are opposite; the trench penetrates the second well region and extends into part of the first well region.

[0036] An embodiment of the present invention also provides another NAND flash memory, including:

[0037] Semiconductor substrate;

[0038] A floating gate layer located on the semiconductor substrate;

[0039] A floating gate oxide layer located between the semiconductor substrate and the floating gate layer;

[0040] An isolation structure located in a portion of the semiconductor substrate, wherein the isolation structure extends between adjacent floating gate oxide layers and between adjacent floating gate layers, and the floating gate oxide layer is recessed relative to the sidewall of the floating gate layer toward the sidewall of the isolation structure;

[0041] The bottom corners of the floating gate layer facing the isolation structure are rounded, and the top corners of the semiconductor substrate facing the isolation structure are rounded.

[0042] Preferably, the method further comprises: a control gate structure spanning the floating gate layer and the isolation structure.

[0043] Preferably, the method further comprises: a bottom corner of the floating gate layer facing the isolation structure is rounded, and a top corner of the semiconductor substrate facing the isolation structure is rounded.

[0044] In the method for forming a NAND flash memory provided by the technical solution of the present invention, after a portion of the floating gate oxide film is laterally etched, the bottom corners of the exposed floating gate film and the top corners of the semiconductor substrate are rounded, so that the bottom corners of the floating gate film toward the groove are finally rounded (that is, the floating gate layer of the finally formed NAND flash memory is rounded toward the bottom corners of the groove), and the top corners of the semiconductor substrate toward the groove are rounded, so that the NAND is not prone to tip discharge, and the accuracy is higher when writing data, thereby improving the working performance of the NAND flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figures 1 to 4 It is a structural schematic diagram of a method for forming a NAND flash memory in the prior art;

[0046] Figure 5is a flow chart of a method for forming a NAND flash memory provided by an embodiment of the present invention;

[0047] Figures 6 to 12 It is a structural schematic diagram of a method for forming a NAND flash memory provided by an embodiment of the present invention.

[0048] Reference numerals:

[0049] 1. Semiconductor substrate; 20. Floating gate oxide material layer; 21. Floating gate oxide film; 22. Floating gate oxide layer; 30. Floating gate material layer; 31. Floating gate film; 32. Floating gate layer; 4. Protective layer; 50. Mask material layer; 51. Mask layer; 6: Isolation structure; 7. Trench; A. Second well region; B. First well region; Z. Sharp corner. DETAILED DESCRIPTION

[0050] The following specific embodiments illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this implementation. On the contrary, the purpose of introducing the invention in conjunction with the implementation is to cover other options or modifications that may extend based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0051] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0052] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0053] The terms “first”, “second”, etc. are only used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0054] In the description of this embodiment, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this embodiment can be understood according to specific circumstances.

[0055] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0056] As described in the background technology, the existing NAND flash memory device has poor performance. For example, the formation process of NAND (NAND flash memory device) in the prior art is as follows: Figures 1 to 4 Specifically, Figure 1 As shown, a semiconductor substrate 1 is first provided, and a floating gate oxide material layer 20 and a floating gate material layer 30 are sequentially formed on the semiconductor substrate 1, and a mask material layer 50 is formed on the floating gate material layer 30; then, as shown in FIG. Figure 2 As shown, the mask material layer 50 and the floating gate material layer 30 are etched and stopped at the floating gate oxide material layer 20; then the floating gate oxide material layer 20 and the semiconductor substrate 1 are further etched to form a Figure 3 The trench 7 shown in FIG. 1 forms a mask layer 51, a floating gate film 31 and a floating gate oxide film 21 at the same time; finally, Figure 4 As shown, an isolation structure 6 is formed in the trench 7 formed by etching and CMP is performed to finally form a NAND flash memory. The finally formed NAND flash memory includes a semiconductor substrate 1, a floating gate layer 32 located on the semiconductor substrate, and a floating gate oxide layer 22 located between the semiconductor substrate 1 and the floating gate layer 32.

[0057] However, when writing to a NAND flash memory device, usually only part of the floating gate layer 32 is written, and the remaining floating gate layer 32 is in a floating state. The floating gate layer 32 in the floating state has a higher voltage, while the floating gate layer 32 where data is written has a lower voltage. Figure 1-Figure 4 As shown, in the current processing, the bottom corner of the floating gate layer 32 facing the groove 7 and the top corner of the semiconductor substrate 1 facing the groove 7 are sharp corners, which will cause the tip discharge phenomenon, that is, the electrons on the side of the floating gate layer 32 in the suspended state will be transferred to the side of the floating gate layer 32 where data is written, which will reduce the voltage of the floating gate layer 32 in the suspended state. As a result, the voltage of the floating gate layer 32 where data is written is close to that of the floating gate layer 32 in the suspended state, and it is easy to cause erroneous operation when writing data, which will reduce the performance of the NAND flash memory device.

[0058] In order to solve the problem of poor performance of NAND flash memory in the prior art due to the sharp corners of the bottom edge of the floating gate layer facing the groove and the top edge of the semiconductor substrate facing the groove, the present invention provides a method for forming a NAND flash memory. Specifically, as Figures 5 to 10 shown.

[0059] refer to Figure 5 The flowchart of the method for forming a NAND flash memory provided by the embodiment of the present invention is shown. The method for forming a NAND flash memory provided by the embodiment of the present invention specifically includes the following steps:

[0060] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate has a floating gate oxide material layer and a floating gate material layer located on the floating gate oxide material layer;

[0061] Step S2: forming a trench penetrating the floating gate material layer, the floating gate oxide material layer and a portion of the semiconductor substrate, and forming the floating gate material layer into a floating gate film, and forming the floating gate oxide material layer into a floating gate oxide film;

[0062] Step S3: forming a protective layer on the inner wall of the trench, the protective layer covering the semiconductor substrate and the floating gate film and exposing the floating gate oxide film;

[0063] Step S4: laterally etching a portion of the floating gate oxide film to expose the bottom corner of the floating gate film toward the trench and the top corner of the semiconductor substrate toward the trench;

[0064] Step S5: after etching part of the floating gate oxide film laterally, rounding the bottom corners of the exposed floating gate film and the top corners of the exposed semiconductor substrate.

[0065] In the NAND flash memory formed by the above method, the floating gate film has rounded corners toward the bottom of the trench, and the semiconductor substrate has rounded corners toward the top of the trench, so that the NAND is not prone to leakage, the durability of the NAND is enhanced, and the working performance of the NAND is improved.

[0066] The method for forming corners of a NAND flash memory device provided by the present invention is described in detail below with reference to the accompanying drawings.

[0067] Figures 6 to 10 It is a schematic diagram of the structure of a NAND flash memory at each stage corresponding to the method for forming a NAND flash memory provided by an embodiment of the present invention.

[0068] refer to Figure 6 First, a semiconductor substrate 1 is provided, on which a floating gate oxide material layer 20 and a floating gate material layer 30 located on the floating gate oxide material layer 20 are provided.

[0069] Specifically, the material of the semiconductor substrate 1 is silicon, germanium or silicon germanium. The material of the semiconductor substrate 1 can also be other semiconductor materials, which will not be listed one by one here.

[0070] The material of the floating gate oxide material layer 20 may be silicon oxide; the material of the floating gate material layer 30 may be polysilicon, etc., which are common materials in the prior art and are not listed one by one here.

[0071] It should be noted that, before the floating gate film 31 and the floating gate oxide film 21 are formed, a mask material layer 50 is present on the surface of the floating gate material layer 30 .

[0072] refer to Figure 7 , forming a groove 7 penetrating the floating gate material layer 30, the floating gate oxide material layer 20 and a portion of the semiconductor substrate 1, and forming the floating gate material layer 30 into a floating gate film 31, and forming the floating gate oxide material layer 20 into a floating gate oxide film 21.

[0073] In this embodiment, the method for forming the groove 7 is etching, and specifically, it can be dry etching.

[0074] It should be noted that before forming the floating gate film 31 and the floating gate oxide film 21 , a mask material layer 50 is provided on the surface of the floating gate material layer 30 ; during the process of forming the groove 7 , the groove 7 penetrates the mask material layer 50 and forms the mask material layer 50 into a mask layer 51 .

[0075] like Figures 6 to 12 The mask layer 51 includes an intermediate layer in contact with the floating gate film 31, a hard mask layer on the intermediate layer, and a mask oxide layer on the hard mask layer.

[0076] Of course, this embodiment only schematically lists these three layers of materials as the mask layer 51 , and those skilled in the art may select different mask material layers 50 as the mask layer according to actual needs.

[0077] It should also be noted that before forming the groove 7, the semiconductor substrate 1 includes a first well region and a second well region located on the first well region and adjacent to the first well region, and the conductivity type of the first well region is opposite to the conductivity type of the second well region; after forming the groove 7, the groove 7 passes through the second well region and extends into part of the first well region.

[0078] For details, see Fig.12 , the first well region is Fig.12 The first well region B in the second well region is Fig.12 The second well region A in.

[0079] That is to say, the semiconductor substrate 1 has two regions with opposite electrical properties, namely the first well region B and the second well region A. The second well region A is closer to the floating gate oxide material layer 20, and the first well region B is farther from the floating gate oxide material layer 20, and the two well regions are adjacent. The trench 7 completely penetrates the second well region A, and a part of it is in the first well region B.

[0080] Then refer to Figure 8 A protection layer 4 is formed on the inner wall of the trench 7 , and the protection layer 4 covers the semiconductor substrate 1 and the floating gate film 31 and exposes the floating gate oxide film 21 .

[0081] Specifically, in this embodiment, the method for forming the protection layer 4 includes: performing nitridation treatment on the material of the floating gate film 31 on the inner wall of the trench and the material of the semiconductor substrate 1 .

[0082] That is, the material of the protective layer 4 formed initially covers the semiconductor substrate 1 and the floating gate film 31 , and the width of the floating gate oxide film 21 in the horizontal direction is equal to the total width of the protective layer 4 and the floating gate film 31 in the horizontal direction.

[0083] Furthermore, in this embodiment, the material of the protective layer 4 includes silicon nitride, and the thickness of the protective layer 4 is 20 angstroms to 50 angstroms.

[0084] Of course, this embodiment only schematically lists the materials and thicknesses of the protective layer 4 , and those skilled in the art may select other appropriate materials and thicknesses according to actual conditions.

[0085] Next, refer to Fig. 9 , a portion of the floating gate oxide film 21 is laterally etched to expose the bottom corner of the floating gate film 31 toward the trench 7 and to expose the top corner of the semiconductor substrate 1 toward the trench 7 .

[0086] Specifically, in this embodiment, the etching amount of the part of the floating gate oxide film 21 that is laterally etched is 30 angstroms to 50 angstroms.

[0087] Then refer to Fig.10 After a portion of the floating gate oxide film 21 is laterally etched, the bottom corners of the exposed floating gate film and the top corners of the exposed semiconductor substrate are rounded.

[0088] Specifically, in the rounding process, part of the material at the bottom corner of the floating gate film 31 and part of the material at the top corner of the semiconductor substrate 1 are removed.

[0089] In this embodiment, the rounding process includes an isotropic etching process, and of course it can also be other processes, which are not specifically limited in this embodiment. In addition, the rounding process includes a wet etching process, and the etching solution used in the wet etching process is a hydrofluoric acid solution.

[0090] Furthermore, in this embodiment, the hydrofluoric acid solution for wet etching may be an aqueous solution of hydrofluoric acid (DHF) or a buffered oxide etchant (BOE), which is not specifically limited in this embodiment.

[0091] In this embodiment, reference Fig.10 and Fig.11 After the rounding treatment, the bottom corners of the floating gate film 31 facing the trench 7 are rounded, and the top corners of the semiconductor substrate 1 facing the trench 7 are rounded.

[0092] refer to Fig.12 , after smooth processing, also includes:

[0093] Remove the protective layer 4 (refer to Fig.11 ).

[0094] After the protection layer 4 is removed, an isolation structure 6 is formed in the trench 7 .

[0095] It should be noted that after the isolation structure 6 is formed, a control gate structure spanning the floating gate film 31 and the isolation structure 6 is formed on the semiconductor substrate 1; the floating gate film 31 and the floating gate oxide film 21 on the side of the control gate structure are etched away, so that the floating gate film 31 forms a floating gate layer 32, and the floating gate oxide film 21 forms a floating gate oxide layer 22.

[0096] By adopting the above scheme, after a portion of the floating gate oxide film is laterally etched, the bottom corners of the exposed floating gate film and the top corners of the semiconductor substrate are rounded, so that the bottom corners of the floating gate film toward the groove are rounded (that is, the floating gate layer of the NAND flash memory finally formed is rounded toward the bottom corners of the groove), and the top corners of the semiconductor substrate toward the groove are rounded. In this way, the NAND is not prone to tip discharge, and the accuracy is higher when writing data, thereby improving the working performance of the NAND flash memory device.

[0097] Based on the above-mentioned method for forming a NAND flash memory, this embodiment further provides a NAND flash memory, including:

[0098] Semiconductor substrate;

[0099] A floating gate film located on a semiconductor substrate;

[0100] A floating gate oxide film located between the semiconductor substrate and the floating gate film;

[0101] A trench is located in a portion of the semiconductor substrate, wherein the trench extends between adjacent floating gate oxide films and between adjacent floating gate films, and the floating gate oxide film is recessed relative to the sidewall of the floating gate film toward the sidewall of the trench;

[0102] The floating gate film has a rounded bottom corner toward the trench, and the semiconductor substrate has a rounded top corner toward the trench.

[0103] It should be noted that the materials of the semiconductor substrate, floating gate film, and floating gate oxide film in this embodiment are the same as those in the above-mentioned method for forming the NAND flash memory, and will not be described in detail here.

[0104] Furthermore, in the NAND flash memory provided in this embodiment, the bottom corners of the floating gate film facing the trench are rounded, and the top corners of the semiconductor substrate facing the trench are rounded.

[0105] Furthermore, the sidewall of the floating gate oxide film toward the trench is recessed by 30 angstroms to 50 angstroms relative to the sidewall of the floating gate film.

[0106] Furthermore, the semiconductor substrate includes a first well region and a second well region located on and adjacent to the first well region, the conductivity type of the first well region is opposite to that of the second well region; the trench penetrates the second well region and extends into part of the first well region.

[0107] By adopting the above scheme, after a portion of the floating gate oxide film is laterally etched, the bottom corners of the exposed floating gate film and the top corners of the semiconductor substrate are rounded, so that the bottom corners of the floating gate film toward the groove are rounded (that is, the floating gate layer of the NAND flash memory finally formed is rounded toward the bottom corners of the groove), and the top corners of the semiconductor substrate toward the groove are rounded. In this way, the NAND is not prone to tip discharge, and the accuracy is higher when writing data, thereby improving the working performance of the NAND flash memory device.

[0108] This embodiment also provides another NAND flash memory, including:

[0109] Semiconductor substrate;

[0110] A floating gate layer located on a semiconductor substrate;

[0111] A floating gate oxide layer located between the semiconductor substrate and the floating gate layer;

[0112] An isolation structure is located in a portion of the semiconductor substrate, and the isolation structure extends between adjacent floating gate oxide layers and between adjacent floating gate layers, and the floating gate oxide layer is recessed relative to the sidewall of the floating gate layer toward the sidewall of the isolation structure;

[0113] The bottom corner of the floating gate layer toward the isolation structure is rounded, and the top corner of the semiconductor substrate toward the isolation structure is rounded.

[0114] Furthermore, the other NAND flash memory also includes: a control gate structure spanning the floating gate layer and the isolation structure.

[0115] Furthermore, the bottom corners of the floating gate layer of the other NAND flash memory facing the isolation structure are rounded, and the top corners of the semiconductor substrate facing the isolation structure are rounded.

[0116] By adopting the above scheme, after a portion of the floating gate oxide film is laterally etched, the bottom corners of the exposed floating gate film and the top corners of the semiconductor substrate are rounded, so that the bottom corners of the floating gate film toward the isolation structure are rounded (that is, the bottom corners of the floating gate layer of the NAND flash memory finally formed are rounded toward the isolation structure), and the top corners of the semiconductor substrate toward the isolation structure are rounded. In this way, the NAND is not prone to tip discharge, and the accuracy is higher when writing data, thereby improving the working performance of the NAND flash memory device.

[0117] Although the present invention has been illustrated and described with reference to certain preferred embodiments of the present invention, it should be understood by those skilled in the art that the above is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art may make various changes in form and details, including making several simple deductions or substitutions, without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a NAND flash memory, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has a floating gate oxide material layer and a floating gate material layer located on the floating gate oxide material layer; Forming a trench penetrating the floating gate material layer, the floating gate oxide material layer and a portion of the semiconductor substrate, and forming the floating gate material layer into a floating gate film, and forming the floating gate oxide material layer into a floating gate oxide film; forming a protective layer on the inner wall of the trench, wherein the protective layer covers the semiconductor substrate and the floating gate film and exposes the floating gate oxide film; Laterally etching a portion of the floating gate oxide film to expose a bottom corner of the floating gate film toward the trench and a top corner of the semiconductor substrate toward the trench; After laterally etching part of the floating gate oxide film, the exposed bottom corners of the floating gate film and the exposed top corners of the semiconductor substrate are rounded, during which part of the material at the bottom corners of the floating gate film and part of the material at the top corners of the semiconductor substrate are removed.

2. The method for forming a NAND flash memory according to claim 1, wherein: The rounding process includes an isotropic etching process.

3. The method for forming a NAND flash memory according to claim 1, wherein: The rounding treatment includes a wet etching process, and the etching solution used in the wet etching process is a hydrofluoric acid solution.

4. The method for forming a NAND flash memory according to claim 1, wherein: After the rounding treatment, the bottom corner of the floating gate film facing the trench is rounded, and the top corner of the semiconductor substrate facing the trench is rounded.

5. The method for forming a NAND flash memory according to claim 1, wherein: The etching amount of the floating gate oxide film in the lateral etching part is 30 angstroms to 50 angstroms.

6. The method for forming a NAND flash memory according to claim 1, wherein: After the smoothing process is performed, the method further includes: removing the protective layer; After removing the protection layer, an isolation structure is formed in the trench.

7. The method for forming a NAND flash memory according to claim 1, wherein: The method for forming the protection layer includes: performing nitridation treatment on the material of the floating gate film on the inner wall of the trench and the material of the semiconductor substrate.

8. The method for forming a NAND flash memory according to claim 1, wherein: Before forming the floating gate film and the floating gate oxide film, a mask material layer is provided on the surface of the floating gate material layer; during the process of forming the trench, the trench penetrates the mask material layer and the mask material layer forms a mask layer.

9. The method for forming a NAND flash memory according to claim 1, wherein: The material of the protection layer includes silicon nitride.

10. The method for forming a NAND flash memory according to claim 1, wherein: The thickness of the protective layer is 20 angstroms to 50 angstroms.

11. The method for forming a NAND flash memory according to claim 1, wherein: Before forming the groove, the semiconductor substrate includes a first well region and a second well region located on the first well region and adjacent to the first well region, and the conductivity type of the first well region is opposite to the conductivity type of the second well region; after forming the groove, the groove penetrates the second well region and extends into part of the first well region.

12. The method for forming a NAND flash memory according to claim 6, wherein: Also includes: After forming the isolation structure, forming a control gate structure spanning the floating gate film and the isolation structure on the semiconductor substrate; The floating gate film and the floating gate oxide film on the side of the control gate structure are removed by etching, so that the floating gate film forms a floating gate layer, and the floating gate oxide film forms a floating gate oxide layer.

13. A NAND flash memory, characterized in that: The NAND flash memory is formed according to the method for forming a NAND flash memory according to any one of claims 1 to 12 and comprises: Semiconductor substrate; a floating gate film located on the semiconductor substrate; A floating gate oxide film located between the semiconductor substrate and the floating gate film; A trench located in a portion of the semiconductor substrate, wherein the trench extends between adjacent floating gate oxide films and between adjacent floating gate films, and the floating gate oxide film is recessed relative to the sidewall of the floating gate film toward the sidewall of the trench; The floating gate film has a rounded bottom corner toward the trench, and the semiconductor substrate has a rounded top corner toward the trench.

14. The NAND flash memory according to claim 13, wherein: The bottom corner of the floating gate film facing the trench is rounded, and the top corner of the semiconductor substrate facing the trench is rounded.

15. The NAND flash memory according to claim 13, wherein: The floating gate oxide film is recessed by 30 angstroms to 50 angstroms toward the sidewall of the trench relative to the sidewall of the floating gate film.

16. The NAND flash memory according to claim 13, characterized in that: The semiconductor substrate includes a first well region and a second well region located on and adjacent to the first well region, wherein the conductivity type of the first well region is opposite to that of the second well region; the trench penetrates the second well region and extends into a portion of the first well region.

17. A NAND flash memory, characterized in that: The NAND flash memory is formed according to the method for forming a NAND flash memory according to any one of claims 1 to 12 and comprises: Semiconductor substrate; a floating gate layer located on the semiconductor substrate; A floating gate oxide layer located between the semiconductor substrate and the floating gate layer; An isolation structure located in a portion of the semiconductor substrate, wherein the isolation structure extends between adjacent floating gate oxide layers and between adjacent floating gate layers, and the floating gate oxide layer is recessed relative to the sidewall of the floating gate layer toward the sidewall of the isolation structure; The bottom corners of the floating gate layer facing the isolation structure are rounded, and the top corners of the semiconductor substrate facing the isolation structure are rounded.

18. The NAND flash memory according to claim 17, wherein: Also includes: A control gate structure spans the floating gate layer and the isolation structure.

19. The NAND flash memory according to claim 17, wherein: The bottom corner of the floating gate layer facing the isolation structure is rounded, and the top corner of the semiconductor substrate facing the isolation structure is rounded.

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