Structure and control method for realizing uninterrupted optical output of EDFA

Abstract

The present invention discloses a structure and a control method for realizing uninterrupted optical output of an EDFA. By appropriately adjusting the PUMP drive and control structure, it is realized that when the FPGA needs to be updated, the TEC driver or chip located outside the (main) FPGA maintains the drive control of the PUMP chip. When updating the main drive or standby drive FPGA, the present invention has no impact on the existing services, which not only maintains the original scalability and expandability, but also increases the maintainability and upgradability. In particular, by adopting a dual-FPGA structure and using a fast parallel FPGA programming scheme, the upgrade time can be reduced to the order of 20 ms.

Description

Technical Field

[0001] The present invention relates to the technical field of EDFA control, and particularly to a structure and a control method for realizing uninterrupted optical output of an EDFA. Background Art

[0002] In an EDFA control system, maintaining stable output of an optical driving pump is a very critical index whether during system operation or maintenance. As Figure 1 shown, at present, the vast majority of EDFA control systems adopt the method of directly driving a pump (PUMP) by an FPGA, and this method has good scalability and expandability. However, in the traditional direct driving structure of an EDFA pump, when the FPGA is upgraded, since the FPGA cannot maintain the output, the output optical signal is interrupted, affecting the service. Summary of the Invention

[0003] The purpose of the present invention is to provide a structure and a control method for realizing uninterrupted optical output of an EDFA. The specific NTA hardware upgrade control structure of the present invention can be divided into two categories: a single-FPGA structure and a dual-FPGA structure, and a suitable structure can be selected according to application requirements.

[0004] The technical solution adopted by the present invention is as follows:

[0005] A single-FPGA structure for realizing uninterrupted optical output of an EDFA, which includes an FPGA, a DAC (digital-to-analog conversion) circuit, an external TEC driver, and a PUMP chip. A PUMP driver and a TEC controller are integrated in the FPGA. The output end of the PUMP driver is connected to the input end of the DAC circuit, the output end of the DAC circuit is connected to the PUMP integrated on the PUMP chip, the output end of the TEC controller is connected to the external TEC driver, and the output end of the external TEC driver is connected to the TEC integrated on the PUMP chip.

[0006] A single-FPGA control method for realizing uninterrupted optical output of an EDFA, which includes the following steps:

[0007] Step 1: Pause the PUMP driver, and at this time, keep the original driving value unchanged;

[0008] Step 2: Stop updating the external TEC controller. Since then, the external TEC takes over the TEC control;

[0009] Step 3: Save the FPGA scene to a non-volatile memory, such as an external FLASH device. The content includes the current control value and driving value of the PUMP, the TEC control value, and other values that need to be maintained, such as the VOA setting;

[0010] Step 4: Start FPGA reconfiguration. During this process, since the PIN of the FPGA remains weakly pulled up, the PUMP drive is not updated;

[0011] Step 5: Restore the scene;

[0012] Step 6: Restore TEC control;

[0013] Step 7: Start updating the PUMP drive value.

[0014] Furthermore, the non-volatile memory in Step 3 is an external FLASH device, and the FPGA scene content includes the PUMP current control value, PUMP drive value, TEC control value, and VOA setting.

[0015] A dual-FPGA structure for realizing uninterrupted EDFA optical output, which includes a main drive FPGA, a standby drive FPGA, a DAC circuit, an external TEC driver, and a PUMP chip. Both the main drive FPGA and the standby drive FPGA integrate a PUMP driver, a TEC controller, and a TEC driver, and the TEC controller and the TEC driver are internally interconnected. The output ends of the PUMP drivers of the main drive FPGA and the standby drive FPGA are respectively connected to the input ends of the DAC circuit, the output end of the DAC circuit is connected to the PUMP integrated on the PUMP chip, the output ends of the TEC drivers of the main drive FPGA and the standby drive FPGA are respectively connected to the TEC integrated on the PUMP chip, the standby drive FPGA integrates an FPP driver, and the standby drive FPGA is connected to the main drive through the FPP driver and performs fast FPGA reconstruction on the FPGA.

[0016] A dual-FPGA control method for realizing uninterrupted EDFA optical output, which includes the following steps:

[0017] Step 1: Pause the main PUMP driver;

[0018] Step 2: Stop the main TEC controller, output in tri-state, start the standby TEC controller, and maintain the PUMP temperature;

[0019] Step 3: Copy the main PUMP drive status value to the standby PUMP driver and start the standby PUMP driver;

[0020] Step 4: Save the scene to any storage device, such as an external SDRAM or the internal RAM of the standby FPGA;

[0021] Step 5: Start FPP configuration and reconstruct the main drive FPGA;

[0022] Step 6: Restore the main drive scene;

[0023] Step 6: Restore the main drive TEC control;

[0024] Step 7: Start the main drive FPGA and start updating the PUMP drive value.

[0025] Further, in step 4, the storage device includes an external SDRAM or a RAM inside the standby drive FPGA.

[0026] The present invention adopts the above technical solutions, makes appropriate adjustments to the PUMP drive and control structure, and realizes that when the FPGA needs to be updated, the TEC driver or chip located outside the (main) FPGA maintains the drive control of the PUMP chip. When the main drive or standby drive FPGA is updated, the present invention has no impact on the existing services, which not only maintains the original scalability and expandability, but also increases the maintainability and upgradability. In particular, with the dual FPGA structure and the use of the fast parallel FPGA programming scheme (FPP: Fast Passive Parallel), the upgrade time can be reduced to the order of 20 ms. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments;

[0028] Figure 1 It is a schematic diagram of the structure of an existing EDFA control system;

[0029] Figure 2 It is a schematic diagram of a single FPGA structure for realizing uninterrupted EDFA optical output according to the present invention;

[0030] Figure 3 It is a schematic diagram of a dual FPGA structure for realizing uninterrupted EDFA optical output according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] As Figure 2 or Figure 3 shown, the specific NTA hardware upgrade control structure of the present invention can be divided into two categories: single FPGA structure and dual FPGA structure, and an appropriate structure can be selected according to application requirements.

[0032] The present invention discloses a single FPGA structure for realizing uninterrupted optical output of EDFA, namely a single FPGA non-service impact (NTA) structure. In this structure, the driving part in the TEC control and driving originally located inside the FPGA is moved outside the FPGA, and an existing TEC controller in the market is utilized. The purpose is to maintain the driving pump temperature within a set range during the FPGA upgrade. The single FPGA structure includes an FPGA, a DAC (digital-to-analog conversion) circuit, an external TEC driver, and a PUMP chip. The PUMP driver and the TEC controller are integrated inside the FPGA. The output end of the PUMP driver is connected to the input end of the DAC circuit. The output end of the DAC circuit is connected to the PUMP integrated on the PUMP chip. The output end of the TEC controller is connected to the external TEC driver. The output end of the external TEC driver is connected to the TEC integrated on the PUMP chip.

[0033] A single FPGA control method for realizing uninterrupted optical output of EDFA includes the following steps:

[0034] Step 1: Pause the PUMP driver, and at this time, keep the original driving value unchanged;

[0035] Step 2: Stop updating the external TEC controller. Since then, the external TEC takes over the TEC control;

[0036] Step 3: Save the FPGA scene to a non-volatile memory, such as an external FLASH device. The content includes the current PUMP control value and driving value, the TEC control value, and other values that need to be maintained, such as the VOA setting;

[0037] Step 4: Start the FPGA reconstruction. During this process, since the PIN of the FPGA remains weakly pulled up, there is no update for the PUMP drive;

[0038] Step 5: Restore the scene;

[0039] Step 6: Restore the TEC control;

[0040] Step 7: Start updating the PUMP drive value.

[0041] Further, the non-volatile memory in Step 3 is an external FLASH device, and the FPGA scene content includes the current PUMP control value, the PUMP drive value, the TEC control value, and the VOA setting.

[0042] The present invention also discloses a dual FPGA structure for realizing uninterrupted optical output of EDFA. This structure utilizes a control FPGA as a backup driving FPGA. When the main driving FPGA is reconstructed, the backup driving FPGA takes over the PUMP and TEC tasks. At the same time, the backup driving FPGA acts as a fast configuration controller (FPP: Fast Passive Parallel) to achieve fast FPGA reconstruction.

[0043] The dual-FPGA structure includes a main drive FPGA, a standby drive FPGA, a DAC circuit, an external TEC driver, and a PUMP chip. Both the main drive FPGA and the standby drive FPGA integrate a PUMP driver, a TEC controller, and a TEC driver inside, and the TEC controller and the TEC driver are interconnected inside. The output ends of the PUMP drivers of the main drive FPGA and the standby drive FPGA are respectively connected to the input ends of the DAC circuit. The output end of the DAC circuit is connected to the PUMP integrated on the PUMP chip. The output ends of the TEC drivers of the main drive FPGA and the standby drive FPGA are respectively connected to the TEC integrated on the PUMP chip. The standby drive FPGA integrates an FPP driver, and the standby drive FPGA is connected to the main drive through the FPP driver and performs rapid FPGA reconfiguration on the FPGA.

[0044] A dual-FPGA control method for realizing uninterrupted EDFA optical output includes the following steps:

[0045] Step 1: Pause the main PUMP driver;

[0046] Step 2: Stop the main TEC controller, output in tri-state, start the standby TEC controller, and maintain the PUMP temperature;

[0047] Step 3: Copy the main PUMP drive status value to the standby PUMP driver and start the standby PUMP driver;

[0048] Step 4: Save the scene to any storage device, such as an external SDRAM or the internal RAM of the standby FPGA;

[0049] Step 5: Start FPP configuration and reconfigure the main drive FPGA;

[0050] Step 6: Restore the main drive scene;

[0051] Step 6: Restore the main drive TEC control;

[0052] Step 7: Start the main drive FPGA and start updating the PUMP drive value.

[0053] Further, in Step 4, the storage device includes an external SDRAM or the internal RAM of the standby drive FPGA.

[0054] With the above technical solutions, the present invention makes appropriate adjustments to the PUMP drive and control structure, enabling the TEC driver or chip located outside the (main) FPGA to maintain the drive control of the PUMP chip when the FPGA needs to be updated. When updating the main drive or standby drive FPGA, the present invention has no impact on the existing services, which not only maintains the original scalability and expandability but also increases the maintainability and upgradability. In particular, with the dual-FPGA structure and the use of the fast parallel FPGA programming scheme (FPP: Fast Passive Parallel), the upgrade time can be reduced to the order of 20 ms.

Claims

1. A single FPGA control method for realizing uninterrupted optical output of EDFA. The single FPGA structure for realizing uninterrupted optical output of EDFA includes an FPGA, a DAC circuit, an external TEC driver, and a PUMP chip. The PUMP driver and the TEC controller are integrated in the FPGA. The output end of the PUMP driver is connected to the input end of the DAC circuit. The output end of the DAC circuit is connected to the PUMP integrated on the PUMP chip. The output end of the TEC controller is connected to the external TEC driver. The output end of the external TEC driver is connected to the TEC integrated on the PUMP chip. It is characterized in that: The single FPGA control method includes the following steps: Step 1: Pause the PUMP driver of the FPGA and maintain the original driving value unchanged. Step 2: Stop updating the external TEC controller, and the external TEC takes over the TEC control. Step 3: Save the FPGA context to a non-volatile memory. Step 4: Start FPGA reconfiguration. The PINs of the FPGA are kept in weak pull-up, and the PUMP drive has no update. Step 5: Restore the FPGA context. Step 6: Restore the TEC control of the FPGA. Step 7: Start updating the PUMP drive value.

2. The single FPGA control method for realizing uninterrupted optical output of EDFA according to claim 1. It is characterized in that: The non-volatile memory in Step 3 is an external FLASH device. The FPGA context content includes the current PUMP control value, the PUMP drive value, the TEC control value, and the VOA setting.

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