Coupling loop circuit, noise filter circuit, and circuit generation method

Abstract

A coupled loop circuit (10) is constructed in such a manner that a sixth conductor (16) intersects a second conductor (12) in three dimensions, an eighth conductor (18) intersects each of the second conductor (12) and the fourth conductor (14) in three dimensions, a first loop region (61) and a second loop region (62) overlap in space, and an overlapping region (63) of the first loop region (61) and the second loop region (62) is formed by the second conductor (12), the fourth conductor (14), the sixth conductor (16) and the eighth conductor (18).

Description

Technical Field

[0001] The present invention relates to a coupled loop circuit and a noise filter circuit including a plurality of conductors.

[0002] Furthermore, the present invention relates to a circuit generation method for wiring a conductor line on a substrate. Background Art

[0003] Patent Document 1 listed below discloses a circuit module that ensures high isolation in a wide frequency band.

[0004] The circuit module disclosed in Patent Document 1 includes a first connection line connected to a first element, a second connection line connected to a second element, and a ground line connecting a connection point between the first connection line and the second connection line to the ground line via a bypass capacitor.

[0005] Furthermore, a first inductor is connected in series to the first connection line, and a second inductor is connected in series to the second connection line.

[0006] The first inductor and the second inductor are arranged so as to be electromagnetically coupled to each other, and the mutual inductance caused by the electromagnetic field coupling cancels out the inductance parasitic in the bypass capacitor (hereinafter referred to as "parasitic inductance").

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2013-077663 Summary of the invention

[0010] In the circuit module disclosed in Patent Document 1, the first inductor and the second inductor are stacked on different layers in the substrate, and the first inductor and the second inductor overlap in space. If there is no positional offset in the spatial overlap between the first inductor and the second inductor, the parasitic inductance is offset by the mutual inductance caused by electromagnetic field coupling.

[0011] However, when a positional deviation occurs in the spatial overlap between the first inductor and the second inductor, there is a problem that the parasitic inductance cannot be canceled out by the mutual inductance due to electromagnetic field coupling.

[0012] The present invention is made to solve the above-mentioned problems, and its object is to obtain a coupled loop circuit and a noise filter circuit that can eliminate parasitic inductance even if a positional shift occurs in the spatial overlap between a first loop region formed by first to fourth conductors and a second loop region formed by fifth to eighth conductors.

[0013] Another object of the present invention is to obtain a circuit generation method for generating a circuit capable of eliminating parasitic inductance even when a positional shift occurs in the spatial overlap between a first loop region and a second loop region.

[0014] A coupled loop circuit according to the present invention is characterized in that it comprises: first to fourth conductors arranged in a loop shape to form a first loop region; and fifth to eighth conductors arranged in a loop shape to form a second loop region, wherein one end of the first conductor is connected to one end of the second conductor, the other end of the second conductor is connected to one end of the third conductor, the other end of the third conductor is connected to one end of the fourth conductor, the other end of the fourth conductor is connected to one end of the fifth conductor, the other end of the fifth conductor is connected to one end of the sixth conductor, the other end of the sixth conductor is connected to one end of the seventh conductor, and the other end of the seventh conductor is connected to one end of the eighth conductor, the sixth conductor intersects the second conductor in three dimensions, and the eighth conductor intersects the second conductor and the fourth conductor in three dimensions, the first loop region and the second loop region overlap in space, and an overlapping region of the first loop region and the second loop region is formed by the second conductor, the fourth conductor, the sixth conductor, and the eighth conductor.

[0015] According to the present invention, a coupled loop circuit is configured in such a manner that the sixth conductor intersects the second conductor in three dimensions, the eighth conductor intersects the second conductor and the fourth conductor in three dimensions, the first loop region and the second loop region overlap in space, and the overlapping region between the first loop region and the second loop region is formed by the second conductor, the fourth conductor, the sixth conductor, and the eighth conductor. Therefore, the coupled loop circuit according to the present invention can eliminate parasitic inductance even if positional deviation occurs in the spatial overlap between the first loop region and the second loop region. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a diagram showing a configuration of a noise filter circuit according to the first embodiment.

[0017] Figure 2 This is a plan view showing a first plane 1 a of a substrate 1 on which the noise filter circuit according to the first embodiment is formed.

[0018] Figure 3 This is a plan view showing a second plane 1 b in the substrate 1 on which the noise filter circuit according to the first embodiment is formed.

[0019] Figure 4A 1 is a diagram showing a configuration of a coupling loop circuit 10 according to Embodiment 1. Figure 4B 1 is an explanatory diagram showing a first loop region 61 formed by a first conductor 11, a second conductor 12, a third conductor 13, and a fourth conductor 14. Figure 4C1 is an explanatory diagram showing a second loop region 62 formed by a fifth conductor 15, a sixth conductor 16, a seventh conductor 17, and an eighth conductor 18. Figure 4D 1 is an explanatory diagram showing a spatially overlapping region 63 between the first loop region 61 and the second loop region 62 .

[0020] Figure 5 This is an explanatory diagram showing a conductor formed on a first plane 1 a of a substrate 1 among a plurality of conductors in the coupled loop circuit 10 according to the first embodiment.

[0021] Figure 6 This is an explanatory diagram showing a conductor formed on the second plane 1 b of the substrate 1 among a plurality of conductors in the coupled loop circuit 10 according to the first embodiment.

[0022] Figure 7 It is shown Figure 1 The circuit diagram of the noise filter circuit is shown.

[0023] Figure 8 Yes Figure 7 This is a circuit diagram of the noise filter circuit shown in Figure 1 that is converted into an equivalent circuit.

[0024] Fig. 9 is a value B indicating the size of the spatial overlap region 63 between the first loop region 61 and the second loop region 62. z 's illustration.

[0025] Fig.10 It is an explanatory diagram showing the position of the first loop area 61 and the position of the second loop area 62 .

[0026] Fig.11 This is a side view showing the substrate 1 on which the noise filter circuit according to the first embodiment is formed.

[0027] Fig.12 This is a flowchart showing the circuit generation method according to the first embodiment.

[0028] Fig.13A 1 is an explanatory diagram showing a state in which the first loop region 61 is offset relative to the second loop region 62 in the direction indicated by the arrow (right direction in the figure). Fig. 13B 1 is an explanatory diagram showing a state in which the first loop region 61 is offset relative to the second loop region 62 in the direction indicated by the arrow (in the lower direction in the figure). Fig. 13C This is an explanatory diagram showing a state in which the first loop area 61 is offset with respect to the second loop area 62 in the direction indicated by the arrow (upper right direction in the figure).

[0029] Fig.14The diagram is an explanatory diagram showing simulation results of transmission characteristics of high-frequency signals when there is a positional shift in spatial overlap between a first inductor and a second inductor and when there is no positional shift in spatial overlap in the circuit module disclosed in Patent Document 1.

[0030] Fig.15 It is shown in Figure 1 1 is an explanatory diagram of simulation results of transmission characteristics of high-frequency signals when the positions of the conductors in the first plane 1a or the second plane 1b in the noise filter circuit are deviated from the desired positions and when the positions are not deviated from the desired positions.

[0031] Fig.16 This is an explanatory diagram showing the intervals between conductors arranged on the same plane and the like as simulation conditions for the transmission characteristics of high-frequency signals.

[0032] Fig.17 1 is a diagram showing a configuration of another noise filter circuit according to the first embodiment.

[0033] Fig.18 1 is a plan view showing a first plane 1 a of a substrate 1 on which another noise filter circuit according to the first embodiment is formed.

[0034] Fig.19 This is a plan view showing a second plane 1 b in a substrate 1 on which another noise filter circuit according to the first embodiment is formed.

[0035] Fig. 20 1 is a diagram showing a configuration of a noise filter circuit according to the second embodiment.

[0036] Fig.21 This is a plan view showing a first plane 1 a of a substrate 1 on which a noise filter circuit according to a second embodiment is formed.

[0037] Fig. 22 This is a plan view showing a second plane 1 b in a substrate 1 on which a noise filter circuit according to a second embodiment is formed.

[0038] Fig.23 It is shown Fig. 20 The circuit diagram of the noise filter circuit is shown.

[0039] Fig.24 Yes Fig.23 This is a circuit diagram of the noise filter circuit shown in Figure 1 that is converted into an equivalent circuit.

[0040] (Explanation of symbols)

[0041] 1: substrate; 1a: first plane; 1b: second plane; 2, 2a, 2b: input / output terminals; 3, 3a, 3b: input / output terminals; 10: coupling loop circuit; 10a: first coupling loop circuit; 10b: second coupling loop circuit; 11: first conductor; 12: second conductor; 13: third conductor; 14: fourth conductor; 15: fifth conductor; 16: sixth conductor; 17: seventh conductor; 18: eighth conductor; 21-25: vias; 26: conductor; 27-31, 33: vias; 32: capacitor; 34: ground; 35: capacitor; 41, 51: capacitor; 42, 52: parasitic inductance; 43, 44: inductance; 45: mutual inductance; 61: first loop region; 62: second loop region; 63: overlapping region. DETAILED DESCRIPTION

[0042] Hereinafter, in order to explain the present invention in more detail, the mode for carrying out the present invention will be described with reference to the accompanying drawings.

[0043] Implementation method 1.

[0044] Figure 1 1 is a diagram showing a configuration of a noise filter circuit according to the first embodiment.

[0045] Figure 2 FIG. 1 is a plan view showing a first plane 1 a of a substrate 1 on which a noise filter circuit according to Embodiment 1 is formed. Figure 3 This is a plan view showing a second plane 1 b in the substrate 1 on which the noise filter circuit according to the first embodiment is formed.

[0046] Figure 4A 1 is a diagram showing a configuration of a coupling loop circuit 10 according to the first embodiment.

[0047] Figure 4B 1 is an explanatory diagram showing a first loop region 61 formed by the first conductor 11 , the second conductor 12 , the third conductor 13 , and the fourth conductor 14 .

[0048] Figure 4C 1 is an explanatory diagram showing a second loop region 62 formed by the fifth conductor 15 , the sixth conductor 16 , the seventh conductor 17 , and the eighth conductor 18 .

[0049] Figure 4D 1 is an explanatory diagram showing a spatially overlapping region 63 between the first loop region 61 and the second loop region 62 .

[0050] Figure 5 This is an explanatory diagram showing a conductor formed on a first plane 1 a of a substrate 1 among a plurality of conductors in the coupled loop circuit 10 according to the first embodiment.

[0051] Figure 6 This is an explanatory diagram showing a conductor formed on the second plane 1 b of the substrate 1 among a plurality of conductors in the coupled loop circuit 10 according to the first embodiment.

[0052] exist Figure 1 It is described that when observing the second plane 1 b in the substrate 1 , the conductor and the like formed on the first plane 1 a are seen.

[0053] Figure 1 This is a diagram showing the structure of the noise filter circuit, and does not accurately show the length and width of each conductor included in the noise filter circuit. Therefore, the length and width of each conductor are slightly different from the length and width of each conductor described in FIG. 4 .

[0054] exist Figures 1 to 6 In the embodiment, the substrate 1 has a first plane 1a and a second plane 1b.

[0055] The first plane 1 a is the back surface of the substrate 1 , and the second plane 1 b is the front surface of the substrate 1 .

[0056] However, this is just an example, and the first plane 1 a may be the front surface of the substrate 1 , and the second plane 1 b may be the back surface of the substrate 1 .

[0057] The input / output terminal 2 is a terminal for inputting and outputting high-frequency signals. Figure 1 In FIG. 1 , the input / output terminal 2 is recorded as port (1).

[0058] The input / output terminal 3 is a terminal for inputting and outputting high-frequency signals. Figure 1 In FIG. 1 , the input / output terminal 3 is recorded as port (2).

[0059] exist Figure 1 In the noise filter circuit shown, for example, the input / output terminal 2 is used as a terminal for inputting a high-frequency signal, and the input / output terminal 3 is used as a terminal for outputting a high-frequency signal.

[0060] Figure 1 The noise filter circuit shown includes a coupled loop circuit 10 , and the coupled loop circuit 10 includes a first conductor line and a second conductor line.

[0061] The first conductor line includes a first conductor 11, a second conductor 12, a third conductor 13, and a fourth conductor 14. The first conductor 11, the second conductor 12, the third conductor 13, and the fourth conductor 14 are arranged in a loop shape to form a first loop region 61. The first loop region 61 is Figure 4B The area with a slash in it.

[0062] The second conductor line includes a fifth conductor 15, a sixth conductor 16, a seventh conductor 17, and an eighth conductor 18. The fifth conductor 15, the sixth conductor 16, the seventh conductor 17, and the eighth conductor 18 are arranged in a loop shape to form a second loop region 62. The second loop region 62 is Figure 4C The area with a slash in it.

[0063] The first loop region 61 and the second loop region 62 overlap in space.

[0064] The spatial overlap area 63 between the first loop area 61 and the second loop area 62 is Figure 4D The area with a slash in it.

[0065] The first conductor 11 is disposed on the first plane 1 a . One end of the first conductor 11 is connected to one end of the second conductor 12 via a via 22 , and the other end of the first conductor 11 is connected to the input / output terminal 2 via a via 21 .

[0066] The second conductor 12 is disposed on the second plane 1 b . One end of the second conductor 12 is connected to one end of the first conductor 11 via a via 22 , and the other end of the second conductor 12 is connected to one end of the third conductor 13 via a via 23 .

[0067] The third conductor 13 is disposed on the first plane 1 a . One end of the third conductor 13 is connected to the other end of the second conductor 12 via a via 23 , and the other end of the third conductor 13 is connected to one end of the fourth conductor 14 via a via 24 .

[0068] The fourth conductor 14 is disposed on the second plane 1 b . One end of the fourth conductor 14 is connected to the other end of the third conductor 13 via a via 24 , and the other end of the fourth conductor 14 is connected to one end of a conductor 26 via a via 25 .

[0069] The fifth conductor 15 is disposed on the second plane 1 b . One end of the fifth conductor 15 is connected to the other end of the conductor 26 via a via 27 , and the other end of the fifth conductor 15 is connected to one end of the sixth conductor 16 via a via 28 .

[0070] The sixth conductor 16 is disposed on the first plane 1 a . One end of the sixth conductor 16 is connected to the other end of the fifth conductor 15 via a via 28 , and the other end of the sixth conductor 16 is connected to one end of the seventh conductor 17 via a via 29 .

[0071] The sixth conductor 16 is arranged so as to three-dimensionally intersect the second conductor 12 .

[0072] The seventh conductor 17 is disposed on the second plane 1 b . One end of the seventh conductor 17 is connected to the other end of the sixth conductor 16 via a via 29 , and the other end of the seventh conductor 17 is connected to one end of the eighth conductor 18 via a via 30 .

[0073] The eighth conductor 18 is disposed on the first plane 1 a . One end of the eighth conductor 18 is connected to the other end of the seventh conductor 17 via a via 30 , and the other end of the eighth conductor 18 is connected to the input / output terminal 3 via a via 31 .

[0074] The eighth conductor 18 is arranged so as to three-dimensionally intersect the second conductor 12 and the fourth conductor 14 .

[0075] The via 21 is inserted into the substrate 1 in order to electrically connect the input / output terminal 2 and the other end of the first conductor 11 .

[0076] The via 22 is inserted into the substrate 1 in order to electrically connect one end of the first conductor 11 and one end of the second conductor 12 .

[0077] The via 23 is inserted into the substrate 1 in order to electrically connect the other end of the second conductor 12 and one end of the third conductor 13 .

[0078] The via 24 is inserted into the substrate 1 in order to electrically connect the other end of the third conductor 13 and one end of the fourth conductor 14 .

[0079] The via 25 is inserted into the substrate 1 in order to electrically connect the other end of the fourth conductor 14 and one end of the conductor 26 .

[0080] The conductor 26 is disposed on the first plane 1 a . One end of the conductor 26 is connected to the other end of the fourth conductor 14 via a via 25 , and the other end of the conductor 26 is connected to one end of the fifth conductor 15 via a via 27 .

[0081] The via 27 is inserted into the substrate 1 to electrically connect the other end of the conductor 26 and one end of the fifth conductor 15. The via 25, the conductor 26, and the via 27 are connecting portions between the first conductor line and the second conductor line.

[0082] exist Figures 1 to 3 In the noise filter circuit shown, the conductor 26 is arranged on the first plane 1a. However, the present invention is not limited to this, and the conductor 26 may be arranged on the second plane 1b.

[0083] When the conductor 26 is arranged on the second plane 1b, one end of the conductor 26 is connected to the other end of the fourth conductor 14, and the other end of the conductor 26 is connected to one end of the fifth conductor 15. When the conductor 26 is arranged on the second plane 1b, the vias 25 and 27 are unnecessary.

[0084] For example, when the fourth conductor 14 is L-shaped or the fifth conductor 15 is L-shaped and the other end of the fourth conductor 14 and one end of the fifth conductor 15 are directly connected, the conductor 26 is not required.

[0085] The via 28 is inserted into the substrate 1 in order to electrically connect the other end of the fifth conductor 15 and one end of the sixth conductor 16 .

[0086] The via 29 is inserted into the substrate 1 in order to electrically connect the other end of the sixth conductor 16 and one end of the seventh conductor 17 .

[0087] The via 30 is inserted into the substrate 1 in order to electrically connect the other end of the seventh conductor 17 and one end of the eighth conductor 18 .

[0088] The via 31 is inserted into the substrate 1 in order to electrically connect the other end of the eighth conductor 18 and the input / output terminal 3 .

[0089] The capacitor 32 is disposed on the second plane 1 b . One end of the capacitor 32 is connected to the via 27 , which is a connection portion between the first conductor line and the second conductor line, and the other end of the capacitor 32 is connected to the ground 34 via a via 33 .

[0090] The via 33 is inserted into the substrate 1 in order to electrically connect the other end of the capacitor 32 and the ground line 34 .

[0091] The ground line 34 is formed on the first plane 1 a .

[0092] Figure 7 It is shown Figure 1 The circuit diagram of the noise filter circuit is shown.

[0093] exist Figure 7 41 is the capacitance C of capacitor 32.

[0094] 42 is the parasitic inductance L of the ground path including the capacitor 32 ESL , is the sum of the parasitic inductance in the capacitor 32 and the inductance of the substrate 1 .

[0095] 43 is the inductance L0 of the first conductor line, and 44 is the inductance L0 of the second conductor line.

[0096] 45 is the mutual inductance M caused by the electromagnetic field coupling between the first conductor line and the second conductor line.

[0097] Figure 8 Yes Figure 7 This is a circuit diagram of the noise filter circuit shown in Figure 1 that is converted into an equivalent circuit.

[0098] Next, explain Figure 1 The operation of the noise filter circuit is shown.

[0099] about Figure 1 The noise filter circuit shown can efficiently remove high-frequency noise even without the coupling loop circuit 10 if the parasitic inductance 42 is close to 0.

[0100] However, the actual parasitic inductance 42 is not 0, so Figure 1 The noise filter circuit shown has a coupled loop circuit 10 to eliminate the parasitic inductance 42 .

[0101] Specifically, the parasitic inductance 42 is cancelled out by the mutual inductance M caused by the electromagnetic field coupling between the first conductor line and the second conductor line.

[0102] The mutual inductance M is determined by the interlinkage amount Φ, which is the amount of interlinkage between the magnetic flux generated by the current flowing through the first conductor line and the second conductor line.

[0103] Regarding the cross-linkage amount Φ, the size B of the spatial overlap region 63 between the first conductor line and the second conductor line is z The larger it is, the larger it becomes, if the size B of the overlapping area 63 z If it does not change, it is constant.

[0104] Therefore, regarding the mutual inductance M, if the size B of the overlapping area 63 is z Unchanging and constant.

[0105] Fig. 9 is a value B indicating the size of the spatial overlap region 63 between the first loop region 61 and the second loop region 62. z In the illustration of Fig. 9 The area with slashes in the figure represents a spatially overlapping area 63 .

[0106] Size B of the overlapping area 63 z Use B z =x0×y0. Fig. 9 In the example of , x0=y0. However, this is just an example, and x0≠y0 may also be possible.

[0107] Fig.10 It is an explanatory diagram showing the position of the first loop area 61 and the position of the second loop area 62 .

[0108] exist Fig.10 In the diagram, the X axis is parallel to the second conductor 12, the fourth conductor 14, the fifth conductor 15, and the seventh conductor 17. The Y axis is parallel to the first conductor 11, the third conductor 13, the sixth conductor 16, and the eighth conductor 18.

[0109] Fig.11 This is a side view showing the substrate 1 on which the noise filter circuit according to the first embodiment is formed. Fig.11 The substrate 1 shown is a substrate having a thickness h.

[0110] The mutual inductance M is expressed as shown in the following formula (1).

[0111]

[0112] In formula (1), i = 1, 2, j = 1, 2. x is the length of the overlapping region 63 in the X-axis direction, a y It is the length of the overlapping area 63 in the Y-axis direction.

[0113] δx1 is the protruding length of the first loop region 61 relative to the second loop region 62 in the −X axis direction, and δx2 is the protruding length of the first loop region 61 relative to the second loop region 62 in the +X axis direction.

[0114] δy1 is the protruding length of the second loop region 62 relative to the first loop region 61 in the −Y axis direction, and δy2 is the protruding length of the second loop region 62 relative to the first loop region 61 in the +Y axis direction.

[0115] μ is the magnetic permeability between the first loop region 61 and the second loop region 62 .

[0116] Here, the circuit generation method of the coupling loop circuit 10 is as follows: Fig.12 As shown, steps ST1 to ST3 are used to represent the coupled loop circuit 10. By executing steps ST1 to ST3, a coupled loop circuit 10 is generated.

[0117] Fig.12 This is a flowchart showing the circuit generation method according to the first embodiment.

[0118] Hereinafter, the contents of steps ST1 to ST3 will be described in detail.

[0119] Step ST1

[0120] exist Fig.12 In the circuit forming method shown, the first conductor 11 and the third conductor 13 are each wired as a conductor included in the first conductor line on the first plane 1a of the substrate 1, and the conductor 26 is wired on the first plane 1a.

[0121] In addition, Fig.12 In the circuit generation method shown, the sixth conductor 16 and the eighth conductor 18 are each wired as a conductor included in the second conductor line on the first plane 1a.

[0122] Step ST2

[0123] exist Fig.12 In the circuit forming method shown, the second conductor 12 and the fourth conductor 14 are each wired on the second plane 1 b of the substrate 1 as a conductor included in the first conductor line.

[0124] In addition, Fig.12In the circuit generation method shown, the fifth conductor 15 and the seventh conductor 17 are each wired as a conductor included in the second conductor line on the second plane 1b.

[0125] Step ST3

[0126] exist Fig.12 In the circuit forming method shown, a plurality of via holes are formed in the substrate 1, thereby connecting each conductor wired on the first plane 1a and each conductor wired on the second plane 1b.

[0127] Specifically, it is as follows.

[0128] (a) The input / output terminal 2 and the other end of the first conductor 11 are connected by forming a via hole 21 in the substrate 1 .

[0129] (b) By forming the via hole 22 in the substrate 1 , one end of the first conductor 11 and one end of the second conductor 12 are connected.

[0130] (c) The via hole 23 is formed in the substrate 1 to connect the other end of the second conductor 12 and one end of the third conductor 13 .

[0131] (d) The other end of the third conductor 13 and one end of the fourth conductor 14 are connected by forming a via hole 24 in the substrate 1 .

[0132] (e) The via hole 25 is formed in the substrate 1 to connect the other end of the fourth conductor 14 and one end of the conductor 26 .

[0133] (f) The via hole 27 is formed in the substrate 1 to connect the other end of the conductor 26 and one end of the fifth conductor 15 .

[0134] (g) The other end of the fifth conductor 15 and one end of the sixth conductor 16 are connected by forming a via hole 28 in the substrate 1 .

[0135] (h) The via hole 29 is formed in the substrate 1 to connect the other end of the sixth conductor 16 and one end of the seventh conductor 17 .

[0136] (i) The via hole 30 is formed in the substrate 1 to connect the other end of the seventh conductor 17 and one end of the eighth conductor 18 .

[0137] (j) The other end of the eighth conductor 18 and the input / output terminal 3 are connected by forming a via hole 31 in the substrate 1 .

[0138] exist Fig.12In the circuit generation method shown, in step ST1, the first conductor 11, the third conductor 13, the sixth conductor 16, the eighth conductor 18, and the conductor 26 are each wired on the first plane 1a. Thereafter, in step ST2, the second conductor 12, the fourth conductor 14, the fifth conductor 15, and the seventh conductor 17 are each wired on the second plane 1b.

[0139] Therefore, for example, even if the positions of the conductors arranged on the first plane 1 a match the desired positions as designed positions, the positions of the conductors arranged on the second plane 1 b may deviate from the desired positions.

[0140] When the positions of the conductors wired on the second plane 1b are deviated from the desired positions, the position of the first loop region 61 may be deviated from the position of the first loop region 61 when it coincides with the desired position (hereinafter referred to as "the positive position of the first loop region 61"). In addition, when the positions of the conductors wired on the second plane 1b are deviated from the desired positions, the position of the second loop region 62 may be deviated from the position of the second loop region 62 when it coincides with the desired position (hereinafter referred to as "the positive position of the second loop region 62").

[0141] Conversely, even if the positions of the conductors arranged on the second plane 1 b match the desired positions, the positions of the conductors arranged on the first plane 1 a may deviate from the desired positions.

[0142] When the positions of the conductors arranged on the first plane 1a are deviated from the desired positions, the position of the first loop region 61 may be deviated from the positive position of the first loop region 61. In addition, when the positions of the conductors arranged on the first plane 1a are deviated from the desired positions, the position of the second loop region 62 may be deviated from the positive position of the second loop region 62.

[0143] Figures 13A to 13C It is an explanatory diagram showing an example of the spatial positional shift between the first loop area 61 and the second loop area 62 .

[0144] Fig.13A The first loop region 61 is shown to be offset relative to the second loop region 62 in the direction indicated by the arrow (rightward in the figure).

[0145] Fig. 13B The first loop region 61 is shown to be offset relative to the second loop region 62 in the direction indicated by the arrow (downward direction in the figure).

[0146] Fig. 13C The first loop region 61 is shown to be offset relative to the second loop region 62 in the direction indicated by the arrow (upper right direction in the figure).

[0147] However, in Fig.12 In the circuit generation method shown, in step ST1, when the sixth conductor 16 is wired on the first plane 1a, the sixth conductor 16 is made to intersect the second conductor 12 three-dimensionally (hereinafter referred to as "first three-dimensional intersection").

[0148] Furthermore, in step ST1, when the eighth conductor 18 is wired on the first plane 1a, the eighth conductor 18 is three-dimensionally intersected with each of the second conductor 12 and the fourth conductor 14 (hereinafter referred to as "second three-dimensional intersection").

[0149] Therefore, even if the first loop area 61 is offset relative to the second loop area 62 in the direction indicated by the arrow, as long as the offset is within the range of achieving the first and second grade separations, the size B of the overlapping area 63 is z No change.

[0150] Figures 13A to 13C The size B of the overlapping area 63 is shown z =x0×y0 and Fig. 9 The size B of the overlapping area 63 is shown z =x0×y0 is the same.

[0151] If the size B of the overlapping area 63 z If φ does not change, the mutual inductance M caused by the electromagnetic field coupling between the first conductor line and the second conductor line does not change.

[0152] When the first conductor line and the second conductor line are arranged at positions where electromagnetic field coupling occurs, the mutual inductance M caused by the electromagnetic field coupling is as follows: Figure 8 The inductance L0 added to the first conductor line and the inductance L0 added to the second conductor line are shown respectively.

[0153] In addition, regarding the parasitic inductance 42 of the ground path including the capacitor 32, from the parasitic inductance L ESL Subtract 2 times the mutual inductance M.

[0154] Therefore, if the mutual inductance M is twice the parasitic inductance L ESL By designing the mutual inductance M in a consistent manner, the parasitic inductance L can be eliminated. ESL .

[0155] Figure 1 The noise filter circuit shown has a structure that makes the mutual inductance M twice as large as the parasitic inductance L. ESL The first conductor line and the second conductor line are identical.

[0156] Regarding the first conductor line and the second conductor line, the parasitic inductance L is equal to twice the mutual inductance M. ESLIn a consistent manner, the length α of the overlapping area 63 in the X-axis direction is designed respectively. x , the length α of the overlapping region 63 in the Y-axis direction y , the thickness h and magnetic permeability μ of the substrate 1.

[0157] Fig.14 The diagram is an explanatory diagram showing simulation results of transmission characteristics of high-frequency signals when there is a positional shift in spatial overlap between a first inductor and a second inductor and when there is no positional shift in spatial overlap in the circuit module disclosed in Patent Document 1.

[0158] Fig.15 It is shown in Figure 1 1 is an explanatory diagram of simulation results of transmission characteristics of high-frequency signals when the positions of the conductors in the first plane 1a or the second plane 1b in the noise filter circuit are deviated from the desired positions and when the positions are not deviated from the desired positions.

[0159] exist Fig.14 as well as Fig.15 In FIG. 1 , the vertical axis represents the parameter S21 which is one of the S parameters, and the horizontal axis represents the frequency of the high-frequency signal input to the circuit module or the noise filter circuit.

[0160] Fig.16 This is an explanatory diagram showing the intervals between conductors arranged on the same plane and the like as simulation conditions for the transmission characteristics of high-frequency signals.

[0161] The interval between the second conductor 12 and the fourth conductor 14 is y0 = 3.2 mm.

[0162] The interval between the second conductor 12 and the seventh conductor 17 is 1 mm, and the interval between the fifth conductor 15 and the seventh conductor 17 is y0+5=8.2 mm.

[0163] The interval between the sixth conductor 16 and the eighth conductor 18 is x0 = 3.2 mm.

[0164] The distance between the first conductor 11 and the third conductor 13 is x0+5=8.2 mm.

[0165] In the circuit module disclosed in Patent Document 1, Fig.14 As shown in FIG. 1 , the transmission characteristics of the high-frequency signal when there is a positional shift in the spatial superposition of the first inductor and the second inductor are different from the transmission characteristics of the high-frequency signal when there is no positional shift in the spatial superposition.

[0166] Therefore, in this circuit module, the mutual inductance when there is a positional offset in the spatial overlap between the first inductor and the second inductor is different from the mutual inductance when there is no positional offset in the spatial overlap.

[0167] exist Figure 1 In the noise filter circuit shown, Fig.15 As shown, the transmission characteristics of high-frequency signals when the positions of the conductors in the first plane 1a or the second plane 1b are deviated from the desired positions and the transmission characteristics of high-frequency signals when the positions are not deviated from the desired positions are substantially consistent.

[0168] Therefore, in Figure 1 In the noise filter circuit shown, the mutual inductance M when the positions of the conductors are deviated from the desired positions and the mutual inductance M when the positions of the conductors are not deviated from the desired positions are substantially equal.

[0169] In the first embodiment described above, the coupled loop circuit 10 is configured such that the sixth conductor 16 and the second conductor 12 are three-dimensionally intersected, the eighth conductor 18 and the second conductor 12 and the fourth conductor 14 are three-dimensionally intersected, the first loop region 61 and the second loop region 62 are spatially overlapped, and the overlapping region 63 of the first loop region 61 and the second loop region 62 is formed by the second conductor 12, the fourth conductor 14, the sixth conductor 16, and the eighth conductor 18. Therefore, even if the coupled loop circuit 10 is positionally misaligned in the spatial overlap between the first loop region 61 and the second loop region 62, the parasitic inductance L of the ground path including the capacitor 32 can be eliminated. ESL .

[0170] In the coupled loop circuit 10 shown in FIG. 4 , the first loop region 61 has a rectangular shape, and the second loop region 62 has a rectangular shape.

[0171] However, this is just an example, and for example, the shape of the first loop region 61 may be a parallelogram, and the shape of the second loop region 62 may be a parallelogram.

[0172] However, even when the shapes of the first loop region 61 and the second loop region 62 are parallelograms, the third conductor 13, the sixth conductor 16, and the eighth conductor 18 are each arranged in parallel with the first conductor 11. In addition, the fourth conductor 14, the fifth conductor 15, and the seventh conductor 17 are each arranged in parallel with the second conductor 12.

[0173] In addition, the sixth conductor 16 intersects the second conductor 12 in three dimensions, and the eighth conductor 18 intersects the second conductor 12 and the fourth conductor 14 in three dimensions.

[0174] exist Figures 1 to 3 In the coupled loop circuit 10 included in the noise filter circuit shown, each of the first conductor line and the second conductor line has a conductor arranged on the first plane 1 a and a conductor arranged on the second plane 1 b .

[0175] Specifically, the first conductor 11 , the third conductor 13 , the sixth conductor 16 , and the eighth conductor 18 are each arranged on the first plane 1 a , and the second conductor 12 , the fourth conductor 14 , the fifth conductor 15 , and the seventh conductor 17 are each arranged on the second plane 1 b .

[0176] However, this is merely an example, and the coupled loop circuit 10 may be configured such that the first conductor line includes only conductors arranged on the first plane 1 a , and the second conductor line includes only conductors arranged on the second plane 1 b .

[0177] Specifically, if Figures 17 to 19 As shown, the first conductor 11, the second conductor 12, the third conductor 13 and the fourth conductor 14 are respectively arranged on the first plane 1a, and the fifth conductor 15, the sixth conductor 16, the seventh conductor 17 and the eighth conductor 18 are respectively arranged on the second plane 1b. In addition, the conductor 26 is arranged on the second plane 1b, and the vias 21 to 25 and 28 to 30 are not required.

[0178] Fig.17 1 is a diagram showing a configuration of another noise filter circuit according to the first embodiment.

[0179] Fig.18 1 is a plan view showing a first plane 1a of a substrate 1 on which another noise filter circuit according to the first embodiment is formed. Fig.19 This is a plan view showing a second plane 1 b in a substrate 1 on which another noise filter circuit according to the first embodiment is formed.

[0180] For example, when the fourth conductor 14 has an L-shape and the other end of the fourth conductor 14 is directly connected to the via 27 , the conductor 26 is not necessary.

[0181] Alternatively, the coupled loop circuit 10 may be configured such that the first conductor line includes only conductors disposed on the second plane 1 b , and the second conductor line includes only conductors disposed on the first plane 1 a .

[0182] Specifically, the coupled loop circuit 10 may be configured such that the first conductor 11, the second conductor 12, the third conductor 13, and the fourth conductor 14 are disposed on the second plane 1b, and the fifth conductor 15, the sixth conductor 16, the seventh conductor 17, and the eighth conductor 18 are disposed on the first plane 1a.

[0183] Implementation method 2.

[0184] The noise filter circuit according to the first embodiment is a single-ended noise filter circuit.

[0185] In the second embodiment, a differential noise filter circuit will be described.

[0186] Fig. 20 1 is a diagram showing a configuration of a noise filter circuit according to the second embodiment.

[0187] Fig.21 FIG. 1 is a plan view showing a first plane 1 a of a substrate 1 on which a noise filter circuit according to a second embodiment is formed. Fig. 22 This is a plan view showing a second plane 1 b in a substrate 1 on which a noise filter circuit according to a second embodiment is formed.

[0188] exist Fig. 20 It is described that when observing the second plane 1 b in the substrate 1 , the conductor and the like formed on the first plane 1 a are seen.

[0189] exist Figure 20 to Figure 22 In, with Figures 1 to 3 The same reference numerals represent the same or corresponding parts, and thus their descriptions are omitted.

[0190] Fig. 20 The noise filter circuit shown includes a first coupled loop circuit 10 a and a second coupled loop circuit 10 b .

[0191] The configuration of each of the first coupling loop circuit 10 a and the second coupling loop circuit 10 b is the same as that of the coupling loop circuit 10 shown in FIG. 4 .

[0192] However, one end of the first conductor 11 included in the first coupling loop circuit 10a is connected to the input / output terminal 2a, and the other end of the eighth conductor 18 included in the first coupling loop circuit is connected to the input / output terminal 3a.

[0193] One end of the first conductor 11 included in the second coupling loop circuit 10 b is connected to the input-output terminal 3 b , and the eighth conductor 18 included in the second coupling loop circuit 10 b is connected to the input-output terminal 2 b .

[0194] The input / output terminal 2a and the input / output terminal 2b are a pair of differential input / output ports. Fig. 20 In the example, it is recorded as port (1).

[0195] The input / output terminal 3a and the input / output terminal 3b are a pair of differential input / output ports. Fig. 20 In the example, it is recorded as port (2).

[0196] exist Fig. 20In the noise filter circuit shown, in the second coupling loop circuit 10b, the first conductor 11 included in the first conductor line is connected to the input-output terminal 3b, and the eighth conductor 18 included in the second conductor line is connected to the input-output terminal 2b. However, this is only an example, and in the second coupling loop circuit 10b, the first conductor 11 included in the first conductor line may be connected to the input-output terminal 2b, and the eighth conductor 18 included in the second conductor line may be connected to the input-output terminal 3b.

[0197] One end of the capacitor 35 is connected to one end of the fifth conductor 15 included in the first coupling loop circuit 10 a , and the other end of the capacitor 35 is connected to one end of the fifth conductor 15 included in the second coupling loop circuit 10 b .

[0198] The first coupled loop circuit 10a is similar to the coupled loop circuit 10 shown in FIG. 4. Even if a positional offset occurs between the first loop region 61 and the second loop region 62, as long as the positional offset is within the range of achieving the first and second three-dimensional intersections, the size B of the overlap region 63 is z No change.

[0199] In the second coupled loop circuit 10b, even if there is a positional shift between the first loop region 61 and the second loop region 62, as long as the positional shift is within the range of achieving the first and second three-dimensional intersections, the size B of the overlap region 63 is z No change.

[0200] Fig.23 It is shown Fig. 20 The circuit diagram of the noise filter circuit is shown in Fig.23 In, with Figure 7 as well as Fig. 20 The same reference numerals represent the same or corresponding parts, and thus their descriptions are omitted.

[0201] 51 is the capacitance C of the capacitor 35 .

[0202] 52 is the parasitic inductance L of the path including the capacitor 35 ESL , is the sum of the parasitic inductance in the capacitor 35 and the inductance of the substrate 1 .

[0203] Fig.24 Yes Fig.23 This is a circuit diagram of the noise filter circuit shown in Figure 1 that is converted into an equivalent circuit.

[0204] The first conductor line included in the first coupling loop circuit 10a and the second conductor line included in the first coupling loop circuit 10a are arranged at positions where electromagnetic field coupling occurs. The mutual inductance M caused by the electromagnetic field coupling is as follows: Fig.24As shown, the inductance L0 is added to the first conductor line included in the first coupling loop circuit 10a and the inductance L0 is added to the second conductor line included in the first coupling loop circuit 10a.

[0205] The first conductor line included in the second coupling loop circuit 10b and the second conductor line included in the second coupling loop circuit 10b are arranged at positions where electromagnetic field coupling occurs. The mutual inductance M caused by the electromagnetic field coupling is as follows: Fig.24 As shown, the inductance L0 is added to the first conductor line included in the second coupling loop circuit 10b and the inductance L0 is added to the second conductor line included in the second coupling loop circuit 10b.

[0206] In addition, the parasitic inductance 52 of the path including the capacitor 35 is reduced from the parasitic inductance L ESL Subtract 2 times the mutual inductance M.

[0207] Therefore, if the mutual inductance M is twice the parasitic inductance L ESL By designing the mutual inductance M in a consistent manner, the parasitic inductance L can be eliminated. ESL .

[0208] Fig. 20 The first coupling loop circuit 10a and the second coupling loop circuit 10b in the noise filter circuit shown in the figure each have a circuit structure such that twice the mutual inductance M and the parasitic inductance L ESL The first conductor line and the second conductor line are identical.

[0209] Regarding the first conductor line and the second conductor line, the parasitic inductance L is equal to twice the mutual inductance M. ESL In a consistent manner, the length α of the overlapping area 63 in the X-axis direction is designed respectively. x , the length α of the overlapping region 63 in the Y-axis direction y , the thickness h and magnetic permeability μ of the substrate 1.

[0210] In the second embodiment described above, the noise filter circuit is configured such that the sixth conductor 16 and the second conductor 12 are three-dimensionally intersected in each of the first coupling loop circuit 10a and the second coupling loop circuit 10b, and the eighth conductor 18 and the second conductor 12 and the fourth conductor 14 are three-dimensionally intersected. Therefore, even if the noise filter circuit is misaligned in the spatial overlap between the first loop region 61 and the second loop region 62, the parasitic inductance L of the path including the capacitor 35 can be eliminated. ESL .

[0211] Furthermore, the present invention can realize free combination of the embodiments, modification of arbitrary components of the embodiments, or omission of arbitrary components of the embodiments within the scope of the invention.

[0212] Industrial Applicability

[0213] The present invention is suitable for a coupled loop circuit and a noise filter circuit including a plurality of conductors.

[0214] Furthermore, the present invention is suitable for a circuit generation method for wiring a conductor line on a substrate.

Claims

1. A coupled loop circuit, characterized in that: have: The first to fourth conductors are arranged in a loop shape to form a first loop region; and The fifth to eighth conductors are arranged in a loop shape to form a second loop region. One end of the first conductor is connected to one end of the second conductor, The other end of the second conductor is connected to one end of the third conductor. The other end of the third conductor is connected to one end of the fourth conductor. The other end of the fourth conductor is connected to one end of the fifth conductor, The other end of the fifth conductor is connected to one end of the sixth conductor, The other end of the sixth conductor is connected to one end of the seventh conductor, The other end of the seventh conductor is connected to one end of the eighth conductor, The sixth conductor and the second conductor are three-dimensionally intersected, The eighth conductor intersects the second conductor and the fourth conductor in a three-dimensional manner. The first loop region and the second loop region overlap in space, and an overlapping region of the first loop region and the second loop region is formed by the second conductor, the fourth conductor, the sixth conductor, and the eighth conductor. The overlapping region is designed in such a manner that twice the mutual inductance caused by electromagnetic field coupling between the first conductor line including the first to fourth conductors and the second conductor line including the fifth to eighth conductors coincides with the parasitic inductance.

2. The coupling loop circuit according to claim 1, characterized in that: The first conductor is arranged on a first plane of the substrate. The second conductor is disposed on the second plane of the substrate, and one end of the second conductor is connected to one end of the first conductor via a via hole. The third conductor is arranged on the first plane, and one end of the third conductor is connected to the other end of the second conductor via a via hole. The fourth conductor is arranged on the second plane, and one end of the fourth conductor is connected to the other end of the third conductor via a via hole. The fifth conductor is disposed on the second plane, and one end of the fifth conductor is connected to the other end of the fourth conductor. The sixth conductor is disposed on the first plane, and one end of the sixth conductor is connected to the other end of the fifth conductor via a via hole. The seventh conductor is disposed on the second plane, and one end of the seventh conductor is connected to the other end of the sixth conductor via a via hole. The eighth conductor is disposed on the first plane, and one end of the eighth conductor is connected to the other end of the seventh conductor via a via hole.

3. The coupling loop circuit according to claim 1, characterized in that: The first conductor, the second conductor, the third conductor, and the fourth conductor are each arranged on a first plane of the substrate. The fifth conductor, the sixth conductor, the seventh conductor, and the eighth conductor are each arranged on the second plane of the substrate. The other end of the fourth conductor and one end of the fifth conductor are connected via a via.

4. The coupling loop circuit according to claim 1, characterized in that: The third conductor is arranged in parallel with the first conductor. The fourth conductor is arranged in parallel with the second conductor. The fifth conductor is arranged in parallel with the second conductor. The sixth conductor is arranged in parallel with the first conductor, The seventh conductor is arranged in parallel with the second conductor, The eighth conductor is arranged in parallel with the first conductor.

5. A noise filter circuit, characterized in that: have: The first conductor line includes first to fourth conductors arranged in a loop shape to form a first loop region; The second conductor line includes fifth to eighth conductors arranged in a loop shape to form a second loop region; as well as a capacitor having one end connected to a connection portion between the first conductor line and the second conductor line and the other end connected to a ground line, One end of the first conductor is connected to one end of the second conductor, The other end of the second conductor is connected to one end of the third conductor. The other end of the third conductor is connected to one end of the fourth conductor. The other end of the fourth conductor is connected to one end of the fifth conductor, The other end of the fifth conductor is connected to one end of the sixth conductor, The other end of the sixth conductor is connected to one end of the seventh conductor, The other end of the seventh conductor is connected to one end of the eighth conductor, The sixth conductor and the second conductor are three-dimensionally intersected, The eighth conductor intersects the second conductor and the fourth conductor in a three-dimensional manner. The first loop region and the second loop region overlap in space, and an overlapping region of the first loop region and the second loop region is formed by the second conductor, the fourth conductor, the sixth conductor, and the eighth conductor. The overlapping region is designed so that twice the mutual inductance caused by electromagnetic field coupling between the first conductor line and the second conductor line coincides with the parasitic inductance.

6. The noise filter circuit according to claim 5, characterized in that have: A first coupling loop circuit comprises the first conductor line and the second conductor line; as well as The second coupling loop circuit comprises the first conductor line and the second conductor line. One end of the capacitor is connected to one end of a fifth conductor included in the first coupling loop circuit, and the other end of the capacitor is connected to one end of a fifth conductor included in the second coupling loop circuit instead of being connected to a ground line. The sixth conductor included in the first coupling loop circuit and the second conductor included in the first coupling loop circuit intersect each other in three dimensions. The eighth conductor included in the first coupling loop circuit intersects the second conductor included in the first coupling loop circuit and the fourth conductor included in the first coupling loop circuit in a three-dimensional manner. The sixth conductor included in the second coupling loop circuit intersects the second conductor included in the second coupling loop circuit in a three-dimensional manner. The eighth conductor included in the second coupling loop circuit intersects the second conductor included in the second coupling loop circuit and the fourth conductor included in the second coupling loop circuit in a three-dimensional manner.

7. A circuit generation method, characterized in that: In order to form the first loop region, a first conductor line including first to fourth conductors having a loop shape is wired on the substrate. In order to form a second loop region, a second conductor line including fifth to eighth conductors having a loop shape is wired on the substrate. connecting one end of the first conductor and one end of the second conductor, connecting the other end of the second conductor and one end of the third conductor, connecting the other end of the third conductor and one end of the fourth conductor, connecting the other end of the fourth conductor and one end of the fifth conductor, connecting the other end of the fifth conductor and one end of the sixth conductor, connecting the other end of the sixth conductor and one end of the seventh conductor, connecting the other end of the seventh conductor and one end of the eighth conductor, When the first conductor line and the second conductor line are respectively wired on the substrate, the sixth conductor is three-dimensionally crossed with the second conductor in such a manner that the first loop area and the second loop area overlap in space, and the eighth conductor is three-dimensionally crossed with each of the second conductor and the fourth conductor, and the overlapping area of ​​the first loop area and the second loop area is formed by the second conductor, the fourth conductor, the sixth conductor, and the eighth conductor, The overlapping region is designed so that twice the mutual inductance caused by electromagnetic field coupling between the first conductor line and the second conductor line coincides with the parasitic inductance.

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