Method of forming a semiconductor device

Abstract

The present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate on which fins are formed, the fins including a dense region and a sparse region; forming a spacer between adjacent fins in the sparse region; forming a dielectric layer on the substrate, on sidewalls and at the top of the fins; forming an amorphous silicon layer on the dielectric layer and on sidewalls of the spacer; removing the amorphous silicon layer by a wet etching process, wherein the etching solution of the wet etching process contains alcohol. When the present invention uses the wet etching process to remove the amorphous silicon layer, the etching solution of the wet etching contains alcohol, so that when removing the amorphous silicon layer, the amorphous silicon layer between the spacer and the fins can be completely eliminated or substantially eliminated, and there will be no residual amorphous silicon layer between the fins and the spacer, thereby improving the performance and quality of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor device. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, the device is currently widely used. The traditional planar device has a weakened ability to control the channel current, resulting in a short-channel effect and leakage current, ultimately affecting the electrical performance of the semiconductor device.

[0003] In order to overcome the short-channel effect of the device and suppress the leakage current, the prior art has proposed a fin field-effect transistor (Fin FET). The fin field-effect transistor is a common multi-gate device. The structure of the fin field-effect transistor includes: a fin portion and an isolation structure on the surface of the semiconductor substrate, the isolation structure covering the sidewalls of part of the fin portion, a gate structure located on the substrate and spanning the fin portion; source regions and drain regions in the fin portions on both sides of the gate structure.

[0004] However, with the reduction of the size of semiconductor devices and the increase of device density, the performance of the formed fin field-effect transistors is unstable. Summary of the Invention

[0005] The problem solved by the present invention is to provide a method for forming a semiconductor device, thereby improving the service performance of the semiconductor device.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, including the steps of: providing a substrate on which a fin portion is formed, the fin portion including a dense area and a sparse area; forming a spacer between adjacent fin portions in the sparse area; forming a dielectric layer on the substrate, on the sidewalls and the top of the fin portion; forming an amorphous silicon layer on the dielectric layer and on the sidewalls of the spacer; removing the amorphous silicon layer by a wet etching process, and the etching solution of the wet etching process contains alcohol.

[0007] Optionally, the alcohol is isopropyl alcohol or ethanol or 1,6-hexanediol.

[0008] Optionally, the etching solution further includes an alkaline aqueous solution.

[0009] Optionally, the alkaline aqueous solution is a mixture of an alkaline solution and water, and the alkaline solution is an NH4OH alkaline solution or a TMAH alkaline solution or an EDA alkaline solution or a KOH alkaline solution.

[0010] Optionally, the volume ratio of the alkaline solution to the water ranges from 1:1 to 1:80.

[0011] Optionally, the volume ratio of the alkaline solution to the alcohol ranges from 1:1 to 1:5.

[0012] Optionally, before removing the amorphous silicon layer, it further includes: performing a heat treatment on the amorphous silicon layer.

[0013] Optionally, the heat treatment is a high-temperature annealing treatment.

[0014] Optionally, the temperature range used in the wet etching process is 25°C to 80°C.

[0015] Optionally, before forming the spacer, it further includes: forming an isolation layer on the substrate, and the isolation layer covers a part of the sidewalls of the fins.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] After forming the fins and the spacer on the substrate, a dielectric layer will be formed on the substrate and on the sidewalls and the top of the fins, and this dielectric layer will be used as a gate dielectric layer subsequently; after forming the dielectric layer, an amorphous silicon layer is formed on the dielectric layer and on the sidewalls and the top of the spacer. When using the wet etching process to remove the amorphous silicon layer, since the etching solution in the wet etching process contains alcohol, when removing the amorphous silicon layer, the amorphous silicon layer between the spacer and the fins can be completely removed, and there will be no residual amorphous silicon layer between the fins and the spacer, thereby improving the quality and performance reliability of the semiconductor device. This is because when using the wet etching process to remove the amorphous silicon layer, when the etching solution reacts with the amorphous silicon layer, a large number of hydrogen bubbles will be generated. These hydrogen bubbles adhere to the surface of the amorphous silicon layer to form a pseudo-mask, and the amorphous silicon layer covered by the pseudo-mask is protected, and the etching solution cannot etch it. However, since the etching solution in the wet etching process contains alcohol, the addition of alcohol greatly reduces the surface tension of the etching solution. During the etching process, the hydrogen bubbles generated on the surface of the amorphous silicon layer become small and can quickly leave the surface of the amorphous silicon layer, which prevents the hydrogen bubbles from staying and being unable to form a pseudo-mask, thereby facilitating the etching of the amorphous silicon layer, eliminating the residue of the amorphous silicon layer, and making the formed semiconductor device have reliable performance and high quality. Description of the Drawings

[0018] Figures 1 to 5 A schematic structural diagram of the formation process of a semiconductor device in an embodiment;

[0019] Figures 6 to 11 It is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention. Detailed Embodiments

[0020] With the rapid development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller. As the density of semiconductor devices increases, the performance of the formed semiconductor devices is unstable, which limits the use of semiconductor devices. For the specific formation process, please refer to Figures 1 to 5 .

[0021] First, refer to Figure 1 , a substrate 100 is provided, and fins 110 are formed on the substrate 100. The fins 110 include a dense area 111 and a sparse area 112.

[0022] Refer to Figure 2 To form a spacer 120 between the fins 110 in the sparse area 112.

[0023] Before forming the spacer 120, an isolation layer (not shown in the figure) is formed on the substrate 100.

[0024] Refer to Figure 3 , a dielectric layer 130 is formed on the substrate 100, on the sidewalls and the top of the fins 110.

[0025] Refer to Figure 4 , an amorphous silicon layer 140 is formed on the dielectric layer 130 and on the sidewalls of the spacer 120.

[0026] Refer to Figure 5 , etch to remove the amorphous silicon layer 140.

[0027] The inventor analyzed and found that the performance of the semiconductor devices formed by this formation method is poor, which seriously affects the use of semiconductor devices. From the Figure 5 dotted line, it can be seen that the amorphous silicon layer between the fins and the spacer cannot be removed, resulting in the residue of the amorphous silicon layer and affecting the performance of the semiconductor devices. The reason why the amorphous silicon layer at the dotted line is not removed is as follows: on the one hand, when forming the spacer, the ideal state is that the spacer can be formed exactly in the middle position between adjacent fins. However, as the semiconductor size shrinks, the spacer cannot be accurately formed in the middle position, resulting in one side of the spacer being closer to the fin and the other side being farther from the fin. The smaller the distance, the more difficult it is to remove the amorphous silicon layer; on the other hand, when etching the amorphous silicon layer, the etching solution reacts with the amorphous silicon layer, generating a large number of hydrogen bubbles. These hydrogen bubbles are unevenly attached to the surface of the amorphous silicon layer as a pseudo-mask, preventing the etching from proceeding. However, due to the small distance between the bottom of the fin and the bottom of the spacer, the generated hydrogen bubbles are less likely to escape from the etching liquid. The more hydrogen bubbles accumulate, the stronger the blocking effect on the etching. These two aspects together result in the inability to etch and remove the amorphous silicon layer at the dotted line, thus causing the residue of the amorphous silicon layer and affecting the performance of the formed semiconductor devices.

[0028] The inventors' research found that adding alcohol to the etching solution for removing the amorphous silicon layer can reduce the surface tension of the etching solution by using the alcohol, enabling the hydrogen bubbles generated during the etching process to quickly escape from the etching solution, so that they will not accumulate on the surface of the amorphous silicon layer, preventing the residence of hydrogen bubbles and thus unable to form a pseudo mask, which is beneficial to better etching and removing the amorphous silicon layer, thereby reducing the residue of the amorphous silicon layer and improving the performance of the formed semiconductor device.

[0029] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0030] Figures 6 to 11 It is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention.

[0031] First, refer to Figure 6 , and provide a substrate 200.

[0032] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate 200 may be single crystal silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanide, or gallium arsenide.

[0033] Refer to Figure 7 , and form fins 300 on the substrate 200, and the fins 300 include a dense area 310 and a sparse area 320.

[0034] In this embodiment, the process steps for forming the fins 300 include: forming a patterned layer (not shown in the figure) on the substrate 200, the patterned layer corresponding to the position where the fins 300 need to be formed, using the patterned layer as a mask to etch a part of the thickness of the substrate 200, forming a plurality of discrete fins 300 on the substrate 200, and removing the patterned layer.

[0035] In other embodiments, the process steps for forming the fins 300 may also be depositing a material layer of the fins 300 on the substrate 200, forming a patterned layer on the material layer of the fins 300, the patterned layer corresponding to the position of the formed fins 300, using the patterned layer as a mask to etch the material layer of the fins 300 until the surface of the substrate 200 is exposed, forming a plurality of discrete fins 300 on the substrate 200, and removing the patterned layer.

[0036] In this embodiment, the fin portion 300 includes the sparse region 320 and the dense region 310. The distance between adjacent fin portions 300 in the sparse region 320 is greater than the distance between adjacent fin portions 300 in the dense region 310. This is set according to the actual circuit design requirements.

[0037] In this embodiment, an isolation layer 210 is formed on the substrate 200, and the isolation layer 210 covers a part of the sidewalls of the fin portion 300.

[0038] In this embodiment, the material of the isolation layer 210 is silicon oxide; in other embodiments, the material of the isolation layer 210 is silicon nitride, silicon oxynitride, etc.

[0039] In other embodiments, the isolation layer 210 is not formed on the substrate 200.

[0040] In this embodiment, the purpose of forming the isolation layer 210 on the substrate 200 is, on the one hand, to ensure that the surface of the substrate 200 is not damaged subsequently; on the other hand, the isolation layer 210 isolates adjacent fins to prevent subsequent phenomena such as leakage and short circuit.

[0041] The method of forming the isolation layer 210 includes: forming an isolation layer film (not shown) covering the fin portion 300 on the substrate 200; performing etch-back on the isolation layer film to form the isolation layer 210.

[0042] The process of forming the isolation layer film is a deposition process, such as a fluid chemical vapor deposition process. Using the fluid chemical vapor deposition process to form the isolation layer film makes the filling performance of the isolation layer film better.

[0043] The steps of the fluid chemical vapor deposition process used to form the isolation layer film include: forming an isolation fluid layer on the substrate 200; performing water vapor annealing to make the isolation fluid layer form the isolation layer film.

[0044] The parameters of the water vapor annealing include: the gases used include oxygen, ozone, and gaseous water, and the annealing temperature is 350 degrees Celsius to 750 degrees Celsius.

[0045] Reference Figure 8 , an isolator 400 is formed between adjacent fin portions in the sparse region 320.

[0046] In this embodiment, the function of forming the isolator 400 between adjacent fin portions 300 in the sparse region 320 is to distinguish different functional regions.

[0047] In this embodiment, the top height of the isolator 400 is higher than the top height of the fin portion 300.

[0048] In this embodiment, the material of the spacer 400 is silicon oxide; in other embodiments, the material of the spacer 400 is silicon nitride, silicon oxynitride, etc.

[0049] In this embodiment, the spacer 400 is formed in a conventional manner, and no further description will be given here.

[0050] Reference Figure 9 , a dielectric layer 500 is formed on the substrate 200, on the sidewalls and the top of the fin 300.

[0051] In this embodiment, since the isolation layer 210 is formed on the substrate 200, the dielectric layer 500 is formed on the isolation layer 210, on the sidewalls and the top of the fin 300.

[0052] In this embodiment, the material of the dielectric layer 500 is a high-k dielectric layer (dielectric constant greater than 3.9).

[0053] In this embodiment, before forming the dielectric layer 500, an interface layer 220 is formed on the sidewalls and the top of the fin 300. The purpose of forming the interface layer 220 is to facilitate the adhesion of the dielectric layer 500 on the top and sidewalls of the fin 300, so as to form a dielectric layer 500 with good quality, and at the same time repair the surface of the fin 300.

[0054] The material of the interface layer 220 includes silicon oxide. The process of forming the interface layer 220 includes an oxidation process.

[0055] In this embodiment, the interface layer 220 extends onto the substrate 200.

[0056] In this embodiment, the material of the dielectric layer 500 includes hafnium oxide; in other embodiments, the material of the dielectric layer 500 can also be zirconium oxide, hafnium silicate, lanthanum oxide, zirconium silicate, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate or aluminum oxide, etc.

[0057] In this embodiment, the dielectric layer 500 is formed by a chemical vapor deposition process; in other embodiments, the dielectric layer 500 can also be formed by an atomic layer deposition process or a physical vapor deposition process.

[0058] Reference Figure 10 , an amorphous silicon layer 600 is formed on the dielectric layer 500 and on the sidewalls of the spacer 400.

[0059] In this embodiment, before forming the amorphous silicon layer 600, it further includes: forming a TiN layer 510 on the substrate 200, on the sidewalls and the top of the fin 300.

[0060] In this embodiment, the purpose of forming the TiN layer 510 is to use the TiN layer 510 as a barrier layer to play a blocking role.

[0061] In this embodiment, since the material of the dielectric layer 500 is a high-k dielectric layer and there are many oxygen vacancies in the dielectric layer 500, it is necessary to remove the oxygen vacancies. Therefore, it is necessary to form the amorphous silicon layer 600 on the sidewalls of the dielectric layer 500 and the spacer 400.

[0062] Reference Figure 11 , a wet etching process is used to remove the amorphous silicon layer 600, and the etching solution of the wet etching process contains alcohol.

[0063] In this embodiment, the alcohol is isopropyl alcohol; in other embodiments, the alcohol can also be ethanol or 1,6-hexanediol.

[0064] In this embodiment, since when the amorphous silicon layer 600 is removed by wet etching, the etching solution of the wet etching contains alcohol, the formed amorphous silicon layer 600 can be completely removed, thereby eliminating the residue of the amorphous silicon layer 600 and improving the quality of the formed semiconductor device. This is because adding alcohol to the etching solution can reduce the liquid surface tension of the etching solution. Reducing the liquid surface tension of the etching solution means that when bubbles are generated in the etching solution, the bubbles can quickly escape from the etching solution. In this way, when hydrogen bubbles are generated by the chemical reaction between the etching solution and the amorphous silicon layer 600, the hydrogen bubbles can quickly escape from the etching liquid and will not stay on the surface of the amorphous silicon layer 600 as a pseudo mask, thus not preventing the progress of the etching reaction process and enabling the amorphous silicon layer 600 to be well removed. This method has good compatibility with the CMOS process and low cost, improving the performance and reliability of the semiconductor device.

[0065] In this embodiment, the etching solution further includes an alkaline aqueous solution, which is the main reaction substance that reacts with the amorphous silicon layer 600 to remove the amorphous silicon layer 600.

[0066] In this embodiment, the alkaline aqueous solution is a mixture of an alkaline solution and water.

[0067] In this embodiment, the alkaline solution is an NH4OH solution; in other embodiments, the alkaline solution can also be a TMAH alkaline solution or an EDA alkaline solution or a KOH alkaline solution.

[0068] In this embodiment, the alkaline aqueous solution is a mixed solution of an NH4OH solution and water, and the reaction mechanism between the alkaline aqueous solution and the amorphous silicon layer 600 is Si + NH4OH + H2O → Si(OH)62- +H2. It can be seen from the reaction mechanism that a large amount of hydrogen is generated during the etching of the amorphous silicon layer 600. Hydrogen is insoluble in water, resulting in a large number of hydrogen bubbles in the etching solution. If the surface tension of the etching solution is very high, the hydrogen bubbles are not easily released from the etching solution, leading to an aggregation phenomenon. This will act as a pseudo-mask on the surface of the amorphous silicon layer 600, preventing the etching from continuing and being unfavorable for the removal of the amorphous silicon layer 600. However, if the surface tension of the etching solution is reduced, the formed hydrogen bubbles can easily escape from the etching solution, thus not preventing the etching process and facilitating the etching and removal of the amorphous silicon layer 600.

[0069] In this embodiment, the reason why adding isopropyl alcohol to the etching solution can reduce the surface tension of the etching solution is that isopropyl alcohol also has a significant effect on reducing the surface tension of the etching solution. In an aqueous solution, the hydroxyl group in isopropyl alcohol is tightly bound to water molecules through hydrogen bonds, while the alkyl groups on both sides have a weaker binding force with water molecules. In this way, compared with the water molecules originally bound by hydrogen bonds, the intermolecular force between water molecules is greatly reduced, which significantly reduces the surface tension of the etching solution.

[0070] In this embodiment, the volume ratio range of the alkaline solution to the water is between 1:1 and 1:80, that is, the volume ratio of the NH4OH alkaline solution to the water is between 1:1 and 1:80. When the volume ratio of the NH4OH alkaline solution to the water is greater than 1:1, the volume of the NH4OH alkaline solution is relatively large at this time, and the concentration of the formed alkaline aqueous solution is too high, resulting in damage to the TiN layer 510 during the etching and removal of the amorphous silicon layer 600. The TiN layer 510 cannot be etched during the formation of semiconductor devices, otherwise it will cause damage to the formed fin 300 by diffused ions. When the volume ratio of the NH4OH alkaline solution to the water is less than 1:80, the mass of water is relatively large at this time, and the concentration of the formed alkaline aqueous solution is too low. When etching and removing the amorphous silicon layer 600, due to the too low concentration of the formed alkaline aqueous solution, it cannot react sufficiently with the amorphous silicon layer 600, making it impossible to etch and remove the formed amorphous silicon layer 600 and unable to meet the actual process requirements.

[0071] In this embodiment, an alkaline aqueous solution is formed by using a volume ratio of the NH4OH alkaline solution to the water of 1:5. This is because this ratio can ensure the etching rate of removing the amorphous silicon layer 600 while ensuring no damage to the TiN layer 510 at the bottom of the amorphous silicon layer 600.

[0072] In this embodiment, the volume ratio of the alkaline solution to the alcohol ranges from 1:1 to 1:5, that is, the volume ratio of the NH4OH alkaline solution to the alcohol is 1:1 to 1:5. When the volume ratio of the NH4OH alkaline solution to the alcohol is greater than 1:1, the volume of the alcohol added at this time is small, and the volume of the NH4OH alkaline solution is large. At this time, the reaction is intense and a large amount of hydrogen gas is generated. However, due to the small volume of the alcohol added, the surface tension of the liquid is not sufficiently reduced, so the hydrogen gas generated cannot escape from the etching solution in time, resulting in the accumulation of hydrogen gas, forming a pseudo mask, affecting the etching effect of the amorphous silicon layer 600, and easily causing residues of the amorphous silicon layer 600; when the volume ratio of the NH4OH alkaline solution to the alcohol is less than 1:5, the volume of the alcohol added is too large, and the volume of the NH4OH alkaline solution is relatively small, resulting in insufficient alkaline substances to react with the amorphous silicon layer 600, so that the speed of etching and removing the amorphous silicon layer 600 becomes slow, affecting the production efficiency.

[0073] In this embodiment, the volume ratio of the alkaline solution of NH4OH to the alcohol is 1:1. This is because this ratio can not only ensure the rate of removing the amorphous silicon layer 600, but also well reduce the surface tension of the etching liquid, so that the formation rate of hydrogen gas and the rate of hydrogen gas escaping from the liquid are balanced.

[0074] In this embodiment, the process temperature range of the wet etching process is 25°C to 80°C.

[0075] In this embodiment, the advantage of using the above wet etching process parameters for wet etching is that compared with dry etching, the interface layer 220 and the fin portion 300 will not be damaged by plasma, thus ensuring the formation quality of the interface layer 220 and the fin portion 300, and improving the quality of the formed semiconductor device.

[0076] In this embodiment, before removing the amorphous silicon layer 600, it further includes: performing heat treatment on the amorphous silicon layer 600.

[0077] In this embodiment, the purpose of performing heat treatment is to remove oxygen vacancies in the high-k dielectric layer.

[0078] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, Including the steps of: Providing a substrate on which fins are formed, the fins including a dense region and a sparse region; Forming a spacer between adjacent fins in the sparse region for differentiating different functional regions, the spacer being in an inverted trapezoidal shape; Forming a dielectric layer on the substrate, on sidewalls and at the top of the fins; Forming an amorphous silicon layer on the dielectric layer and on sidewalls of the spacer; Removing the amorphous silicon layer by a wet etching process, the etching solution of the wet etching process containing an alcohol; Before forming the amorphous silicon layer, it further includes: forming a TiN layer on the substrate, on sidewalls and at the top of the fins.

2. The method for forming a semiconductor device according to claim 1, wherein, The alcohol is isopropyl alcohol or ethanol or 1,6 - hexanediol.

3. The method for forming a semiconductor device according to claim 1, wherein The etching solution further includes an alkaline aqueous solution.

4. The method for forming a semiconductor device according to claim 3, wherein, The alkaline aqueous solution is a mixture of an alkaline solution and water, and the alkaline solution is an NH4OH alkaline solution or a TMAH alkaline solution or an EDA alkaline solution or a KOH alkaline solution.

5. The method for forming a semiconductor device according to claim 4, wherein, The volume ratio range of the alkaline solution to the water is 1:1 to 1:

80.

6. The method for forming a semiconductor device according to claim 4, wherein, The volume ratio range of the alkaline solution to the alcohol is 1:1 to 1:

5.

7. The method for forming a semiconductor device according to claim 1, wherein, Before removing the amorphous silicon, it further includes: performing a heat treatment on the amorphous silicon layer.

8. The method for forming a semiconductor device according to claim 7, wherein The heat treatment is a high - temperature annealing treatment.

9. The method for forming a semiconductor device according to claim 1, wherein, The temperature range adopted by the wet etching process is 25°C to 80°C.

10. The method for forming a semiconductor device according to claim 1, wherein, Before forming the spacer, it further includes: forming an isolation layer on the substrate, the isolation layer covering a part of sidewalls of the fins.

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