Printed Circuit Board

Abstract

The present invention provides a printed circuit board, which includes: a substrate having a first surface and a second surface opposite to the first surface, and having a through portion penetrating between the first surface and the second surface; and a through hole disposed in at least a part of the through portion, wherein the through hole includes a first metal layer, the first metal layer has a first groove portion facing the inside of the through portion from the first surface of the substrate and a second groove portion facing the inside of the through portion from the second surface of the substrate, and the first metal layer has a first region and a second region, and the first region and the second region have different average grain sizes.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0001424, filed with the Korean Intellectual Property Office on January 6, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] In the case of using a thick core substrate or in the case of a multilayer substrate, a conductive material may be formed along the wall of a via hole and a via filled with an insulating material (such as a plated through hole (PTH)) may be used. However, in this case, there is a problem in that the reliability and heat dissipation characteristics of the product may be reduced due to the introduction of the insulating material.

[0004] In addition, in the case of a multilayer substrate, stacked vias or staggered vias (wherein a plurality of vias are connected in the vertical direction) may be considered. However, even in this case, the process may be complicated and the manufacturing cost may be increased, and defects such as cracks and delamination of the vias may occur.

[0005] Therefore, it may be desirable to form a filled via in a through portion penetrating a thick core substrate or a multilayer substrate, but voids may occur when plating is performed in a simple manner to fill the through portion. Summary of the Invention

[0006] One aspect of the present disclosure is to provide a printed circuit board including a filled through via without voids.

[0007] Another aspect of the present disclosure is to provide a printed circuit board having improved heat dissipation characteristics and reliability.

[0008] According to one aspect of the present disclosure, a printed circuit board includes: a substrate having a first surface and a second surface opposite to the first surface, and having a through portion penetrating between the first surface and the second surface; and a through via filling at least a part of the through portion, wherein the through via includes a first metal layer having a first groove portion facing the inside of the through portion from the first surface of the substrate and a second groove portion facing the inside of the through portion from the second surface of the substrate, and the first metal layer has a first region and a second region having different average grain sizes.

[0009] According to one aspect of the present disclosure, a printed circuit board includes: a substrate having a first surface and a second surface opposite to the first surface, and having a through portion penetrating between the first surface and the second surface; and a through hole disposed in at least a part of the through portion. The through hole includes regions where a first crystal grain and a second crystal grain are respectively disposed. The region where the first crystal grain is disposed is disposed between the regions where the second crystal grains are disposed. The first crystal grain and the second crystal grain have different average crystal grain sizes. The width of each of the regions where the second crystal grains are disposed increases first and then decreases in a direction from the first surface to the second surface or in a direction from the second surface to the first surface. Description of the Drawings

[0010] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic cross-sectional view of a first plating layer of a printed circuit board 100A according to an example;

[0012] Figure 2 is a schematic cross-sectional view of a printed circuit board 100A according to an example;

[0013] Figures 3A to 3B is a cross-sectional photograph of a first plating layer and a second plating layer of a printed circuit board 100A according to an example;

[0014] Figure 4 is a schematic cross-sectional view of a printed circuit board 100B according to another example;

[0015] Figure 5 is a schematic cross-sectional view of a printed circuit board 100C according to another example;

[0016] Figure 6 is a schematic cross-sectional view of a printed circuit board 100D according to another example;

[0017] Figure 7 is a schematic cross-sectional view of a printed circuit board 100E according to another example; and

[0018] Figure 8 is a schematic cross-sectional view of a printed circuit board 100F according to another example. Detailed Description of the Embodiments

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0020] Printed circuit board

[0021] Figure 1It is a schematic cross-sectional view of the first plating layer of the printed circuit board 100A according to the example.

[0022] Figure 2 It is a schematic cross-sectional view of the printed circuit board 100A according to the example.

[0023] Figures 3A to 3B It is a schematic cross-sectional photograph of the first plating layer and the second plating layer of the printed circuit board 100A according to the example.

[0024] Referring to Figures 1 to 3B According to the example, the printed circuit may include: a substrate 110 having a first surface 110-1 and a second surface 110-2 opposite to the first surface 110-1, and having a through portion H penetrating between the first surface 110-1 and the second surface 110-2; and a through hole V filling at least a part of the through portion H.

[0025] The through hole V may include a first metal layer 120, a second metal layer 130, and a third metal layer 140.

[0026] The first metal layer 120 may be respectively disposed on the wall surface (not marked) of the through portion H, on the first surface 110-1 of the substrate 110, and on the second surface 110-2 of the substrate 110, and may be covered by the second metal layer 130.

[0027] The second metal layer 130 may fill at least a part of the through portion H of the substrate 110, and may have a first groove portion G1 facing the inside of the through portion H from the first surface 110-1 of the substrate 110 and a second groove portion G2 facing the inside of the through portion H from the second surface 110-2 of the substrate 110. The shape of each of the first groove portion G1 and the second groove portion G2 is not particularly limited. In the drawings, each of the first groove portion G1 and the second groove portion G2 is shown as having a smoothly curved shape, but is not limited thereto.

[0028] In addition, the second metal layer 130 may have a first region 131, a second region 132, and a third region 133. The second region 132 may have a 2-1 region 132-1 and a 2-2 region 132-2, and the third region 133 may include a 3-1 region 133-1 and a 3-2 region 133-2. The boundaries between the first region 131, the second region 132, and the third region 133 may not be clear, and it may be difficult to determine the exact boundaries with the naked eye. The shape of the boundary surface of the first region 131, the second region 132, and the third region 133 of the second metal layer 130 is not particularly limited. In the drawings, the boundary surface between the first region 131, the second region 132, and the third region 133 is shown as having a smoothly curved shape, but is not limited thereto.

[0029] The first region 131 of the second metal layer 130 may be disposed in the central portion of the substrate 110 in its thickness direction. Accordingly, the second region 132 and the third region 133 may be further disposed on both sides of the first region 131 in the through-hole H. Additionally, the central portion may be a term for describing the relative arrangement relationship among the first region 131, the second region 132, and the third region 133, and the central portion may not be construed as being limited to the center in the thickness direction between the first surface 110-1 and the second surface 110-2 of the substrate 110.

[0030] The surface of the first region 131 of the second metal layer 130 may have a structure in which a region corresponding to the central axis C of the through-hole V is recessed into the through-hole H. For example, the surface of the first region 131 of the second metal layer 130 may have a structure recessed inwardly facing the interior of the through-hole H.

[0031] The second region 132 of the second metal layer 130 may include a 2-1 region 132-1 facing the interior of the second metal layer 130 from the surface of the first groove portion G1 and a 2-2 region 132-2 facing the interior of the second metal layer 130 from the surface of the second groove portion G2. In addition, the first region 131 may be disposed between the 2-1 region 132-1 and the 2-2 region 132-2 of the second metal layer 130.

[0032] Each of the 2-1 region 132-1 and the 2-2 region 132-2 of the second metal layer 130 may have a convex shape in which the width of the cross-section increases and then decreases from the surface of each of the first groove portion G1 and the second groove portion G2 facing the interior of the second metal layer 130.

[0033] In this specification, the width may represent: in a cross-section, the distance measured in a direction perpendicular to the direction from the first surface 110-1 to the second surface 110-2 of the substrate 110 or in a direction perpendicular to the direction from the second surface 110-2 to the first surface 110-1 of the substrate 110.

[0034] The third region 133 of the second metal layer 130 may include: a 3-1 region 133-1 extending from the wall surface of the through-hole H and surrounding at least a part of the 2-1 region 132-1; and a 3-2 region 133-2 extending from the wall surface of the through-hole H and surrounding at least a part of the 2-2 region 132-2. For example, the 3-1 region 133-1 may fill at least a part of the space between the wall surface of the through-hole H and the 2-1 region 132-1. Similarly, the 3-2 region 133-2 may fill at least a part of the space between the wall surface of the through-hole H and the 2-2 region 132-2.

[0035] In addition, the first region 131, the second region 132, and the third region 133 of the second metal layer 130 may have different average grain sizes.

[0036] The average grain size of the first region 131 may be smaller than the average grain size of the second region 132. For example, the average grain size of the first region 131 may be smaller than the average grain size of each of the 2-1 region 132-1 and the 2-2 region 132-2 of the second metal layer 130. If desired, the average grain size of the third region 133 may be smaller than the average grain size of the second region 132. For example, the second metal layer 130 may have the largest average grain size in the second region 132.

[0037] The average grain size of the first region 131 may be larger than the average grain size of the third region 133, and the average grain size of each of the first region 131 and the third region 133 may be substantially similar. However, the present disclosure is not limited thereto, and the average grain size of the first region 131 may be smaller than the average grain size of the third region 133.

[0038] The large average grain size and the small average grain size are based on the average value of the grain sizes included in each region. The average grain size may be based on the average particle diameter of the grains included in each region.

[0039] In addition, the sum of the thickness T2a of the 2-1 region 132-1 and the thickness T2b of the 2-2 region 132-2 of the second metal layer 130 may be greater than the thickness T1 of the first region 131. That is, the relationship: T2a + T2b > T1 may be satisfied. In addition, each of the thickness T2a of the 2-1 region 132-1 and the thickness T2b of the 2-2 region 132-2 of the second metal layer 130 may be thicker than the thickness T1 of the first region 131.

[0040] In this specification, the thickness may represent the distance measured in the direction from the first surface 110-1 of the substrate 110 to the second surface 110-2 or in the direction from the second surface 110-2 of the substrate 110 to the first surface 110-1. In addition, the thickness may be measured in a region corresponding to the central axis C of the via V.

[0041] The third metal layer 140 may be disposed on the second metal layer 130 and may fill at least a part of each of the first groove portion G1 and the second groove portion G2. The average grain size of the grains in the third metal layer 140 may be smaller than the average grain size of the second region 132 of the second metal layer 130.

[0042] The thickness T3 of the second metal layer 130 can be greater than the sum of the thickness T4a of the region of the third metal layer 140 filling the first groove portion G1 and the thickness T4a of the region of the third metal layer 140 filling the second groove portion G2. That is, the relationship: T3>T4a+T4b can be satisfied. Here, the thickness T3 of the second metal layer 130 can be equal to T1+T2a+T2b (which is the sum of the thickness of the first region and the thickness of the second region of the second metal layer 130). In addition, the thickness T3 of the second metal layer 130 can be greater than each of the thickness T4a of the region of the third metal layer 140 filling the first groove portion G1 and the thickness T4b of the region of the third metal layer 140 filling the second groove portion G2.

[0043] In addition, each of the first metal layer 120, the second metal layer 130, and the third metal layer 140 can extend to and be disposed on the first surface 110-1 and the second surface 110-2 of the substrate 110. Thus, each of the first metal layer 120, the second metal layer 130, and the third metal layer 140 can form via pads and / or wiring patterns.

[0044] In addition, in the case of using a thick core substrate or a multi-layer substrate, a conductive material can be formed along the wall of the via hole and a via hole with an insulating material filled in its interior (e.g., a plated through hole (PTH)) can be used. However, in this case, there are the following problems: the reliability and heat dissipation characteristics of the product are reduced due to the introduction of the insulating material.

[0045] In addition, in the case of a multi-layer structure, a stacked via or a staggered via in which a plurality of vias are connected in the vertical direction can be considered. However, even in this case, there are the following problems: the process may be complex and the manufacturing cost may increase, and defects such as cracks and delamination of the via may also occur.

[0046] Therefore, it is desirable to form a filled via in the through portion penetrating the thick core substrate or the multi-layer substrate, but when plating is performed in a simple manner to fill the interior of the through portion, voids may occur.

[0047] However, according to the present disclosure, the growth rate of the plating grains can be finely controlled to fill the interior of the through portion without voids, thereby forming a filled through via independent of the depth of the through portion. Therefore, the process can be simplified, the manufacturing cost can be reduced, and the heat dissipation characteristics and reliability of the substrate can also be improved.

[0048] In addition, the substrate 110 may include an insulating layer 111. A thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material (such as glass cloth or glass fabric) (for example, prepreg (PPG), ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used as the forming material of the insulating layer 111. If necessary, a photosensitive dielectric (PID) resin can be used.

[0049] In addition, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof can be used as the forming material for each of the first metal layer 120, the second metal layer 130, and the third metal layer 140. The forming materials for each of the first metal layer 120, the second metal layer 130, and the third metal layer 140 may include the same material and may include different materials from each other.

[0050] The first metal layer 120 may be a metal seed layer that can be used to improve the bonding force between the insulating layer and the second metal layer 130. The second metal layer 130 may be a bridge layer that mainly fills the wall surface of the through-hole H and can be formed by pulse periodic reverse (PPR) electroplating in which the direction of the pulse current is periodically reversed. The third metal layer 140 may be a plating layer that secondarily fills the wall surface of the through-hole H and can be formed by direct current (DC) electroplating. The second metal layer 130 may be referred to as the first plating layer, and the third metal layer 140 may be referred to as the second plating layer.

[0051] For example, the first metal layer 120, which is a seed layer for plating by electroless plating and / or electroplating, can be formed, and then a current can be applied to the first metal layer 120 in a PPR manner, thereby forming the second metal layer 130. In this case, the waveform conditions of the PPR may have multiple steps (for example, five steps or more), and the current density and time in each step may be the same or different from each other. However, from the viewpoint of controlling the growth rate of the plated grains described above, it may be preferable to maintain the average value (Iavg) of the current density, which is closely related to the plating rate, at 1.5 ASD (A / dm 2) or less. In this case, the growth rate of the plated grains can be easily controlled to form a plurality of regions 131, 132, and 133 having the above-mentioned average grain size. As a result, the phenomenon of lack of supply of metal ions in the process of forming the bridge layer by plating can be prevented, thereby suppressing the appearance of voids. Thereafter, the second metal layer 130 can be plated in a DC manner to form the third metal layer 140. Therefore, there may be a visible boundary between the first metal layer 120 and the second metal layer 130, and there may be a visible boundary between the second metal layer 130 and the third metal layer 140. The boundaries between the above-mentioned regions of the second metal layer 130 may also be visible.

[0052] Figure 4 is a schematic cross-sectional view of a printed circuit board 100B according to another example.

[0053] Referring to Figure 4 , in the printed circuit board 100B according to another example, the through hole V in the printed circuit board 100A according to the example may further include a fourth metal layer 114, and the fourth metal layer 114 is respectively disposed on the first surface 110-1 and the second surface 110-2 of the substrate 110 and is covered by the first metal layer 120.

[0054] The substrate 110 may have an insulating layer 111 and a fourth metal layer 114 (such as a metal foil, etc.) disposed on the insulating layer 111. For example, the substrate 110 may be a copper-clad laminate (CCL) having copper foils attached to one surface or two surfaces of the insulating layer 111.

[0055] In addition, unnecessary portions of the metal foil can be removed in a process such as etching, and the remaining metal foil after the removal process can become Figure 4 the fourth metal layer 114 shown in

[0056] Other details are substantially the same as those described in the printed circuit board 100A according to the example, and the detailed description thereof will be omitted.

[0057] Figure 5 is a schematic cross-sectional view of a printed circuit board 100C according to another example.

[0058] Referring to Figure 5 , in the printed circuit board 100C according to another example, the substrate 110 in the printed circuit board 100A according to the example may include: a plurality of insulating layers 111; a plurality of wiring layers 112 respectively disposed on the plurality of insulating layers 111; and a plurality of via layers 113 penetrating each of the plurality of insulating layers 111 and connecting the plurality of wiring layers 112 to each other.

[0059] The number of each of the plurality of insulating layers 111, the plurality of wiring layers 112, and the plurality of via layers 113 can be changed according to the design. That is, the number of each of the plurality of insulating layers 111, the plurality of wiring layers 112, and the plurality of via layers 113 can be greater than or less than the number shown in the drawings.

[0060] Each of the first surface 110-1 and the second surface 110-2 of the substrate 110 can be based on the insulating layer 111. Accordingly, at least a part of the wiring layer 112 can be provided on each of the first surface 110-1 and the second surface 110-2 of the substrate.

[0061] The through via V can be formed by a plating method according to an example, and thus the through via V that penetrates the multilayer substrate without voids can be formed.

[0062] A thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material (such as glass cloth or glass fabric) (for example, prepreg (PPG), ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used as a forming material for each of the plurality of insulating layers 111. If necessary, a photosensitive dielectric (PID) resin can be used. The forming materials for each of the plurality of insulating layers 111 can include the same material or different materials from each other.

[0063] Each of the plurality of wiring layers 112 can provide various wirings. Each of the plurality of wiring layers 112 can include, for example, a ground pattern, a power pattern, a signal pattern, etc.

[0064] A metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof can be used as a forming material for each of the plurality of wiring layers 112. The forming materials for each of the plurality of wiring layers 112 can include the same material and can include different materials from each other.

[0065] Each of the plurality of wiring layers 112 can include a plurality of metal layers. For example, each of the plurality of wiring layers 112 can include a metal seed layer and a metal plating layer. The metal seed layer can be formed together with the first metal layer 120, and thus can have the same thickness as the first metal layer 120.

[0066] Each of the plurality of via layers 113 can perform various functions according to its design. For example, each of the plurality of via layers 113 can include a connection via for signal connection, a connection via for ground connection, a connection via for power connection, etc.

[0067] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys can be used as the formation material for vias included in each of the plurality of via layers 113. The vias included in each of the plurality of via layers 113 can be filled vias in which the interior of the via hole is completely filled with a conductive material, or can be formed by forming a conductive material along the walls of the via hole. When the via is formed by forming a conductive material along the walls of the via hole, the interior of the via hole can be filled with an insulating material.

[0068] In addition, the vias included in each of the plurality of via layers 113 can have known shapes, such as a cylindrical shape, a conical shape, etc. When the vias included in each of the plurality of via layers 113 have a conical shape, a part of the vias included in each of the plurality of via layers 113 can have a conical shape along the same direction as each other, and another part of the vias can have a conical shape along the opposite direction. The vias included in each of the plurality of via layers 113 can also have a conical shape along the same direction.

[0069] Furthermore, the sum of the thicknesses of the first metal layer 120, the second metal layer 130, and the third metal layer 140 can be substantially the same as the thickness of the wiring layer 112 provided on the first surface 110-1 of the substrate 110. Here, the sum of the thicknesses of the first metal layer 120, the second metal layer 130, and the third metal layer 140 can refer to the sum of the thicknesses of the portions of the first metal layer 120, the second metal layer 130, and the third metal layer 140 provided on the first surface 110-1 of the substrate 110. Similarly, the sum of the thicknesses of the first metal layer 120, the second metal layer 130, and the third metal layer 140 can be substantially the same as the thickness of the wiring layer 112 provided on the second surface 110-2 of the substrate 110. Here, the sum of the thicknesses of the first metal layer 120, the second metal layer 130, and the third metal layer 140 can refer to the sum of the thicknesses of the portions of the first metal layer 120, the second metal layer 130, and the third metal layer 140 provided on the second surface 110-2 of the substrate 110. Substantially the same is a concept that encompasses not only the case of being exactly the same but also the error ranges that may occur in the structure and / or process.

[0070] The through via V can be connected to at least one of the plurality of wiring layers 112. Therefore, the through via V can be used to connect a part of the plurality of wiring layers 112 to each other.

[0071] Other details are substantially the same as those described in the printed circuit board 100A according to the example, and the detailed description thereof will be omitted.

[0072] Figure 6It is a schematic cross-sectional view of a printed circuit board 100D according to another example.

[0073] Referring to Figure 6 , the printed circuit board 100D according to another example may further include a fourth metal layer 114 in the printed circuit board 100C according to the example. The fourth metal layer 114 is respectively disposed on the first surface 110-1 and the second surface 110-2 of the substrate 110 and is covered by the first metal layer 120.

[0074] As shown in the drawings, the fourth metal layer 114 may also be disposed between the first surface 110-1 of the substrate 110 and the wiring layer 112 disposed on the first surface 110-1 of the substrate 110. Similarly, the fourth metal layer 114 may also be disposed between the second surface 110-2 of the substrate 110 and the wiring layer 112 disposed on the second surface 110-2 of the substrate 110.

[0075] The substrate 110 may have an insulating layer 111 and a fourth metal layer 114 (such as a metal foil) disposed on the insulating layer 111. For example, the substrate 110 may be a copper-clad laminate (CCL) having copper foils attached to one or both surfaces of the insulating layer 111.

[0076] In addition, unnecessary portions of the metal foil may be removed in a process such as etching, and the remaining metal foil after the removal process may become Figure 6 the fourth metal layer 114 shown in

[0077] Other details are substantially the same as those described in the printed circuit board 100C according to another example, and its detailed description will be omitted.

[0078] Figure 7 It is a schematic cross-sectional view of a printed circuit board 100E according to another example.

[0079] Referring to Figure 7 , the printed circuit board 100E according to another example may further include a stacked layer 210 in the printed circuit board 100A according to the example. The stacked layer 210 is respectively disposed on the first surface 110-1 and the second surface 110-2 of the substrate 110.

[0080] The stacked layer 210 may include an insulating layer 211, a wiring layer 212 disposed on the insulating layer 211, and a via layer 213 that penetrates the insulating layer 211 and connects the through via V and the wiring layer 212.

[0081] In the drawings, although the stacked layer 210 is shown as being disposed on the first surface 110-1 and the second surface 110-2 of the substrate 110, the stacked layer 210 may be disposed on only any one of the first surface 110-1 and the second surface 110-2 of the substrate 110.

[0082] In addition, the number of each of the insulating layer 211, the wiring layer 212, and the via layer 213 included in the stacked layer 210 may be greater than the number shown in the drawings. That is, each of the insulating layer 211, the wiring layer 212, and the via layer 213 may be a plurality of insulating layers 211, a plurality of wiring layers 212, and a plurality of via layers 213, respectively. In this case, the number of each of the insulating layer 211, the wiring layer 212, and the via layer 213 included in the stacked layer 210 on the first surface 110-1 of the substrate 110 may be the same as or different from the number of each of the insulating layer 211, the wiring layer 212, and the via layer 213 included in the stacked layer 210 on the second surface 110-2 of the substrate 110.

[0083] In addition, the substrate 110 may be a thick core substrate having a thickness greater than the thickness of the insulating layer 211. The through via V may be formed by a plating method according to an example, and thus, a through via V that penetrates the core substrate without voids may be formed.

[0084] A thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material (such as glass cloth or glass fabric) (for example, prepreg (PPG), ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) may be used as a material for forming the insulating layer 211. If necessary, a photosensitive dielectric (PID) resin may be used.

[0085] The wiring layer 212 may provide a plurality of wirings. For example, the wiring layer 212 may include a ground pattern, a power pattern, a signal pattern, etc.

[0086] A metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used as a material for forming the wiring layer 212.

[0087] The via layer 213 may perform various functions according to the design. For example, the via layer 213 may include a connection via for signal connection, a connection via for ground connection, a connection via for power connection, etc.

[0088] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys can be used as the formation material for vias included in via layer 213. The vias included in via layer 213 can be filled vias in which the interior of the via holes are completely filled with a conductive material, or can be formed by forming a conductive material along the walls of the via holes. When the vias are formed by forming a conductive material along the walls of the via holes, the interior of the via holes can be filled with an insulating material.

[0089] The vias included in via layer 213 can have known shapes, such as a cylindrical shape, a conical shape, etc.

[0090] Figure 8 is a schematic cross-sectional view of printed circuit board 100F according to another example.

[0091] Refer to Figure 8 , printed circuit board 100F according to another example can further include a fourth metal layer 114 in printed circuit board 100E according to another example. The fourth metal layer 114 is respectively disposed on the first surface 110-1 and the second surface 110-2 of the substrate 110 and is covered by the first metal layer 120.

[0092] The substrate 110 can have an insulating layer 111 and a fourth metal layer 114 (such as a metal foil) disposed on the insulating layer 111. For example, the substrate 110 can be a copper-clad laminate (CCL) having copper foils attached to one surface or both surfaces of the insulating layer 111.

[0093] In addition, unnecessary portions of the metal foil can be removed in a process such as etching, and the remaining metal foil after the removal process can become Figure 8 the fourth metal layer 114 shown in

[0094] Other details are substantially the same as those described in printed circuit board 100E according to another example, and thus their detailed descriptions will be omitted.

[0095] Furthermore, the above-mentioned stacked layer 210 can be disposed in printed circuit boards 100C and 100D.

[0096] Throughout the specification, it will be understood that when an element such as a layer, region, or wafer (substrate) is referred to as being "on" another element, "connected to" another element, or "coupled to" another element, the element can be directly "on" the other element, directly "connected to" the other element, or directly "coupled to" the other element, or there can be other elements intervening between them. In contrast, when an element is referred to as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there can be no elements intervening between them. The same reference numerals always denote the same elements. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of two or more of the associated listed items. It will be apparent that, although the terms "first", "second", and "third", etc. may be used herein to describe various components, assemblies, regions, layers, and / or portions, these components, assemblies, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, assembly, region, layer, or portion from another component, assembly, region, layer, or portion. Thus, without departing from the teachings of the exemplary embodiments, the first component, first assembly, first region, first layer, or first portion discussed above could also be referred to as the second component, second assembly, second region, second layer, or second portion.

[0097] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms. It will be further understood that the term "comprising" as used in this specification, lists the presence of stated features, integers, steps, operations, components, elements, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof.

[0098] As described above, according to an embodiment of the present disclosure, a printed circuit board including a void-free filled through-hole can be provided.

[0099] According to another aspect of the present disclosure, a printed circuit board having improved heat dissipation characteristics and reliability can be provided.

[0100] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a substrate having a first surface and a second surface opposite to the first surface, and having a through portion penetrating between the first surface and the second surface; and a through hole disposed in at least a part of the through portion, wherein the through hole includes a first metal layer having a first groove portion facing the inside of the through portion from the first surface of the substrate and a second groove portion facing the inside of the through portion from the second surface of the substrate, and the first metal layer has a first region and a second region having different average grain sizes, wherein the first region of the first metal layer includes: a first - 1 region facing the inside of the first metal layer from the surface of the first groove portion; and a first - 2 region facing the inside of the first metal layer from the surface of the second groove portion, the second region of the first metal layer is disposed between the first - 1 region and the first - 2 region, and the average grain size in the first - 1 region and the first - 2 region is greater than the average grain size in the second region.

2. The printed circuit board according to claim 1, wherein, the sum of the thicknesses of the first - 1 region and the first - 2 region is greater than the thickness of the second region located between the first - 1 region and the first - 2 region.

3. The printed circuit board according to claim 2, wherein, each of the thicknesses of the first - 1 region and the first - 2 region is greater than the thickness of the second region located between the first - 1 region and the first - 2 region.

4. The printed circuit board according to claim 1, wherein, the first - 1 region of the first metal layer has a convex shape in which the width of the cross - section increases and then decreases from the surface of the first groove portion facing the inside of the first metal layer, and the first - 2 region of the first metal layer has a convex shape in which the width of the cross - section increases and then decreases from the surface of the second groove portion facing the inside of the first metal layer.

5. The printed circuit board according to claim 1, wherein, the first metal layer further includes a third region, and the third region includes: a third - 1 region extending from the wall surface of the through portion and surrounding at least a part of the first - 1 region; and a third - 2 region extending from the wall surface of the through portion and surrounding at least a part of the first - 2 region.

6. The printed circuit board according to claim 5, wherein, the average grain size in the third region is greater than the average grain size in the second region and less than the average grain size in the first region; or the average grain size in the second region is greater than the average grain size in the third region and less than the average grain size in the first region.

7. The printed circuit board according to claim 1, wherein, the through hole further includes a second metal layer disposed on the first metal layer, and The second metal layer is disposed in at least a portion of each of the first groove portion and the second groove portion.

8. The printed circuit board according to claim 7, wherein, the thickness of the first metal layer is greater than the sum of the thickness of the region of the second metal layer disposed in the first groove portion and the thickness of the region of the second metal layer disposed in the second groove portion.

9. The printed circuit board according to claim 7, wherein, the thickness of the first metal layer is respectively greater than the thickness of the region of the second metal layer disposed in the first groove portion and the thickness of the region of the second metal layer disposed in the second groove portion.

10. The printed circuit board according to claim 7, wherein, each of the first metal layer and the second metal layer extends on the first surface of the substrate and the second surface of the substrate.

11. The printed circuit board according to claim 10, the printed circuit board further includes a third metal layer, the third metal layer is respectively disposed on the wall surface of the through portion, on the first surface of the substrate and on the second surface of the substrate, and the third metal layer is covered by the first metal layer.

12. The printed circuit board according to claim 11, wherein, the through via further includes a fourth metal layer, the fourth metal layer is respectively disposed on the first surface of the substrate and on the second surface of the substrate, and the fourth metal layer is covered by the third metal layer.

13. The printed circuit board according to claim 1, wherein, the substrate includes: a plurality of insulating layers; a plurality of wiring layers respectively disposed on the plurality of insulating layers; and a plurality of via layers respectively penetrating the plurality of insulating layers and connecting the plurality of wiring layers to each other.

14. The printed circuit board according to claim 13, wherein, the through via is connected to at least one of the plurality of wiring layers.

15. The printed circuit board according to claim 1, the printed circuit board further includes a stacked layer, the stacked layer includes: an insulating layer disposed on at least one of the first surface and the second surface of the substrate; a wiring layer disposed on the insulating layer; and a via layer penetrating the insulating layer and connecting the through via and the wiring layer, wherein the thickness of the substrate is greater than the thickness of the insulating layer.

16. A printed circuit board, comprising: a substrate having a first surface and a second surface opposite to the first surface, and having a through portion penetrating between the first surface and the second surface; and a through via disposed in at least a portion of the through portion, wherein the through via includes regions respectively provided with a first crystal grain and a second crystal grain, the region provided with the first crystal grain is disposed between the regions provided with the second crystal grain, the average crystal grain size of the first crystal grain is smaller than the average crystal grain size of the second crystal grain, and the width of each of the regions provided with the second crystal grain increases first and then decreases in the direction from the first surface to the second surface or in the direction from the second surface to the first surface.

17. The printed circuit board according to claim 16, wherein, the through via further includes a region provided with a third crystal grain, and the region provided with the third crystal grain extends from the wall surface of the through portion and surrounds at least a part of each of the regions provided with the second crystal grains.

18. The printed circuit board according to claim 16, wherein, the regions provided with the second crystal grains each have a groove portion facing the inside of the through portion.

19. The printed circuit board according to claim 18, wherein the printed circuit board further includes a metal layer provided in each groove portion.

20. The printed circuit board according to claim 19, wherein, the average crystal grain size of the crystal grains in the metal layer is smaller than the average crystal grain size of the second crystal grains.

21. The printed circuit board according to claim 17, wherein, the average crystal grain size of the third crystal grains is larger than the average crystal grain size of the first crystal grains and smaller than the average crystal grain size of the second crystal grains; or the average crystal grain size of the first crystal grains is larger than the average crystal grain size of the third crystal grains and smaller than the average crystal grain size of the second crystal grains.

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