Driver integrated circuit and display driving device including the same

Abstract

The present application discloses a driver integrated circuit and a display driver device including the same. This document discloses a miniaturized driver integrated circuit IC comprising multiple circuits, the driver IC comprising: a first substrate; a first circuit driven at a first voltage level and mounted on the first substrate; a second substrate bonded to the first substrate; and a second circuit comprising one or more sub-circuits driven at a second voltage level higher than the first voltage level, wherein at least one of the one or more sub-circuits is mounted on the second substrate.

Description

Technical Field

[0001] The present disclosure relates to a driver integrated circuit (IC). Background Art

[0002] As the information society develops, demands for display devices for displaying images in various forms are increasing. Therefore, recently, various types of display devices such as liquid crystal display (LCD) devices or organic light emitting display (OLED) devices have been used.

[0003] The display device includes a display panel and a driver integrated circuit (IC). The display panel includes a plurality of pixels arranged in a matrix, and each pixel includes red (R), green (G), and blue (B) sub-pixels. In addition, each pixel or each sub-pixel emits light in grayscale according to the image, thereby displaying the image on the entire display panel.

[0004] Image data indicating grayscale values ​​of individual pixels or sub-pixels is transmitted to the display panel through the driver IC.

[0005] Figure 1 FIG is a plan view showing the structure of a conventional driver IC. Figure 1 As shown, the driver IC 1 includes a first circuit 3 driven at a first level voltage, a second circuit 4 driven at a second level voltage, and a third circuit 5 driven at a third level voltage, which are formed on one substrate 2. In this case, the first level voltage means a low voltage, the second level voltage means a medium voltage, and the third level voltage means a high voltage.

[0006] Recently, according to the demand for miniaturization of driver IC 1, it is necessary to reduce the area XY of driver IC 1. As the functions of circuits 3 to 5 become more complex, it is difficult to reduce the size of circuits 3 to 5, so there is a problem in that there is a limit in reducing the size of driver IC 1. Summary of the Invention

[0007] Accordingly, the present disclosure relates to a driver integrated circuit (IC) that can be miniaturized and a display device including the same.

[0008] The present disclosure also relates to a driver IC manufactured by a wafer-on-wafer process and a display device including the same.

[0009] According to one aspect of the present disclosure, a driver IC including multiple circuits is provided, which includes: a first substrate; a first circuit driven with a first level voltage and mounted on the first substrate; a second substrate bonded to the first substrate; and a second circuit including one or more sub-circuits driven with a second level voltage higher than the first level voltage, wherein at least one of the one or more sub-circuits is mounted on the second substrate.

[0010] According to one aspect of the present disclosure, a display driving device is provided, which includes: a first substrate; a second substrate bonded to the first substrate; a first circuit configured to receive first image data from an external system, convert the first image data into second image data to allow the second image data to be displayed on a display panel, and sample the second image data; and a second circuit configured to convert the sampled second image data into a source signal and output the source signal to a data line of the display panel, wherein the first circuit and the second circuit are divided and mounted on the first substrate and the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0012] Figure 1 is a plan view showing the structure of a conventional driver integrated circuit (IC);

[0013] Figure 2 is a schematic block diagram showing the structure of a driver IC (10) according to one embodiment of the present disclosure;

[0014] Figure 3 is a diagram showing a first surface on which a circuit is formed by disassembling a first substrate and a second substrate of a driver IC according to an embodiment of the present disclosure;

[0015] Figure 4 is a diagram showing a first surface on which a circuit is formed by disassembling a first substrate and a second substrate of a driver IC according to another embodiment of the present disclosure;

[0016] Figure 5 is a diagram showing a display device to which a driver IC according to one embodiment of the present disclosure is applied;

[0017] Figure 6 is a diagram showing a circuit constituting a driver IC (10) according to one embodiment of the present disclosure;

[0018] Figure 7is a plan view showing first surfaces of respective substrates of a first substrate and a second substrate by detaching a driver IC according to one embodiment of the present disclosure;

[0019] Figure 8 is a plan view showing first surfaces of respective substrates of a first substrate and a second substrate by detaching a driver IC according to another embodiment of the present disclosure;

[0020] Figure 9 is a plan view showing first surfaces of respective substrates of a first substrate and a second substrate by detaching a driver IC when a data driving circuit is implemented as a separate driver IC. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0022] In this specification, it should be noted that similar reference numerals that have been used to represent similar elements in other drawings are used for elements whenever possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed descriptions will be omitted. The terms described in this specification should be understood as follows.

[0023] The advantages and features of the present disclosure and methods for implementing the same will become apparent through the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0024] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Like reference numerals will always refer to like elements. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the key points of the present disclosure, the detailed description will be omitted.

[0025] In the case of using “including,” “having,” and “comprising” described in the present specification, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless mentioned otherwise.

[0026] When interpreting an element, although not explicitly described, the element is interpreted as including a range of error.

[0027] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on," "above," "below," and "beside," one or more other parts may be disposed between the two parts, unless "immediately" or "directly" is used.

[0028] When describing a time relationship, for example, when a time sequence is described as "after," "following," "next to," and "before," discontinuous cases may be included unless "immediately" or "directly" is used.

[0029] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0030] The X-axis direction, the Y-axis direction, and the Z-axis direction should not be interpreted solely as a geometric relationship in which the relationship therebetween is perpendicular, but may indicate a wider range of directivities within which the elements of the present disclosure function.

[0031] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, in addition to the first, second, or third item, the meaning of "at least one of the first, second, and third items" means all combinations of two or more of the first, second, and third items.

[0032] As will be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure may be partially or fully coupled or combined with each other, and may interoperate with each other in different ways and be driven technically. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0033] Figure 2 1 is a schematic block diagram showing the structure of a driver integrated circuit (IC) 10 according to one embodiment of the present disclosure. Figure 2 As shown, the driver IC 10 according to one embodiment of the present disclosure includes a first substrate 11, a second substrate 12, a first circuit 13, and a second circuit 14. Figure 2 As shown, the driver IC 10 may further include a third circuit 15 .

[0034] The first circuit 13 is mounted on the first substrate 11. In one embodiment, the first circuit 13 may be mounted on a first surface of the first substrate 11. In this case, the first surface means a surface facing the second substrate 12.

[0035] The second circuit 14 is mounted on the second substrate 12. The second substrate 12 is bonded to the first substrate 11. In one embodiment, the second circuit 14 may be mounted on a first surface of the second substrate 12. In this case, the first surface means a surface facing the first substrate 11.

[0036] The third circuit 15 is mounted on the second substrate 12. In one embodiment, the third circuit 15 may be mounted on the first surface of the second substrate 12.

[0037] In this case, the first surface of the first substrate 11 and the first surface of the second substrate 12 may be bonded using any one of a wire bonding method using a wire, a flip chip bonding method using a bump for connection, and a through silicon via (TSV) bonding method.

[0038] The first circuit 13 is driven by a first level voltage. In this case, the first level voltage may mean a low voltage. In one embodiment, the first circuit 13 may be formed on the first surface of the first substrate 11.

[0039] In one embodiment, the first circuit 13 may include at least one first sub-circuit.

[0040] The second circuit 14 is driven by a second level voltage. In this case, the second level voltage may be a voltage higher than the first level voltage and may mean a medium voltage. In one embodiment, the second circuit 14 may be formed on the first surface of the second substrate 12.

[0041] In one embodiment, the second circuit 14 may include at least one second sub-circuit. When the second circuit 14 includes a plurality of second sub-circuits, at least one of the plurality of second sub-circuits may be mounted on the second substrate 12, and the remaining second sub-circuits may be mounted on the first substrate 11. Figure 2 The second circuit 14 is shown as being formed on the second substrate 12 , but this is merely exemplary and the present disclosure is not limited thereto.

[0042] In this case, the number of second sub-circuits to be mounted on the first substrate 11 can be set in proportion to the size of the excess area after the first circuit 13 is mounted on the first substrate 11. For example, when the size of the dummy area 16 remaining after the first circuit 13 is mounted on the first substrate 11 is less than or equal to a first reference value, all second sub-circuits are determined to be mounted on the second substrate 12. Alternatively, when the size of the dummy area 16 remaining after the first circuit 13 is mounted on the first substrate 11 is greater than the first reference value and less than a second reference value, at least one of the second sub-circuits can be mounted on the first substrate 11, and all remaining second sub-circuits can be mounted on the second substrate 12. When the size of the dummy area 16 is greater than the second reference value, only the number of second sub-circuits less than or equal to the reference number can be mounted on the second substrate 12, and the remaining number of second sub-circuits can be mounted on the first substrate 11.

[0043] As described in the above embodiment, the second circuit 14 may be formed only on the second substrate 12 , alternatively, the second circuit 14 may be divided and formed on the first substrate 11 and the second substrate 12 .

[0044] According to this embodiment, Figure 3 and Figure 4 As shown, a second circuit 14 may be formed. Figure 3 FIG. 1 is a diagram illustrating a first surface of a first substrate and a second substrate on which a circuit is formed by disassembling a driver IC according to an embodiment of the present disclosure. Figure 4 FIG. 1 is a diagram illustrating a first surface of a first substrate and a second substrate on which a circuit is formed by detaching a driver IC according to another embodiment of the present disclosure.

[0045] like Figure 3 As shown, the second circuit 14 may be formed only on the second substrate 12. However, since only the first circuit 13 is formed on the first substrate 11, the dummy area 16 may be formed on the first substrate 11, unlike the second substrate 12 on which the second circuit 14 and the third circuit 15 are formed.

[0046] Specifically, in order to bond the first substrate 11 and the second substrate 12, the areas XY of the first substrate 11 and the second substrate 12 should be the same. Therefore, since the second circuit 14 and the third circuit 15 are formed on the second substrate 12, but only the first circuit 13 is formed on the first substrate 11, a dummy area 16 can be formed in the first substrate 11. Due to the dummy area 16, the size of the driver IC 10 increases.

[0047] Therefore, according to another example of the present disclosure, when the second circuit 14 includes a plurality of second sub-circuits, in the driver IC 10 , the second circuit 14 is divided and formed on the first substrate 11 and the second substrate 12 .

[0048] like Figure 4 As shown, the second circuit 14 may be divided and formed on the first substrate 11 and the second substrate 12. At least one of the plurality of sub-circuits constituting the second circuit 14 is formed on the second substrate 12, and the remaining sub-circuits are formed on the first substrate 11.

[0049] Refer again Figure 2 , the third circuit 15 is driven with a third level voltage. In this case, the third level voltage may be a voltage higher than the first level voltage and the second level voltage, and may mean a high voltage. In one embodiment, the third circuit 15 may include at least one third sub-circuit.

[0050] In the above embodiment, the first to third circuits 13 to 15 are electrically connected to process data.

[0051] In one embodiment, Figure 2 The driver IC 10 shown may be a driver IC for a display. In this case, the driver IC 10 may be a data driver circuit. In this case, the driver IC 10 may include a first circuit 13 and a second circuit 14. The first circuit 13 may include a shift register circuit and a latch circuit, and the second circuit 14 may include a level shifter circuit, a digital-to-analog converter circuit, and an output buffer circuit.

[0052] Alternatively, the driver IC 10 may be a driver IC for a mobile display. In this case, the timing controller, data driver circuit, and gate driver circuit may be integrally formed in the driver IC 10. In this case, the driver IC 10 includes a first circuit 13 and a second circuit 14. The first circuit 13 may include a timing controller, a shift register circuit for the data driver circuit, and a latch circuit for the data driver circuit. The second circuit may include a level shifter circuit, a digital-to-analog converter circuit, and an output buffer circuit. Furthermore, the driver IC 10 may further include a third circuit 15, which may include a gate driver circuit.

[0053] In addition, the driver IC 10 according to the present disclosure can be manufactured using a stacked wafer process. Compared to manufacturing using a single wafer, in the present disclosure, since the circuits of the driver IC 10 are divided and formed on the first substrate and the second substrate and manufactured by bonding the first substrate and the second substrate, there is an effect that the number of required masks is reduced, thereby reducing production costs.

[0054] As described above, since the driver IC 10 according to the present disclosure is manufactured through the stacked wafer process, circuits are divided and formed on two substrates.

[0055] Specifically, since the driver IC 10 according to the present disclosure includes circuits driven with different levels of voltage, the circuits are not formed on a single substrate but are divided according to driving voltages of the respective circuits and formed on the first and second substrates.

[0056] In addition, for electrical connection between circuits, the driver IC 10 according to the present disclosure is formed such that a first surface of a first substrate and a first surface of a second substrate formed with circuits driven at different levels of voltage are bonded facing each other.

[0057] Hereinafter, an example case in which the driver IC according to the present disclosure is applied to a driver IC for a mobile display will be described.

[0058] Figure 5 1 is a diagram illustrating a display device to which a driver IC according to an embodiment of the present disclosure is applied. The display device 50 according to the present disclosure includes a display panel 60, a power supply 65, and an external system 80. In addition, the display device 50 according to the present disclosure includes a driver IC 10.

[0059] The display panel 60 may be an organic light-emitting panel including an organic light-emitting device, or may be a liquid crystal panel including liquid crystals. That is, all types of panels currently in use may be used as the display panel 60 of the present disclosure. Therefore, the display device according to the present disclosure may also be an organic light-emitting display device, a liquid crystal display device, or various types of display devices other than organic light-emitting display devices and liquid crystal display devices. However, for ease of description, a liquid crystal display device will be described below as an example of the present disclosure.

[0060] Therefore, a case where the display panel 60 is a liquid crystal panel will be described below as an example of the present disclosure.

[0061] When the display panel 60 is a liquid crystal panel, a plurality of data lines DL1 to DLd, a plurality of gate lines GL1 to GLg crossing the data lines DL1 to DLd, a plurality of thin film transistors (TFTs) formed at intersections of the data lines DL1 to DLd and the gate lines GL1 to GLg, a plurality of pixel electrodes for charging data voltages to pixels, and a common electrode for driving liquid crystals charged in a liquid crystal layer together with the pixel electrodes are formed on a lower glass substrate of the display panel 60, and due to the crossing structure of the data lines DL1 to DLd and the gate lines GL1 to GLg, the pixels are arranged in a matrix.

[0062] A black matrix (BM) and color filters are formed on an upper glass substrate of the display panel 60. A space between the lower and upper glass substrates is filled with liquid crystal.

[0063] The liquid crystal mode applied to the display panel 60 of the present disclosure may include a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, and a fringe field switching (FFS) mode, as well as any other type of liquid crystal mode. In addition, the display device 50 according to the present disclosure may be implemented in any form such as a transmissive liquid crystal display, a semi-transmissive liquid crystal display, or a reflective liquid crystal display.

[0064] The display panel 60 displays an image in response to the gate signal and the source signal output from the driver IC 10 .

[0065] The power supply 65 is mounted on the main board 90 and supplies a voltage for driving the display panel 60, the driver IC 10, and the external system 80. In this case, various circuit elements may be mounted on the main board 90 in addition to the power supply 65.

[0066] The power supply 65 generates voltages according to the driving voltages of the circuits included in the driver IC 10 and supplies the voltages to the circuits. In this case, the driving voltages of the circuits of the driver IC 10 may include a first level voltage, a second level voltage, and a third level voltage. The first level voltage means a low voltage, the second level voltage means a medium voltage, and the third level voltage means a high voltage.

[0067] For example, the first level voltage may be in the range of 0.9V to 1.8V, the second level voltage may be 8V, and the third level voltage may be 25V.

[0068] In addition, the power supply 65 supplies power for driving the display panel 60 to the display panel 60 to allow the display panel 60 to operate.

[0069] The driver IC 10 may include a timing control circuit 110 for controlling a gate driving circuit 120 and a data driving circuit 130 formed in the display panel 60, a gate driving circuit 120 for controlling signals input to the gate lines GL1 to GLg, and a data driving circuit 130 for controlling signals input to the data lines DL1 to DLd formed in the display panel 60.

[0070] In this case, despite the Figure 5 The driver IC 10 is shown as being mounted on the display panel 60 , but this is merely exemplary, and the driver IC 10 may be separated from the display panel 60 and mounted on the display panel 60 through a separate board.

[0071] In addition, if Figure 5 As shown, the timing control circuit 110 , the gate driving circuit 120 , and the data driving circuit 130 constituting the driver IC 10 may be formed as a single chip package, or may be formed separately.

[0072] Below, we will refer to Figure 6 The various components of the driver IC 10 are described in more detail.

[0073] Figure 6 is a diagram showing a circuit constituting the driver IC 10 according to one embodiment of the present disclosure.

[0074] like Figure 6 As shown, the timing control circuit 110 supplies a gate control signal GCS to the gate driving circuit 120 to control the gate driving circuit 120. Specifically, the timing control circuit 110 receives first image data and a timing signal from the external system 80. The timing control circuit 110 generates the gate control signal GCS for controlling the gate driving circuit 120 and generates the data control signal DCS for controlling the data driving circuit 130 according to the timing signal.

[0075] In one embodiment, the timing control circuit 110 generates a gate control signal GCS including a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE) signal.

[0076] In one embodiment, the timing control circuit 110 generates a data control signal DCS including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable (SOE) signal.

[0077] The timing control circuit 110 transmits a gate control signal GCS to the gate driving circuit 120 and transmits a data control signal DCS to the data driving circuit 130 .

[0078] The timing control circuit 110 arranges the first image data received from the external system 80. Specifically, the timing control circuit 110 generates the second image data by arranging the first image data according to the structure and characteristics of the display panel 60.

[0079] The timing control circuit 110 transmits the second image data to the data driving circuit 130 .

[0080] The gate driving circuit 120 outputs a gate signal synchronized with the source signal generated by the data driving circuit 130 to the gate lines GL1 to GLg according to the timing signal generated by the timing control circuit 110. Specifically, the gate driving circuit 120 outputs a gate signal synchronized with the source signal to the gate lines GL1 to GLg according to the GSP, GSC, and GOE signals generated by the timing control circuit 110.

[0081] The gate driving circuit 120 includes a gate shift register circuit, a gate level shifter circuit, etc. In this case, the gate shift register circuit can be directly formed on the TFT array substrate of the display panel 60 through a gate-in-panel (GIP) process. In this case, the gate driving circuit 120 supplies GSP and GSC to the gate shift register circuit formed on the TFT array substrate through the GIP process.

[0082] The data driving circuit 130 converts the second image data into source signals based on the timing signals generated by the timing control circuit 110. Specifically, the data driving circuit 130 converts the second image data into source signals based on the SSP, SSC, and SOE signals. The data driving circuit 130 outputs the source signal corresponding to one horizontal line to the data lines DL1 to DLd during each horizontal period in which the gate signal is supplied to the gate line.

[0083] In this case, the data driving circuit 130 may receive a gamma voltage from a gamma voltage generator (not shown) and convert the second image data into a source signal using the gamma voltage.

[0084] For this reason, Figure 6 As shown, the data driving circuit 130 includes a shift register circuit 210 , a latch circuit 220 , a level shifter circuit 230 , a digital-to-analog converter circuit 240 , and an output buffer circuit 250 .

[0085] The shift register circuit 210 receives the SSP and SSC from the timing control circuit 110 and sequentially shifts the SSP according to the SSC to output a sampling signal. The shift register circuit 210 transmits the sampling signal to the latch circuit 220.

[0086] The latch circuit 220 sequentially samples and latches the second image data in predetermined units according to the sampling signal and transmits the latched second image data to the level shifter circuit 230 .

[0087] The level shifter circuit 230 amplifies the level of the latched second image data. Specifically, the level shifter circuit 230 amplifies the level of the second image data to a level that allows the DAC circuit 240 to be driven. The level shifter circuit 230 transmits the amplified second image data to the DAC circuit 240.

[0088] The D / A converter circuit 240 converts the second image data into a source signal which is an analog signal, and transmits the source signal converted into the analog signal to the output buffer circuit 250 .

[0089] The output buffer circuit 250 outputs the source signal to the data line. Specifically, the output buffer circuit 250 buffers the source signal according to the SOE signal generated by the timing control circuit 110 and outputs the buffered source signal to the data line.

[0090] Below, we will refer to Figure 7 The structure of the driver IC 10 when the driver IC according to the present disclosure is applied to a driver IC for a mobile display is described in more detail.

[0091] Figure 7 is a plan view illustrating first surfaces of respective substrates by disassembling a first substrate and a second substrate of a driver IC applied to a mobile display according to one embodiment of the present disclosure.

[0092] like Figure 7 As shown, the driver IC 10 according to the present disclosure includes a first substrate 11 , a second substrate 12 , a first circuit 13 , a second circuit 14 , and a third circuit 15 .

[0093] The first circuit 13 is formed on the first surface of the first substrate 11. The first substrate 11 is bonded to the second substrate 12. Specifically, the first surface of the first substrate 11 faces the first surface of the second substrate 12 and is bonded.

[0094] The second circuit 14 and the third circuit 15 are formed on the first surface of the second substrate 12. The second substrate 12 is bonded to the first substrate 11. Specifically, the first surface of the second substrate 12 is bonded facing the first surface of the first substrate 11.

[0095] In this case, bonding of the first substrate 11 and the second substrate 12 may be performed using a method such as a wire bonding method using wires, a flip-chip bonding method using bumps for connection, or a method of forming TSVs.

[0096] The first circuit 13 is formed on the first surface of the first substrate 11. The first circuit 13 is a circuit driven by a first level voltage. In this case, the first level voltage may mean a low voltage. For example, the first level voltage may be in the range of 0.9V to 1.8V.

[0097] The first circuit 13 is electrically connected to the second circuit 14 and the third circuit 15 .

[0098] In one embodiment, the first circuit 13 may include a logic circuit.

[0099] In one embodiment, the first circuit 13 may include a timing control circuit 110, a shift register circuit 210 of a data driving circuit 130, and a latch circuit 220 of the data driving circuit 130. As described above, the timing control circuit 110, the shift register circuit 210, and the latch circuit 220 are driven with a first level voltage.

[0100] According to the above-described embodiment, the first circuit 13 receives the first image data from the external system 80 and converts the first image data into the second image data to sample the second image data, thereby allowing the second image data to be displayed on the display panel.

[0101] The second circuit 14 is formed on the first surface of the second substrate 12. The second circuit 14 is a circuit driven by a second voltage level. In this case, the second voltage level may be a voltage higher than the first voltage level and may mean a medium voltage. For example, the second voltage level may be 8V.

[0102] The second circuit 14 is electrically connected to the first circuit 13 and the third circuit 15 .

[0103] In an implementation, the second circuit 14 may include a level shifter circuit 230 of the data driving circuit 130 , a digital-to-analog converter circuit 240 of the data driving circuit 130 , and an output buffer circuit 250 of the data driving circuit 130 .

[0104] According to the above embodiment, the second circuit 14 converts the second image data sampled by the first circuit 13 into a source signal and outputs the source signal to the data line of the display panel.

[0105] The third circuit 15 is formed on the first surface of the second substrate 12. The third circuit 15 is a circuit driven by a third voltage level. In this case, the third voltage level may be a voltage level higher than the second voltage level, and may mean a high voltage. For example, the third voltage level may be 25V.

[0106] The third circuit 15 is electrically connected to the first circuit 13 and the second circuit 14 .

[0107] In one embodiment, the third circuit 15 may include a gate driving circuit 120. According to the above embodiment, the third circuit 15 outputs a gate signal synchronized with a source signal to a gate line of the display panel.

[0108] As described above, in the driver IC 10 according to the present disclosure, the first to third circuits 13 to 15 are formed on the first and second substrates 11 and 12 rather than a single substrate, and the first and second substrates 11 and 12 are bonded, so that the area XY of the driver IC 10 can be reduced.

[0109] However, in the above embodiment, dummy area 16 exists in first substrate 11 on which first circuit 13 is formed. Therefore, in another embodiment of the present disclosure, in order to reduce the size of the driver IC, at least one of the plurality of sub-circuits constituting second circuit 14 is formed on second substrate 12, and the remaining sub-circuits are formed in dummy area 16 of first substrate 11.

[0110] Below, we will refer to Figure 8 A driver IC according to another embodiment of the present disclosure is described in more detail. However, detailed description of the same contents as the above description will be omitted herein.

[0111] Figure 8 is a plan view illustrating first surfaces of respective substrates of a first substrate and a second substrate by detaching a driver IC according to another embodiment of the present disclosure.

[0112] like Figure 8 As shown, first circuit 13 is formed on the first surface of first substrate 11. In addition, in second circuit 14, at least one sub-circuit is formed on the first surface of first substrate 11, and the remaining sub-circuits are formed on the first surface of second substrate 12. In addition, the remaining sub-circuits of second circuit 14 and third circuit 15 are formed on the first surface of second substrate 12.

[0113] For example, Figure 8 As shown, the level shifter circuit 230 of the second circuit 14 may be formed on the first surface of the first substrate 11, and the digital-to-analog converter circuit 240 and the output buffer circuit 250 of the second circuit 14 may be formed on the first surface of the second substrate 12. Alternatively, Figure 8 Differently, the level shifter circuit 230 and the digital-to-analog converter circuit 240 of the second circuit 14 may be formed on the first surface of the first substrate 11 , and the output buffer circuit 250 may be formed in the second substrate 12 .

[0114] As described above, since the second circuit 14 is divided and formed on the first substrate 11 and the second substrate 12, and thus the dummy area 16 formed in the first substrate 11 can be removed, the sizes of the first substrate 11 and the second substrate 12 are reduced, so that the overall size of the driver IC 10 can also be reduced.

[0115] That is, in the second circuit 14 , at least one sub-circuit is formed on the first surface of the second substrate 12 , and the remaining sub-circuits are formed on the first surface of the first substrate 11 .

[0116] In the above-described one embodiment and another embodiment, the timing control circuit 110, the data driving circuit 130, and the gate driving circuit 120 are described as being implemented as a single driver IC 10. However, as described above, each of the timing control circuit 110, the gate driving circuit 120, and the data driving circuit 130 may be implemented as a separate driver IC.

[0117] In this case, reference will be made to Figure 9 A case in which the data driving circuit 130 is implemented as a separate driver IC 10 is described.

[0118] Figure 9 1 is a plan view showing a first surface of each of the first substrate and the second substrate of the driver IC 10 by detaching the first substrate and the second substrate of the driver IC 10 when the data driving circuit 130 is implemented as a separate driver IC 10. Figure 9 As shown, the driver IC 10 includes a first substrate 11 , a second substrate 12 , a first circuit 13 , and a second circuit 14 .

[0119] The first circuit 13 may be formed on the first surface of the first substrate 11. The first substrate 11 is bonded to the second substrate 12. Specifically, the first surface of the first substrate 11 may be bonded facing the first surface of the second substrate 12.

[0120] The second circuit 14 may be formed on a first surface of the second substrate 12. The second substrate 12 is bonded to the first substrate 11. Specifically, the first surface of the second substrate 12 may be bonded facing the first surface of the first substrate 11.

[0121] The first circuit 13 is formed on the first surface of the first substrate 11. The first circuit 13 is driven with a first level voltage.

[0122] As described above, the first circuit 13 includes the shift register circuit 210 of the data driving circuit 130 and the latch circuit 220 of the data driving circuit 130 .

[0123] The second circuit 14 is formed on the first surface of the second substrate 12. The second circuit 14 is driven with a second level voltage higher than the first level voltage.

[0124] As described above, the second circuit 14 includes the level shifter circuit 230 , the digital-to-analog converter circuit 240 , and the output buffer circuit 250 of the data driving circuit 130 .

[0125] In one embodiment, at least one of the sub-circuits of second circuit 14 may be formed on the first surface of first substrate 11, and the remaining sub-circuits of second circuit 14 may be formed on the second surface of second substrate 12. All of the sub-circuits of second circuit 14 are shown as being formed on second substrate 12. Alternatively, at least one of the sub-circuits of second circuit 14 may be formed on first substrate 11.

[0126] For example, the level shifter circuit 230 of the second circuit 14 may be formed on the first surface of the first substrate 11, and the digital-to-analog converter circuit 240 and the output buffer circuit 250 of the second circuit 14 may be formed on the first surface of the second substrate 12. Alternatively, the level shifter circuit 230 and the digital-to-analog converter circuit 240 of the second circuit 14 may be formed on the first surface of the first substrate 11, and the output buffer circuit 250 of the second circuit 14 may be formed on the first surface of the second substrate 12.

[0127] Refer again Figure 5 , the external system 80 transmits first image data including information about an image to be displayed on the display panel 60 and a timing signal to the driver IC 10 .

[0128] The display device 50 according to the present disclosure may be a large terminal such as a television (TV) or a personal computer (PC), or may be a mobile terminal such as a smartphone, a mobile phone, or a tablet PC.

[0129] When the display device 50 according to the present disclosure is a smart phone, the external system 80 may be a main chip (ie, an application processor (AP)) that receives voice or data by performing wireless communication with an external communication network.

[0130] According to the present disclosure, circuits constituting a driver IC are divided and formed on two substrates, and the two substrates are bonded, so that the driver IC can be miniaturized, and there is an effect that the frame size of a display device mounted with the driver IC can be reduced.

[0131] In addition, according to the present disclosure, since the driver IC is manufactured through the stacked wafer process, the number of masks required for each wafer is reduced, thereby having an effect that the manufacturing cost of the driver IC can be minimized.

[0132] It will be apparent to those skilled in the art that various modifications may be made to the above exemplary embodiments of the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover all such modifications as long as they fall within the scope of the appended claims and their equivalents.

[0133] CROSS-REFERENCE TO RELATED APPLICATIONS

[0134] This application claims the benefit of Korean Patent Application No. 10-2019-0172904, filed on December 23, 2019, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A driver integrated circuit (IC) comprising a plurality of circuits, the driver IC comprising: a first substrate; a first circuit driven by a first level voltage and mounted on the first substrate; a second substrate bonded to the first substrate; a second circuit including one or more sub-circuits driven at a second level voltage higher than the first level voltage, wherein at least one of the one or more sub-circuits is mounted on the second substrate; and A third circuit is driven by a third level voltage higher than the second level voltage and is mounted on the second substrate, wherein the third circuit includes at least one third sub-circuit.

2. The driver IC according to claim 1, wherein The remaining sub-circuits, excluding the sub-circuit mounted on the second substrate, among the one or more sub-circuits constituting the second circuit are mounted on the first substrate.

3. The driver IC according to claim 1, wherein The first circuit is formed on the first surface of the first substrate; At least one of the one or more sub-circuits constituting the second circuit is formed on the first surface of the second substrate, and the remaining sub-circuits of the one or more sub-circuits constituting the second circuit are formed on the first surface of the first substrate; and The first substrate and the second substrate are bonded such that the first surface of the first substrate faces the first surface of the second substrate.

4. The driver IC according to claim 1, wherein The first substrate and the second substrate are bonded by any one of wire bonding, flip chip bonding, and through silicon via bonding. 5 . The driver IC according to claim 1 , which is a driver IC for driving a display and outputs an image signal to a display panel.

6. A display driving device, comprising: a first substrate; a second substrate bonded to the first substrate; a first circuit configured to receive first image data from an external system, convert the first image data into second image data to allow the second image data to be displayed on a display panel, and sample the second image data; as well as a second circuit configured to convert the sampled second image data into a source signal and output the source signal to a data line of the display panel, The first circuit and the second circuit are divided and mounted on the first substrate and the second substrate.

7. The display driving device according to claim 6, wherein: The second circuit includes: a level shifter circuit configured to amplify a level of the latched second image data transmitted from the first circuit; a digital-to-analog converter circuit configured to convert the amplified second image data into the source signal as an analog signal; and an output buffer circuit configured to buffer the source signal according to a source output enable signal generated by a timing control circuit and output the buffered source signal to the display panel, In which, at least one of the level shifter circuit, the digital-to-analog converter circuit and the output buffer circuit is mounted on the second substrate, and the remaining circuits among the level shifter circuit, the digital-to-analog converter circuit and the output buffer circuit are mounted on the first substrate.

8. The display driving device according to claim 6, wherein: The first circuit includes: a shift register circuit configured to receive a source start pulse and a source sampling clock from a timing control circuit, and sequentially shift the source start pulse according to the source sampling clock to output a sampling signal, the timing control circuit receiving the first image data from an external system and converting the first image data into the second image data in a form displayed on a display panel; and A latch circuit is configured to sequentially sample and latch the second image data in predetermined units according to the sampling signal.

9. The display driving device according to claim 6, wherein: The first circuit includes a timing control circuit configured to receive the first image data from an external system, convert the first image data into the second image data in a form displayed on a display panel, generate a source start pulse, a source sampling clock, and a source output enable signal for the second image data, and generate a strobe start pulse, a strobe shift clock, and a strobe output enable signal.

10. The display driving device according to claim 6, wherein: The first circuit is driven with a first level voltage; and The second circuit is driven with a second level voltage higher than the first level voltage.

11. The display driving device according to claim 10 , further comprising a third circuit configured to output a gate signal synchronized with the source signal to a gate line of the display panel, in, The third circuit is mounted on the second substrate.

12. The display driving device according to claim 11, wherein: The third circuit is driven with a third level voltage higher than the first level voltage and the second level voltage.

13. The display driving device according to claim 6, wherein: The first circuit is formed on the first surface of the first substrate; At least one of the sub-circuits of the second circuit is formed on the first surface of the second substrate, and the remaining sub-circuits of the second circuit are formed on the first surface of the first substrate; and The first substrate and the second substrate are bonded such that the first surface of the first substrate faces the first surface of the second substrate.

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