Clock signal generating apparatus and method

Abstract

A clock signal generation device and method are disclosed. The device includes: a clock delay circuit configured to receive a reference clock signal and generate N delayed clock signals by using the reference clock signal, where N is a natural number greater than or equal to 2; and an output circuit configured to receive the N delayed clock signals and output at least a part of the N delayed clock signals as an output clock signal, where the phase delay of the delayed clock signal output later in time among the at least a part of the delayed clock signals is greater than or equal to the phase delay of the delayed clock signal output earlier in time, and where the period of the output clock signal is greater than or equal to the period of the reference clock signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0003170, filed with the Korean Intellectual Property Office on January 9, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to a spread - spectrum clock signal generating device for generating a spread - spectrum clock signal. The present disclosure also relates to a spread - spectrum clock signal generating method for generating a spread - spectrum clock signal. Background art

[0004] An electronic circuit can emit electromagnetic energy at the frequency of a clock signal, which may interfere with the operation of other electronic devices. Such electromagnetic energy can be referred to as electromagnetic interference (EMI). Generally, a maximum allowable emission amount of electromagnetic interference can be specified, and exceeding the maximum allowable emission amount may cause unacceptable obstacles to other electronic devices.

[0005] Recently, the requirements for high - performance specifications of electronic devices may increase the area, current consumption, and operating frequency of such electronic devices, making the emission amount of EMI tend to increase. Methods for reducing such an emission amount of EMI may include methods for distributing the bandwidth of the clock signal frequency. Such a method can be referred to as "spread - spectrum clock". Summary of the invention

[0006] This summary of the invention is provided to introduce a series of concepts in a simplified form that will be further described in the detailed description below. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0007] In one general aspect, a clock signal generating device includes: a clock delay circuit configured to receive a reference clock signal and generate N delayed clock signals by using the reference clock signal, where N is a natural number greater than or equal to 2; and an output circuit configured to receive the N delayed clock signals and output at least a part of the N delayed clock signals as an output clock signal, where the phase delay of the delayed clock signal that is output later in time among the at least a part of the delayed clock signals is greater than or equal to the phase delay of the delayed clock signal that is output earlier in time, and where the period of the output clock signal is greater than or equal to the period of the reference clock signal.

[0008] The clock delay circuit may include N sub - clock delay circuits connected in series.

[0009] The output circuit may be configured to output only the delayed clock signals among the at least a portion of the delayed clock signals having a phase delay greater than or equal to 0 and less than 2π.

[0010] In response to the delayed clock signal to be output having a phase delay exceeding 2π, the output circuit may be configured to output a reference clock signal in place of the delayed clock signal to be output.

[0011] The apparatus may further include a phase connection circuit configured to identify the delayed clock signals among the N delayed clock signals having a phase delay exceeding 2π and generate a reference identifier based on the identification result.

[0012] Based on the reference identifier, the output circuit may be configured to output only the delayed clock signals among the at least a portion of the delayed clock signals having a phase delay greater than or equal to 0 and less than 2π.

[0013] The output circuit may include: a memory including a configuration file for identifying the at least a portion of the delayed clock signals; and an output module configured to select at least a portion of the delayed clock signals from the N delayed clocks by using the identifiers included in the configuration file.

[0014] The output module may be configured to generate a count value, read the identifier corresponding to the count value by using the configuration file, and select at least a portion of the delayed clock signals by using the identifier.

[0015] The apparatus may further include a compensation circuit configured to generate a compensation value in response to the period of the output clock signal being less than the period of the reference clock signal such that the output clock signal corresponds to the reference clock signal.

[0016] In another general aspect, a clock signal generation apparatus includes: a clock delay circuit configured to receive a reference clock signal and generate N delayed clock signals by sequentially delaying the reference clock signal, where N is a natural number greater than or equal to 2; and an output circuit configured to receive the N delayed clock signals, select partial clock signals from the N delayed clock signals and the reference clock signal, and output the selected partial clock signals in an order from the minimum phase delay to the maximum phase delay as an output clock signal, where the period of the output clock signal is greater than or equal to the period of the reference clock signal.

[0017] The apparatus may further include a phase connection circuit configured to detect the phases of the N delayed clock signals and generate a reference identifier for identifying the delayed clock signals among the N delayed clock signals having a phase delay exceeding 2π.

[0018] Based on the reference identifier, the output circuit can output only the clock signals in the partial clock signals that have a phase delay greater than or equal to 0 and less than 2π.

[0019] Based on the reference identifier, the output circuit can be configured to output a reference clock signal or a first clock signal in the partial clock signals that has a small phase delay, instead of the clock signals in the partial clock signals that have a phase delay exceeding 2π.

[0020] The device may further include a compensation circuit configured to generate a compensation value in response to the period of the output clock signal being less than the period of the reference clock signal, such that the output clock signal corresponds to the reference clock signal.

[0021] In another general aspect, a method for generating a clock signal includes: receiving a reference clock signal; generating N delayed clock signals by using the reference clock signal, where N is a natural number greater than or equal to 2; and sequentially outputting at least a part of the N delayed clock signals as an output clock signal, where the phase delay of the delayed clock signal output later in time among the at least a part of the delayed clock signals is greater than or equal to the phase delay of the delayed clock signal output earlier in time, and where the period of the output clock signal is greater than or equal to the period of the reference clock signal.

[0022] Sequentially outputting may include: outputting only the delayed clock signals in the at least a part of the delayed clock signals that have a phase delay greater than or equal to 0 and less than 2π.

[0023] Sequentially outputting may include: identifying an excessive phase delay clock signal in the at least a part of the delayed clock signals that has a phase delay exceeding 2π; and outputting the reference clock signal and the minimum phase delay clock signal in the at least a part of the delayed clock signals that has the minimum phase delay, instead of the excessive phase delay clock signal.

[0024] Sequentially outputting may include: generating a count value according to a period, and sequentially outputting the delayed clock signals in the at least a part of the delayed clock signals corresponding to the count value.

[0025] In another general aspect, a method for generating a clock signal includes: receiving a reference clock signal; generating N delayed clock signals by sequentially delaying the reference clock signal, where N is a natural number greater than or equal to 2; receiving the N delayed clock signals; selecting partial clock signals from the N delayed clock signals and the reference clock signal; and outputting the partial clock signals as an output clock signal in an order from the minimum phase delay to the maximum phase delay, where the period of the output clock signal is greater than or equal to the period of the reference clock signal.

[0026] The method may further include: detecting the phases of N delayed clock signals, and generating a reference identifier identifying the delayed clock signals among the N delayed clock signals that have a phase delay exceeding 2π.

[0027] The method may further include: based on the reference identifier, outputting a reference clock signal or a first clock signal having a small phase delay among the partial clock signals to replace the clock signal having a phase delay exceeding 2π among the partial clock signals.

[0028] The method may further include: generating a compensation value in response to the period of the output clock signal being smaller than the period of the reference clock signal, such that the output clock signal corresponds to the reference clock signal.

[0029] Other features and aspects will be apparent from the following detailed description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shows a spread spectrum clock generation system according to one or more embodiments.

[0031] Figure 2 Shows a clock delay circuit according to one or more embodiments.

[0032] Figure 3 Shows a reference clock signal and delayed clock signals according to one or more embodiments.

[0033] Figure 4 Shows an output circuit according to one or more embodiments.

[0034] Figure 5 And Figure 6 Is a diagram for describing the operation of an output module according to one or more embodiments.

[0035] Figure 7 Shows the operation of a phase connection circuit according to one or more embodiments.

[0036] Figure 8 Is a flowchart showing a method of operating a spread spectrum clock generation circuit according to one or more embodiments.

[0037] Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and for clarity, illustration, and convenience, the relative dimensions, ratios, and descriptions of the elements in the drawings may be exaggerated. DETAILED DESCRIPTION

[0038] The following specific embodiments are provided to assist the reader in obtaining a comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be apparent after understanding the disclosure of this application. For example, the operation sequences described herein are merely examples and are not limited to the operation sequences set forth herein, but rather can be changed as will be apparent after understanding the disclosure of this application, except for operations that must occur in a certain order. Additionally, descriptions of features known in the art may be omitted for greater clarity and conciseness.

[0039] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways of implementing the methods, devices, and / or systems described herein, which will be apparent after understanding the disclosure of this application.

[0040] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "coupled to" another element, the element can be directly "on," "connected to," or "coupled to" the other element, or there may be one or more other elements intervening between the element and the other element. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no other elements intervening between the element and the other element.

[0041] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more thereof.

[0042] Although terms such as "first," "second," and "third" may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer, or section from another. Thus, a first component, part, region, layer, or section referred to in the examples described herein could also be referred to as a second component, part, region, layer, or section without departing from the teachings of the examples.

[0043] For ease of description, spatial relative terms such as "above", "on", "below", and "beneath" may be used herein to describe the relationship of one element to another as shown in the figures. Such spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "above" or "on" another element will be "below" or "beneath" the other element. Thus, the term "above" encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly.

[0044] The terms used herein are for the purpose of describing various examples only and are not intended to limit the disclosure. Unless the context clearly dictates otherwise, the articles "a", "an", and "the" are also intended to include the plural forms. The terms "comprising", "including", and "having" specify the presence of the stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0045] Due to manufacturing techniques and / or tolerances, the shapes shown in the figures may vary. Accordingly, the examples described herein are not limited to the specific shapes shown in the figures but also include shape variations that occur during manufacturing.

[0046] It will be apparent after understanding the disclosure of the present application that the features of the examples described herein can be combined in various ways. Moreover, although the examples described herein have various configurations, it will be apparent after understanding the disclosure of the present application that other configurations are feasible.

[0047] In this document, it should be noted that the use of the term "may" with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, and all examples and embodiments are not limited thereto.

[0048] An object of one or more embodiments is to provide a spread-spectrum clock generation device and a spread-spectrum clock generation method for generating a spread-spectrum clock signal.

[0049] Figure 1 A spread-spectrum clock generation system according to one or more embodiments is shown. Referring to Figure 1, the spread spectrum clock generation system 10 can generate a reference clock signal RCLK, and further generate an output clock signal OCLK having a spectrum wider than that of the reference clock signal RCLK based on the reference clock signal RCLK.

[0050] According to a non-limiting example, the spread spectrum clock generation system 10 may include a reference clock generation circuit 100 and a spread spectrum clock generation device 200.

[0051] The reference clock generation circuit 100 can generate a reference clock signal RCLK. According to one or more embodiments, the reference clock generation circuit 100 can generate a reference clock signal RCLK having a constant period. For example, the reference clock generation circuit 100 can be an oscillator, a crystal oscillator, or a CMOS oscillator, and is not limited to such one or more listed example embodiments.

[0052] The spread spectrum clock generation device 200 can receive the reference clock signal RCLK, and can generate an output clock signal OCLK having a spectrum wider than that of the reference clock signal RCLK based on the reference clock signal RCLK. That is, the frequency of the output clock signal OCLK can be evenly distributed over a region wider than the frequency region of the reference clock signal RCLK. Also, the period of the output clock signal OCLK can be greater than or equal to the period of the reference clock signal RCLK. In the present disclosure, the period of the output clock signal OCLK can represent the time period from any rising edge or falling edge of the output clock signal OCLK to the next rising edge or falling edge of the output clock signal OCLK.

[0053] Therefore, since the spread spectrum clock generation device 200 can have a spectrum wider than that of the reference clock signal RCLK, or can have a period longer than that of the reference clock signal RCLK, there can be an overall effect of reducing electromagnetic interference generated in an electronic device or an electronic system in which the spread spectrum clock generation device 200 can be used or installed. Subsequently, this phenomenon will be described in more detail.

[0054] As Figure 1 shown, according to one or more non-limiting examples, the spread spectrum clock generation device 200 may include a clock delay circuit 210, a phase connection circuit 220, an output circuit 230, and a compensation circuit 240.

[0055] The clock delay circuit 210 may receive a reference clock signal RCLK and may generate N delayed clock signals DCLK_1 to DCLK_N based on the reference clock signal RCLK. Here, N is a natural number greater than or equal to 2. According to one or more embodiments, the clock delay circuit 210 may generate N delayed clock signals DCLK_1 to DCLK_N by delaying the reference clock signal RCLK. For example, with respect to the reference clock signal RCLK, each of the delayed clock signals DCLK_1 to DCLK_N may have a phase delay, where the phase delay is greater than or equal to 0 and less than 2π. Each of the delayed clock signals DCLK_1 to DCLK_N has a different phase delay from each other, and the phase delay is not limited to these listed example delays.

[0056] The clock delay circuit 210 may be implemented by using a phase-locked loop (PLL), a delay-locked loop (DLL), or a digitally controlled delay line (DCDL), and the clock delay circuit 210 is not limited to these listed examples of the clock delay circuit 210.

[0057] In addition, the clock delay circuit 210 may output the reference clock signal RCLK.

[0058] The phase connection circuit 220 may receive the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N. According to one or more embodiments, the phase connection circuit 220 may receive the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N through pads, ports, or transmission lines, as non-limiting examples, corresponding to the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N respectively.

[0059] Based on the reference clock signal RCLK, the phase connection circuit 220 may detect the phase delay of each of the delayed clock signals DCLK_1 to DCLK_N and may generate a corresponding phase delay value based on the detection result. For example, the phase connection circuit 220 may compare the time point of the rising edge or falling edge of the reference clock signal RCLK with the time point of the rising edge or falling edge of the delayed clock signals DCLK_1 to DCLK_N. Then the phase connection circuit may generate a phase delay value for each of the delayed clock signals DCLK_1 to DCLK_N with respect to the reference clock signal RCLK based on the comparison result.

[0060] Based on the phase delay value, the phase connection circuit 220 may identify a delayed clock signal among the delayed clock signals DCLK_1 to DCLK_N that has a phase delay value exceeding 2π, such as an excessive phase delay clock signal, and may generate a reference identifier RIDF that can be used to identify the excessive phase delay clock signal based on the identification result.

[0061] According to one or more embodiments, based on the phase delay value, the phase connection circuit 220 may identify a delayed clock signal among the delayed clock signals DCLK_1 to DCLK_N that first exceeds 2π in phase delay, such as an excessive phase delay clock signal. For example, the phase connection circuit 220 may identify the delayed clock signal with the smallest phase delay among the delayed clock signals having a phase delay exceeding 2π.

[0062] The output circuit 230 may generate an output clock signal OCLK by using the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N. According to one or more embodiments, the output circuit 230 may output at least a part of the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N as the output clock signal OCLK.

[0063] According to one or more embodiments, the output circuit 230 may select a delayed clock signal having a phase delay not exceeding 2π from the delayed clock signals DCLK_1 to DCLK_N and output it. For example, the output circuit 230 may identify a delayed clock signal having a phase delay exceeding 2π among the delayed clock signals DCLK_1 to DCLK_N by using a reference identifier RIDF, such as an excessive phase delay clock signal, and may output a delayed clock signal whose phase delay is less than the phase delay of the excessive phase delay clock signal.

[0064] The compensation circuit 240 may generate a compensation value according to the output clock signal OCLK. As described above, since the spectrum of the output clock signal OCLK may be wider than the spectrum of the reference clock signal RCLK, compared with an example of the reference clock signal RCLK that can be used as a system clock signal, it may be necessary to compensate the output clock signal OCLK. That is, the compensation value may be a compensation value or offset of the output clock signal OCLK relative to the reference clock signal RCLK.

[0065] For example, it may be assumed that a clock reference clock signal RCLK having seven cycles will be generated within a specific time period, and an output clock signal OCLK having six cycles will be generated within the specific time period. If a circuit generates a signal based on the reference clock signal RCLK having seven cycles, the circuit will correspondingly generate a signal based on the output clock signal OCLK having six cycles. Therefore, in order to compensate for this difference between these clock signals, the compensation circuit 240 may generate a compensation value that indicates that within the specific time period, the output clock signal OCLK includes one cycle less than the number of cycles generated relative to the reference clock signal RCLK, and the compensation value may be 1 because the difference between the number of cycles associated with the reference clock signal RCLK and the number of cycles associated with the output clock signal OCLK is 1.

[0066] That is, by using the spectrally broadened output clock signal OCLK, the period of the output clock signal OCLK can be increased more than the period of the reference clock signal RCLK. Therefore, the number of clocks or rising edges can be reduced within the same time period, and thus can be compensated by using the compensation circuit 240.

[0067] Figure 2 A clock delay circuit according to one or more embodiments is shown. Referring to Figure 1 and Figure 2 , the clock delay circuit 210 may include a plurality of sub-clock delay circuits 211-1 to 211-N. Although N sub-clock delay circuits 211-1 to 211-N are shown in Figure 2 , one or more embodiments are not limited to the specific number of sub-clock delay circuits 211-1 to 211-N shown in Figure 2 .

[0068] The sub-clock delay circuits 211-1 to 211-N may generate N delayed clock signals DCLK_1 to DCLK_N, for example, by using the reference clock signal RCLK. According to one or more embodiments, the sub-clock delay circuits 211-1 to 211-N may be connected in series. Therefore, a delayed clock signal generated later in time may have a greater phase delay than a delayed clock signal generated earlier in time. Subsequently, in the present disclosure, the fact that a delayed clock signal is generated "relatively earlier" with respect to another clock signal is used to indicate that the delayed clock signal may have a "relatively smaller" phase delay.

[0069] The first sub-clock delay circuit 211-1 can delay the reference clock signal RCLK by a phase delay Td to generate a first delayed clock signal DCLK_1, and the second sub-clock delay circuit 211-2 can generate a second delayed clock signal DCLK_2 by delaying the first delayed clock signal DCLK_1. In a similar manner, the Nth sub-clock delay circuit 211-N can generate the Nth delayed clock signal DCLK_N by delaying the (N-1)th delayed clock signal DCLK_N-1.

[0070] Figure 3 illustrates a reference clock signal and delayed clock signals according to one or more embodiments. Referring to Figures 1 to 3 , the reference clock signal RCLK and N delayed clock signals DCLK_1 to DCLK_N can be illustrated.

[0071] Each of the delayed clock signals DCLK_1 to DCLK_N can have a phase delay with respect to the reference clock signal RCLK. According to one or more embodiments, the delayed clock signals DCLK_1 to DCLK_N can have an increasing phase delay. For example, the first delayed clock signal DCLK_1 can have a phase delay Td with respect to the reference clock signal RCLK, and the second delayed clock signal DCLK_2 can have a phase delay 2*Td with respect to the reference clock signal RCLK. Similarly, the Nth delayed clock signal DCLK_N can correspondingly have a phase delay N*Td.

[0072] However, Figure 3 the phase delays of the delayed clock signals DCLK_1 to DCLK_N with respect to the reference clock signal RCLK shown in

[0073] Figure 4 illustrates an output circuit according to one or more embodiments. Referring to Figures 1 to 4 , the output circuit 230 can include an output module 231 and a memory 233.

[0074] Subsequently, a module mentioned in the present disclosure refers to hardware capable of performing at least one specified function, or refers to hardware including software instructions that cause the hardware to perform the specified function. That is, a specific module described in the present disclosure can refer to a device or circuit capable of performing the corresponding function, or can mean a hardware device on which software instructions for enabling the device to perform the function are executed.

[0075] The output module 231 may control the overall operation of the output circuit 230. According to one or more embodiments, the output module 231 may select at least a part of the clock signals from the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N, and may output the selected at least a part of the clock signals as the output clock signal OCLK.

[0076] According to one or more embodiments, the output module 231 may include any one or any combination of two or more of a central processing unit (CPU), a microcontroller unit (MCU), a microprocessor unit (MPU), a floating point unit (FPU), a digital signal processor (DSP), a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA). However, the output module 231 is not limited to these non-limiting examples of the hardware types for implementing the output module 231.

[0077] The output module 231 may select one of the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N, and may output the selected one clock signal as the output clock signal OCLK. By repeating this selection process, the output module 231 may output at least a part of the clock signals of the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N as the output clock signal OCLK. According to one or more embodiments, the output circuit 230 may output the at least a part of the clock signals in the order of increasing phase delay (i.e., in the order of the smallest phase delay), so that the output clock signal OCLK may be output accordingly.

[0078] In the present disclosure, the order of increasing phase delay means how the output clock signals are sorted, the phase delay of the output clock signals increases or remains the same. That is, for at least a part of the clock signals output as the output clock signal OCLK, the phase delay of the first clock signal may be less than or equal to the phase delay of the second clock signal output after the first clock signal.

[0079] For example, the output module 231 may sequentially output the first clock signal (e.g., the clock signal with the smallest phase delay), the second clock signal,... the k-th clock signal among the at least a part of the clock signals in the order of small phase delay, where k is a natural number equal to or less than N + 1. In such an example, the period during which the first clock signal to the k-th clock signal are output may be referred to as an extended period. For example, the first clock signal may be the reference clock signal RCLK, but the first clock signal is not limited to such a specific non-limiting example.

[0080] The output module 231 may repeatedly output the at least a portion of the clock signals according to an extended period. That is, the first clock signal to the k-th clock signal of the at least a portion of the clock signals may be output through the output module 231, and then the first clock signal may be output again from the start. The output module 231 may repeat such a sequence.

[0081] According to one or more embodiments, the output module 231 may generate a count value, and may select and output a clock signal corresponding to the count value from among the reference clock signal RCLK and the delay clock signals DCLK_1 to DCLK_N. In addition, the output module 231 may output the delay clock signal having the maximum phase delay among the at least a portion of the clock signals, and then may initialize the count value and may output the reference clock signal RCLK.

[0082] According to one or more embodiments, the output module 231 may read a configuration file stored in the memory 233, and then may select at least a portion of the clock signals from among the reference clock signal RCLK and the delay clock signals DCLK_1 to DCLK_N by using the configuration file and the count value.

[0083] The configuration file stored in the memory 233 may store an identifier mapped to the count value. According to one or more embodiments, the configuration file may be a look-up table (LUT).

[0084] The output module 231 may refer to the configuration file to read the identifier corresponding to the count value, and may select at least a portion of the clock signals from among the reference clock signal RCLK and the delay clock signals DCLK_1 to DCLK_N by using the identifier.

[0085] For example, the output module 231 may pre-select at least a portion of the clock signals.

[0086] The identifier may indicate which delay clock signal the corresponding delay clock signal is. That is, the identifier may indicate from which sub-clock delay circuit the corresponding delay clock signal is generated. For example, when the identifier is larger, it may indicate a later-generated delay clock signal.

[0087] According to one or more embodiments, the configuration file stored in the memory 233 may define a function that may have the count value as an input and may have the corresponding identifier as an output. That is, the configuration file may indicate the clock signals to be output through the output circuit 230 among the reference clock signal RCLK and the N delay clock signals DCLK_1 to DCLK_N, and may indicate the output order of the output clock signals.

[0088] In such an example, the function can be an identification function or an increment function. For example, if the first count value is greater than the second count value, the phase delay of the clock signal identified by the first identifier corresponding to the first count value can be greater than the phase delay of the clock signal identified by the second identifier corresponding to the second count value.

[0089] In addition, the identifier corresponding to the count value can vary according to the configuration file. For example, according to the first configuration file, the first delayed clock signal DCLK_1 can be used to indicate the identifier corresponding to the count value "1". Meanwhile, according to the second configuration file, the second delayed clock signal DCLK_2 can be used to indicate the identifier corresponding to the count value "1".

[0090] Based on the reference identifier RIDF, the output module 231 can output the clock signal having a phase delay greater than or equal to 0 and less than 2π among at least a part of the selected clock signals. For example, as described later, when the phase delay of the clock signal to be output exceeds 2π for the kth time, the output circuit 230 can output the first clock signal, that is, the reference clock signal or the clock signal having a small phase delay among at least a part of the selected clock signals, in place of the kth output clock signal.

[0091] According to one or more embodiments, the output module 231 can read the identifier indicating the clock signal having a phase delay less than the phase delay of the clock signal identified by the reference identifier RIDF from the identifiers included in the configuration file, and can select at least a part of the clock signals based on the read identifier.

[0092] The memory 233 can store the data required for the operation of the output circuit 230. According to one or more embodiments, the memory 233 can store the clock configuration file. For example, the memory 233 can include a non-volatile memory and / or a volatile memory.

[0093] Figure 5 and Figure 6 are diagrams for describing the operation of the output module according to one or more embodiments. Referring to Figures 1 to 6 , the output module 231 can output at least a part of the reference clock signal RCLK and the delayed clock signals DCLK_1 to DCLK_N as the output clock signal OCLK.

[0094] The output module 231 may generate a count value such as CNT = 1 during a first period of the reference clock signal RCLK, and may output the reference clock signal RCLK as the output clock signal OCLK according to the generated count value such as CNT = 1. According to one or more embodiments, the output module 231 may read an identifier corresponding to the count value such as CNT = 1 by using the stored configuration file, may select the reference clock signal RCLK by using the identifier, and may accordingly output the reference clock signal RCLK as the output clock signal OCLK.

[0095] Similarly, the output module 231 may generate a count value such as CNT = 2 during a second period of the reference clock signal RCLK, and may output the first delayed clock signal DCLK_1 as the output clock signal OCLK according to the generated count value such as CNT = 2. The output module 231 may generate a count value such as CNT = 3 during a third period of the reference clock signal RCLK, and may output the second delayed clock signal DCLK_2 as the output clock signal OCLK according to the generated count value such as CNT = 3. The output module 231 may generate a count value such as CNT = 4 during a fourth period of the reference clock signal RCLK, and may output the third delayed clock signal DCLK_3 as the output clock signal OCLK according to the generated count value such as CNT = 4. The output module 231 may generate a count value such as CNT = 5 during a fifth period of the reference clock signal RCLK, and may output the fourth delayed clock signal DCLK_4 as the output clock signal OCLK.

[0096] Meanwhile, as a non-limiting example, the output module 231 may generate the count value CNT in response to the reference clock signal RCLK, but is not limited to this specific example. For example, in response to the previously output delayed clock signal, the output module 231 may generate the count value CNT. That is, a first count value such as CNT = 1 may be generated in response to the reference clock signal RCLK, and a second count value such as CNT = 2 may be generated in response to the first delayed clock signal DCLK_1.

[0097] Not only may the delayed clock signals DCLK_1 to DCLK_N have a phase delay with respect to the reference clock signal RCLK, but also the later generated delayed clock signals may have a phase delay greater than or equal to the phase delay of the previously generated delayed clock signals. Therefore, the period of the output clock signal OCLK may be greater than or equal to the period of the reference clock signal RCLK. Accordingly, electromagnetic interference may be reduced.

[0098] As Figure 5 and Figure 6As shown, the spread spectrum clock generation device 200 can generate at least a part of the delay clock signals DCLK_1 to DCLK_4 among the plurality of delay clock signals DCLK_1 to DCLK_N, and can also output at least a part of the delay clock signals DCLK_1 to DCLK_4 as the output clock signal OCLK.

[0099] According to one or more embodiments, Figure 5 the delay clock signals DCLK_1 to DCLK_4 among them can be presented in the order of increasing phase delay. That is, the phase delay of the first delay clock signal DCLK_1 can be less than the phase delay of the second delay clock signal DCLK_2, and the phase delay of the second delay clock signal DCLK_2 can be less than the phase delay of the third delay clock signal DCLK_3. Finally, in such an example, the phase delay of the third delay clock signal DCLK_3 can be less than the phase delay of the fourth delay clock signal DCLK_4. Therefore, by operating in this way, the timing margin of the output clock signal OCLK can be improved.

[0100] According to one or more embodiments, Figure 6 the delay clock signals DCLK_1 to DCLK_4 among them can be sorted in the order of maintaining or increasing phase delay. That is, in a non-limiting example, the phase delay of the first delay clock signal DCLK_1 can be equal to the phase delay of the second delay clock signal DCLK_2, and the phase delay of the second delay clock signal DCLK_2 can be less than the phase delay of the third delay clock signal DCLK_3. The phase delay of the third delay clock signal DCLK_3 can be less than the phase delay of the fourth delay clock signal DCLK_4. Therefore, the timing margin of the output clock signal OCLK can be improved by managing the phase delay using this method.

[0101] Meanwhile, although Figure 5 and Figure 6 show the reference clock signal RCLK and the four delay clock signals DCLK_1 to DCLK_4 that can be output by the output module 231, such a method is only a non-limiting example. The output module 231 can output all or some of the clock signals among the reference clock signal RCLK and the N delay clock signals DCLK_1 to DCLK_N.

[0102] In addition, the output module 231 can output all parts of the clock signal, and then can subsequently output part of the clock signal again from the beginning.

[0103] Figure 7 shows the operation of the phase connection circuit according to one or more embodiments. According to Figure 7, the period Tout of the output clock signal OCLK can be greater than or equal to the period of the reference clock signal RCLK.

[0104] Referring to Figures 1 to 7 , it can be assumed that the phase delay of the (N - 1)-th delayed clock signal DCLK_N-1 with respect to the reference clock signal RCLK can be less than 2π, and the phase delay of the N-th delayed clock signal DCLK_N with respect to the reference clock signal RCLK can exceed 2π.

[0105] In such an example, since the phase delay of the N-th delayed clock signal DCLK_N exceeds 2π, when the N-th delayed clock signal DCLK_N and the reference clock signal RCLK are output, as shown at A, the period Tout' of the output clock signal OCLK' may be shorter than the period of the reference clock signal RCLK, such that the timing margin can be reduced accordingly.

[0106] According to one or more embodiments, based on the phase delay, the phase connection circuit 220 can identify the delayed clock signals among the delayed clock signals DCLK_1 to DCLK_N having a phase delay exceeding 2π and can generate a reference identifier RIFD for identifying the delayed clock signals with a phase delay exceeding 2π according to the identification result.

[0107] The output module 231 can identify the delayed clock signals having a phase delay exceeding 2π by using the reference identifier RIDF. The output module 231 can also determine the phase delay exceeding 2π of the N-th delayed clock signal DCLK_N by using the reference identifier RIDF. According to one or more embodiments, before outputting the N-th delayed clock signal DCLK_N, the output module 231 can also determine that the phase delay of the N-th delayed clock signal DCLK_N to be output is to exceed 2π by using the reference identifier RIDF.

[0108] According to the determined result, the output module 231 can output a clock signal having a phase delay less than 2π instead of outputting the N-th delayed clock signal DCLK_N. For example, as shown at B, the output module 231 can output any one of the delayed clock signals selected from the reference clock signal RCLK and the first delayed clock signal DCLK_1 to the (N - 1)-th delayed clock signal DCLK_N-1.

[0109] Therefore, the period Tout of the output clock signal OCLK can become greater than or equal to the period of the reference clock signal RCLK, and thus, the problem of reduced timing margin can be solved.

[0110] That is, according to one or more phase connection circuits 220, a reference identifier RIDF can be generated for identifying a delayed clock signal having a phase delay exceeding 2π among the delayed clock signals DCLK_1 to DCLK_N. Further, based on the reference identifier, the output circuit 230 can output only the clock signals having a phase delay greater than or equal to 0 and less than 2π in the order of increasing phase delay among the delayed clock signals DCLK_1 to DCLK_N, and then can initialize the output circuit 230 to output the reference clock signal RCLK or a delayed clock signal having a phase delay greater than or equal to 0 and less than 2π. Accordingly, the period Tout of the output clock signal OCLK can become greater than or equal to the period of the reference clock signal RCLK, such that electromagnetic interference can be reduced and timing margin can be improved.

[0111] Figure 8 is a flowchart showing a spread spectrum clock generation method according to one or more embodiments. Referring to Figures 1 to 8 , in operation S100, the spread spectrum clock generation device 200 can generate N delayed clock signals DCLK_1 to DCLK_N by using the reference clock signal RCLK.

[0112] In operation S110, the spread spectrum clock generation device 200 can select partial clock signals from the reference clock signal RCLK and the N delayed clock signals DCLK_1 to DCLK_N.

[0113] In operation S120, the spread spectrum clock generation device 200 can output the selected partial clock signals in the order of increasing phase delay.

[0114] In operation S130, the spread spectrum clock generation device 200 can determine whether the phase delay of the clock signal currently scheduled to be output among the selected partial clock signals exceeds 2π. According to one or more embodiments, based on the configuration file stored in the memory 233 and the reference identifier RIDF sent from the phase connection circuit 220, the spread spectrum clock generation device 200 can determine whether the phase delay of the clock signal currently scheduled to be output exceeds 2π.

[0115] When the phase delay of the clock signal currently scheduled to be output does not exceed 2π, which is recognized as option N in operation S130, the spread spectrum clock generation device 200 can output the clock signal scheduled to be output in operation S140.

[0116] When the phase delay of the clock signal to be output in the current plan exceeds 2π, option Y of S130 is recognized, and the spread spectrum clock generation device 200 can output the reference clock signal RCLK or the delayed clock signal with a phase delay greater than or equal to 0 and less than 2π in operation S150, instead of the clock signal to be output as planned.

[0117] The spread spectrum clock generation device according to one or more embodiments can be implemented using computer software instructions stored in a computer-readable storage medium and executed by a processor.

[0118] Regardless of whether the storage medium is directly and / or indirectly in an original state, a formatted state, an organized state, or any other accessible state, the storage medium can include relational databases, non-relational databases, in-memory databases, and databases that can store data and include distributed-type databases, such as other suitable databases that allow access to data through a storage controller. In addition, the storage medium can include any one or any two or more combinations of primary storage devices, secondary storage devices, tertiary storage devices, offline storage devices, volatile storage devices, non-volatile storage devices, semiconductor storage devices, magnetic storage devices, optical storage devices, and flash devices, hard disk drive storage devices, floppy disk drives, magnetic tapes, or any type of storage device such as other suitable data storage media, and the storage device is not limited to these listed examples.

[0119] In this specification, the software instructions can be any one or any two or more combinations of assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, and source code or object code written in any one or more combinations of programming languages, including object-oriented programming languages such as Smalltalk, C++, etc. and traditional procedural programming languages such as the C programming language or similar programming languages. However, these are only non-limiting examples, and other programming languages can be used.

[0120] While the present disclosure includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be illustrative only and not for purposes of limitation. The description of a feature or aspect in each example is considered to be applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order and / or if components in the described systems, architectures, devices, or circuits are combined in a different manner and / or are replaced or supplemented by other components or their equivalents. Accordingly, the scope of the present disclosure is not limited by the specific embodiments, but is defined by the claims and their equivalents, and all variations within the scope of the claims and their equivalents should be construed as being included in the present disclosure.

Claims

1. A clock signal generating device, comprising: a clock delay circuit configured to receive a reference clock signal and generate N delayed clock signals by using the reference clock signal, where N is a natural number greater than or equal to 2; and an output circuit configured to receive the N delayed clock signals and output at least a part of the N delayed clock signals as an output clock signal, wherein, among the at least a part of the delayed clock signals, the phase delay of the delayed clock signal output later in time is greater than or equal to the phase delay of the delayed clock signal output earlier in time, and wherein the period of the output clock signal is greater than or equal to the period of the reference clock signal.

2. The device according to claim 1, wherein The clock delay circuit includes N sub-clock delay circuits connected in series.

3. The device according to claim 1, wherein, The output circuit is configured to output only the delayed clock signals among the at least a part of the delayed clock signals that have a phase delay greater than or equal to 0 and less than 2π.

4. The device according to claim 3, wherein, The output circuit is configured to output the reference clock signal instead of the delayed clock signal to be output in response to the delayed clock signal to be output having a phase delay exceeding 2π.

5. The device according to claim 1, further comprising a phase connection circuit configured to identify the delayed clock signals among the N delayed clock signals that have a phase delay exceeding 2π and generate a reference identifier according to the identification result.

6. The apparatus according to claim 5, wherein, The output circuit is configured to output only the delayed clock signals among the at least a part of the delayed clock signals that have a phase delay greater than or equal to 0 and less than 2π based on the reference identifier.

7. The device according to claim 1, wherein The output circuit includes: a memory including a configuration file for identifying the at least a part of the delayed clock signals; and an output module configured to select the at least a part of the delayed clock signals from the N delayed clock signals by using the identifier included in the configuration file.

8. The apparatus according to claim 7, wherein The output module is configured to generate a count value, read the identifier corresponding to the count value by using the configuration file, and select the at least a part of the delayed clock signals by using the identifier.

9. The device according to claim 1, further comprising a compensation circuit configured to generate a compensation value in response to the period of the output clock signal being less than the period of the reference clock signal, such that the output clock signal corresponds to the reference clock signal.

10. A clock signal generating device, comprising: a clock delay circuit configured to receive a reference clock signal and generate N delayed clock signals by sequentially delaying the reference clock signal, where N is a natural number greater than or equal to 2; and an output circuit configured to receive the N delayed clock signals, select partial clock signals from the N delayed clock signals and the reference clock signal, and output the selected partial clock signals in the order from the minimum phase delay to the maximum phase delay as an output clock signal, Wherein, the period of the output clock signal is greater than or equal to the period of the reference clock signal.

11. The apparatus according to claim 10, further comprising a phase connection circuit configured to detect the phases of the N delayed clock signals and generate a reference identifier for identifying the delayed clock signals among the N delayed clock signals that have a phase delay exceeding 2π.

12. The apparatus according to claim 11, wherein, The output circuit outputs only the clock signals among the partial clock signals that have a phase delay greater than or equal to 0 and less than 2π based on the reference identifier.

13. The apparatus according to claim 11, wherein, The output circuit is configured to output, based on the reference identifier, the reference clock signal or the first clock signal with a small phase delay among the partial clock signals to replace the clock signals among the partial clock signals that have a phase delay exceeding 2π.

14. The apparatus according to claim 10, further comprising a compensation circuit configured to generate a compensation value in response to the period of the output clock signal being less than the period of the reference clock signal, such that the output clock signal corresponds to the reference clock signal.

15. A clock signal generation method, the method comprising: Receiving a reference clock signal; Generating N delayed clock signals by using the reference clock signal, where N is a natural number greater than or equal to 2; and Sequentially outputting at least a part of the N delayed clock signals as an output clock signal, wherein, among the at least a part of the delayed clock signals, the phase delay of the delayed clock signal output later in time is greater than or equal to the phase delay of the delayed clock signal output earlier in time, and wherein, the period of the output clock signal is greater than or equal to the period of the reference clock signal.

16. The method according to claim 15, wherein, The sequential output includes: outputting only the delayed clock signals among the at least a part of the delayed clock signals that have a phase delay greater than or equal to 0 and less than 2π.

17. The method according to claim 15, wherein, The sequential output includes: Identifying the excessive phase delay clock signals among the at least a part of the delayed clock signals that have a phase delay exceeding 2π; and Outputting the reference clock signal and the minimum phase delay clock signal with the minimum phase delay among the at least a part of the delayed clock signals to replace the excessive phase delay clock signals.

18. The method according to claim 15, wherein, The sequential output includes: Generating a count value according to the period; and Sequentially outputting the delayed clock signals corresponding to the count value among the at least a part of the delayed clock signals.

19. A clock signal generation method, the method comprising: Receiving a reference clock signal; Generating N delayed clock signals by sequentially delaying the reference clock signal, where N is a natural number greater than or equal to 2; Receiving the N delayed clock signals; Selecting partial clock signals from the N delayed clock signals and the reference clock signal; and Outputting the partial clock signals as an output clock signal in the order from the minimum phase delay to the maximum phase delay, wherein, the period of the output clock signal is greater than or equal to the period of the reference clock signal.

20. The method according to claim 19, further comprising: Detect the phases of the N delayed clock signals and generate a reference identifier for identifying the delayed clock signals among the N delayed clock signals that have a phase delay exceeding 2π.

21. The method according to claim 20 further comprises: Based on the reference identifier, output the reference clock signal or the first clock signal with a small phase delay among the partial clock signals to replace the clock signal with a phase delay exceeding 2π in the partial clock signals.

22. The method according to claim 20 further comprises: Generate a compensation value in response to the period of the output clock signal being less than the period of the reference clock signal, such that the output clock signal corresponds to the reference clock signal.

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