Memory device, electronic system, and related apparatus and method

Abstract

The present application relates to memory devices, electronic systems, and related apparatus and methods. The apparatus includes: a stack including an alternating sequence of dielectric structures and conductive structures; a first channel material extending vertically through the stack; and a second channel material adjacent to the first channel material and extending vertically through the stack. The first channel material has a first band gap, and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further includes: a conductive plug structure adjacent to each of the first channel material and the second channel material; and a conductive line structure adjacent to the conductive plug structure.

Description

[0001] Priority claim

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 955,529, filed on December 31, 2019, and U.S. Patent Application No. 16 / 781,733, filed on February 4, 2020, pursuant to 35 U.S.C. §1.19(e), the disclosures of each of which are hereby incorporated by reference in their entirety. Technical Field

[0003] Embodiments disclosed herein relate to microelectronic devices and microelectronic device fabrication. More specifically, embodiments of the present disclosure relate to an apparatus including a device structure (e.g., a vertical memory cell string) including a plurality of channel materials, and to related memory devices and electronic systems, and to methods of forming the apparatus. Background Art

[0004] NAND flash memory is a common type of flash memory device, so called because of the logical form in which the basic memory cell configuration is arranged. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the use of non-volatile memory continues to grow.

[0005] An ongoing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize an architecture that includes an array of vertical strings of memory cells. An example of a conventional vertical string of memory cells includes: a semiconductive material (e.g., channel material) that extends vertically through an opening in a stack of alternating conductive gate materials (e.g., word lines, control gates, access lines) and dielectric materials; and an oxide-nitride-oxide (ONO) structure that is laterally positioned between the semiconductive material of the stack and the channel. Each memory cell of the vertical string includes one conductive gate material and a portion of the ONO structure and a semiconductive material laterally adjacent to the one conductive gate material. This configuration permits a larger number of memory cells to be positioned in a given unit of die surface area by building the memory cell array upward (e.g., vertically) on the die, compared to a structure having a conventional planar (e.g., two-dimensional) arrangement of cells.

[0006] As the technology of 3D memory devices develops, arrays of vertical memory cell strings are produced and designed to have an increased number of alternating conductive gate materials and dielectric materials to increase the number of memory cell access devices (e.g., transistors). This increase results in a stack with a larger height, and a larger vertical memory cell string through the stack with the larger height. The semiconductor material (e.g., channel material) in the larger vertical memory cell string may need to carry an increased current, the so-called "string current", to effectively operate all the memory cells in the vertical string. The use of conventional polysilicon (also known as "polysilicon") material as a channel material may result in insufficient gate-induced drain leakage ("GIDL") current for performing erase functions on such long vertical memory strings. Therefore, polysilicon or silicon nitride channel materials alone may not be sufficient to generate sufficient GIDL current in a stack with a larger height within a reasonable time frame. Summary of the invention

[0007] According to an embodiment of the present disclosure, a device includes: a stack including an alternating sequence of dielectric structures and conductive structures; a first channel material extending vertically through the stack; and a second channel material adjacent to the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The device further includes: a conductive plug structure adjacent to each of the first channel material and the second channel material; and a conductive line structure adjacent to the conductive plug structure.

[0008] According to an embodiment of the present disclosure, another device includes: a first channel material extending vertically through a stack of alternating dielectric structures and conductive structures; and a second channel material adjacent to the first channel material and extending vertically through the stack. The band gap of the second channel material is relatively larger than the band gap of the first channel material. The device further includes a central dielectric material adjacent to the second channel material and extending vertically through the stack.

[0009] According to an embodiment of the present disclosure, a method of forming a device is disclosed. The method includes forming an opening through a stack of alternating conductive materials and dielectric materials. The method includes forming a first channel material within the opening. The method also includes forming a second channel material within the opening and adjacent to the first channel material. The method further includes forming a plug material within the opening and adjacent to each of the first channel material and the second channel material, and the band gap of the second channel material is different from the band gap of each of the first channel material and the plug material.

[0010] In addition, according to an embodiment of the present disclosure, a memory device includes: an access line extending in a first lateral direction; a data line extending in a second lateral direction substantially transverse to the first lateral direction; and a memory cell proximate an intersection of the access line and the data line. The memory cell includes a first channel material having a first band gap and a second channel material having a second band gap relatively larger than the first band gap. The second channel material is laterally adjacent to the first channel material.

[0011] According to an additional embodiment of the present disclosure, an electronic system includes a processor and a microelectronic device operably coupled to the processor. The microelectronic device includes vertical structures extending through a stack of alternating conductive materials and dielectric materials. Each vertical structure includes: a channel structure including a crystalline material laterally adjacent to an amorphous material and substantially surrounding the amorphous material along its height; and a conductive plug structure adjacent to the channel structure. The band gap of the amorphous material of the channel structure is different from the band gap of each crystalline material of the channel structure and the conductive plug structure. The microelectronic device also includes a data line adjacent to the vertical structure and an uppermost conductive gate structure laterally adjacent to the vertical structure. The conductive plug structure vertically overlaps the uppermost conductive gate structure at least partially. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 1H is a simplified partial cross-sectional view illustrating a method of forming an apparatus including a device structure according to an embodiment of the present disclosure ( Figures 1A to 1G ) and simplified partial top view ( Figure 1H ),in Figure 1H The top view is along Figure 1G Intercepted by line HH in.

[0013] Figures 2A to 2I is a simplified partial cross-sectional view illustrating a method of forming another apparatus including a device structure according to an additional embodiment of the present disclosure ( Figures 2A to 2H ) and simplified partial top view ( Fig.2I ),in Fig.2I The top view is along Figure 2H Intercepted by line II in.

[0014] Figure 3 is a partially cutaway perspective view of a vertical memory device including a microelectronic device structure having a stepped structure according to an embodiment of the present disclosure.

[0015] Figure 4 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Disclosed herein is an apparatus (e.g., a microelectronic device, a semiconductor device, a memory device) comprising: a stack including an alternating sequence of dielectric structures and conductive structures; a first channel material extending vertically through the stack; and a second channel material adjacent to the first channel material and extending vertically through the stack. The first channel material has a first band gap, and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to (e.g., electrically coupled to) each of the first channel material and the second channel material; and a conductive line structure adjacent to (e.g., electrically coupled to) the conductive plug structure. The first channel material is conductive to both electrons and holes, and the second channel material is conductive to electrons but not to holes. For example, the first channel material may include a polysilicon material, and the second channel material may include an oxide semiconductor material. Multiple channel materials (e.g., two or more materials) may allow for enhanced current transfer to be provided to the apparatus. In some embodiments, the apparatus further comprises a central dielectric material adjacent to the second channel material and extending vertically through the stack.

[0017] The first channel material may be formed using a conformal deposition process, the second channel material may be formed using a conformal deposition process or a non-conformal deposition process, and the central dielectric material (if present) may be formed using a non-conformal deposition process. A variety of channel materials (e.g., oxide semiconductor materials laterally adjacent to polysilicon materials) may be used to provide enhanced current transport in 3D memory arrays to enhance electronic conductivity without increasing leakage and / or voltage fluctuations during read and program operations. Devices including the first channel material and the second channel material according to embodiments of the present disclosure exhibit improved reliability, lower leakage, and improved electron mobility compared to conventional devices lacking a second vertically oriented channel material.

[0018] The following description provides specific details, such as material composition and processing conditions, in order to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the embodiments of the present disclosure may be practiced without adopting these specific details. In fact, the embodiments of the present disclosure may be practiced in conjunction with conventional semiconductor manufacturing techniques used in the semiconductor industry. In addition, the description provided below does not form a complete process flow for manufacturing equipment. The structure described below does not form a complete microelectronic device. Only those processing stages (e.g., actions) and structures necessary for understanding the embodiments of the present disclosure are described in detail below. Additional stages for forming a complete microelectronic device may be performed by conventional manufacturing techniques.

[0019] The materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, or physical vapor deposition (PVD). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by one of ordinary skill in the art. Unless the context indicates otherwise, material removal may be achieved by any suitable technique including, but not limited to, etching, grinding planarization (e.g., chemical-mechanical planarization), or other known methods.

[0020] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, assembly, structure, device or system. It is expected that the shapes depicted in the drawings will vary due to, for example, manufacturing techniques or tolerances. Therefore, the embodiments described herein should not be interpreted as being limited to specific shapes or regions as described, but rather include shape deviations, such as those caused by manufacturing. For example, a box-shaped region described or described may have rough and / or nonlinear features, and a circular region described or described may include some rough and / or linear features. In addition, the acute angles described may be rounded, and vice versa. Therefore, the regions described in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the region and do not limit the scope of the claims of the present invention. Each figure may not be drawn to scale. In addition, common elements between the drawings may retain the same numbering.

[0021] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes numerical values ​​and degrees of variation of numerical values ​​that one of ordinary skill in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the 90.0% to 110.0% range of the numerical value, such as within the 95.0% to 105.0% range of the numerical value, within the 97.5% to 102.5% range of the numerical value, within the 99.0% to 101.0% range of the numerical value, within the 99.5% to 100.5% range of the numerical value, or within the 99.9% to 100.1% range of the numerical value.

[0024] As used herein, spatially relative terms such as "below," "beneath," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," and similar may be used to conveniently describe the relationship of one element or feature to another, as illustrated in the drawings. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the drawings. For example, if the material in the drawings is inverted, an element described as being "below," "under," "under," or "on the bottom" of other elements or features would be oriented "above" or "on the top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein may be interpreted accordingly.

[0025] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" are referenced to a principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

[0026] As used herein, the term "configured to" refers to the size, shape, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and the device in a predetermined manner.

[0027] As used herein, referring to an element as being "on" or "above" another element means and includes the element being directly on top of, immediately adjacent to (e.g., directly laterally adjacent to, directly vertically adjacent to) another element, directly below another element, or in direct contact with another element. It also includes the element being indirectly on top of, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly vertically adjacent to) another element, indirectly below another element, or near another element, with other elements present in between. In contrast, when an element is referred to as being "directly on" or "immediately adjacent to" another element, there are no intervening elements.

[0028] As used herein, the term "apparatus" includes, but is not limited to, memory devices, and other microelectronic devices (e.g., semiconductor devices) that may or may not incorporate memory, such as logic devices, processor devices, or radio frequency (RF) devices. In addition, the apparatus may incorporate memory as well as other functions, such as a so-called "system on a chip" (SoC) that includes a processor and memory, or an apparatus that includes logic and memory. The apparatus may be a three-dimensional (3D) microelectronic device, including, but not limited to, a 3D NAND flash memory device, such as a 3D floating gate NAND flash memory device or a 3D replacement gate NAND flash memory device.

[0029] As used herein, the phrase "coupled to" refers to structures that are operatively connected to each other, such as through a direct resistive connection or through an indirect connection (eg, electrically connected via another structure).

[0030] As used herein, the term "amorphous" when referring to a material means and refers to a material having a substantially non-crystalline structure.

[0031] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and encompasses the degree to which a person of ordinary skill in the art would understand that the given parameter, characteristic, or condition meets a degree of variance (e.g., within an acceptable tolerance). By way of example, depending on a particular parameter, characteristic, or condition being substantially met, the parameter, characteristic, or condition may be met by at least 90.0%, may be met by at least 95.0%, may be met by at least 99.0%, may be met by at least 99.9%, or even by 100.0%.

[0032] As used herein, the term "substrate" means and includes a material (e.g., base material) or a structure on which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, and the like. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates (such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates), silicon epitaxial layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

[0033] Figures 1A to 1HA method of forming a microelectronic device structure (e.g., a memory device structure) according to an embodiment of the present disclosure is described, the microelectronic device structure including a memory cell at various stages of the method. For simplicity, the formation of a single opening in which a memory cell is formed is described, but a person of ordinary skill in the art will understand that the method may include simultaneously forming multiple (e.g., more than one, a large number) openings in which a memory cell will ultimately be formed. For ease of description Figures 1A to 1H , as Figures 1A to 1H The first direction shown in the direction may be defined as the X direction. Transverse to (eg, perpendicular to) Figure 1H The second direction of the first direction shown in can be defined as the Y direction. Figures 1A to 1G A third direction that is transverse to (eg, perpendicular to) each of the first direction and the second direction and that is in the direction shown in (eg, the vertical direction) may be defined as a Z direction. Figures 2A to 2I Similar directions are defined as shown in , as discussed in more detail below.

[0034] refer to Figure 1A , the device structure 100 includes a stack 104 of alternating layers of conductive material 106 and dielectric material 108 overlying a base conductive material 102 (e.g., a conductive line, such as a source line) on a base material (not shown). The conductive material 106 may be configured as a gate. An opening 110 may extend vertically through the stack 104. Figure 1A, the opening 110 may include a linear elongated opening (e.g., an orifice, a through hole) that exhibits one end at an uppermost surface of the stack 104 and another end at a lowermost surface of the stack 104. In additional embodiments, the opening 110 may exhibit a so-called "U-shaped" configuration having a pair of ends at an uppermost surface of the stack 104. The opening 110 may be a high aspect ratio (HAR) opening, such as having a HAR of at least about 20:1, at least about 50:1, at least about 100:1, or at least about 1000:1. The outer oxide material 112 may be formed laterally adjacent to the sidewalls of the stack 104 within the opening 110. The nitride material 114 may be formed laterally adjacent to the outer oxide material 112 within the opening 110 (e.g., formed laterally inwardly adjacent to the outer oxide material 112). The inner oxide material 116 may be formed laterally adjacent to the nitride material 114 within the opening 110 (e.g., formed laterally adjacent to the nitride material 114 inwardly). Collectively, the outer oxide material 112, the nitride material 114, and the inner oxide material 116 form an oxide-nitride-oxide (ONO) structure. The first plug material 122 (e.g., source contact plug material) may be formed adjacent to the base conductive material 102 (e.g., on or above the base conductive material 102) and formed laterally adjacent to the inner oxide material 116 within the opening 110 inwardly. The first plug material 122 may extend upward from the base conductive material 102 to at least partially vertically overlap with the lowermost conductive material 106A. The uppermost conductive material 106B may be located away from the lowermost conductive material 106A and proximate to the upper surface of the stack 104.

[0035] The alternating conductive material 106 and dielectric material 108 of the stack 104 may each be individually formed using conventional material processes, which are not described in detail herein. As a non-limiting example, the conductive material 106 and the dielectric material 108 may each be individually formed by one or more conventional deposition processes (e.g., PVD process, CVD process, ALD process, spin coating process) used to form the stack 104. As another non-limiting example, an initial stack including a vertical alternating sequence of sacrificial dielectric material and dielectric material is formed by a conventional process (e.g., a conventional deposition process such as one or more of PVD, CVD, and ALD), and then the sacrificial dielectric material is removed and replaced with the conductive material 106 to form the stack 104 by a so-called "replacement gate" process. To remove the sacrificial dielectric material, one or more narrow grooves can be formed through the initial stack to laterally expose the sacrificial dielectric material, an isotropic etch can be performed to selectively remove the sacrificial dielectric material and form gaps (e.g., undercuts) between vertically adjacent dielectric materials 108, and then a conductive material (e.g., one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, or tungsten nitride) can be deposited within the gaps to form conductive material 106.

[0036] refer to Figure 1B , the first channel material 118 can be formed within the opening 110 and formed above the exposed upper surface of the stack 104. The first channel material 118 can be formed adjacent to (eg, on) the sidewalls of the inner oxide material 116 and above the exposed upper surface of the first plug material 122, such as Figure 1B The first channel material 118 may be formed by a conformal deposition process (eg, CVD or ALD). The first channel material 118 may alternatively be epitaxially grown within the opening 110 .

[0037] The first channel material 118 may be formed at any desired thickness. By way of non-limiting example, the first channel material 118 may have an average thickness (e.g., width) of less than about 25 nanometers (nm), for example, in the range of about 1 nm to about 10 nm or about 10 nm to about 20 nm. The first channel material 118 may or may not exhibit a substantially homogeneous distribution of its elements. The first channel material 118 may be crystalline (e.g., single crystal, polycrystalline) or amorphous in whole or in part. The first channel material 118 may be undoped, or may include at least one dopant, such as a p-type dopant or an n-type dopant. In some embodiments, for example, the at least one dopant may include a p-type dopant including phosphorus (P) or arsenic (As). The first channel material 118 may include a gradient of at least one dopant, having a higher dopant concentration and a lower dopant concentration along its vertical portion (e.g., Z direction) and / or horizontal portion (e.g., X direction). The boundary between a region of higher dopant concentration and another region of lower dopant concentration may not necessarily be along a straight line.

[0038] The first channel material 118 may be or include a material exhibiting a room temperature band gap of less than or equal to about 1.4 eV (e.g., in a range of about 0.4 eV to about 0.85 eV, about 0.85 eV to about 1.12 eV, or about 1.12 eV to about 1.4 eV). Additionally, the first channel material 118 may be a semiconductor material including free charge carriers (e.g., electrons, holes), characterized as a conduction band minimum (CBM) material that serves as an electron path, and a valence band maximum (VBM) material that serves as a hole path. By way of example and not limitation, the first channel material 118 may include one or more of polycrystalline silicon (also referred to as "polysilicon," which has a room temperature band gap of about 1.12 eV), silicon germanium (which has a room temperature band gap of about 0.85 eV), germanium (which has a room temperature band gap of about 0.66 eV), and indium gallium arsenide (which has a room temperature band gap of about 0.7 eV).

[0039] refer to Figure 1C, the second channel material 119 may be formed (e.g., non-conformally) inwardly adjacent to the first channel material 118 within the opening 110 and above the exposed upper surface of the first channel material 118 overlying the stack 104. The second channel material 119 may substantially completely fill the remaining portion of the opening 110 (e.g., a substantially cylindrical opening) so as to extend completely laterally between the sidewalls of the first channel material 118 within the opening 110. In some embodiments, the second channel material 119 may be in direct physical contact with the first channel material 118 along one or more interfaces (e.g., a single interface), for example, along a vertical interface therebetween. In other embodiments, one or more optional materials (e.g., barrier materials, charge storage materials, etc.) (not shown) may be located between the second channel material 119 and the first channel material 118. As Figure 1C As shown in , the first channel material 118 may substantially surround (e.g., substantially continuously surround) the second channel material 119 along its entire height. In other words, the first channel material 118 and the second channel material 119 may substantially coexist along a vertical interface therebetween. In some embodiments, the second channel material 119 may be formed on the sidewalls of the first channel material 118 and above the exposed upper surface of the first plug material 122, such as Figure 1C . For example, the second channel material 119 may be in direct physical contact with the first plug material 122. In such embodiments, a portion of the first channel material 118 may initially be formed adjacent to (e.g., formed above) an exposed upper surface of the first plug material 122, which is subsequently removed from the upper surface of the first plug material 122 using one or more conventional removal processes (e.g., one or more so-called “through-etch” processes) prior to the formation of the second channel material 119. In other embodiments, a horizontal portion of the first channel material 118 adjacent to the first plug material 122 may remain between the second channel material 119 and the first plug material 122, such as Figure 1C Indicated by the dashed line in .

[0040] The second channel material 119 may be formed using one or more conventional conformal deposition processes (e.g., one or more of a conventional conformal CVD process or a conventional ALD process). Alternatively, the second channel material 119 may be formed using one or more conventional non-conformal deposition processes (e.g., one or more of a conventional PVD process (e.g., a conventional radio frequency PVD (RFPVD) process) or a conventional non-conformal CVD process). The second channel material 119 may alternatively be epitaxially grown within the opening 110.

[0041] Other processing conditions for forming the first channel material 118 and the second channel material 119, such as the temperature or pressure of the deposition behavior, may be selected as needed to achieve the desired composition of the first channel material 118 and the second channel material 119. By way of non-limiting example, the process temperature may be less than about 600° C., such as between about 200° C. and about 400° C. or between about 400° C. and about 600° C.

[0042] The second channel material 119 can be formed at any desired thickness. By way of non-limiting example, the second channel material 119 can have an average thickness (e.g., width) of less than about 100 nm, for example, in a range of about 10 nm to about 50 nm or about 50 nm to about 100 nm. In some embodiments, the width W of the second channel material 119 is about 100 nm. 119 The width W of the first channel material 118 may be 118 For example, each of the first channel material 118 and the second channel material 119 may occupy Figure 1A In other embodiments, the width W of the second channel material 119 is about one-half of the cross-sectional area of ​​the remainder of the opening 110 illustrated in FIG. 119 The width W of the first channel material 118 may be different from (eg, relatively larger or relatively smaller than) the width W of the first channel material 118. 118 The second channel material 119 may or may not exhibit a substantially homogeneous distribution of its elements. The second channel material 119 may be crystalline (e.g., single crystal) or amorphous in whole or in part. Additionally, the material form of the second channel material 119 may be the same as or different from the material form of the first channel material 118. For example, the material form of the second channel material 119 may be amorphous (e.g., having a substantially non-crystalline structure), and the material form of the first channel material 118 may include small grains of a semiconductive material (e.g., crystalline silicon) within an amorphous phase.

[0043] The second channel material 119 may be undoped, or may include at least one dopant. In some embodiments, the at least one dopant may be a p-type dopant. In other embodiments, the at least one dopant may be an n-type dopant, including but not limited to aluminum (Al) or silicon (Si), but not including phosphorus (P) or arsenic (As). In addition, the at least one dopant of the second channel material 119 may be the same or different from the at least one dopant of the first channel material 118. For example, the at least one dopant of the second channel material 119 may be an n-type dopant, and the at least one dopant of the first channel material 118 may be a p-type dopant. Alternatively, the dopants of the first channel material 118 and the second channel material 119 may be of the same type (e.g., an n-type dopant) with different concentrations relative to each other. The second channel material 119 may include a gradient of at least one dopant, with a higher dopant concentration and a lower dopant concentration along its vertical portion (e.g., Z direction) and / or horizontal portion (e.g., X direction). The boundary between an area of ​​higher dopant concentration and another area of ​​lower dopant concentration may not necessarily be along a straight line.

[0044] By way of non-limiting example, the second channel material 119 may include an oxide semiconductor material, such as zinc tin oxide (Zn x Sn y O, commonly referred to as "ZTO"), indium zinc oxide (In x Zn y O, commonly referred to as "IZO"), indium tin oxide (In x Sn y O z , commonly referred to as "ITO"), zinc oxide (Zn x O), InGaZnO (In x Ga y Zn z O, often referred to as "IGZO") (e.g., amorphous IGZO), indium gallium silicon oxide (In x Ga y Si z O a , commonly referred to as "IGSO"), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxide nitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), indium zinc oxide (In x Zn y O), InGaZnO (In x Ga y Znz O), zirconium oxide indium zinc (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O), aluminum oxide, tin indium zinc (Al x Sn y In z Zn a O), indium aluminum gallium oxide (In x Al y Ga z O a ), Indium Aluminum Gallium Nitride (In x Al y Ga z N), silicon indium zinc oxide (Si x In y Zn z O), zinc tin oxide (Zn x Sn y O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium oxide zinc tin (Zr x Zn y Sn z O), InGaSiO x Ga y Si z O) or similar materials. A chemical formula containing at least one of the above "x", "y", "z" and "a" (for example, Zn x Sn y O、In x Zn y O、In x Ga y Zn z O、In x Ga y Si z O、Al x Sn y In z Zn aO) represents a composite material containing an average ratio of "x" atoms of one element, "y" atoms of another element (if present), "z" atoms of an additional element (if present), and "a" atoms of another element (if present) for each atom of oxygen (O). Since the chemical formula represents relative atomic ratios and a loose chemical structure, the second channel material 119 may include a stoichiometric compound or a non-stoichiometric compound, and the values ​​of "x", "y", "z", and "a" may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having an elemental composition that cannot be represented by a well-defined ratio of natural numbers and violates the law of definite ratios. The second channel material 119 may include stoichiometric variations of the listed materials and / or combinations of materials (e.g., InGaZnO3, In2Zn3O6, etc.).

[0045] The second channel material 119 may be or include a material exhibiting a room temperature bandgap greater than about 1.5 eV (e.g., in the range of about 1.5 eV to about 3.0 eV or about 3.0 eV to about 4.0 eV). The bandgap of the second channel material 119 may be different from (e.g., relatively higher than) the bandgap of the first channel material 118. By way of non-limiting example, the bandgap of the first channel material 118 may be about 1.12 eV, and the bandgap of the second channel material 119 may be about 3.4 eV (e.g., about 3.45 eV). The second channel material 119 may also have a high electron mobility. As used herein, "high mobility" means and includes greater than about 5 cm 2 / V·s (e.g., at least about 10 cm 2 / V·s, for example, 10cm 2 / V·s to about 50cm 2 / V·s, for example, greater than about 15 cm 2 Therefore, the electron mobility of the second channel material 119 may be relatively higher than that of the first channel material 118 (eg, polysilicon having a dielectric constant of about 5 cm 2 / V·s to approximately 15cm 2 / V·s) of electron mobility. In addition, the second channel material 119 may be a semiconductor material containing free charge carriers (e.g., electrons) characterized as a conduction band minimum (CBM) material (e.g., serving as an electron path) rather than a valence band maximum (VBM) material (e.g., not serving as a hole path). In other words, the second channel material 119 may be conductive to electrons but not to holes, while the first channel material 118 may be conductive to electrons as well as conductive to holes. The material of the second channel material 119 may also be less sensitive to voltage changes than the material of the first channel material 118. By using a combination of multiple channel materials, the device structure 100 is less prone to leakage during read and program operations of a device containing the device structure 100. Using more than one channel material can achieve improved reliability, lower leakage, and improved mobility compared to a device structure containing only one channel material (e.g., polysilicon material).

[0046] refer to Figure 1D , portions of the first channel material 118 and the second channel material 119 that vertically extend beyond the plane of the upper surface of the stack 104 (e.g., outside the opening 110) may be removed, for example, by CMP or etching. In addition, portions of each of the first channel material 118 and the second channel material 119 may be selectively removed, for example, by etching, to recess the first channel material 118 and the second channel material 119 within the opening 110. The uppermost surface of the remaining portion of each of the first channel material 118 and the second channel material 119 within the opening 110 may be below the uppermost surface of the stack 104 (e.g., vertically recessed from the uppermost surface), and may be below the upper surface of the uppermost conductive material 106B, as shown. Figure 1D In some embodiments, the upper surfaces of the first channel material 118 and the second channel material 119 may be substantially coplanar with each other. In other embodiments, the upper surface of the second channel material 119 may be different from (eg, relatively higher or relatively lower than) the upper surface of the first channel material 118.

[0047] Next reference Figure 1E, a second plug material 124 (e.g., a drain contact plug material) may be formed within the opening 110 and fill the rest of the opening 110. The second plug material 124 may be adjacent to (e.g., electrically coupled to) each of the first channel material 118 and the second channel material 119. The second plug material 124 may include a semiconductor material, such as one or more of polysilicon, silicon germanium, and germanium. The second plug material 124 may be conductively doped. By way of non-limiting example, the second plug material 124 may include a first concentration of n-type dopants, and the second channel material 119 may include a second concentration of n-type dopants that is different from (e.g., relatively greater than or relatively less than) the first concentration. The process for forming the second plug material 124 may be, for example, CVD or ALD.

[0048] In some embodiments, the band gap of the second plug material 124 may be different from (e.g., relatively larger or smaller than) the band gap of the first channel material 118 and / or the second channel material 119. By way of example and not limitation, the second plug material 124 may exhibit a room temperature band gap of at least about 1.40 eV. In other embodiments, the band gap of the second plug material 124 may be substantially similar to (e.g., substantially equal to) the band gap of at least one of the channel materials (e.g., the first channel material 118). In additional embodiments, the band gap of the second plug material 124 may be smaller than the band gap of each of the first channel material 118 and the second channel material 119. In such embodiments, for example, the second plug material 124 may include a germanium-containing material, while each of the first channel material 118 and the second channel material 119 includes one or more materials with relatively larger band gaps, such as polysilicon and oxide semiconductor materials. Therefore, the band gap of the second channel material 119 may be relatively larger than the band gaps of the second plug material 124 and the first channel material 118. Forming the second channel material 119 from a material exhibiting a room temperature bandgap greater than about 1.5 eV (e.g., about 3.4 eV) can increase the gate induced drain leakage (“GIDL”) current in a vertical string erase operation of a resulting device (e.g., a memory device), as compared to providing only a single channel material (e.g., the first channel material 118) exhibiting a bandgap less than about 1.4 eV (e.g., about 1.12 eV) (the bandgap can be substantially similar to the bandgap of the second plug material 124).

[0049] In addition to within the opening 110, the second plug material 124 may initially be formed adjacent to (e.g., above) the upper surface of the stack 104. The portion of the second plug material 124 that vertically extends beyond the plane of the upper surface of the stack 104 may subsequently be removed, for example, by CMP or etching. The remaining portion of the second plug material 124 may be in direct physical contact with and electrically coupled to each of the first channel material 118 and the second channel material 119. For example, the portion of the second plug material 124 may vertically overlie and be in direct physical contact with the upper surface of the remaining portion of each of the first channel material 118 and the second channel material 119 while being adjacent to, within, and in direct physical contact with the sidewalls of the inner oxide material 116, such that the maximum lateral extent of the second plug material 124 is substantially equal to the maximum lateral extent of the first channel material 118, as shown in FIG. Figure 1E as shown in .

[0050] The uppermost conductive material 106B may have a vertical thickness greater than the corresponding thicknesses of the other conductive materials 106 of the stack 104. The relatively large vertical thickness of the uppermost conductive material 106B may easily lead to a relatively large error margin when forming the range of the second plug material 124 to at least partially vertically overlap with the uppermost conductive material 106B. By way of example and not limitation, the vertical thickness of the uppermost conductive material 106B may be greater than or equal to about 45 nm, while the corresponding vertical thicknesses of the other conductive materials 106 may be about 35 nm.

[0051] refer to Figure 1F , cap material 128 may be formed on or over the upper surface of each of stack 104, outer oxide material 112, nitride material 114, inner oxide material 116, and second plug material 124. Cap material 128 may include one or more dielectric materials, such as one or more of silicon oxide (e.g., silicon dioxide) and silicon nitride. Cap material 128 may be formed using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment not described in detail herein. For example, cap material 128 may be deposited (e.g., by one or more of CVD, PVD, ALD, spin coating) over the upper surface of stack 104, outer oxide material 112, nitride material 114, inner oxide material 116, and second plug material 124.

[0052] refer to Figure 1G, a data line 126 (e.g., a bit line, a digit line) may be formed on or above the uppermost surface of the second plug material 124. The data line 126 may be formed using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment not described in detail herein. For example, a portion of the cap material 128 overlying the second plug material 124 may be removed (e.g., via conventional photolithography patterning and etching processes) to form a plug opening (not shown) overlying the second plug material 124. A conductive material (e.g., tungsten, tungsten nitride, titanium, titanium nitride) may be formed into the plug opening, and an excess portion of the conductive material may be removed (e.g., via a CMP process) to form the data line 126. The data line 126 may extend laterally perpendicular to the conductive material 106 of the stack 104.

[0053] Continue to refer Figure 1G , individual (e.g., a single) conductive material 106 of the stack 104, and adjacent portions of the outer oxide material 112, nitride material 114, inner oxide material 116, first channel material 118, and second channel material 119 laterally adjacent to the individual conductive material 106 may form individual vertical memory cells 120 having a so-called metal-oxide-nitride-oxide-semiconductor ("MONOS") configuration. A vertical stack of multiple (e.g., more than one) vertical memory cells 120 within the opening 110 may form a vertical string (e.g., multiple vertical strings) of memory cells 120. By way of non-limiting example, the device structure 100 includes a three-dimensional NAND flash memory cell. The data line 126 may provide electrical access to the vertical string of memory cells 120. One or more (e.g., one to five) of the lowermost conductive materials 106, 106A may be configured as a select gate source ("SGS"). One or more (e.g., one to five) of the uppermost conductive materials 106, 106B may be configured as a select gate drain ("SGD"). The conductive material 106 between the select gate source and the select gate drain may be configured as an access line (e.g., a word line). There may be any suitable number of access lines in the stack 104, such as about 32, about 64, about 72, about 96, or about 128.

[0054] Figure 1H illustrate Figure 1G A simplified partial top view of the device structure 100 taken along the section line HH. The opening 110 ( Figure 1G ) may include a substantially round (e.g., substantially circular) horizontal cross-sectional area. In other embodiments, the horizontal cross-sectional shape of the opening 110 may have an alternative shape (e.g., non-curved, non-circular, non-circular). Figure 1HAs best shown in the top view of FIG. 1 , the outer oxide material 112 is laterally adjacent to the conductive material 106 and the dielectric material 108 of the stack 104 ( Figure 1G ), nitride material 114 is laterally adjacent to outer oxide material 112, and inner oxide material 116 is laterally adjacent to nitride material 114. First channel material 118 may be laterally adjacent to inner oxide material 116, and second channel material 119 may be laterally adjacent to first channel material 118. Including second channel material 119 adjacent to first channel material 118 may enhance electronic conductivity without increasing leakage during read and program operations, resulting in improved reliability, lower leakage, and improved mobility during operation, compared to conventional devices having a single (e.g., one) channel material.

[0055] Combination Figure 1H refer to Figure 1G , the data line 126 and the second plug material 124 may be coupled to each other along a horizontal interface therebetween. In addition, the second plug material 124 may be coupled to the first channel material 118 along a horizontal interface therebetween, which may be a so-called "homojunction" in which the materials of the second plug material 124 and the first channel material 118 are substantially similar (e.g., substantially the same composition), and therefore exhibit substantially similar (e.g., equal) band gaps on each side of the interface. By way of example and not limitation, each of the second plug material 124 and the first channel material 118 may include polysilicon materials exhibiting substantially equal band gaps. Furthermore, the first channel material 118 and the second channel material 119 may be coupled to each other along a vertical interface therebetween. The vertical interface may be a so-called "heterojunction," where the materials of the first channel material 118 and the second channel material 119 are different and / or exhibit one or more of different dopant concentrations and different dopant profiles, which enhances band bending adjacent to the heterojunction, which may enhance confinement of charge carriers (e.g., electrons) to the first channel material 118 and the second channel material 119. Thus, the first channel material 118 and the second channel material 119 may have band gaps that are different (e.g., unequal) from each other. In some embodiments, the first channel material 118 may be in direct physical contact with the second channel material 119 and substantially surround (e.g., substantially continuously surround) the second channel material 119, such as Figure 1H In other embodiments, the positions of the first channel material 118 (eg, polysilicon material) and the second channel material 119 (eg, oxide semiconductor material) may be reversed so that the first channel material 118 is located in the central portion of the opening 110 ( Figure 1G ) and the second channel material 119 may be in direct physical contact with the first channel material 118 and substantially surround (eg, substantially continuously surround) the first channel material 118.

[0056] During use and operation, current may flow between the material of the second plug material 124 (e.g., polysilicon material) and at least one (e.g., each) of the first channel material 118 and the second channel material 119. The inclusion of the second channel material 119 (e.g., oxide semiconductor material) adjacent to the first channel material 118 enables current to be increased during a read operation without increasing leakage during read and boost operations, which allows a larger cross-sectional area of ​​the channel material to generate GIDL current. In other words, the presence of the second channel material 119 provides increased electron conductivity during a read operation, while the first channel material 118 provides conductivity to generate GIDL-induced holes and conduct the holes via the vertical string for block erasing of the memory cells. Thus, the second channel material 119 achieves increased electron conduction while reducing (e.g., minimizing) leakage during read and program operations, compared to a conventional channel including only a single channel material.

[0057] During operation of the device structure 100, current may be applied to the data line 126, thereby establishing a flow of current (e.g., string current) through at least a portion of the second plug material 124 and to the first channel material 118 and the second channel material 119. Without being bound by any theory, it is believed that when current flows from the data line 126 through the second plug material 124 to at least one (e.g., each) of the first channel material 118 and the second channel material 119, a generation region may be established along the interface located therebetween. When current flows near the interface during the GIDL mode, band-to-band tunneling ("BTBT") may be generated (e.g., enhanced) in the generation region located along at least one (e.g., each) interface. Since the current flows through the second channel material 119 as well as through the first channel material 118, the flow of current is not reduced (e.g., weakened) during the sensing operation. Thus, BTBT may be established or increased without reducing current supplied to the vertical string of memory cells 120, at least in part due to the second channel material 119 having a bandgap that is different from the bandgap of each of the second plug material 124 and the first channel material 118. The increased GIDL current allows more reliable charge to flow into the first channel material 118 and the second channel material 119 to bias the body regions of the individual memory cells 120. Reliable bias voltages are required in many memory operations, such as erase operations, where larger voltage differences are used.

[0058] During a programming operation, a boost operation may be used to bias at least one (e.g., each) of the first channel material 118 and the second channel material 119 of an unselected string to prevent the charge storage structure of the unselected string from being erased in the memory cells 120 that are not selected for the erase operation. In the boost operation, a voltage may be applied to the first channel material 118 and the second channel material 119 at least in part by capacitively coupling the first channel material 118 and the second channel material 119 to an applied voltage on the respective gates of the individual memory cells 120. For example, a voltage (e.g., about 10 volts) may be placed on the gates, and a certain amount of the bias voltage (e.g., about 7 volts) may be transferred to the first channel material 118 and the second channel material 119 via coupling. In some embodiments, the applied voltage may be, for example, a negative voltage applied to the uppermost conductive material 106B. Using the boost operation, the charge within the second channel material 119 may be maintained with reduced (e.g., minimal) leakage to the second plug material 124 and / or the first plug material 122. Thus, a low GIDL current is required during boost operations. Thus, using more than one (e.g., two or more) channel materials with different bandgaps as described above can provide reliable biasing during erase operations, and can also provide reliable charge retention during boost operations. In other words, a larger combined cross-sectional area of ​​the first channel material 118 and the second channel material 119 can be used for so-called "on" current, while a smaller cross-sectional area of ​​the first channel material 118 (e.g., alone) can be used for so-called "off" current to improve string current. Thus, the device structure 100 acts as a thick channel (e.g., the combined first channel material 118 and the second channel material 119) for on current and a thin channel (e.g., the first channel material 118) for off current. The combined first channel material 118 and second channel material 119 enable the on-current to be increased during a read operation without increasing leakage during the read operation, which enables the level of the “on” current to be increased without increasing leakage during the “off” current and / or voltage fluctuations associated with possible notch sites in the polysilicon material of the first channel material 118.

[0059] Therefore, according to an embodiment of the present disclosure, a device includes: a stack including an alternating sequence of alternating dielectric structures and conductive structures; a first channel material extending vertically through the stack; and a second channel material adjacent to the first channel material and extending vertically through the stack. The first channel material has a first band gap, and the second channel material has a second band gap that is relatively larger than the first band gap. The device further includes a conductive plug structure adjacent to each of the first channel material and the second channel material; and a conductive line structure adjacent to the conductive plug structure.

[0060] In addition, according to an embodiment of the present disclosure, a method of forming a device includes forming an opening through a stack of alternating conductive materials and dielectric materials. The method includes forming a first channel material within the opening. The method also includes forming a second channel material within the opening and adjacent to the first channel material. The method further includes forming a plug material within the opening and adjacent to each of the first channel material and the second channel material, and the band gap of the second channel material is different from the band gap of each of the first channel material and the plug material.

[0061] Those skilled in the art will appreciate that according to additional embodiments of the present disclosure, the above description of Figures 1A to 1H The described features and feature configurations may be adapted to the design needs of different microelectronic devices (e.g., different memory devices). By way of non-limiting example, according to additional embodiments of the present disclosure, Figures 2A to 2I A simplified partial cross-sectional view of a method of forming a microelectronic device structure having a configuration different from device structure 100 is shown. Functionally similar features (e.g., structures, devices) are referred to with similar reference numerals throughout the remainder of the description and drawings. To avoid repetition, the remaining figures (including Figures 2A to 2I ). In fact, unless otherwise described below, features designated by reference numerals of previously described features (regardless of whether the previously described features are first described before or after this paragraph) should be understood to be substantially similar to the previously described features.

[0062] Figure 2A A simplified partial cross-sectional view of a device structure 100' is shown. Figure 2A During the processing stages depicted in FIG. 1 , the device structure 100 ′ is Figure 1A The processing stages depicted in may be substantially similar to device structure 100 .

[0063] refer to Figure 2B , the first channel material 118 may be formed (e.g., conformally formed) over the exposed surface of the device structure 100' inside and outside the opening 110 extending vertically through the stack 104. In some embodiments, the first channel material 118 may be epitaxially grown within the opening 110. The first channel material 118 may include the same Figure 1B The first channel material 118 is described as having substantially the same material and properties (eg, structure, dopants, bandgap, etc.).

[0064] refer to Figure 2C, the second channel material 119 can be formed adjacent to (e.g., formed above) an exposed surface of the device structure 100′ inside and outside the opening 110 extending vertically through the stack 104. For example, the second channel material 119 can be formed adjacent to (e.g., formed above) an exposed surface of the first channel material 118, Figure 1C 10. However, the second channel material 119 may be conformally formed on the first channel material 118 without substantially completely filling the opening 110. The second channel material 119 may be formed by a conformal deposition process (e.g., CVD or ALD). The second channel material 119 may alternatively be epitaxially grown within the opening 110. The second channel material 119 may be formed at any desired thickness. By way of non-limiting example, the second channel material 119 may include an average thickness (e.g., width) of less than about 25 nm, for example, in a range of about 1 nm to about 10 nm or about 10 nm to about 20 nm. The second channel material 119 may include the same as described above with reference to Figure 1C The second channel material 119 is described as having substantially the same material and properties (eg, structure, dopant, bandgap, electron mobility, etc.).

[0065] refer to Figure 2D , the central dielectric material 130 may be formed adjacent to the second channel material 119 within the opening 110. The central dielectric material 130 may substantially completely fill the opening 110 (e.g., a substantially cylindrical opening) so as to completely extend laterally between the sidewalls of the second channel material 119 within the opening 110. The central dielectric material 130 may be formed in a central portion of the opening 110 and may, for example, serve as a structural support within the device structure 100′. Figure 2D As shown in , the second channel material 119 can substantially surround (e.g., substantially continuously surround) the central dielectric material 130. The central dielectric material 130 can be formed at any desired thickness. By way of non-limiting example, the central dielectric material 130 can have an average thickness (e.g., width) of less than about 100 nm, for example, in a range of about 20 nm to about 50 nm or about 50 nm to about 100 nm. In some embodiments, the width W of the second channel material 119 is about 100 nm. 119 The width W of the first channel material 118 may be 118 In other embodiments, the width W of the second channel material 119 is substantially similar (eg, substantially the same). 119 The width W of the first channel material 118 may be different from (eg, relatively larger or relatively smaller than) the width W of the first channel material 118. 118 In addition, the width W of the core dielectric material 130 is 130 The width W of the second channel material 119 may be relatively larger than 119 and the width W of the first channel material 118 118The width W of the central dielectric material 130 is 130 It can also be larger than the width W of the first channel material 118 118 The width W of the second channel material 119 is 119 Alternatively, the width W of the core dielectric material 130 is 130 The width W of the second channel material 119 may be substantially similar to or relatively smaller than the width W of the second channel material 119. 119 and / or the width W of the first channel material 118 118 .

[0066] The core dielectric material 130 may be formed of and includes, but is not limited to, oxides (e.g., silicon dioxide (SiO2)), nitrides (e.g., silicon nitride (SiN)), or oxynitrides. In some embodiments, the core dielectric material 130 is a high-quality silicon oxide material, such as ALD SiO x . For example, the central dielectric material 130 may be a highly uniform and highly conformal silicon oxide material (e.g., a highly uniform and highly conformal silicon dioxide material) such that no voids are present in the central portion. The central dielectric material 130 may be highly uniform and highly conformal when deposited. Specifically, the central dielectric material 130 may be formulated to be formed in the HAR opening 110 without forming voids. In other embodiments, the central dielectric material 130 may be formed of and include a material suitable for non-conformal deposition within the opening 110. In additional embodiments, the central dielectric material 130 may be formed of and include air-filled voids.

[0067] The core dielectric material 130 may be formed using one or more conventional conformal deposition processes (e.g., one or more of a conventional conformal CVD process or a conventional ALD process). Alternatively, the core dielectric material 130 may be formed using one or more conventional non-conformal deposition processes (e.g., one or more of a conventional PVD process (e.g., a conventional radio frequency PVD (RFPVD) process) or a conventional non-conformal CVD process).

[0068] refer to Figure 2E , portions of the first channel material 118, the second channel material 119, and the center dielectric material 130 that vertically extend beyond the plane of the upper surface of the stack 104 may then be removed, for example, by CMP or etching. Additionally, portions of each of the first channel material 118, the second channel material 119, and the center dielectric material 130 within the opening 110 may be selectively removed, for example, by etching. An uppermost surface of the remaining portion of each of the first channel material 118, the second channel material 119, and the center dielectric material 130 within the opening 110 may be below (e.g., vertically recessed from) the uppermost surface of the stack 104, and may be below the upper surface of the uppermost conductive material 106B, as shown. Figure 2E In some embodiments, the upper surfaces of the first channel material 118, the second channel material 119, and the core dielectric material 130 may be substantially coplanar with each other. In other embodiments, the upper surfaces of the first channel material 118 and / or the second channel material 119 may be different from each other (e.g., relatively higher or relatively lower), and different from (e.g., relatively higher or relatively lower) the upper surface of the core dielectric material 130.

[0069] refer to Figure 2F , the second plug material 124 may be formed within the opening 110 and fill the remaining portion of the opening 110. The second plug material 124 may be adjacent to (eg, electrically coupled to) each of the first channel material 118 and the second channel material 119. The second plug material 124 may include the same Figure 1E The second plug material 124 may be substantially the same material and properties (eg, dopant, bandgap, etc.) as described above. Figure 1E The second plug material 124 may be formed by processes similar to those described above (e.g., deposition and material removal processes). For example, the second plug material 124 may initially be formed adjacent to (e.g., formed above) an upper surface of the stack 104, except within the opening 110. The portion of the second plug material 124 that vertically extends beyond the plane of the upper surface of the stack 104 may then be removed, for example, by CMP or etching. The remaining portion of the second plug material 124 may be in direct physical contact with and electrically coupled to each of the first channel material 118 and the second channel material 119. For example, a portion of the second plug material 124 may vertically overlie and be in direct physical contact with the upper surfaces of the first channel material 118, the second channel material 119, and the central dielectric material 130, while being adjacent to, within, and in direct physical contact with the inner oxide material 116, such that the maximum lateral extent of the second plug material 124 is substantially equal to the maximum lateral extent of the first channel material 118, as shown in FIG. Figure 2F as shown in .

[0070] refer to Figure 2G , a cap material 128 may be formed on or over the upper surface of the stack 104, the outer oxide material 112, the nitride material 114, and the inner oxide material 116. The cap material 128 may be substantially similar to the previously described Figure 1F The cap material 128 described herein may be used in conjunction with the previously described Figure 1F The capping material 128 is formed in substantially the same manner as described.

[0071] refer to Figure 2HAfter removing a portion of the cap material 128, a data line 126 (eg, a bit line, a digit line) may be formed on or above the uppermost surface of the second plug material 124. The data line 126 may be substantially similar to the previously described Figure 1G The data line 126 described above can be compared with the previously described Figure 1G Data line 126 is formed in substantially the same manner as described. Data line 126 can provide electrical access to the vertical string of memory cells 120.

[0072] Fig.2I illustrate Figure 2H A simplified partial top view of the device structure 100' taken along the section line II. The opening 110 ( Figure 2H ) may include a substantially round (e.g., substantially circular) horizontal cross-sectional area. In other embodiments, the horizontal cross-sectional shape of the opening 110 may have an alternative shape (e.g., non-curved, non-circular, non-circular). Fig.2I As best shown in the top view of FIG. 1 , the outer oxide material 112 is laterally adjacent to the conductive material 106 and the dielectric material 108 of the stack 104 ( Figure 2H ), nitride material 114 is laterally adjacent to outer oxide material 112, and inner oxide material 116 is laterally adjacent to nitride material 114. First channel material 118 may be laterally adjacent to inner oxide material 116, second channel material 119 may be laterally adjacent to first channel material 118, and central dielectric material 130 may be laterally adjacent to second channel material 119 within a central portion of opening 110 ( Figure 2H In some embodiments, the first channel material 118 may be in direct physical contact with the second channel material 119 and substantially surround (eg, substantially continuously surround) the second channel material 119, such as Fig.2I . In other embodiments, the positions of the first channel material 118 (e.g., polysilicon material) and the second channel material 119 (e.g., oxide semiconductor material) may be reversed such that the first channel material 118 is positioned proximate to the central dielectric material 130 located within the central portion of the opening 110 and the second channel material 119 may be in direct physical contact with and substantially surround (e.g., substantially continuously surround) the first channel material 118. Including the second channel material 119 adjacent to the first channel material 118 may enhance electronic conductivity without increasing leakage and / or voltage fluctuations during read and program operations, resulting in improved reliability, lower leakage, and improved mobility during operation, compared to conventional devices having a central dielectric material and a single (e.g., one) channel material. By including the central dielectric material 130, confining carriers within a reduced dimension (e.g., width) of the first channel material 118 may result in enhanced channel control.

[0073] Therefore, according to an embodiment of the present disclosure, a device includes: a first channel material extending vertically through a stack of alternating dielectric structures and conductive structures; and a second channel material adjacent to the first channel material and extending vertically through the stack. The band gap of the second channel material is relatively larger than the band gap of the first channel material. The device further includes a central dielectric material adjacent to the second channel material and extending vertically through the stack.

[0074] Figure 3 A partially cut-away perspective view of a portion of a microelectronic device 300 (e.g., a vertical memory device such as a 3D NAND flash memory device) is illustrated, the microelectronic device 300 including a microelectronic device structure 302 including a level 304 of conductive and insulating structures defining a stepped structure 306 and a contact structure 308 electrically connected to the steps of the stepped structure 306. Although the vertical memory device (e.g., a 3D NAND flash memory device) is shown by way of example, one of ordinary skill in the art will appreciate that the GIDL current is increased as the enhancement mode BTBT is produced while the leakage is reduced by utilizing the second channel material 119 in conjunction with the second plug material 124 and the first channel material 118 ( Figure 1F ) is not dependent on a particular storage medium, and the second channel material 119 may be utilized in any such memory device including similar materials and processes. In the current example, the microelectronic device structure 302 (e.g., the level 304 including the conductive and insulating structures, the stepped structure 306, and the contact structure 308) may be substantially similar to the previously described embodiments, respectively. Figures 1A to 1H 2A to 2I (e.g., including layers of conductive material 106 and dielectric material 108) and can be formed in substantially the same manner as the device structures 100, 100'. The microelectronic device 300 may further include vertical strings 312 of memory cells 320 coupled in series with each other, data lines 326 (e.g., corresponding to Figures 1A to 2I100 ′), a data line 126, a source level 318, an access line 310, a first select gate 314 (e.g., an upper select gate, a drain select gate (SGD)), a select line 322, a second select gate 324 (e.g., a lower select gate, a source select gate (SGS)), and an additional contact structure 316 of the device structure 100, 100′ shown in FIG. 100 . The vertical string 312 of memory cells 320 extends vertically and orthogonally to the conductive lines and levels (e.g., data line 326, source level 318, level 304 of the microelectronic device structure 302, access line 310, first select gate 314, select line 322, second select gate 324), and the contact structure 308 and additional contact structure 316 can electrically couple the components to each other as shown (e.g., electrically coupling the select line 322 to the first select gate 314, and electrically coupling the access line 310 to the level 304 of the microelectronic device structure 302). The microelectronic device 300 may also include a control unit 328, which may include one or more of the following: a string driver circuit, a pass gate, a circuit for selecting a gate, a circuit for selecting a conductive line (e.g., data line 326, access line 310), a circuit for amplifying a signal, and a circuit for sensing a signal. For example, the control unit 328 may be electrically coupled to the data line 326, the source layer 318, the access line 310, the first select gate 314, and the second select gate 324.

[0075] Therefore, according to an embodiment of the present disclosure, a memory device includes: an access line extending in a first lateral direction; a data line extending in a second lateral direction substantially transverse to the first lateral direction; and a memory cell proximate an intersection of the access line and the data line. The memory cell includes a first channel material having a first band gap and a second channel material having a second band gap relatively larger than the first band gap. The second channel material is laterally adjacent to the first channel material.

[0076] The microelectronic device structure (eg, device structure 100, 100') and microelectronic device (eg, microelectronic device 300) according to embodiments of the present disclosure may be used in embodiments of electronic systems of the present disclosure. For example, Figure 4 4 is a block diagram of an illustrative electronic system 400 according to an embodiment of the present disclosure. The electronic system 400 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., a or The electronic system 400 includes at least one memory device 402. The memory device 402 may include, for example, one or more embodiments of the microelectronic device structures (e.g., device structures 100, 100') and microelectronic devices (e.g., microelectronic device 300) previously described herein. The electronic system 400 may further include at least one electronic signal processor device 404 (often referred to as a "microprocessor"). The electronic signal processor device 404 may optionally include embodiments of the microelectronic device structures (e.g., device structures 100, 100') and microelectronic devices (e.g., microelectronic device 300) previously described herein. The electronic system 400 may further include one or more input devices 406 for inputting information into the electronic system 400 by a user, such as a mouse or other pointing device, keyboard, touch pad, button, or control panel. The electronic system 400 may further include one or more output devices 408 for outputting information (e.g., visual or audio output) to a user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 406 and output device 408 may include a single touch screen device that can be used to input information into electronic system 400 and output visual information to a user. Input device 406 and output device 408 may be in electrical communication with one or more of memory device 402 and electronic signal processor device 404.

[0077] Therefore, according to an embodiment of the present disclosure, an electronic system includes a processor and a microelectronic device operably coupled to the processor. The microelectronic device includes a vertical structure extending through a stack of alternating conductive materials and dielectric materials, and a data line adjacent to the vertical structure. Each vertical structure includes a channel structure, which includes a crystalline material laterally adjacent to an amorphous material and substantially surrounding the amorphous material along its height; and a conductive plug structure adjacent to the channel structure. The band gap of the amorphous material of the channel structure is different from the band gap of each crystalline material of the channel structure and the conductive plug structure. The electronic system further includes an uppermost conductive gate structure laterally adjacent to the vertical structure. The conductive plug structure vertically overlaps the uppermost conductive gate structure at least partially.

[0078] The multiple (e.g., two or more) channel materials disclosed herein can provide enhanced current transfer in 3D memory arrays, which can be suitable for use with devices having an increased number of stacked transistors. The different (e.g., higher) band gap of the disclosed second channel material can allow the GIDL current value to be increased to obtain improved reliability, lower leakage, and improved mobility compared to a device structure that includes only a first channel material (e.g., polysilicon). The method facilitates forming the device structure in a simple and cost-effective manner using lower process temperatures and simplified process behaviors. In addition, the multiple channel materials can be applicable to many 3D memory architectures that include select gate source and select gate drain transistors. The scalability of subsequent device structures (e.g., 3D NAND flash memory device structures) using multiple channel materials according to embodiments of the present disclosure can also be enhanced.

[0079]

[0013] Embodiments of the present disclosure may be further characterized as set forth below but are not limited to the manner set forth below.

[0080] Embodiment 1: A device comprising: a stack including an alternating sequence of dielectric structures and conductive structures; a first channel material extending vertically through the stack, the first channel material having a first band gap; a second channel material adjacent to the first channel material and extending vertically through the stack, the second channel material having a second band gap relatively larger than the first band gap; a conductive plug structure adjacent to each of the first channel material and the second channel material; and a conductive line structure adjacent to the conductive plug structure.

[0081] Embodiment 2: The apparatus of Embodiment 1, wherein the conductive plug structure comprises a conductive material having a third band gap, the second band gap being larger than each of the first band gap and the third band gap.

[0082] Embodiment 3: The apparatus of Embodiment 2, wherein the third band gap is substantially equal to the first band gap.

[0083] Embodiment 4: The device according to any one of embodiments 1 to 3, wherein: an interface between the second channel material and the first channel material comprises a heterojunction; and another interface between the conductive plug structure and the first channel material comprises a homojunction.

[0084] Embodiment 5: The apparatus of any one of Embodiments 1 to 4, wherein each of the conductive plug structure, the first channel material, and the second channel material comprises an n-type dopant, the second channel material having a greater concentration of the n-type dopant than the conductive plug structure.

[0085] Embodiment 6: The device of any one of embodiments 1 to 5, wherein the first channel material is conductive to both electrons and holes, and the second channel material is conductive to electrons but not to holes, and the mobility of the second channel material is relatively higher than the electron mobility of the first channel material.

[0086] Embodiment 7: The device of any one of embodiments 1 to 6, wherein: the second channel material extends laterally between the sidewalls of the first channel material; the upper surfaces of the first channel material and the second channel material are substantially coplanar with each other; and the conductive plug structure is in direct physical contact with each of the first channel material and the second channel material.

[0087] Embodiment 8: The apparatus of any one of Embodiments 1 to 7, wherein the first channel material comprises a polysilicon material and the second channel material comprises an oxide semiconductor material, the first channel material directly physically contacts the second channel material and substantially surrounds the second channel material along its entire height.

[0088] Embodiment 9: A device comprising: a first channel material extending vertically through a stack of alternating dielectric structures and conductive structures; a second channel material adjacent to the first channel material and extending vertically through the stack, wherein the band gap of the second channel material is relatively larger than the band gap of the first channel material; and a central dielectric material adjacent to the second channel material and extending vertically through the stack.

[0089] Embodiment 10: The apparatus of Embodiment 9, further comprising a conductive plug structure adjacent to each of the first channel material and the second channel material, wherein a maximum lateral extent of the conductive plug structure is substantially equal to a maximum lateral extent of the first channel material.

[0090] Embodiment 11: The apparatus of Embodiment 9 or Embodiment 10, wherein the width of the first channel material is substantially equal to the width of the second channel material, and the width of the central dielectric material is greater than the combined widths of the first channel material and the second channel material.

[0091] Embodiment 12: The apparatus of Embodiment 11, wherein the width of the first channel material is between about 1 nm and about 20 nm, the width of the second channel material is between about 1 nm and about 20 nm, and the width of the central dielectric material is between about 20 nm and about 100 nm.

[0092] Embodiment 13: A device according to any one of embodiments 9 to 12, wherein: the first channel material includes a first dopant, which includes phosphorus or arsenic; and the second channel material includes a second dopant, which includes aluminum or silicon, and the second channel material is substantially completely free of phosphorus and arsenic.

[0093] Embodiment 14: A method of forming a device, comprising: forming an opening through a stack of alternating conductive materials and dielectric materials; forming a first channel material within the opening; forming a second channel material within the opening and adjacent to the first channel material; and forming a plug material within the opening and adjacent to each of the first channel material and the second channel material, the second channel material having a band gap different from the band gap of each of the first channel material and the plug material.

[0094] Embodiment 15: The method of Embodiment 14, wherein forming the first channel material within the opening comprises conformally forming the first channel material on sidewalls of the stack, the opening having a substantially cylindrical shape.

[0095] Embodiment 16: A method according to embodiment 14 or embodiment 15, wherein forming the second channel material comprises: forming the second channel material non-conformally on the sidewalls of the first channel material; and removing portions of the first channel material and the second channel material within the opening so that the first channel material and the second channel material are recessed below the upper surface of the uppermost conductive material of the stack.

[0096] Embodiment 17: The method of any one of Embodiments 14 to 16, further comprising forming a central dielectric material on sidewalls of the second channel material and within the opening.

[0097] Embodiment 18: The method of any one of Embodiments 14 to 17, wherein forming the first channel material and forming the second channel material comprises epitaxially growing at least one of the first channel material and the second channel material within the opening.

[0098] Embodiment 19: The method of any one of Embodiments 14 to 18, wherein forming the second channel material comprises selecting the second channel material to have a band gap greater than a band gap of the first channel material and the plug material.

[0099] Embodiment 20: A memory device comprising: an access line extending in a first lateral direction; a data line extending in a second lateral direction substantially transverse to the first lateral direction; and a memory cell proximate an intersection of the access line and the data line, the memory cell comprising: a first channel material having a first band gap; and a second channel material having a second band gap relatively larger than the first band gap, the second channel material being laterally adjacent to the first channel material.

[0100] Embodiment 21: The memory device of Embodiment 20, further comprising first and second conductive plugs in direct contact with each of the first and second channel materials.

[0101] Embodiment 22: The memory device of Embodiment 20 or Embodiment 21, further comprising a center dielectric material laterally adjacent to the second channel material, wherein the first channel material comprises a polysilicon material, the second channel material comprises an oxide semiconductor material, and the center dielectric material comprises an oxide material.

[0102] Embodiment 23: The memory device of any one of Embodiments 20-22, wherein the first band gap of the first channel material is between approximately 0.4 eV and approximately 1.4 eV, and the second band gap of the second channel material is between approximately 1.5 eV and approximately 4.0 eV.

[0103] Embodiment 24: The memory device of any one of Embodiments 20-23, wherein the memory device comprises a three-dimensional NAND memory device.

[0104] Embodiment 25: An electronic system comprising: a processor; and a microelectronic device operably coupled to the processor, the microelectronic device comprising: vertical structures extending through a stack of alternating conductive materials and dielectric materials, each of the vertical structures comprising: a channel structure comprising a crystalline material laterally adjacent to an amorphous material and substantially surrounding the amorphous material along its height; and a conductive plug structure adjacent to the groove structure, the band gap of the amorphous material of the groove structure being different from the band gap of each of the crystalline materials of the groove structure and the conductive plug structure; a data line adjacent to the vertical structures; and an uppermost conductive gate structure laterally adjacent to the vertical structures, the conductive plug structure at least partially vertically overlapping with the uppermost conductive gate structure.

[0105] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown in the drawings by way of example and have been described in detail herein. However, the present disclosure is not limited to the specific forms disclosed. In fact, the present disclosure covers all modifications, equivalents and alternatives that fall within the scope of the following claims and their legal equivalents.

Claims

1. A device comprising: a stack comprising an alternating sequence of dielectric structures and conductive structures; an oxide-nitride-oxide ONO structure comprising substantially linear sidewalls extending vertically through the stack; a first channel material directly laterally adjacent to the ONO structure and including substantially linear sidewalls extending vertically through the stack, the first channel material having a first band gap; a second channel material adjacent to the first channel material and including a substantially linear sidewall extending vertically through the stack along an entire height of the first channel material, the second channel material having a second band gap relatively larger than the first band gap, the first channel material being laterally interposed between the ONO structure and the second channel material, wherein lower surfaces of the first channel material and the second channel material are vertically elevated relative to a lower surface of the ONO structure; a conductive plug structure adjacent to each of the first channel material and the second channel material; as well as A conductive line structure is adjacent to the conductive plug structure. 2 . The apparatus of claim 1 , wherein the conductive plug structure comprises a conductive material having a third band gap, the second band gap being larger than each of the first band gap and the third band gap.

3. The apparatus of claim 2, wherein the third band gap is substantially equal to the first band gap.

4. The apparatus according to claim 1, wherein: an interface between the second channel material and the first channel material comprises a heterojunction; and Another interface between the conductive plug structure and the first channel material includes a homojunction. 5 . The apparatus of claim 1 , wherein each of the conductive plug structure, the first channel material, and the second channel material comprises an n-type dopant, the second channel material having a greater concentration of the n-type dopant than the conductive plug structure.

6. The apparatus of claim 1, wherein the first channel material is conductive to both electrons and holes, and the second channel material is conductive to electrons and not conductive to holes, the mobility of the second channel material being relatively higher than the electron mobility of the first channel material.

7. The apparatus of claim 1, wherein: The second channel material extends laterally between sidewalls of the first channel material; upper surfaces of the first channel material and the second channel material are substantially coplanar with each other; and The conductive plug structure is in direct physical contact with each of the first channel material and the second channel material.

8. The apparatus of claim 1, wherein the first channel material comprises a polysilicon material and the second channel material comprises an oxide semiconductor material, the first channel material directly physically contacting the second channel material and substantially surrounding the second channel material along the entire height of the first channel material.

9. The apparatus of claim 1, wherein end surfaces of the conductive structures proximate the first channel material are substantially aligned with each other.

10. The apparatus of claim 1, wherein a lower portion of the conductive plug structure is laterally aligned with an upper portion of an uppermost conductive structure of the stack of conductive structures.

11. The device of claim 1, wherein upper surfaces of the first channel material and the second channel material are vertically recessed relative to an upper surface of the ONO structure.

12. The apparatus of claim 1, wherein the conductive plug structure is directly laterally adjacent to the ONO structure, an outer sidewall of each of the first channel material and the conductive plug structure coinciding with an inner sidewall of the ONO structure.

13. An apparatus comprising: an oxide-nitride-oxide ONO structure extending vertically through a stack of alternating dielectric and conductive structures; a first channel material of a channel structure directly laterally adjacent to the ONO structure and extending vertically through the stack; and A second channel material of the channel structure, which is adjacent to the first channel material and extends vertically through the stack, the first channel material being laterally interposed between the ONO structure and the second channel material, wherein a band gap of the second channel material is relatively larger than a band gap of the first channel material, each of the first channel material and the second channel material of the channel structure comprises a substantially vertical sidewall along its height, and lower surfaces of the first channel material and the second channel material are substantially coplanar with each other.

14. The apparatus of claim 13, further comprising a conductive plug structure adjacent to each of the first channel material and the second channel material, wherein an outer sidewall of the conductive plug structure is substantially coplanar with an outer sidewall of the first channel material.

15. The apparatus of claim 13, further comprising a center dielectric material adjacent to the second channel material and extending vertically through the stack, wherein a width of the first channel material is substantially equal to a width of the second channel material, and a width of the center dielectric material is greater than a combined width of the first channel material and the second channel material.

16. The apparatus of claim 15, wherein the width of the first channel material is between 1 nm and 20 nm, the width of the second channel material is between 1 nm and 20 nm, and the width of the center dielectric material is between 20 nm and 100 nm.

17. The apparatus of claim 13, wherein: The first channel material includes a first dopant including phosphorus or arsenic; and The second channel material includes a second dopant including aluminum or silicon, and the second channel material is substantially completely free of phosphorus and arsenic.

18. A method of forming a device, comprising: forming an opening through the stack of alternating conductive and dielectric structures; forming an oxide-nitride-oxide (ONO) structure including substantially linear sidewalls within the opening; forming a first channel material within the opening and directly laterally adjacent to the ONO structure, the first channel material comprising substantially linear sidewalls extending through the stack; forming a second channel material adjacent to the first channel material within the opening, the second channel material comprising a substantially linear sidewall extending vertically through the stack along an entire height of the first channel material, the first channel material being laterally interposed between the ONO structure and the second channel material, a second band gap of the second channel material being relatively larger than a first band gap of the first channel material, and lower surfaces of the first channel material and the second channel material being vertically elevated relative to a lower surface of the ONO structure; as well as forming a conductive plug structure within the opening and adjacent to each of the first channel material and the second channel material; as well as A conductive line structure is formed adjacent to the conductive plug structure.

19. The method of claim 18, wherein forming the first channel material within the opening comprises conformally forming the first channel material on sidewalls of the stack, the opening having a substantially cylindrical shape.

20. The method of claim 18, wherein forming the second channel material comprises: forming the second channel material non-conformally on sidewalls of the first channel material; as well as Portions of the first and second channel materials within the openings are removed such that the first and second channel materials are recessed below an upper surface of an uppermost conductive material of the stack.

21. The method of claim 18, further comprising forming a central dielectric material on sidewalls of the second channel material and within the opening.

22. The method of claim 18, wherein forming the first channel material and forming the second channel material comprises epitaxially growing at least one of the first channel material and the second channel material within the opening.

23. The method of claim 18, wherein forming the second channel material comprises selecting the second channel material to have a bandgap greater than a bandgap of the conductive plug structure.

24. A memory device comprising: an access line extending in a first lateral direction; a data line extending in a second lateral direction substantially transverse to the first lateral direction; as well as A memory cell, which is close to the intersection of the access line and the data line, the memory cell comprising: an oxide-nitride-oxide ONO structure extending vertically through a stack of alternating dielectric and conductive structures; a first channel material directly laterally adjacent to the ONO structure and having a first band gap; and A second channel material having a second band gap relatively larger than the first band gap, the first channel material being laterally interposed between the ONO structure and the second channel material, a lower surface of the second channel material being substantially coplanar with a lower surface of the first channel material.

25. The memory device of claim 24, further comprising first and second conductive plugs in direct contact with each of the first and second channel materials.

26. The memory device of claim 24, further comprising a center dielectric material laterally adjacent to the second channel material, wherein the first channel material comprises a polysilicon material, the second channel material comprises an oxide semiconductor material, and the center dielectric material comprises an oxide material.

27. The memory device of claim 24, wherein the first bandgap of the first channel material is between 0.4 eV and 1.4 eV, and the second bandgap of the second channel material is between 1.5 eV and 4.0 eV.

28. The memory device of claim 24, wherein the memory device comprises a three-dimensional NAND memory device.

29. An electronic system comprising: processor; and a microelectronic device operatively coupled to the processor, the microelectronic device comprising: vertical structures extending through the stack of alternating conductive and dielectric materials, each of said vertical structures comprising: an oxide-nitride-oxide ONO structure extending vertically through the stack; a channel structure comprising a crystalline material laterally interposed between the ONO structure and an amorphous material, the crystalline material substantially surrounding the amorphous material along its height; and a conductive plug structure adjacent to the channel structure, the amorphous material of the channel structure having a band gap relatively larger than a band gap of each of the crystalline materials of the channel structure and the conductive plug structure; a data line adjacent to the vertical structure; and A conductive gate structure includes an uppermost conductive material of the stack of conductive materials laterally adjacent to the vertical structure, the conductive plug structure at least partially vertically overlapping the conductive gate structure.

Images