Metal oxide semiconductor field effect transistor and method for manufacturing the same

Abstract

The present invention discloses a metal oxide semiconductor field effect transistor and a manufacturing method thereof. The metal oxide semiconductor field effect transistor comprises a substrate structure, a plurality of doped regions, a plurality of groove oxide layers, a plurality of semiconductor layer structures, a dielectric layer structure and a metal structure. The substrate structure comprises a base layer and an epitaxial layer. The epitaxial layer has a plurality of grooves. The groove depth of each groove is X1 micrometers. A plurality of doped regions are respectively formed at the bottom of the plurality of grooves. A plurality of groove oxide layers are respectively formed on the inner walls of the plurality of grooves. The oxide layer thickness of each groove oxide layer is X2 micrometers. X1 and X2 meet the following relationship: 0.05X1≤X2≤0.25X1. A plurality of semiconductor layer structures are respectively formed in a plurality of grooves to form a plurality of trench structures. A dielectric layer structure is formed on a plurality of semiconductor layer structures. A metal structure is formed on a dielectric layer structure. Thus, the metal oxide semiconductor field effect transistor can withstand a higher operating voltage without burning.

Description

Technical Field

[0001] The present invention relates to a metal oxide semiconductor field effect transistor, and in particular to a metal oxide semiconductor field effect transistor suitable for use in a power supply and a manufacturing method thereof. Background Art

[0002] With the advancement of electronic technology and the trend of miniaturization of electronic products, more and more electronic components are produced using integrated circuit processes. However, integrated circuit type electronic components need to consider many aspects, such as: high voltage resistance, mutual interference or noise resistance, especially electronic components used in power supplies. Since power supplies need to accept high voltage input, high voltage input will cause integrated circuit type electronic components to burn out, which will lead to power supply failure, which is the main reason why the size of power supplies cannot be reduced.

[0003] Among them, metal oxide semiconductor field effect transistors are also often used in power supplies. Since metal oxide semiconductor field effect transistors have a very fast operating speed and perform very well in voltage signal processing, metal oxide semiconductor field effect transistors are used as converters. In response to the trend of miniaturization of electronic products, metal oxide semiconductor field effect transistors are gradually developing in the direction of integrated circuits. However, when the power supply is subjected to high voltage, the integrated circuit type metal oxide semiconductor field effect transistor will also burn out because it cannot withstand the high voltage.

[0004] Therefore, the inventors of the present invention felt that the above-mentioned deficiencies could be improved, and therefore devoted themselves to research and applied scientific theories, and finally proposed the present invention which has a reasonable design and effectively improves the above-mentioned deficiencies. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a metal oxide semiconductor field effect transistor and a manufacturing method thereof in view of the deficiencies in the prior art.

[0006] In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a metal oxide semiconductor field effect transistor, which includes: a substrate structure, which includes: a substrate layer; and an epitaxial layer, which is formed on the substrate layer, and the epitaxial layer has a plurality of grooves that are recessed from the surface of the epitaxial layer on the side opposite to the substrate layer and arranged at intervals from each other; wherein a groove depth of each of the grooves is X1 microns, and X1 is a real number greater than zero; a plurality of doped regions, which are respectively formed at the bottom of the plurality of grooves and diffused toward a portion of the epitaxial layer; a plurality of groove oxide layers, which are respectively formed on the inner walls of the plurality of grooves, the bottoms of the plurality of groove oxide layers are respectively in contact with the plurality of doped regions, and each of the groove oxide layers is surrounded by a groove; wherein a groove depth of each of the groove oxide layers is X1 microns, and X1 is a real number greater than zero; a plurality of doped regions, which are respectively formed at the bottoms ... a groove is formed in a surrounding manner in each of the groove oxide layers; wherein a groove depth of each of the groove oxide layers is X1 microns, and a groove depth of each of the groove oxide layers is X1 microns, and a groove depth of each of the groove oxide layers is X1 microns, The thickness of the oxide layer is X2 microns, and X2 is a real number greater than zero; wherein, in each of the grooves and the corresponding groove oxide layer, X1 and X2 satisfy the following relationship: 0.05X1≤X2≤0.25X1; a plurality of semiconductor layer structures, which are respectively formed and filled in the plurality of grooves, so as to form a plurality of trench structures together with the plurality of trench oxide layers; a dielectric layer structure, which is formed and covered on the plurality of semiconductor layer structures and is located above the epitaxial layer; and a metal structure, which is formed on the surface of the dielectric layer structure on the side opposite to the base layer, and the metal structure is electrically connected to at least one of the plurality of trench structures; wherein the metal oxide semiconductor field effect transistor is suitable for passing an operating voltage between 50 volts and 800 volts.

[0007] Preferably, in each of the grooves and its corresponding groove oxide layer, the groove depth X1 of the groove is between 4 microns and 7 microns, the oxide layer thickness X2 of the groove oxide layer is between 0.5 microns and 0.9 microns, and X1 and X2 satisfy the following relationship: 0.071X1≤X2≤0.225X1.

[0008] Preferably, the metal oxide semiconductor field effect transistor is suitable for an operating voltage of not less than 75 volts and not more than 275 volts.

[0009] Preferably, in each of the grooves and its corresponding groove oxide layer, the groove depth X1 of the groove is between 7 microns and 16 microns, the oxide layer thickness X2 of the groove oxide layer is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relationship: 0.075X1≤X2≤0.22X1.

[0010] Preferably, the metal oxide semiconductor field effect transistor is suitable for an operating voltage of not less than 275 volts and not more than 800 volts.

[0011] Preferably, the epitaxial layer further includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is formed on the base layer, and the second epitaxial layer is formed on the first epitaxial layer, so that the first epitaxial layer is located between the base layer and the second epitaxial layer; wherein an interface is formed between the first epitaxial layer and the second epitaxial layer, and the interface is roughly located at the bottom of the plurality of grooves and extends to connect between the plurality of doped regions; wherein the plurality of grooves are recessed from a surface of the second epitaxial layer opposite to the first epitaxial layer, and are located in the second epitaxial layer.

[0012] Preferably, the conductive type of the base layer is the same as the conductive type of the first epitaxial layer and the same as the conductive type of the second epitaxial layer; wherein the doping concentration of the base layer is higher than the doping concentration of the first epitaxial layer and the second epitaxial layer, and the doping concentration of the first epitaxial layer is different from the doping concentration of the second epitaxial layer.

[0013] The present invention also discloses a method for manufacturing a metal oxide semiconductor field effect transistor, comprising: providing a substrate structure; wherein the substrate structure includes a substrate layer and an epitaxial layer formed on the substrate layer; forming a plurality of grooves on the epitaxial layer according to a preset groove depth; wherein the plurality of grooves are recessed at intervals on a surface of the epitaxial layer opposite to the substrate layer; wherein the preset groove depth is defined as X1 micrometers, and X1 is a real number greater than zero; forming a plurality of doped regions at the bottoms of the plurality of grooves; wherein the plurality of doped regions are diffused from the bottoms of the plurality of grooves toward a portion of the epitaxial layer; forming a plurality of groove oxide layers on the inner walls of the plurality of grooves according to a preset oxide layer thickness; wherein the plurality of groove oxide layers are respectively in contact with the plurality of doped regions, and each of the groove oxide layers has a thickness of 0. A groove is formed by surrounding the oxide layer; wherein the preset oxide layer thickness is defined as X2 microns, X2 is a real number greater than zero, and X1 and X2 satisfy the following relationship: 0.05X1≤X2≤0.25X1; a plurality of semiconductor layer structures are respectively formed in the plurality of the grooves, so that the plurality of semiconductor layer structures can respectively form a plurality of trench structures together with the plurality of the groove oxide layers; a dielectric layer structure is formed on the plurality of the semiconductor layer structures, so that the plurality of the semiconductor layer structures are covered by the dielectric layer structure, and the dielectric layer structure is located above the epitaxial layer; and a metal structure is formed on a surface of the dielectric layer structure on a side opposite to the base layer to form a metal oxide semiconductor field effect transistor; wherein the metal structure is electrically connected to at least one of the plurality of trench structures.

[0014] Preferably, the value X2 and the value X1 meet one of the following conditions: if the preset groove depth X1 is between 4 microns and 7 microns, the preset oxide layer thickness X2 is between 0.5 microns and 0.9 microns, and X1 and X2 meet the following relationship: 0.071X1≤X2.225X1, so that the metal oxide semiconductor field effect transistor finally formed is suitable for passing an operating voltage of not less than 75 volts and not more than 275 volts; if the preset groove depth X1 is between 7 microns and 16 microns, the preset oxide layer thickness X2 is between 1.2 microns and 1.5 microns, and X1 and X2 meet the following relationship: 0.075X1≤X2≤0.22X1, so that the metal oxide semiconductor field effect transistor finally formed is suitable for passing an operating voltage of not less than 275 volts and not more than 800 volts.

[0015] In summary, the technical solution provided by the present invention disclosed in the embodiment of the present invention can achieve the technical solution of "a groove depth of each of the grooves is X1 microns, and X1 is a real number greater than zero" and "an oxide layer thickness of each of the groove oxide layers is X2 microns, and X2 is a real number greater than zero; wherein, in each of the grooves and its corresponding groove oxide layer, X1 and X2 satisfy the following relationship: 0.05X1≤X2≤0.25X1", so that the finally formed metal oxide semiconductor field effect transistor can withstand a higher operating voltage without burning, thereby improving the reliability of the device.

[0016] Another beneficial effect of the present invention is that the technical solution provided by the present invention can adjust the trench depth of the trench and the oxide layer thickness of the trench oxide layer accordingly so that the final formed metal oxide semiconductor field effect transistor can be suitable for different operating voltage specification requirements.

[0017] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and are not intended to limit the protection scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 4 is a schematic diagram of a metal oxide semiconductor field effect transistor according to an embodiment of the present invention.

[0019] Figure 2A The manufacturing flow chart of metal oxide semiconductor field effect transistor (I) is shown in FIG.

[0020] Figure 2B The manufacturing flow chart of metal oxide semiconductor field effect transistor (II) is shown in FIG.

[0021] Figure 2C The manufacturing flow chart of metal oxide semiconductor field effect transistor (III) is shown.

[0022] Figure 2D Figure 4 is a manufacturing flow chart of a metal oxide semiconductor field effect transistor.

[0023] Figure 2E Figure 5 is a manufacturing flow chart of a metal oxide semiconductor field effect transistor.

[0024] Figure 2F Figure 6 is a manufacturing flow chart of a metal oxide semiconductor field effect transistor.

[0025] Figure 2G Figure 7 is a manufacturing flow chart of a metal oxide semiconductor field effect transistor. DETAILED DESCRIPTION

[0026] The following is an explanation of the disclosed embodiments of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual sizes. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0027] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0028] [Method for manufacturing metal oxide semiconductor field effect transistor]

[0029] See also Figure 1 ,and Figures 2A to 2G As shown, an embodiment of the present invention provides a method for manufacturing a metal oxide semiconductor field effect transistor, which includes steps S110 to S170. In this embodiment, the metal oxide semiconductor field effect transistor is a power component, such as a power supply or a transformer, but the present invention is not limited thereto. It must be noted that the order of each step recorded in this embodiment and the actual operation method can be adjusted according to needs and are not limited to the description of this embodiment.

[0030] The present embodiment first describes the method for manufacturing a metal oxide semiconductor field effect transistor. For ease of understanding, the present embodiment takes a unit region of a metal oxide semiconductor field effect transistor as an example and describes it with a cross-sectional view. Please refer to the drawings corresponding to each step and refer to the drawings of other steps as needed. The specific steps of the method for manufacturing a metal oxide semiconductor field effect transistor are described as follows.

[0031] like Figure 2A As shown, step S110 includes: providing a substrate structure 1. The substrate structure 1 includes: a base layer 11 and an epitaxial layer 12 formed on the base layer 11. The two surfaces of the substrate structure 1 located on opposite sides are respectively defined as a top surface and a bottom surface (both are not numbered in the figure). Among them, the side surface of the epitaxial layer 12 opposite to the base layer 11 is the top surface, and the side surface of the base layer 11 opposite to the epitaxial layer 12 is the bottom surface.

[0032] More specifically, the material of the base layer 11 may be, for example, an N-type doped semiconductor or a P-type doped semiconductor, the epitaxial layer 12 may be, for example, formed on the base layer 11 by an epitaxy process, and the conductivity type of the epitaxial layer 12 may be, for example, the same as the conductivity type of the base layer 11 (e.g., N-type doping or P-type doping). In the present embodiment, the base layer 11 is an N-type doped semiconductor, and the epitaxial layer 12 is also an N-type doped semiconductor, and the doping concentration of the base layer 11 is higher than the doping concentration of the epitaxial layer 12, but the present invention is not limited thereto.

[0033] Please continue reading Figure 2A As shown, in this embodiment, the epitaxial layer 12 further includes a first epitaxial layer 121 and a second epitaxial layer 122. First, the first epitaxial layer 121 is formed on the base layer 11 by an epitaxial process, and then, the second epitaxial layer 122 is formed on the first epitaxial layer 121 by an epitaxial process, so that the first epitaxial layer 121 is located between the base layer 11 and the second epitaxial layer 122, and an interface 123 is formed between the first epitaxial layer 121 and the second epitaxial layer 122.

[0034] The conductivity type of the base layer 11 is the same as that of the first epitaxial layer 121 and the second epitaxial layer 122. That is, the conductivity types of the base layer 11, the first epitaxial layer 121, and the second epitaxial layer 122 are all N-type doped, but the present invention is not limited thereto.

[0035] The doping concentration of the base layer 11 is higher than the doping concentration of the first epitaxial layer 121 , and the doping concentration of the base layer 11 is also higher than the doping concentration of the second epitaxial layer 122 .

[0036] In one embodiment of the present invention, the doping concentration of the base layer 11 is approximately between 10 18 / cm 3 Up to 10 19 / cm 3 The doping concentration of the first epitaxial layer 121 is approximately between 10 14 / cm 3 Up to 10 16 / cm 3 and the doping concentration of the second epitaxial layer 122 is also approximately between 10 14 / cm 3 Up to 10 16 / cm 3Furthermore, the doping concentration of the first epitaxial layer 121 is different from the doping concentration of the second epitaxial layer 122, and the doping concentrations of the first epitaxial layer 121 and the second epitaxial layer 122 are uniform.

[0037] like Figure 2B As shown, step S120 includes: forming a plurality of grooves 13 on the epitaxial layer 12 according to a predetermined groove depth. The plurality of grooves 13 may be formed by etching, for example, but the present invention is not limited thereto.

[0038] Furthermore, the plurality of grooves 13 are recessed at intervals on the surface of the epitaxial layer 12 opposite to the base layer 11. The preset groove depth is defined as X1 micrometers, and X1 is a real number greater than zero. In this embodiment, X1 is a real number not less than 4 and not greater than 16.

[0039] Accordingly, each of the trenches 13 is formed to have a trench depth of X1 micrometers.

[0040] Specifically, the bottoms of the grooves 13 are not in contact with the base layer 11 but are spaced apart from the base layer 11. In other words, the grooves 13 are recessed from the top surface of the substrate structure 1 and are not in contact with the base layer 11 of the substrate structure 1.

[0041] More specifically, an interface 123 is formed between the first epitaxial layer 121 and the second epitaxial layer 122, and the interface 123 is substantially located at (or aligned with) the bottom of the plurality of trenches 13 and is extendedly connected between the plurality of doped regions 2 as described below (eg Figure 2C ). Wherein, the plurality of grooves 13 are recessed from the surface of the side of the second epitaxial layer 122 opposite to the first epitaxial layer 121, and the plurality of grooves 13 are approximately located in the second epitaxial layer 122 and above the first epitaxial layer 121. In addition, the plurality of grooves 13 are not in contact with or only partially overlap the first epitaxial layer 121, but the present invention is not limited thereto. It is worth mentioning that in the present embodiment, although the interface 123 is illustrated by cutting flush with the bottom of the plurality of grooves 13 as an example, the present invention is not limited thereto. For example, the interface 123 may also be, for example, disposed adjacently below the bottom of the plurality of grooves 13 and spaced a short distance from the bottom of the plurality of grooves 13.

[0042] It should be noted that in Figure 2B In the embodiment, the groove depths X1 of the plurality of grooves 13 are described as being the same, but the present invention is not limited thereto. For example, in an embodiment not shown in the present invention, the groove depths X1 of the plurality of grooves 13 may also be different from each other.

[0043] Furthermore, it should be noted that the above-mentioned multiple trenches 13 are described from the perspective of cross-section views for trenches 13 at different locations in the epitaxial layer 12. From a holistic perspective, the trenches 13 may be interconnected or separated, and the present invention is not limited thereto.

[0044] like Figure 2C As shown, step S130 includes: forming a plurality of doped regions 2 at the bottom of the plurality of trenches 13, respectively, and the plurality of doped regions 2 are diffused from the bottom of the plurality of trenches 13 toward a portion of the epitaxial layer 12. The plurality of doped regions 2 can be formed, for example, by an ion implantation process, but the present invention is not limited thereto.

[0045] That is to say, a doping region 2 is formed at the bottom of each of the grooves 13, and each of the doping regions 2 diffuses from the bottom of the corresponding groove 13 toward the portion of the epitaxial layer 12. Accordingly, each of the doping regions 2 is surrounded by the bottom of the corresponding groove 13. Furthermore, in the present embodiment, each of the doping regions 2 only diffuses slightly from the bottom of the corresponding groove 13 toward the portion of the epitaxial layer 12, and presents a half-moon-shaped structure, and each of the doping regions 2 does not contact the base layer 11, but is separated from the base layer 11 by a distance. It is worth mentioning that in the present embodiment, each of the doping regions 2 is partially located in the first epitaxial layer 121, and the other part is located in the second epitaxial layer 122.

[0046] Furthermore, in this embodiment, the conductivity type of the plurality of doped regions 2 is different from the conductivity type of the base layer 11 and the conductivity type of the epitaxial layer 12. That is, the plurality of doped regions 2 in this embodiment are P-type doped semiconductors, and the implanted ion species may be, for example, boron ions (B+).

[0047] In addition, it is worth mentioning that the plurality of doped regions 2 (P-type doped semiconductor) can form a PN junction diode (PN Junction Diode) together with the epitaxial layer 12 (N-type doped semiconductor).

[0048] In one embodiment of the present invention, the doping concentration of the plurality of doping regions 2 is approximately between 10 15 / cm 3 Up to 10 17 / cm 3 between.

[0049] It is worth mentioning that the doping concentration of the first epitaxial layer 121, the second epitaxial layer 122, and the plurality of doping regions 2 should be low (eg, not greater than 10 17 / cm 3) to reduce the conductivity of these components, so that the final formed metal oxide semiconductor field effect transistor 100 can withstand a higher operating voltage. If the doping concentration of the first epitaxial layer 121, the second epitaxial layer 122, and the plurality of doping regions 2 needs to be a high doping concentration (e.g., greater than 10 18 / cm 3 ), the finally formed MOSFET 100 may be burned out due to the excessively high operating voltage.

[0050] like Figure 2D As shown, step S140 includes: extendingly forming an oxide layer structure 3 on a surface of the epitaxial layer 12 opposite to the base layer 11 and on the inner walls of the plurality of trenches 13 according to a predetermined oxide layer thickness. The oxide layer structure 3 can be formed, for example, by a low temperature oxide deposition (LTO deposition) process, but the present invention is not limited thereto.

[0051] More specifically, the oxide layer structure 3 includes a plurality of trench oxide layers 31 and a cap oxide layer 32. The plurality of trench oxide layers 31 are respectively formed on the inner walls of the plurality of trenches 13 and respectively abut against the plurality of doping regions 2, and each of the trench oxide layers 31 surrounds a groove 33. Furthermore, the cap oxide layer 32 is formed on the side surface of the epitaxial layer 12 opposite to the base layer 11 (that is, the top surface of the epitaxial layer 12), and is extendedly connected between the plurality of trench oxide layers 31. In addition, the material of the oxide layer structure 3 may be, for example, a silicon compound or other dielectric material. For example, the silicon compound may be, for example, silicon dioxide or a silicate, and is preferably silicon dioxide, but the present invention is not limited thereto.

[0052] The preset oxide layer thickness is defined as X2 micrometers, and X2 is a real number greater than zero. In this embodiment, X2 is a real number not less than 0.5 and not greater than 1.5, but the present invention is not limited thereto. Accordingly, each of the trench oxide layers 31 is formed with an oxide layer thickness of X2 micrometers.

[0053] Furthermore, the preset trench depth X1 and the preset oxide layer thickness X2 satisfy the following relationship:

[0054] 0.05X1≤X2≤0.25X1.

[0055] According to the above configuration, since the trench depth X1 of each of the trenches 13 is between 4 microns and 16 microns, the oxide layer thickness X2 of each of the trench oxide layers 31 is between 0.5 microns. Up to 1.5 microns Between, and the material of each of the trench oxide layers 31 is silicon dioxide or silicate with high resistance and low conductivity, so the metal oxide semiconductor field effect transistor 100 finally formed in this embodiment is suitable for passing an operating voltage between 50 volts and 800 volts, and preferably between 200 volts and 700 volts.

[0056] It is worth mentioning that the manufacturing method of the metal oxide semiconductor field effect transistor of this embodiment can adjust the numerical range of the preset trench depth X1 according to the predetermined working voltage specification requirements, and adjust the numerical range of the preset oxide layer thickness X2 accordingly according to the numerical range of the preset trench depth X1, so that the finally formed metal oxide semiconductor field effect transistor 100 is suitable for the above-mentioned predetermined working voltage specification requirements, and the finally formed metal oxide semiconductor field effect transistor 100 will not be burned due to the excessively high voltage. Thereby, the reliability of the finally formed metal oxide semiconductor field effect transistor 100 is improved.

[0057] More specifically, in this embodiment, the numerical range of the preset trench depth X1 and the numerical range of the preset oxide layer thickness X2 meet one of the following conditions:

[0058] If the preset trench depth X1 is between 4 μm and 7 μm, the preset oxide layer thickness X2 is between 0.5 μm. To 0.9 micron and X1 and X2 satisfy the following relationship: 0.071X1≤X2≤0.225X1, so that the finally formed metal oxide semiconductor field effect transistor 100 is suitable for passing an operating voltage of not less than 75 volts and not more than 275 volts, and preferably not less than 100 volts and not more than 250 volts.

[0059] Specifically, if the preset trench depth X1 is between 7 μm and 16 μm, the preset oxide layer thickness X2 is between 1.2 μm and 1.6 μm. Up to 1.5 microns and X1 and X2 satisfy the following relationship: 0.075X1≤X2≤0.22X1, so that the finally formed metal oxide semiconductor field effect transistor 100 is suitable for passing an operating voltage of not less than 275 volts and not more than 800 volts, and preferably not less than 300 volts and not more than 700 volts.

[0060] If the numerical range of the preset trench depth X1 and the numerical range of the preset oxide layer thickness X2 do not meet one of the above conditions, the metal oxide semiconductor field effect transistor 100 formed finally will not be suitable for passing the above predetermined working voltage, and may be burned or have poor reliability. For example, if the oxide layer thickness X2 of the trench oxide layer 31 is too thin, the metal oxide semiconductor field effect transistor 100 formed finally will be unable to withstand high voltage due to the reduced resistance value, and may be burned.

[0061] like Figure 2E Please also refer to Figure 1 As shown, step S150 includes: forming a plurality of semiconductor layer structures 4 in the recesses 33 surrounded by the plurality of trench oxide layers 31 , respectively, so that the plurality of semiconductor layer structures 4 and the plurality of trench oxide layers 31 are formed into a plurality of trench structures T together.

[0062] Specifically, the plurality of semiconductor layer structures 4 are respectively filled in the grooves 33 surrounded by the plurality of trench oxide layers 31, and the plurality of semiconductor layer structures 4 can be exposed to the outside through, for example, an etch back step (etch back). Figure 2E The top surface of the semiconductor layer structure 4 in the embodiment of the present invention is lower than the outer surface of the capping oxide layer 32 (that is, Figure 2E The surface of the coating oxide layer 32 opposite to the epitaxial layer 12 is preferably a surface of the coating oxide layer 32 in the second epitaxial layer 122, but the present invention is not limited thereto. Furthermore, the surfaces of the plurality of semiconductor layer structures 4 exposed to the outside are substantially flush with the top surface of the second epitaxial layer 122. In addition, the material of the plurality of semiconductor layer structures 4 may be, for example, doped poly-silicon.

[0063] It is worth mentioning that in one embodiment of the present invention, the plurality of trenches 13 can be defined as deep trenches, and a plurality of shallow trenches (not shown) can be further formed between the plurality of deep trenches 13, and the trench depth of the shallow trenches is less than the trench depth of the deep trenches. The shallow trenches with a shallower depth can be used to form a trench gate structure, and the deep trenches with a deeper depth can be used to form a trench source structure. In addition, the bottom of the substrate structure 1 can be used to connect a drain conductor, but the present invention is not limited thereto.

[0064] like Figure 2FAs shown, step S160 includes: forming and covering a dielectric layer structure 5 (inter layer dielectric, ILD) on the oxide layer structure 3 and the plurality of semiconductor layer structures 4, so that the oxide layer structure 3 and the plurality of semiconductor layer structures 4 are buried in the dielectric layer structure 5. The dielectric layer structure 5 can be formed, for example, by chemical vapor deposition, but the present invention is not limited thereto. For example, the dielectric layer structure 5 can also be formed, for example, by physical vapor deposition or other suitable deposition processes. Furthermore, the material of the dielectric layer structure 5 can be, for example, a silicon compound or other dielectric material.

[0065] Furthermore, the outer surface of the dielectric layer structure 5 may be planarized by, for example, a chemical mechanical polishing (CMP) process, but the present invention is not limited thereto.

[0066] like Figure 2G Please also refer to Figure 1 As shown, step S170 includes: forming a metal structure 6 on a surface of the dielectric layer structure 5 opposite to the base layer 11, and the metal structure 6 partially penetrates the dielectric layer structure 5 to be electrically connected to at least one of the trench structures T among the plurality of trench structures T. The metal structure 6 can be formed, for example, by deposition, and the metal structure 6 is an integrated structure formed of an aluminum-silicon-copper alloy in this embodiment, but is not limited thereto in practical applications.

[0067] Specifically, the metal structure 6 includes a conductive portion 61 and two contact plugs 62 integrally formed with the conductive portion 61. The conductive portion 61 is formed on a surface of the dielectric layer structure 5 opposite to the base layer 11, and the two contact plugs 62 are arranged at intervals from each other, and the two contact plugs 62 respectively penetrate the dielectric layer structure 5, so that the conductive portion 61 can be electrically connected to two adjacent trench structures T among the plurality of trench structures T through the two contact plugs 62. In addition, the width of each contact plug 62 is smaller than the width of the corresponding trench structure T and also smaller than the width of the corresponding trench 13.

[0068] More specifically, the two contact plugs 62 are respectively formed through the dielectric layer structure 5, and the two contact plugs 62 are respectively partially extended into the semiconductor layer structure 4 of the two trench structures T, so that the conductive portion 61 can be respectively electrically connected to the semiconductor layer structure 4 of the two trench structures T through the two contact plugs 62 (such as Figure 1). Thus, the semiconductor layer structures 4 of the two trench structures T are set at the same potential as the two contact plugs 62 electrically connected thereto.

[0069] Furthermore, in this embodiment, the conductive portion 61 only covers a portion of the outer surface of the dielectric layer structure 5 , and another portion of the outer surface of the dielectric layer structure 5 is exposed to the outside.

[0070] It is worth mentioning that before forming the metal structure 6 , the manufacturing method of this embodiment further includes: forming two contact grooves (not numbered in the figure) in the dielectric layer structure 5 by etching, so as to provide the two contact plugs 62 mentioned above to be formed therein respectively.

[0071] After implementing the above-mentioned steps S110 to S170, the following steps can be completed: Figure 1 The metal oxide semiconductor field effect transistor 100 (or trench power device) shown in the figure, but in actual application, each step does not exclude the possibility of replacing with a reasonable variation. Furthermore, it should be emphasized that the above steps are described from the perspective of a cross-sectional view. Under the premise of complying with the above steps, the possibility of implementing the present invention with various design layouts is not excluded. In other words, if viewed from a top view, the metal oxide semiconductor field effect transistor of this embodiment can have different design layout forms.

[0072] Furthermore, it is worth mentioning that the metal structure 6 partially penetrates the dielectric layer structure 5 to directly contact and electrically connect to at least one of the plurality of trench structures T, but the present invention is not limited thereto. For example, the metal structure 6 may not penetrate the dielectric layer structure 5, but may be electrically connected to at least one of the plurality of trench structures T by providing a conductive wire. In this case, the metal structure 6 may not directly contact any trench structure T.

[0073] [Metal Oxide Semiconductor Field Effect Transistor]

[0074] The above is a description of the manufacturing method of the metal oxide semiconductor field effect transistor of the embodiment of the present invention, and the specific structure of the metal oxide semiconductor field effect transistor 100 of the present embodiment is described below. It must be noted that although the metal oxide semiconductor field effect transistor 100 of the present embodiment is manufactured by the above manufacturing method, the present invention is not limited thereto. In other words, the metal oxide semiconductor field effect transistor of the present invention can also be manufactured by other transistor manufacturing methods.

[0075] like Figure 1As shown, this embodiment further discloses a metal oxide semiconductor field effect transistor 100 , which includes a substrate structure 1 , a plurality of doped regions 2 , an oxide layer structure 3 , a plurality of semiconductor layer structures 4 , a dielectric layer structure 5 , and a metal structure 6 .

[0076] The substrate structure 1 includes a base layer 11 and an epitaxial layer 12. The epitaxial layer 12 is formed on the base layer 11, and has a plurality of grooves 13. The plurality of grooves 13 are recessed from the surface of the epitaxial layer 12 opposite to the base layer 11 and are arranged at intervals from each other. A groove depth of each groove 13 is X1 micrometers, and X1 is a real number greater than zero.

[0077] The doped regions 2 are respectively formed at the bottom of the trenches 13 and diffused toward the epitaxial layer 12 .

[0078] The oxide layer structure 3 includes a plurality of groove oxide layers 31 and a cap oxide layer 32. The plurality of groove oxide layers 31 are respectively formed on the inner walls of the plurality of grooves 13 and respectively abut against the plurality of doping regions 2, and each of the groove oxide layers 31 surrounds a groove 33. Furthermore, the cap oxide layer 32 is formed on the surface of the side of the epitaxial layer 12 opposite to the base layer 11 and is extendedly connected between the plurality of groove oxide layers 31. The thickness of an oxide layer of each groove oxide layer 31 is X2 microns, and X2 is a real number greater than zero. In each of the grooves and the corresponding groove oxide layer, X1 and X2 satisfy the following relationship: 0.05X1≤X2≤0.25X1.

[0079] The plurality of semiconductor layer structures 4 are respectively formed in the plurality of grooves 33 , and the plurality of semiconductor layer structures 4 can be respectively formed into a plurality of trench structures T together with the plurality of trench oxide layers 31 .

[0080] The dielectric layer structure 5 is formed and covers the oxide layer structure 3 and the plurality of semiconductor layer structures 4 .

[0081] The metal structure 6 is formed on a surface of the dielectric layer structure 5 opposite to the base layer 11 and partially penetrates the dielectric layer structure 5, so that the metal structure 6 can be electrically connected to at least one of the plurality of trench structures T, but the present invention is not limited thereto. For example, the metal structure 6 may also be, for example, not penetrate the dielectric layer structure 5, but be electrically connected to at least one of the plurality of trench structures T by setting a conductive wire.

[0082] According to the above configuration, the MOSFET 100 of this embodiment is suitable for passing an operating voltage between 50V and 800V, and preferably between 200V and 700V.

[0083] It is worth mentioning that the metal oxide semiconductor field effect transistor 100 of the present embodiment can have different trench depths X1 according to different operating voltage specification requirements, and the oxide layer thickness X2 is adjusted accordingly according to the trench depth X1, so that the metal oxide semiconductor field effect transistor 100 is suitable for the required operating voltage specification requirements and the metal oxide semiconductor field effect transistor 100 will not be burned due to the excessively high voltage.

[0084] In one embodiment of the present invention, the trench depth X1 of the trench 13 is between 4 microns and 6 microns, the oxide layer thickness X2 of the trench oxide layer 31 is between 0.5 microns and 0.6 microns, and X1 and X2 satisfy the following relationship: 0.08X1≤X2≤0.15X1.

[0085] Accordingly, the MOSFET 100 is suitable for an operating voltage of not less than 75 volts and not more than 125 volts.

[0086] In one embodiment of the present invention, the trench depth X1 of the trench 13 is between 5 microns and 7 microns, the oxide layer thickness X2 of the trench oxide layer 31 is between 0.7 microns and 0.9 microns, and X1 and X2 satisfy the following relationship: 0.10X1≤X2≤0.18X1.

[0087] Accordingly, the MOSFET 100 is suitable for an operating voltage of not less than 125V and not more than 275V.

[0088] In one embodiment of the present invention, the trench depth X1 of the trench 13 is between 7 microns and 16 microns, the oxide layer thickness X2 of the trench oxide layer 31 is between 1.2 microns and 1.5 microns, and X1 and X2 satisfy the following relationship: 0.075X1≤X2≤0.22X1.

[0089] Accordingly, the MOSFET 100 is suitable for an operating voltage of not less than 275 volts and not more than 800 volts.

[0090] It is worth mentioning that, as described in the above embodiment, the number of the plurality of grooves 13 is 5, and the number of the plurality of trench structures T corresponds to the number of the plurality of grooves 13 and is also 5, but the present invention is not limited thereto, and the number of the plurality of grooves 13 and the number of trench structures T can be adjusted according to design requirements.

[0091] [Beneficial Effects of Embodiments]

[0092] One of the beneficial effects of the present invention is that the technical solution provided by the present invention can achieve the technical solution of "a groove depth of each of the grooves is X1 microns, and X1 is a real number greater than zero" and "an oxide layer thickness of each of the groove oxide layers is X2 microns, and X2 is a real number greater than zero; wherein, in each of the grooves and its corresponding groove oxide layer, X1 and X2 satisfy the following relationship: 0.05X1≤X2≤0.25X1", so that the finally formed metal oxide semiconductor field effect transistor can withstand a higher operating voltage without burning, thereby improving the reliability of the device.

[0093] Another beneficial effect of the present invention is that the technical solution provided by the present invention can adjust the trench depth of the trench and the oxide layer thickness of the trench oxide layer accordingly so that the final formed metal oxide semiconductor field effect transistor can be suitable for different operating voltage specification requirements.

[0094] In addition, in terms of chip design, since the technical solution provided by the present invention can withstand a higher operating voltage without the need for serial connection of a metal oxide semiconductor field effect transistor, the area occupied by the metal oxide semiconductor field effect transistor of the present invention on the chip can be greatly reduced, and other electronic components can be designed on the chip, making the chip more functional.

[0095] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the scope of the present invention.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: The metal oxide semiconductor field effect transistor comprises: A substrate structure comprising: a basal layer; and an epitaxial layer formed on the base layer, and the epitaxial layer has a plurality of grooves which are recessed from a surface of the epitaxial layer opposite to the base layer and are arranged at intervals from each other; wherein a groove depth of each of the grooves is X1 micrometers, and X1 is a real number greater than zero; a plurality of doped regions, which are respectively formed at the bottom of the plurality of trenches and diffused toward a portion of the epitaxial layer; A plurality of groove oxide layers, which are respectively formed on the inner walls of the plurality of grooves, the bottoms of the plurality of groove oxide layers are respectively in contact with the plurality of doped regions, and each of the groove oxide layers is surrounded by a groove; wherein an oxide layer thickness of each of the groove oxide layers is X2 microns, and X2 is a real number greater than zero; wherein, in each of the grooves and the corresponding groove oxide layer, the groove depth X1 of the groove is between 7 microns and 16 microns, the oxide layer thickness X2 of the groove oxide layer is between 1.2 microns and 1.5 microns, and X1 and X2 meet the following relationship: 0.075X1≤X2≤0.22X1; A plurality of semiconductor layer structures are respectively formed and filled in the plurality of grooves to form a plurality of trench structures together with the plurality of trench oxide layers; a dielectric layer structure formed on and covering the plurality of semiconductor layer structures and located above the epitaxial layer; and a metal structure formed on a surface of the dielectric layer structure opposite to the base layer, and the metal structure is electrically connected to at least one of the plurality of trench structures; The metal oxide semiconductor field effect transistor is suitable for receiving an operating voltage of not less than 275 volts and not more than 800 volts.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The metal oxide semiconductor field effect transistor is suitable for receiving an operating voltage of not less than 300 volts and not more than 700 volts.

3. The metal oxide semiconductor field effect transistor according to claim 1 or 2, characterized in that: The epitaxial layer further includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is formed on the base layer, and the second epitaxial layer is formed on the first epitaxial layer, so that the first epitaxial layer is located between the base layer and the second epitaxial layer; wherein an interface is formed between the first epitaxial layer and the second epitaxial layer, and the interface is roughly located at the bottom of the plurality of the grooves and extends to connect between the plurality of the doped regions; wherein the plurality of the grooves are recessed from a surface of the second epitaxial layer opposite to the first epitaxial layer, and are located in the second epitaxial layer.

4. The metal oxide semiconductor field effect transistor according to claim 3, characterized in that: The conductive type of the base layer is the same as the conductive type of the first epitaxial layer and the conductive type of the second epitaxial layer; wherein the doping concentration of the base layer is higher than the doping concentration of the first epitaxial layer and the doping concentration of the second epitaxial layer, and the doping concentration of the first epitaxial layer is different from the doping concentration of the second epitaxial layer.

5. A method for manufacturing a metal oxide semiconductor field effect transistor, characterized in that: The method for manufacturing the metal oxide semiconductor field effect transistor comprises: A substrate structure is provided; wherein the substrate structure comprises a base layer and an epitaxial layer formed on the base layer; A plurality of grooves are formed on the epitaxial layer according to a preset groove depth; wherein the plurality of grooves are recessed at intervals on a surface of the epitaxial layer opposite to the base layer; wherein the preset groove depth is defined as X1 micrometers, and X1 is a real number greater than zero; Forming a plurality of doped regions at the bottom of the plurality of trenches respectively; wherein the plurality of doped regions are diffused from the bottom of the plurality of trenches toward a portion of the epitaxial layer; A plurality of trench oxide layers are respectively formed on the inner walls of the plurality of trenches according to a preset oxide layer thickness; wherein the plurality of trench oxide layers are respectively in contact with the plurality of doped regions, and each of the trench oxide layers surrounds a groove; wherein the preset oxide layer thickness is defined as X2 microns, X2 is a real number greater than zero, wherein the preset trench depth X1 is between 7 microns and 16 microns, the preset oxide layer thickness X2 is between 1.2 microns and 1.5 microns, and X1 and X2 meet the following relationship: 0.075X1≤X2≤0.22X1; Forming a plurality of semiconductor layer structures in the plurality of grooves respectively, so that the plurality of semiconductor layer structures can form a plurality of trench structures together with the plurality of trench oxide layers respectively; forming a dielectric layer structure on the plurality of semiconductor layer structures, so that the plurality of semiconductor layer structures are covered by the dielectric layer structure, and the dielectric layer structure is located above the epitaxial layer; and A metal structure is formed on a surface of the dielectric layer structure opposite to the base layer to form a metal oxide semiconductor field effect transistor; wherein the metal structure is electrically connected to at least one of the plurality of trench structures; wherein the metal oxide semiconductor field effect transistor is suitable for passing an operating voltage of not less than 275 volts and not more than 800 volts.

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