Semiconductor device structure and method for forming the same

Abstract

The present disclosure provides a semiconductor device structure and a method for forming the same. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure above the substrate. The semiconductor device structure includes a gate stack above the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source / drain structure and a second source / drain structure above the substrate. The gate stack is between the first source / drain structure and the second source / drain structure. The semiconductor device structure includes an inner spacer layer, which covers the sidewalls of the first source / drain structure and is partially located between the gate stack and the first source / drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure above the gate stack and extending into the inner spacer layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor manufacturing technology, and more particularly to a semiconductor device structure with a nanostructure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits. Each generation has smaller and more complex circuits than the previous generation. However, such advances have increased the complexity of processing and manufacturing integrated circuits.

[0003] In the history of integrated circuit evolution, as the geometry size (i.e., the smallest component (or line) that can be produced using a production process) decreases, the functional density (i.e., the number of interconnected devices per unit chip area) generally increases. This scaling process generally provides some benefits by increasing production efficiency and reducing related costs.

[0004] However, as feature sizes continue to decrease, production processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at increasingly smaller sizes. Summary of the invention

[0005] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate; a first nanostructure above the substrate; a gate stack above the substrate and surrounding the first nanostructure; a first source / drain structure and a second source / drain structure above the substrate, wherein the gate stack is between the first source / drain structure and the second source / drain structure; an inner spacer layer covering the sidewalls of the first source / drain structure and partially located between the gate stack and the first source / drain structure, wherein the first nanostructure passes through the inner spacer layer; and a dielectric structure above the gate stack and extending into the inner spacer layer.

[0006] According to some other embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin above the base; a nanostructure above the fin; a gate stack covering and surrounding the fin and the nanostructure; a first source / drain structure and a second source / drain structure above the fin, wherein the gate stack is between the first source / drain structure and the second source / drain structure; an inner spacer covering the sidewall of the first source / drain structure and partially located between the gate stack and the first source / drain structure, wherein the inner spacer surrounds the nanostructure between the gate stack and the first source / drain structure; and a dielectric structure above the gate stack, wherein the dielectric structure has an extension extending toward the first source / drain structure, and the inner spacer surrounds the extension.

[0007] According to yet other embodiments, a method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, an inner spacer, a first source / drain structure, a second source / drain structure, a dielectric layer, and a gate stack, wherein the first nanostructure is between the second nanostructure and the substrate, the gate stack surrounds the first nanostructure and the second nanostructure, the gate stack is between the first source / drain structure and the second source / drain structure, the inner spacer is between the gate stack and the first source / drain structure, and the dielectric layer is above the first source / drain structure and the second source / drain structure; removing a first portion of the gate stack above the second nanostructure to form a trench in the dielectric layer; removing a second portion of the second nanostructure below the trench; removing a third portion of the second nanostructure above the inner spacer through the trench; and forming a dielectric structure in the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Through the following detailed description in conjunction with the attached drawings, the content of the embodiments of the present invention can be better understood. It should be emphasized that, according to the standard practice in the industry, many components are not drawn to scale. In fact, in order to clearly discuss, the size of various components may be arbitrarily increased or reduced.

[0009] Figure 1A to Figure 1N are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0010] Figure 1A-1 According to some embodiments Figure 1A A perspective view of a semiconductor device structure.

[0011] Figure 1N-1 According to some embodiments Figure 1N A perspective view of a semiconductor device structure.

[0012] Figure 2 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0013] Figure 3 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0014] Figure 4 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0015] Figure 5 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0016] Figure 6 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0017] Fig. 7Ais a top view of a semiconductor device structure according to some embodiments.

[0018] Figure 7B According to some embodiments, Fig. 7A The section line 7B-7B' in FIG. 7 shows a schematic cross-sectional view of the semiconductor device structure.

[0019] Figure 7C According to some embodiments, Fig. 7A The section line 7C-7C' in FIG. 7 shows a schematic cross-sectional view of the semiconductor device structure.

[0020] Fig.7D According to some embodiments, Fig. 7A The section line 7D-7D' in FIG. 7 shows a schematic cross-sectional view of the semiconductor device structure.

[0021] Figure 8 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0022] Fig. 9 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0023] Figure 10A to Figure 10G is a perspective view of various stages of a process for forming a semiconductor device structure in accordance with some embodiments.

[0024] Figure 10G-1 According to some embodiments Figure 10G A perspective view of a semiconductor device structure.

[0025] The reference numerals are as follows:

[0026] 1A,1A',1N,1N',7B,7B',7C,7C',7D,7D',10G,10G': hatching

[0027] 100, 200, 300, 400, 500, 600, 700, 800, 900: semiconductor device structure

[0028] 110: Base

[0029] 111,126d,166,181,194,211,212a,214a,216a,218,222,251,916,922,932: Top surface

[0030] 112: Base

[0031] 114: Fins

[0032] 120: Nanostructure stacking

[0033] 120a,126a,128a,164,174,TR1,TR2: Groove

[0034] 121,122,123,124,125,126,127,128: Nanostructures

[0035] 121a,122a,123a,124a,125a,126a',126s,127a,128a',128s,142a,144a,152,162,172: side wall

[0036] 126b,126c,128b,128c,701,702,703:Partial

[0037] 130: Isolation layer

[0038] 140,210: Gate stack

[0039] 142,212: Gate dielectric layer

[0040] 144: Gate electrode

[0041] 150,240: Mask layer

[0042] 160: Interval structure

[0043] 170: Inner spacer

[0044] 176: Upper surface

[0045] 180: Source / drain structure

[0046] 190,250a,910: Dielectric layer

[0047] 192,256,912,914:Through hole

[0048] 214: Work function metal layer

[0049] 216: Gate electrode layer

[0050] 220,810,920,930: Contact structure

[0051] 230: Anti-reflection layer

[0052] 242: Opening

[0053] 250: Dielectric structure

[0054] 252,254: Extension

[0055] 252a,254a: gap

[0056] D1,D2: distance

[0057] W1,W2,W3,W4,W5: Width DETAILED DESCRIPTION

[0058] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed on or above a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present invention may reuse reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0059] In addition, spatially relative terms may be used herein, such as "under", "beneath", "below", "above", "above" and similar terms, which are used to facilitate the description of the relationship between one (or some) element or component and another (or some) element or component as shown in the figure. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used herein will also be interpreted according to the orientation after the rotation.

[0060] Those skilled in the art will understand the terms "substantially" or "approximately" in the specification, such as "substantially flat" or "substantially coplanar", etc. In some embodiments, the adjective substantially can be removed. Where applicable, the term "substantially" can also include embodiments with "entirely", "completely", "all", etc. The combination of the term "approximately" and a specific distance or size should be interpreted as not excluding deviations from the specified distance or size. The term "substantially" or "approximately" can vary in different technologies and is within the range of deviations understood by those skilled in the art. For example, the term "substantially" or "approximately" can also be about a specified 90% or higher, such as a specified 95% or higher, in particular a specified 99% or higher, including a specified 100%, but the present invention is not limited thereto. In addition, terms such as "substantially parallel" or "substantially perpendicular" can be interpreted as not excluding minor deviations from the specified arrangement, and can include, for example, deviations of up to 10°. The word "substantially" does not exclude "completely", for example, a composition that is "substantially free of" Y can be completely free of Y.

[0061] Some embodiments of the present invention are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in other logical orders.

[0062] The gate all around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines optical lithography and a self-aligned process, allowing the pitch of the pattern to be produced to be smaller than the pitch of the pattern obtained using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and the sacrificial layer is patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the gate all around structure.

[0063] Figure 1A to Figure 1N is a schematic cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1A-1 According to some embodiments Figure 1A A perspective view of a semiconductor device structure. Figure 1A According to some embodiments, Figure 1A-1 The cross-sectional line 1A-1A' in FIG. 1 shows a schematic cross-sectional view of the semiconductor device structure.

[0064] According to some embodiments, Figure 1A and Figure 1A-1 As shown, a substrate 110 is provided. According to some embodiments, the substrate 110 has a base 112 and a fin 114 above the base 112. The substrate 110 includes, for example, a semiconductor substrate. For example, the substrate 110 includes a semiconductor wafer (eg, a silicon wafer) or a portion of a semiconductor wafer.

[0065] In some embodiments, the substrate 110 is made of an elemental semiconductor material, including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure. In some other embodiments, the substrate 110 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof. The substrate 110 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0066] According to some embodiments, Figure 1A and Figure 1A-1 As shown, a nanostructure stack 120 is formed above the fin 114. According to some embodiments, the nanostructure stack 120 includes nanostructures 121, 122, 123, 124, 125, 126, 127, and 128.

[0067] According to some embodiments, nanostructures 121, 122, 123, 124, 125, 126, 127, and 128 are sequentially stacked on fin 114. According to some embodiments, nanostructures 121, 122, 123, 124, 125, 126, 127, and 128 include nanowires or nanosheets.

[0068] According to some embodiments, nanostructures 121, 123, 125 and 127 are made of the same first material. According to some embodiments, the first material is different from the material of substrate 110. According to some embodiments, the first material comprises an elemental semiconductor material, which comprises silicon or germanium in a single crystal structure, a polycrystalline structure or an amorphous structure.

[0069] According to some embodiments, the first material includes a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof.

[0070] According to some embodiments, nanostructures 122, 124, 126, and 128 are made of the same second material. According to some embodiments, the second material is different from the first material. According to some embodiments, the second material is the same as the material of substrate 110. According to some embodiments, the second material comprises an elemental semiconductor material, which comprises silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0071] According to some embodiments, the second material includes a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof.

[0072] According to some embodiments, Figure 1A-1 and Figure 1A As shown, an isolation layer 130 is formed over the base 112. According to some embodiments, the fin 114 is partially embedded in the isolation layer 130. According to some embodiments, the isolation layer 130 surrounds the fin 114.

[0073] According to some embodiments, the isolation layer 130 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide), a nitrogen-containing material (e.g., silicon oxynitride), a low-k material, a porous dielectric material, glass, or a combination thereof. According to some embodiments, the glass includes borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof.

[0074] According to some embodiments, the isolation layer 130 is formed by a deposition process (or a spin coating process), a chemical mechanical polishing process, and an etching back process. According to some embodiments, the deposition process includes a chemical vapor deposition (CVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a flowable chemical vapor deposition (FCVD) process, a sputtering process, or a combination thereof.

[0075] According to some embodiments, Figure 1A and Figure 1A-1 As shown, a gate stack 140 and a mask layer 150 are formed over the nanostructure stack 120, the fin 114, and the isolation layer 130. According to some embodiments, the gate stack 140 includes a gate dielectric layer 142 and a gate electrode 144. According to some embodiments, the gate electrode 144 is over the gate dielectric layer 142.

[0076] According to some embodiments, gate dielectric layer 142 is located between gate electrode 144 and nanostructure stack 120. According to some embodiments, gate dielectric layer 142 is also located between gate electrode 144 and fin 114. According to some embodiments, gate dielectric layer 142 is located between gate electrode 144 and isolation layer 130.

[0077] According to some embodiments, the gate dielectric layer 142 is made of an oxide-containing material, such as silicon oxide. According to some embodiments, the gate dielectric layer 142 is formed using a chemical vapor deposition process and an etching process. According to some embodiments, the gate electrode 144 is made of a semiconductor material, such as polysilicon. According to some embodiments, the gate electrode 144 is formed using a chemical vapor deposition process and an etching process.

[0078] According to some embodiments, mask layer 150 is located above gate stack 140. According to some embodiments, mask layer 150 is made of a different material than gate stack 140. According to some embodiments, mask layer 150 is made of nitride (eg, silicon nitride) or oxynitride (eg, silicon oxynitride).

[0079] According to some embodiments, Figure 1A and Figure 1A-1 As shown, a spacer structure 160 is formed over the gate dielectric layer 142, the gate electrode 144, and the sidewalls 142a, 144a, and 152 of the mask layer 150. According to some embodiments, the spacer structure 160 surrounds the gate stack 140 and the mask layer 150. According to some embodiments, the spacer structure 160 is located over the nanostructure stack 120, the fin structure 114, and the isolation layer 130.

[0080] According to some embodiments, the spacer structure 160 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. According to some embodiments, the spacer structure 160 is made of a material different from that of the gate stack 140 and the mask layer 150. According to some embodiments, the formation of the spacer structure 160 includes a deposition process and an anisotropic etching process.

[0081] According to some embodiments, Figure 1B As shown, ends of nanostructures 121, 123, 125, and 127 that are not covered by gate stack 140 and spacer structure 160 are removed. The removal process forms trenches 120a in nanostructure stack 120 according to some embodiments.

[0082] According to some embodiments, Figure 1B As shown, the sidewalls 121a, 123a, 125a and 127a of the nanostructures 121, 123, 125 and 127 are substantially aligned (or substantially coplanar) with the sidewall 162 of the spacer structure 160. According to some embodiments, the removal process includes an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0083] According to some embodiments, Figure 1CAs shown, a portion of the nanostructures 121, 123, 125, and 127 is removed through the trench 120a. According to some embodiments, the removal process includes an etching process, such as a dry etching process or a wet etching process.

[0084] According to some embodiments, Figure 1C As shown, an inner spacer layer 170 is formed over the sidewalls 121a, 123a, 125a, and 127a of the nanostructures 121, 123, 125, and 127. According to some embodiments, the inner spacer layer 170 directly contacts the sidewalls 121a, 123a, 125a, and 127a. According to some embodiments, as Figure 1C As shown, the sidewalls 172 of the inner spacer layer 170 are substantially aligned (or substantially coplanar) with the sidewalls 162 of the isolation structure 160 .

[0085] According to some embodiments, the inner spacer layer 170 is made of an insulating material, such as an oxide-containing material (e.g., silicon oxide), a nitride-containing material (e.g., silicon nitride), a nitrogen oxide-containing material (e.g., silicon oxynitride), a carbide-containing material (e.g., silicon carbide), a high dielectric constant material (e.g., HfO2, ZrO2, HfZrO2, or Al2O3), or a low dielectric constant material.

[0086] According to some embodiments, the term "high dielectric constant material" refers to a material having a dielectric constant greater than that of silicon dioxide. According to some embodiments, the term "low dielectric constant material" refers to a material having a dielectric constant less than that of silicon dioxide.

[0087] In some embodiments, the inner spacer layer 170 is formed using a deposition process and an etching process. According to some embodiments, the deposition process includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a similar process.

[0088] In some other embodiments, the inner spacer layer 170 is formed using a selective deposition process, such as an atomic layer deposition process. In some other embodiments, instead of removing a portion of the nanostructures 121, 123, 125, and 127 through the trench 120a, the inner spacer layer 170 is formed by directly oxidizing a portion of the nanostructures 121, 123, 125, and 127 through the trench 120a.

[0089] According to some embodiments, Figure 1D As shown, a source / drain structure 180, such as a stressor structure, is formed in the trench 120a. According to some embodiments, the source / drain structure 180 surrounds the nanostructures 122, 124, 126, and 128. According to some embodiments, the source / drain structure 180 directly contacts the nanostructures 122, 124, 126, and 128, the spacer structure 160, the inner spacer layer 170, and the substrate 110.

[0090] In some embodiments, the source / drain structure 180 is made of a semiconductor material (eg, silicon germanium). In some embodiments, the source / drain structure 180 is doped with a P-type dopant. According to some embodiments, the P-type dopant includes a group IIIA element. The group IIIA element includes boron or other suitable materials.

[0091] In some other embodiments, the source / drain structure 180 is made of a semiconductor material, such as silicon or silicon carbide. According to some embodiments, the source / drain structure 180 is doped with an N-type dopant, such as a group VA element. The group VA element includes phosphorus (P), antimony (Sb), or other suitable group VA materials. According to some embodiments, the source / drain structure 180 is formed using an epitaxial process.

[0092] According to some embodiments, Figure 1D As shown, a dielectric layer 190 is formed over the source / drain structure 180. According to some embodiments, the dielectric layer 190 includes a dielectric material, such as an oxide-containing material (e.g., silicon oxide), a nitride-containing material (e.g., silicon oxynitride), a low dielectric constant material, a porous dielectric material, glass, or a combination thereof.

[0093] According to some embodiments, the glass includes borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or a combination thereof. According to some embodiments, the dielectric layer 190 is formed by a deposition process (e.g., a chemical vapor deposition process) and a planarization process (e.g., a chemical mechanical polishing process).

[0094] According to some embodiments, Figure 1D and Figure 1E As shown, the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms a trench 164 in the spacer structure 160. According to some embodiments, as Figure 1D and Figure 1E As shown, nanostructures 121, 123, 125, and 127 are removed via trench 164. According to some embodiments, the removal process for removing gate stack 140, mask layer 150, and nanostructures 121, 123, 125, and 127 includes an etching process, such as a wet etching process or a dry etching process.

[0095] According to some embodiments, Figure 1EAs shown, a gate stack 210 is formed in the trench 164. According to some embodiments, the gate stack 210 surrounds the nanostructures 122, 124, 126, and 128. According to some embodiments, the nanostructures 122, 124, 126, and 128 pass through the gate stack 210, the inner spacer layer 170, and the source / drain structure 180. According to some embodiments, the gate stack 210 includes a gate dielectric layer 212, a work function metal layer 214, and a gate electrode layer 216.

[0096] According to some embodiments, the gate dielectric layer 212 conformally covers the inner wall and bottom surface of the nanostructures 122, 124, 126 and 128 and the trench 164. According to some embodiments, the gate dielectric layer 212 is made of a high dielectric constant material, such as HfO2, La2O3, CaO, ZrO2, HfZrO2 or Al2O3. The gate dielectric layer 212 is formed using an atomic layer deposition process or other suitable processes.

[0097] According to some embodiments, a work function metal layer 214 is conformally formed on the gate dielectric layer 212. The work function metal layer 214 is made of a titanium-containing material (e.g., TiN or TiSiN), a tantalum-containing material (e.g., TaN), or other suitable conductive materials. The work function metal layer 214 is formed using an atomic layer deposition process or other suitable processes.

[0098] According to some embodiments, a gate electrode layer 216 is formed over the work function metal layer 214. The gate electrode layer 216 is made of metal (e.g., W, Al, Ta, Ti, or Au), metal nitride (TiN or TaN), or other suitable conductive materials. The gate electrode layer 216 is formed using an atomic layer deposition process or other suitable processes.

[0099] According to some embodiments, Figure 1F As shown, a portion of the dielectric layer 190 is removed to form a via 192 in the dielectric layer 190. According to some embodiments, the via 192 exposes the source / drain structure 180 thereunder. According to some embodiments, the removal process includes an etching process, such as an anisotropic etching process (eg, a dry etching process).

[0100] According to some embodiments, Figure 1F As shown, a contact structure 220 is formed in the through hole 192. According to some embodiments, the contact structure 220 is electrically connected to the source / drain structure 180 thereunder. According to some embodiments, the contact structure 220 directly contacts the source / drain structure 180 thereunder. According to some embodiments, as Figure 1F As shown, the contact structure 220 , the dielectric layer 190 , the spacer structure 160 , and the top surfaces 222 , 194 , 166 , and 218 of the gate stack 210 are substantially coplanar.

[0101] According to some embodiments, the contact structure 220 is made of metal (e.g., tungsten, aluminum, copper, or cobalt), alloys thereof, or similar materials. According to some embodiments, the contact structure 220 is formed using a deposition process (e.g., a physical vapor deposition process or a chemical vapor deposition process) and a planarization process (e.g., a chemical mechanical polishing process).

[0102] According to some embodiments, Figure 1G As shown, an anti-reflection layer 230 is formed over the contact structure 220, the dielectric layer 190, the spacer structure 160, and the gate stack 210. The anti-reflection layer 230 is made of metal (e.g., Cr), semiconductor, nitride (e.g., CrN, SiN, TiN, or TiSiN), oxide (CrON or Cr2O3), carbide (e.g., SiC), oxynitride (e.g., SiON), oxycarbide (e.g., SiOC), or a combination thereof. The anti-reflection layer 230 is formed using a deposition process or other suitable process.

[0103] According to some embodiments, Figure 1G As shown, a mask layer 240 is formed over the anti-reflection layer 230. According to some embodiments, the mask layer 240 has an opening 242. According to some embodiments, the opening 242 exposes a portion of the anti-reflection layer 230 over the gate stack 210. According to some embodiments, the mask layer 240 is made of a polymer material, such as a photoresist material. According to some embodiments, the formation of the mask layer 240 uses a spin coating process and an optical lithography process.

[0104] According to some embodiments, Figure 1G As shown, after forming the mask layer 240, the mask layer 240 and the anti-reflection layer 230 are subjected to a descum process to remove residues generated by forming the mask layer 240. According to some embodiments, the removal process includes an etching process, such as a plasma etching process. According to some embodiments, the process gas of the plasma etching process includes nitrogen (N2) and oxygen (O2). According to some embodiments, the process pressure is in the range of about 3 mTorr to about 30 mTorr.

[0105] Thereafter, according to some embodiments, as Figure 1H As shown, the anti-reflective layer 230 exposed by the opening 242 is removed. According to some embodiments, the removal process includes an etching process, such as a plasma etching process. According to some embodiments, the process gas of the plasma etching process includes chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr) and helium (He). According to some embodiments, the process pressure is in the range of about 3mTorr to about 30mTorr.

[0106] Thereafter, according to some embodiments, as Figure 1H As shown, a portion of the gate stack 210 above the nanostructure 128 and in the trench 164 is removed. According to some embodiments, the removal process includes an etching process, such as a plasma etching process. According to some embodiments, the process gas of the plasma etching process includes chlorine (Cl2) and boron trichloride (BCl3). According to some embodiments, the process pressure is in the range of about 5 mTorr to about 50 mTorr.

[0107] Thereafter, according to some embodiments, as Figure 1H As shown, a cleaning process is performed on the mask layer 240 , the anti-reflection layer 230 , the spacer structure 160 , and the nanostructure 128 to remove residues generated by the aforementioned processes.

[0108] According to some embodiments, the cleaning process includes an etching process, such as a plasma etching process. According to some embodiments, the process gas of the plasma etching process includes diazene (N2H2), nitrogen (N2) and hydrogen (H2). According to some embodiments, the process pressure is in the range of about 20mTorr to about 100mTorr.

[0109] According to some embodiments, the plasma is carried out in the same plasma chamber (not shown). Figure 1G The slag removal process Figure 1H The removal process and the cleaning process are performed on the anti-reflection layer 230 and the portion of the gate stack 210 above the nanostructure 128 exposed by the opening 242. That is, according to some embodiments, the removal process and the cleaning process are performed in-situ.

[0110] According to some embodiments, the plasma chamber has an electrostatic chuck (ESC) and a chamber wall. According to some embodiments, the chamber wall surrounds the electrostatic chuck. According to some embodiments, the electrostatic chuck is used to support a wafer (e.g., substrate 110). According to some embodiments, the temperature (or processing temperature) of the plasma chamber is in the range of about 60° C. to about 120° C.

[0111] Thereafter, according to some embodiments, as Fig. 1I As shown, nanostructure 128 below trench 164 of spacer structure 160 is removed via trench 164 to form trench 128a in nanostructure 128. According to some embodiments, nanostructure 128 is divided into portions 128b and 128c by trench 128a. According to some embodiments, portions 128b and 128c are spaced apart from each other.

[0112] According to some embodiments, the removal process includes an etching process, such as an anisotropic etching process (e.g., a plasma etching process). According to some embodiments, the process gas of the plasma etching process includes hydrogen bromide (HBr), oxygen (O2), and chlorine (Cl2). According to some embodiments, the process pressure is in the range of about 3 mTorr to about 20 mTorr.

[0113] Thereafter, according to some embodiments, as Fig. 1I As shown, an over-etching process is performed on the nanostructure 128 to remove residues generated by the removal process of the nanostructure 128 below the trench 164. According to some embodiments, the over-etching process includes a plasma etching process.

[0114] According to some embodiments, the process gas of the plasma etching process includes nitrogen trifluoride (NF3) and chlorine (Cl2). According to some embodiments, the process pressure is in the range of about 20 mTorr to about 60 mTorr. According to some embodiments, the process temperature of the removal process and the over-etching process of the nanostructure 128 below the trench 164 is in the range of about 50° C. to about 70° C.

[0115] Thereafter, according to some embodiments, as Figure 1J As shown, a portion of the gate stack 210 above the nanostructure 126 and in the trench 174 of the inner spacer layer 170 is removed. According to some embodiments, the removal process includes an etching process, such as a plasma etching process. According to some embodiments, the process gas of the plasma etching process includes chlorine (Cl2) and boron trichloride (BCl3). According to some embodiments, the process pressure is in the range of about 5 mTorr to about 50 mTorr.

[0116] Thereafter, according to some embodiments, as Figure 1J As shown, a cleaning process is performed on the mask layer 240, the anti-reflection layer 230, the spacer structure 160, the inner spacer layer 170, and the nanostructures 126 and 128 to remove residues generated by the aforementioned processes. According to some embodiments, the cleaning process includes an etching process, such as a plasma etching process.

[0117] According to some embodiments, the process gas of the plasma etching process includes diimide (N2H2), nitrogen (N2) and hydrogen (H2). According to some embodiments, the process pressure ranges from about 20 mTorr to about 100 mTorr. According to some embodiments, the process temperature and pressure of the removal process of the portion of the gate stack 210 above the nanostructure 126 are Figure 1J The temperature of the cleaning process is in the range of about 60°C to about 120°C.

[0118] Thereafter, according to some embodiments, as Figure 1KAs shown, the nanostructure 126 below the groove 164 of the spacer structure 160 is removed via the groove 164 to form a groove 126a in the nanostructure 126. According to some embodiments, the nanostructure 126 is divided into parts 126b and 126c by the groove 126a. According to some embodiments, the parts 126b and 126c are spaced apart from each other.

[0119] According to some embodiments, the removal process includes an etching process, such as an anisotropic etching process (e.g., a plasma etching process). According to some embodiments, the process gas of the plasma etching process includes hydrogen bromide (HBr), oxygen (O2), and chlorine (Cl2). According to some embodiments, the process pressure is in the range of about 3 mTorr to about 20 mTorr.

[0120] Thereafter, according to some embodiments, as Figure 1K As shown, an over-etching process is performed on the nanostructure 126 to remove residues generated by the removal process of the nanostructure 126 under the trench 164. According to some embodiments, the over-etching process includes a plasma etching process.

[0121] According to some embodiments, the process gas of the plasma etching process includes nitrogen trifluoride (NF3) and chlorine (Cl2). According to some embodiments, the process pressure is in the range of about 20 mTorr to about 60 mTorr. According to some embodiments, the process temperature of the removal process and the over-etching process of the nanostructure 126 under the trench 164 is in the range of about 50° C. to about 70° C.

[0122] According to some embodiments, in some embodiments, the plasma chamber (not shown) is used to carry out Figure 1G The slag removal process Figure 1H a process for removing and cleaning the anti-reflective layer 230 and a portion of the gate stack 210 above the nanostructure 128 exposed by the opening 242, Fig. 1I The removal process and over-etching process of the nanostructure 128 below the trench 164, Figure 1J a process for removing and cleaning a portion of the gate stack 210 above the nanostructure 126, Figure 1K The removal process and the over-etching process of the nanostructure 126 below the trench 164. That is, according to some embodiments, the aforementioned descum process, the aforementioned removal process, the aforementioned cleaning process, and the aforementioned over-etching process are performed in situ.

[0123] According to some embodiments, Figure 1K and Figure 1LAs shown, a portion of nanostructures 126 and 128 is removed from sidewalls 126s and 128s of nanostructures 126 and 128 via trench 164 of spacer structure 160. According to some embodiments, the removal process widens trenches 126a and 128a. According to some embodiments, after the removal process, trench 126a extends into inner spacer layer 170, and trench 128a extends between spacer structure 160 and inner spacer layer 170.

[0124] According to some embodiments, the removal process also removes an upper portion of the gate stack 210 above the nanostructures 124. According to some embodiments, after the removal process, top surfaces 212a, 214a, and 216a of the gate dielectric layer 212, the work function metal layer 214, and the gate electrode layer 216 are substantially coplanar.

[0125] According to some embodiments, top surfaces 212a, 214a, and 216a are lower than top surface 126d of nanostructure 126. According to some embodiments, top surfaces 212a, 214a, and 216a are lower than upper surface 176 of inner spacer layer 170. According to some embodiments, the removal process comprises an isotropic etching process, such as a (lateral) wet etching process.

[0126] According to some embodiments, Figure 1M As shown, the anti-reflection layer 230 and the mask layer 240 are removed. According to some embodiments, the removal process includes an etching process, such as a plasma etching process. According to some embodiments, Figure 1M As shown, a dielectric layer 250 a is formed in the trenches 164 , 128 a , 174 , and 126 a of the spacer structure 160 , the nanostructure 128 , the inner spacer layer 170 , and the nanostructure 126 .

[0127] According to some embodiments, the dielectric layer 250a is made of a low-k dielectric material. According to some embodiments, in some other embodiments, the dielectric layer 250a is made of an insulating material, such as an oxide-containing material (e.g., silicon oxide), a nitride-containing material (e.g., silicon nitride), a nitrogen oxide-containing material (e.g., silicon oxynitride), or a carbide-containing material (e.g., silicon carbide).

[0128] According to some embodiments, the dielectric layer 250a is formed using a deposition process. According to some embodiments, the deposition process includes an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a flowable chemical vapor deposition (FCVD) process, a sputtering process, or a combination thereof.

[0129] Figure 1N-1 According to some embodiments Figure 1NA perspective view of a semiconductor device structure. Figure 1N According to some embodiments, Figure 1N-1 The cross-sectional line 1N-1N' in FIG. 1 shows a schematic cross-sectional view of the semiconductor device structure.

[0130] According to some embodiments, Figure 1M , Figure 1N and Figure 1N-1 As shown, a portion of dielectric layer 250a outside trenches 164, 128a, 174, and 126a is removed. According to some embodiments, dielectric layer 250a remaining in trenches 164, 128a, 174, and 126a forms dielectric structure 250. According to some embodiments, in this step, semiconductor device structure 100 is substantially formed.

[0131] In accordance with some embodiments, top surfaces 222, 194, 166, and 251 of contact structure 220, dielectric layer 190, spacer structure 160, and dielectric structure 250 are substantially coplanar. In accordance with some embodiments, dielectric structure 250 extends laterally into inner spacer layer 170. In accordance with some embodiments, dielectric structure 250 extends laterally between inner spacer layer 170 and spacer structure 160.

[0132] According to some embodiments, dielectric structure 250 directly contacts nanostructures 126 and 128. According to some embodiments, dielectric structure 250 directly contacts gate dielectric layer 212, work function metal layer 214, and gate electrode layer 216.

[0133] In some embodiments, a distance D1 between top surface 211 of gate stack 210 and top surface 111 of substrate 110 is smaller than a distance D2 between top surface 181 and top surface of source / drain structure 180. According to some embodiments, dielectric structure 250 passes through nanostructures 126 and 128 above gate stack 210.

[0134] According to some embodiments, dielectric structure 250 has extensions 252 and 254. According to some embodiments, extension 252 is between inner spacer layer 170 and spacer structure 160. According to some embodiments, extension 254 penetrates into inner spacer layer 170. That is, inner spacer layer 170 surrounds extension 254 according to some embodiments.

[0135] According to some embodiments, the extension 254 passes through the inner spacer layer 170. According to some embodiments, the width W1 of the spacer structure 160, the width W2 of the extension 252, and the width W3 of the extension 254 are substantially equal to each other.

[0136] According to some embodiments, nanostructure 126 (including portions 126b and 126c) does not extend into inner spacer layer 170. According to some embodiments, nanostructure 128 (including portions 128b and 128c) does not extend between inner spacer layer 170 and spacer structure 160. According to some embodiments, the removal process includes a planarization process, such as a chemical polishing process.

[0137] According to some embodiments, due to the removal of a portion of the nanostructure 126 in the inner spacer layer 170, the distance between the nanostructure 126 and the gate stack 210 increases. Therefore, according to some embodiments, the parasitic capacitance between the gate stack 210 and the nanostructure 126 is reduced.

[0138] Similarly, according to some embodiments, due to the removal of a portion of the nanostructure 128 above the inner spacer layer 170, the distance between the nanostructure 128 and the gate stack 210 increases. Therefore, according to some embodiments, the parasitic capacitance between the gate stack 210 and the nanostructure 128 is reduced. As a result, according to some embodiments, the performance of the semiconductor device structure 100 is improved.

[0139] Figure 2 is a schematic cross-sectional view of a semiconductor device structure 200 according to some embodiments. Figure 2 As shown, the semiconductor device structure 200 is similar to Figure 1N The semiconductor device structure 100 is shown in FIG. 1 , except that the nanostructure 126 (including portions 126 b and 126 c ) extends into the inner spacer layer 170 , and the nanostructure 128 (including portions 128 b and 128 c ) extends between the inner spacer layer 170 and the spacer structure 160 .

[0140] According to some embodiments, the width W2 of the extension 252 is less than the width W1 of the spacing structure 160. According to some embodiments, the width W3 of the extension 254 is less than the width W1 of the spacing structure 160. According to some embodiments, the width W2 of the extension 252 is substantially equal to the width W3 of the extension 254.

[0141] In some embodiments, the width W2 of the extension portion 252 is smaller than the width W3 of the extension portion 254. In some other embodiments, the width W2 of the extension portion 252 is larger than the width W3 of the extension portion 254.

[0142] Figure 3 is a schematic cross-sectional view of a semiconductor device structure 300 according to some embodiments. Figure 3 As shown, the semiconductor device structure 300 is similar to Figure 1N The semiconductor device structure 100 is shown in FIG. 1 , except that the dielectric structure 250 extends into or penetrates into the source / drain structure 180 .

[0143] According to some embodiments, extension 252 of dielectric structure 250 is above inner spacer layer 170 and extends into source / drain structure 180. According to some embodiments, extension 254 of dielectric structure 250 passes through inner spacer layer 170 and extends into source / drain structure 180.

[0144] According to some embodiments, the width W2 of the extension 252 is greater than the width W1 of the spacing structure 160. According to some embodiments, the width W3 of the extension 254 is greater than the width W1 of the spacing structure 160. According to some embodiments, the width W2 of the extension 252 is substantially equal to the width W3 of the extension 254.

[0145] In some embodiments, the width W2 of the extension portion 252 is smaller than the width W3 of the extension portion 254. In some other embodiments, the width W2 of the extension portion 252 is larger than the width W3 of the extension portion 254.

[0146] According to some embodiments, the formation of the semiconductor device structure 300 includes: performing Figure 1A to Figure 1K removing the nanostructures 126 and 128 in or above the inner spacer layer 170 and the source / drain structure 180; and performing Figure 1M to Figure 1N steps.

[0147] Figure 4 is a schematic cross-sectional view of a semiconductor device structure 400 according to some embodiments. Figure 4 As shown, the semiconductor device structure 400 is similar to Figure 1N The semiconductor device structure 100 is shown in FIG. 1 , except that the dielectric structure 250 has voids 252 a and 254 a in the trenches 128 a and 126 a of the nanostructures 128 and 126 .

[0148] According to some embodiments, void 252a is located in extension 252. According to some embodiments, void 254a is located in extension 254. According to some embodiments, voids 252a and 254a are filled with air. In some other embodiments, voids 252a and 254a are filled with a gas, such as an inert gas, nitrogen, or other suitable gas.

[0149] According to some embodiments, since the (relative) dielectric constant of air or gas is low (about 1), the formation of voids 252a and 254a reduces the dielectric constant of dielectric structure 250 between gate stack 210 and nanostructures 128 and 126. Therefore, according to some embodiments, the formation of voids 252a and 254a reduces the parasitic capacitance between gate stack 210 and nanostructures 128 and 126. As a result, according to some embodiments, the performance of semiconductor device structure 400 is improved.

[0150] According to some embodiments, the width W4 of the gap 252a is substantially equal to the width W1 of the spacing structure 160. According to some embodiments, the width W5 of the gap 254a is substantially equal to the width W1 of the spacing structure 160.

[0151] According to some embodiments, the dielectric structure 250 is formed using a deposition process (eg, a chemical vapor deposition process) and a planarization process (eg, a chemical mechanical polishing process). Figure 4 The deposition rate of the deposition process (eg, chemical vapor deposition process) of the dielectric structure 250 is greater than that of the deposition process used to form the dielectric structure 250. Figure 1N The deposition rate of the deposition process (eg, atomic layer deposition process) of the dielectric structure 250 .

[0152] Figure 5 is a schematic cross-sectional view of a semiconductor device structure 500 according to some embodiments. Figure 5 As shown, the semiconductor device structure 500 is similar to Figure 4 The semiconductor device structure 400 is shown in FIG. 4 , except that in the semiconductor device structure 500 , the width W4 of the gap 252 a or the width W5 of the gap 254 a is smaller than the width W1 of the spacer structure 160 .

[0153] Figure 6 is a schematic cross-sectional view of a semiconductor device structure 600 according to some embodiments. Figure 6 As shown, the semiconductor device structure 600 is similar to Figure 3 The semiconductor device structure 300 and Figure 4 The semiconductor device structure 400 is shown in FIG. 4 , except that in the semiconductor device structure 600 , the width W4 of the void 252 a or the width W5 of the void 254 a is greater than the width W1 of the isolation structure 160 . In accordance with some embodiments, the voids 252 a and 254 a extend into the source / drain structure 180 .

[0154] Fig. 7A is a top view of a semiconductor device structure 700 according to some embodiments. Figure 7B According to some embodiments, Fig. 7A The section line 7B- 7B′ in FIG. 7 shows a schematic cross-sectional view of the semiconductor device structure 700 . Figure 7C According to some embodiments, Fig. 7A The section line 7C- 7C′ in FIG. 7 shows a schematic cross-sectional view of the semiconductor device structure 700 . Fig.7D According to some embodiments, Fig. 7A The section line 7D-7D′ in FIG. 7 shows a schematic cross-sectional view of the semiconductor device structure 700 .

[0155] According to some embodiments, Fig. 7AAs shown, semiconductor device structure 700 has portions 701, 702, and 703. According to some embodiments, portions 701, 702, and 703 are connected to each other. According to some embodiments, Fig. 7A and Figure 7B As shown, part 701 and Figure 1N The semiconductor device structure 100 is similar or identical to that of FIG.

[0156] According to some embodiments, Fig. 7A and Figure 7C As shown, portion 702 and Figure 1F The semiconductor device structures are similar or identical. According to some embodiments, Fig. 7A and Fig.7D As shown, portion 703 and Figure 1F The semiconductor device structures are similar or identical.

[0157] According to some embodiments, Fig. 7A , Figure 7B , Figure 7C and Fig.7D As shown, portion 701 has two channel nanostructures (i.e., nanostructures 122 and 124), while portion 702 or 703 has four channel nanostructures (i.e., nanostructures 122, 124, 126, and 128). That is, according to some embodiments, the number of channel nanostructures in different portions of semiconductor device structure 700 can be changed according to different requirements.

[0158] Figure 8 FIG. 8 is a cross-sectional view of a semiconductor device structure 800 according to some embodiments. Figure 8 As shown, according to some embodiments, the semiconductor device structure 800 is similar to Figure 1N The semiconductor device structure 100 has a contact structure 810 in addition to the semiconductor device structure 800 .

[0159] According to some embodiments, the contact structure 810 passes through the dielectric structure 250 and the nanostructures 126 and 128. According to some embodiments, the contact structure 810 is electrically connected to the gate stack 210. According to some embodiments, the contact structure 810 directly contacts the gate stack 210. According to some embodiments, the contact structure 810 is made of metal (e.g., tungsten, aluminum, or copper), alloys thereof, or similar materials.

[0160] According to some embodiments, the contact structure 810 is formed using a deposition process (eg, a physical vapor deposition process or a chemical vapor deposition process) and a planarization process (eg, a chemical mechanical polishing process).

[0161] Fig. 9 is a schematic cross-sectional view of a semiconductor device structure 900 according to some embodiments. Fig. 9 As shown, the semiconductor device structure 900 is similar to Figure 1N The semiconductor device structure 100 includes a dielectric layer 910 and contact structures 920 and 930 in addition to the semiconductor device structure 900 .

[0162] According to some embodiments, dielectric layer 910 is formed over dielectric layer 190, contact structure 220, spacer structure 160, and dielectric structure 250. According to some embodiments, dielectric layer 910 includes a dielectric material, such as an oxide-containing material (e.g., silicon oxide), an oxide-nitride-containing material (e.g., silicon oxynitride), a low dielectric constant material, a porous dielectric material, glass, or a combination thereof.

[0163] According to some embodiments, the glass includes borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or a combination thereof. According to some embodiments, the dielectric layer 910 is formed by a deposition process (eg, a chemical vapor deposition process).

[0164] According to some embodiments, the contact structure 920 passes through the dielectric layer 910. According to some embodiments, the contact structure 920 is electrically connected to the contact structure 220 thereunder. According to some embodiments, the contact structure 920 directly contacts the contact structure 220 thereunder. According to some embodiments, the contact structure 920 is made of metal (e.g., tungsten, aluminum, or copper), alloys thereof, or similar materials.

[0165] According to some embodiments, the contact structure 930 passes through the dielectric layer 910, the dielectric structure 250, and the nanostructures 126 and 128. According to some embodiments, the contact structure 930 is electrically connected to the gate stack 210. According to some embodiments, the contact structure 930 directly contacts the gate stack 210.

[0166] In some embodiments, dielectric layer 910 and top surfaces 916, 922, and 932 of contact structures 920 and 930 are substantially coplanar. According to some embodiments, contact structure 930 is made of metal (eg, tungsten, aluminum, or copper), alloys thereof, or similar materials.

[0167] According to some embodiments, the formation of contact structures 920 and 930 includes: removing a portion of the dielectric layer 910 to form through holes 912 and 914 above the contact structure 220 and the dielectric structure 250; removing a portion of the dielectric structure 250 to form a through hole 256 in the dielectric structure 250; depositing a conductive layer (not shown) in the through holes 912, 914 and 256 and above the dielectric layer 910; and removing the conductive layer outside the through holes 912, 914 and 256.

[0168] Figure 10A to Figure 10Gis a cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1A After the steps, Fig. 10A As shown, ends of the nanostructures 121 , 122 , 123 , 124 , 125 , 126 , 127 , and 128 that are not covered by the gate stack 140 and the spacer structure 160 are removed.

[0169] According to some embodiments, Fig. 10A As shown, the sidewalls 121a, 122a, 123a, 124a, 125a, 126a', 127a and 128a' of the nanostructures 121, 122, 123, 123, 124, 125, 126, 127 and 128 are substantially aligned (or substantially coplanar) with the sidewall 162 of the spacer structure 160. According to some embodiments, the removal process includes an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0170] According to some embodiments, Fig. 10B As shown, Figure 1D The step of forming a source / drain structure 180 and a dielectric layer 190 on the substrate 110. According to some embodiments, as Fig. 10B and Fig. 10C As shown, the gate stack 140 and the mask layer 150 are removed. According to some embodiments, the removal process forms a trench 164 in the spacer structure 160. According to some embodiments, as Fig. 10C As shown, portions of nanostructures 121, 123, 125, and 127 beneath trench 164 are removed. According to some embodiments, the removal process includes an anisotropic etching process, such as a dry etching process.

[0171] According to some embodiments, Fig. 10D As shown, the remaining nanostructures 121, 123, 125 and 127 are oxidized to form an inner spacer layer 170. Thereafter, according to some embodiments, as Fig. 10D As shown, Figure 1E The step of forming the gate stack 210 in the trench 164 is performed, and the gate stack 210 surrounds the nanostructures 122, 124, 126 and 128. Thereafter, according to some embodiments, as Fig. 10D As shown, Figure 1F The step of forming the contact structure 220 in the dielectric layer 190 is performed.

[0172] According to some embodiments, Fig. 10D and Fig.10E As shown, Figure 1G to Figure 1KThe steps of forming an anti-reflective layer 230 and a mask layer 240 over the dielectric layer 190, the contact structure 220 and the spacer structure 160, and sequentially removing the gate stack 210 in the trench 164, the nanostructure 128 under the trench 164, the gate stack 210 between the nanostructures 126 and 128, and the nanostructure 126 under the trench 164. According to some embodiments, the removal process forms trenches 128a, 174 and 126a in the nanostructure 128, the inner spacer layer 170 and the nanostructure 126, respectively. According to some embodiments, the trenches 126a, 174 and 128a are connected to the trench 164.

[0173] According to some embodiments, nanostructure 126 is divided into parts 126b and 126c by groove 126a. According to some embodiments, parts 126b and 126c are spaced apart from each other. According to some embodiments, nanostructure 128 is divided into parts 128b and 128c by groove 128a. According to some embodiments, parts 128b and 128c are spaced apart from each other.

[0174] According to some embodiments, Fig.10E and Fig.10F As shown, portions 126b, 126c, 128b, and 128c are removed via the groove 164 of the spacer structure 160. According to some embodiments, in this step, the nanostructures 126 and 128 are completely removed. In some embodiments, after removing portions 126b, 126c, 128b, and 128c, a groove TR1 between the spacer structure 160 and the inner spacer layer 170 and a groove TR2 in the inner spacer layer 170 are formed.

[0175] Figure 10G-1 According to some embodiments Figure 10G According to some embodiments, as Figure 10G and Figure 10G-1 As shown, Figure 1M and Figure 1N The step of removing the anti-reflective layer 230 and the mask layer 240 and forming a dielectric structure 250 in the trenches 164, 174, TR1 and TR2. According to some embodiments, the dielectric structure 250 directly contacts the source / drain structure 180. According to some embodiments, in this step, the semiconductor device structure 1000 is substantially formed.

[0176] According to some embodiments, the removal of portions 126b and 126c of nanostructure 126 in inner spacer layer 170 prevents parasitic capacitance from being generated between gate stack 210 and nanostructure 126. Thus, according to some embodiments, the performance of semiconductor device structure 1000 is improved.

[0177] The processes and materials used to form the semiconductor device structures 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , and 1000 may be similar or identical to the processes and materials described above for forming the semiconductor device structure 100 .

[0178] According to some embodiments, semiconductor device structures and methods for forming the same are provided. According to some embodiments, the method (for forming the semiconductor device structure) removes portions of the nanostructures above the gate stack and in the inner spacer layer to increase the distance between the gate stack and the nanostructure. Therefore, according to some embodiments, the parasitic capacitance between the gate stack and the nanostructure is reduced. As a result, according to some embodiments, the performance of the semiconductor device structure is improved.

[0179] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure above the substrate. The semiconductor device structure includes a gate stack above the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source / drain structure surrounding the first nanostructure. The semiconductor device structure includes a second source / drain structure surrounding the first nanostructure. The gate stack is between the first source / drain structure and the second source / drain structure. The semiconductor device structure includes an inner spacer layer, which covers the sidewalls of the first source / drain structure and is partially located between the gate stack and the first source / drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure above the gate stack and extending into the inner spacer layer.

[0180] According to some embodiments, the first nanostructure is between the first source / drain structure and the second source / drain structure. According to some embodiments, the first source / drain structure and the second source / drain structure surround the first nanostructure. According to some embodiments, the semiconductor device structure further includes a second nanostructure above the first nanostructure, wherein the second nanostructure has a first portion and a second portion spaced apart from each other, the first source / drain structure further surrounds the first portion, and the second source / drain structure further surrounds the second portion. According to some embodiments, the first portion passes through the first source / drain structure and does not extend into the inner spacer layer. According to some embodiments, the first portion passes through the first source / drain structure and partially extends into the inner spacer layer. According to some embodiments, the gate stack includes a gate dielectric layer, a work function layer, and a gate electrode layer sequentially stacked above the first nanostructure, and the dielectric structure directly contacts the gate dielectric layer, the work function layer, and the gate electrode layer. According to some embodiments, a first distance between a first top surface of the gate stack and a second top surface of the substrate is less than a second distance between a third top surface of the first source / drain structure and a second top surface. According to some embodiments, the dielectric structure further extends into the first source / drain structure.

[0181] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure and a second nanostructure above the substrate. The first nanostructure is between the second nanostructure and the substrate. The semiconductor device structure includes a gate stack above the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source / drain structure surrounding the first nanostructure and the second nanostructure. The semiconductor device structure includes a second source / drain structure surrounding the first nanostructure and the second nanostructure. The gate stack is between the first source / drain structure and the second source / drain structure. The semiconductor device structure includes an inner spacer layer, which covers the sidewalls of the first source / drain structure and is partially located between the gate stack and the first source / drain structure. The semiconductor device structure includes a dielectric structure passing through the second nanostructure above the gate stack. The dielectric structure has an extension extending into the inner spacer layer.

[0182] According to some embodiments, the extension has a void. According to some embodiments, the extension extends into the first source / drain structure. According to some embodiments, the void extends into the first source / drain structure. According to some embodiments, the semiconductor device structure further includes a contact structure that passes through the dielectric structure and is connected to the gate stack.

[0183] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, an inner spacer, a first source / drain structure, a second source / drain structure, a dielectric layer, and a gate stack. The first nanostructure is between the second nanostructure and the substrate, the first source / drain structure, the second source / drain structure, and the gate stack surround the first nanostructure and the second nanostructure, the gate stack is between the first source / drain structure and the second source / drain structure, the inner spacer is between the gate stack and the first source / drain structure, and the dielectric layer is above the first source / drain structure and the second source / drain structure. The method includes removing a first portion of the gate stack above the second nanostructure to form a trench in the dielectric layer. The method includes removing a second portion of the second nanostructure below the trench. The method includes removing a third portion of the second nanostructure above the inner spacer through the trench. The method includes forming a dielectric structure in the trench.

[0184] According to some embodiments, the dielectric structure is further formed above the inner spacer layer. According to some embodiments, the dielectric structure above the inner spacer layer has a void. According to some embodiments, removing the third portion of the second nanostructure above the inner spacer layer further removes a fourth portion of the gate stack above the first nanostructure. According to some embodiments, the first source / drain structure surrounds the first nanostructure and the second nanostructure, and removing the third portion of the second nanostructure above the inner spacer layer further removes a fifth portion of the second nanostructure in the first source / drain structure. According to some embodiments, the dielectric structure is further formed above the inner spacer layer and in the first source / drain structure.

[0185] The above summarizes the components of several embodiments so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present invention, and they can make various changes, substitutions and adjustments without violating the spirit and scope of the embodiments of the present invention.

Claims

1. A semiconductor device structure, comprising: a base; a first nanostructure above the substrate; a gate stack over the substrate and surrounding the first nanostructure; a first source / drain structure and a second source / drain structure above the substrate, wherein the gate is stacked between the first source / drain structure and the second source / drain structure; an inner spacer layer covering the sidewalls of the first source / drain structure and partially located between the gate stack and the first source / drain structure, wherein the first nanostructure passes through the inner spacer layer; as well as A dielectric structure is above the gate stack and extends into the inner spacer layer. 2 . The semiconductor device structure of claim 1 , wherein the first nanostructure is between the first source / drain structure and the second source / drain structure. 3 . The semiconductor device structure of claim 1 , wherein the first source / drain structure and the second source / drain structure surround the first nanostructure.

4. The semiconductor device structure of claim 3, further comprising: A second nanostructure is above the first nanostructure, wherein the second nanostructure has a first portion and a second portion spaced apart from each other, the first source / drain structure further surrounds the first portion, and the second source / drain structure further surrounds the second portion. 5 . The semiconductor device structure of claim 4 , wherein the first portion passes through the first source / drain structure and does not extend into the inner spacer layer. 6 . The semiconductor device structure of claim 4 , wherein the first portion passes through the first source / drain structure and partially extends into the inner spacer layer.

7. The semiconductor device structure as claimed in claim 1, wherein the gate stack comprises a gate dielectric layer, a work function layer and a gate electrode layer stacked in sequence above the first nanostructure, and the dielectric structure directly contacts the gate dielectric layer, the work function layer and the gate electrode layer.

8. The semiconductor device structure of claim 1, wherein a first distance between a first top surface of the gate stack and a second top surface of the substrate is smaller than a second distance between a third top surface of the first source / drain structure and the second top surface.

9. The semiconductor device structure of claim 1, wherein the dielectric structure further extends into the first source / drain structure.

10. A semiconductor device structure, comprising: A substrate having a base and a fin above the base; a nanostructure above the fin; A gate stack wraps around the fin and the nanostructure; a first source / drain structure and a second source / drain structure above the fin, wherein the gate is stacked between the first source / drain structure and the second source / drain structure; an inner spacer layer covering the sidewalls of the first source / drain structure and partially located between the gate stack and the first source / drain structure, wherein the inner spacer layer surrounds the nanostructure between the gate stack and the first source / drain structure; as well as A dielectric structure is above the gate stack, wherein the dielectric structure has an extension extending toward the first source / drain structure and the inner spacer layer surrounds the extension. The semiconductor device structure as claimed in claim 10 , wherein the extension portion has a gap. 12 . The semiconductor device structure of claim 11 , wherein the extension extends into the first source / drain structure. 13 . The semiconductor device structure of claim 12 , wherein the void extends into the first source / drain structure.

14. The semiconductor device structure of claim 10, further comprising: A contact structure passes through the dielectric structure and is connected to the gate stack.

15. A method for forming a semiconductor device structure, comprising: Providing a substrate, a first nanostructure, a second nanostructure, an inner spacer, a first source / drain structure, a second source / drain structure, a dielectric layer and a gate stack, wherein the first nanostructure is between the second nanostructure and the substrate, the gate stack surrounds the first nanostructure and the second nanostructure, the gate stack is between the first source / drain structure and the second source / drain structure, the inner spacer is between the gate stack and the first source / drain structure, and the dielectric layer is above the first source / drain structure and the second source / drain structure; removing a first portion of the gate stack above the second nanostructure to form a trench in the dielectric layer; removing a second portion of the second nanostructure below the trench; removing a third portion of the second nanostructure above the inner spacer layer through the trench; as well as A dielectric structure is formed in the trench. 16 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein the dielectric structure is further formed above the inner spacer layer. 17 . The method for forming a semiconductor device structure as claimed in claim 16 , wherein the dielectric structure above the inner spacer layer has a gap. 18 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein removing the third portion of the second nanostructure above the inner spacer layer further removes a fourth portion of the gate stack above the first nanostructure.

19. The method for forming a semiconductor device structure as described in claim 18, wherein the first source / drain structure surrounds the first nanostructure and the second nanostructure, and removing the third portion of the second nanostructure above the inner spacer layer also removes a fifth portion of the second nanostructure in the first source / drain structure. 20 . The method for forming a semiconductor device structure as claimed in claim 19 , wherein the dielectric structure is further formed above the inner spacer layer and in the first source / drain structure.

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