Nonvolatile memory device with resistive switching layer and operation method thereof

Abstract

A nonvolatile memory device according to one embodiment includes: a substrate; a resistive switching layer disposed on the substrate; a gate insulating layer disposed on the resistive switching layer; a gate electrode layer disposed on the gate insulating layer; and a first electrode pattern layer and a second electrode pattern layer respectively disposed on the substrate and configured to contact different portions of the resistive switching layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Application No. 10-2019-0179517, filed on December 31, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having a resistive switching layer and an operating method thereof. Background Art

[0004] Since the trend of semiconductor devices includes reducing design rules and increasing integration, research on semiconductor device structures that can ensure structural stability and signal storage operation reliability is continuously conducted. Currently, non-volatile memory devices such as flash memories that use a three-layer stacked structure as a charge storage structure have been widely used, and the three-layer stacked structure includes: a charge tunneling layer, a charge trap layer, and a charge blocking layer.

[0005] Recently, various nonvolatile memory devices having structures different from those of existing flash memory devices have been proposed. One example of a nonvolatile memory device is a resistive memory device. When a flash memory device implements a storage function via charge storage, in a resistive memory device, a resistance state of a storage layer in a memory cell changes between a high resistance state and a low resistance state in a variable manner, and the changed resistance state is stored in a nonvolatile manner, thereby writing predetermined signal information into the memory cell. Summary of the invention

[0006] A nonvolatile memory device according to one aspect of the present disclosure includes: a substrate; a resistive switching layer disposed on the substrate; a gate insulating layer disposed on the resistive switching layer; a gate electrode layer disposed on the gate insulating layer, and a first electrode pattern layer and a second electrode pattern layer, which are respectively disposed on the substrate and are disposed to contact different portions of the resistive switching layer.

[0007] According to another aspect of the present disclosure, a nonvolatile memory device includes: a substrate; a gate electrode layer disposed on the substrate; a gate insulating layer disposed on the substrate and disposed to surround the gate electrode layer; a first electrode pattern layer and a second electrode pattern layer disposed on the substrate and disposed on opposite sides of the gate electrode layer, respectively; and a resistive switching layer disposed on the gate insulating layer and on the first electrode pattern layer and the second electrode pattern layer. The resistive switching layer includes oxygen vacancies and movable metal ions.

[0008] According to another aspect of the present disclosure, a nonvolatile memory device includes: a substrate; a first electrode pattern layer and a second electrode pattern layer, which are disposed on the substrate and are spaced apart from each other; a resistive switching layer, which is disposed on the first electrode pattern layer and the second electrode pattern layer; and a gate insulating layer and a gate electrode layer, which are sequentially disposed on the resistive switching layer. The resistive switching layer includes oxygen vacancies and movable metal ions.

[0009] According to another aspect of the present disclosure, a method for operating a non-volatile memory device is disclosed. In the method for operating the non-volatile memory device, a non-volatile memory device is provided, which includes: a resistive layer, which is arranged on a substrate; a gate insulating layer and a gate electrode layer, which are sequentially arranged on the resistive layer; and a first electrode pattern layer and a second electrode pattern layer, which are respectively arranged on the substrate to contact different parts of the resistive layer. A first gate voltage is applied to the gate electrode layer to move oxygen vacancies or movable metal ions in the resistive layer to a filament formation region of the resistive layer. A set voltage is applied between the first electrode pattern layer and the second electrode pattern layer to form a conductive filament in the resistive layer, and the first electrode pattern layer and the second electrode pattern layer are electrically connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view schematically illustrating a nonvolatile memory device according to an embodiment of the present disclosure.

[0011] Figures 2 to 4 is a view illustrating a set operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0012] Figure 5 is a view illustrating a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0013] Figure 6 is a cross-sectional view of a nonvolatile memory device according to a comparative example.

[0014] Figure 7 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0015] Figures 8 to 10 is a view illustrating a set operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0016] Fig.11 is a view illustrating a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0017] Fig.12is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0018] Fig.13 and Fig.14 2 are views respectively explaining a set operation and a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0019] Fig.15 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0020] Fig.16 and Fig.17 2 are views respectively explaining a set operation and a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, the embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, in order to clearly represent the components of each device, the size of the components (e.g., the width and thickness of the components) is enlarged. The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be interpreted as different according to those of ordinary skill in the art to which the embodiments belong. If specifically defined, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by those of ordinary skill in the art to which the embodiments belong.

[0022] In addition, unless otherwise clearly utilized in the context, the expression of the singular form of a word should be understood to include the plural form of the word. It will be understood that the terms "comprise", "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, element, part, or a combination thereof, but are not used to exclude the presence or possibility of adding one or more other features, numbers, steps, operations, components, elements, parts, or a combination thereof.

[0023] In addition, when performing a method or manufacturing method, each process constituting the method may be performed in a different order than that specified, unless a specific order is clearly described in the context. In other words, each process may be performed in the same manner as the stated order, and each process may be performed substantially simultaneously. In addition, at least a portion of each of the above processes may be performed in a reverse order.

[0024] In this specification, the term "predetermined direction" may refer to a direction including a direction determined in a coordinate system and a direction opposite to the direction. As an example, in an xyz coordinate system, the z direction may include a direction parallel to the z direction. That is, the z direction may refer to all directions as follows: a direction in which the absolute value of the z axis increases along the positive direction of the z axis from the origin 0, and a direction in which the absolute value of the z axis increases along the negative direction of the z axis from the origin 0. In the xyz coordinate system, the x direction and the y direction may be interpreted in substantially the same manner, respectively.

[0025] Figure 1 Schematically shows a cross-sectional view of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 1 , the nonvolatile memory device 1 may include: a substrate 101; a resistive layer 120 disposed on the substrate 101; a gate insulating layer 130 disposed on the resistive layer 120; a gate electrode layer 140 disposed on the gate insulating layer 130; and a first electrode pattern layer 150 and a second electrode pattern layer 160, which are disposed on the substrate 101 and contact different parts of the resistive layer 120 respectively. The gate insulating layer 130 may surround the gate electrode layer 140, and may insulate the gate electrode layer 140 from the resistive layer 120, the first electrode pattern layer 150, and the second electrode pattern layer 160. In addition, the nonvolatile memory device 1 may further include a device insulating layer 105 on the substrate 101. The device insulating layer 105 may be configured to insulate the gate insulating layer 130, the gate electrode layer 140, the first electrode pattern layer 150, and the second electrode pattern layer 160 from the substrate 101.

[0026] See also Figure 1 The provided substrate 101 may include a semiconductor material. Specifically, the semiconductor material may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The substrate 101 may be doped with an n-type dopant or a p-type dopant. As an example, the substrate 101 may include a well region doped with an n-type dopant or a p-type dopant.

[0027] The device insulating layer 105 may be disposed on the substrate 101. The device insulating layer 105 may insulate the gate insulating layer 130, the gate electrode layer 140, the first electrode pattern layer 150, and the second electrode pattern layer 160 from the substrate 101. The device insulating layer 105 may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0028] Despite Figure 1Although not shown in the figure, at least one conductive layer and at least one insulating layer may be provided between the substrate 101 and the device insulating layer 105. The conductive layer and the insulating layer may form various circuit patterns. That is, as a non-limiting example, the conductive layer and the insulating layer may form a plurality of wirings, or may constitute a passive element such as a capacitor or a resistor, or an active element such as a diode or a transistor.

[0029] See again Figure 1 , the gate electrode layer 140 may be disposed on the device insulating layer 105. The gate electrode layer 140 may be a pattern of a conductive film. The gate electrode layer 140 may include a conductive material. The conductive material may, for example, include a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may, for example, include: n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0030] The gate insulating layer 130 may be disposed on the gate electrode layer 140. In one embodiment, the gate insulating layer 130 may be disposed to surround the gate electrode layer 140. The gate insulating layer 130 may contact the first electrode pattern layer 150 and the second electrode pattern layer 160 in a lateral direction such as the x-axis direction. The gate insulating layer 130 may electrically insulate the first electrode pattern layer 150 and the second electrode pattern layer 160 from the gate electrode layer 140. In addition, the gate insulating layer 130 may prevent oxygen vacancies or movable metal ions in the resistive layer 120 from moving to the gate electrode layer 140. The gate insulating layer may, for example, include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and the like.

[0031] See also Figure 1 , the first electrode pattern layer 150 and the second electrode pattern layer 160 may be disposed on opposite sides of each other based on the gate electrode layer 140 on the device insulating layer 105. The first electrode pattern layer 150 and the second electrode pattern layer 160 may each contact the gate insulating layer 130 in a lateral direction. The first electrode pattern layer 150 and the second electrode pattern layer 160 may be electrically insulated from the gate electrode layer 140 by the gate insulating layer 130. The upper surfaces of the first electrode pattern layer 150 and the second electrode pattern layer 160 may be located at the same level as the upper surface of the gate insulating layer 130.

[0032] The first electrode pattern layer 150 and the second electrode pattern layer 160 may each include a conductive material. The conductive material may, for example, include a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may, for example, include: n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0033] The resistive layer 120 may be disposed on the first electrode pattern layer 150 and the second electrode pattern layer 160 and on the gate insulating layer 130. The resistive layer 120 may have a first surface LS120 and a second surface US120 opposite to the first surface LS120. As shown in the figure, the resistive layer 120 may contact the first electrode pattern layer 150, the second electrode pattern layer 160 and the gate insulating layer 130 at the first surface LS120.

[0034] The resistive layer 120 may include a variable resistance material. In the variable resistance material, the internal resistance state may be changed in a variable manner according to the polarity or magnitude of the applied voltage. In addition, the changed internal resistance state may be stored in the variable resistance material in a non-volatile manner after the applied voltage is removed. As an example, a high resistance state and a low resistance state distinguished from each other may be selectively stored in the variable resistance material. In other words, the variable resistance material may have a predetermined first resistance value corresponding to the high resistance state, and may have a predetermined second resistance value corresponding to the low resistance state. The first resistance value and the second resistance value of the resistive layer may be determined according to the type of the variable resistance material.

[0035] In one embodiment, the variable resistance material may include oxygen vacancies or movable metal ions. The oxygen vacancies may be positively charged. The metal ions may be cations with positive charges or anions with negative charges. In one embodiment, the variable resistance material may include, for example, titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, iron oxide, or a combination of two or more thereof. In other embodiments, the variable resistance material may include: PCMO (Pr 1-x Ca x MnO3,0 <x<1)、LCMO(La 1-x Ca x MnO3,0 <x<1)、BSCFO(Ba 0.5 Sr 0.5 Co 0.8 Fe 0.2 O 3-δ)、YBCO (YB a2 Cu3O 7-x , 0 < x < 1), (Ba,Sr)TiO3 doped with chromium (Cr) or niobium (Nb), SrZrO3 doped with chromium (Cr) or vanadium (V), (La,Sr)MnO3, Sr 1-x La x TiO3 (0 < x < 1), La 1-x Sr x FeO3 (0 < x < 1), La 1-x Sr x CoO3 (0 < x < 1), SrFeO 2.7 、LaCoO3, RuSr2GdCu2O3 and YBa2Cu3O7, or a combination of two or more of them. As another example, the variable resistance material may include: germanium - antimony - tellurium (GST), arsenic - antimony - tellurium (As - Sb - Te), tin - antimony - tellurium (Sn - Sb - Te), tin - indium - antimony - tellurium (Sn - In - Sb - Te), arsenic - germanium - antimony - tellurium (As - Ge - Sb - Te), Ge x Se 1-x (0 < x < 1), silver sulfide (Ag2S), copper sulfide (Cu2S), cadmium sulfide (CdS), zinc sulfide (ZnS) and cerium oxide (CeO2), or a combination of two or more of them.

[0036] See Figure 1 , the first electrode pattern layer 150 may have a pattern edge portion 150A located in the boundary region where the resistive change layer 120 contacts the gate insulating layer 130. Similarly, the second electrode pattern layer 160 may have a pattern edge portion 160A in the boundary region where the resistive change layer 120 and the gate insulating layer 130 contact. Although not specifically shown in Figure 1 , the pattern edge portions 150A and 160A may extend along the y - direction. When a voltage is applied between the first electrode pattern layer 150 and the second electrode pattern layer 160, the electric field generated by the applied voltage may be concentrated on the pattern edge portions 150A and 160A.

[0037] Hereinafter, a method of operating the non - volatile memory device 1 will be described with reference to Figures 2 to 5 . Figures 2 to 4 is a view illustrating the setting operation of the non - volatile memory device 1 according to an embodiment of the present disclosure. When the resistive change layer of the non - volatile memory device 1 has a high - resistance state, the setting operation may be an operation of changing the resistance state of the resistive change layer to a low - resistance state. Figure 51 is a diagram illustrating a reset operation of the nonvolatile memory device 1 according to an embodiment of the present disclosure. The reset operation may be an operation of changing a resistance state of the resistive change layer from a low resistance state to a high resistance state.

[0038] See also Figure 2 , the above references can be provided Figure 1 The nonvolatile memory device 1 described above. The resistive switching layer 120 may include oxygen vacancies or movable metal ions 125. In one embodiment, the oxygen vacancies or movable metal ions 125 may be uniformly distributed inside the resistive switching layer 120. In one example, the resistive switching layer 120 is provided with oxygen vacancies 125 having a positive charge. As another embodiment, when the resistive switching layer 120 includes the movable metal ions 125, substantially the same operating method may be applied.

[0039] See also Figure 3 , a first gate voltage may be applied to the gate electrode layer 140. The first gate voltage may include a bias voltage having a negative polarity. Under the influence of the first gate voltage, the oxygen vacancies 125 inside the resistive layer 120 may move to a filament formation region adjacent to the first surface LS120. The filament formation region is a region for generating the conductive filaments 10, which will be described later, and may refer to an inner region of the resistive layer 120 adjacent to the gate insulating layer 130 and the first electrode pattern layer 150 and the second electrode pattern layer 160.

[0040] According to one embodiment, the concentration or size of oxygen vacancies 125 moving to the filament formation region may be controlled by controlling the magnitude of the first gate voltage. The concentration of oxygen vacancies 125 may determine the diameter of the conductive filament formed in the operation described below.

[0041] See also Figure 4 When the first gate voltage is applied to the gate electrode layer 140, a set voltage may be applied between the first electrode pattern layer 150 and the second electrode pattern layer 160. As a result, an electric field generated by the set voltage may be formed inside the resistive layer 120, and a conductive filament 10 electrically connecting the first electrode pattern layer 150 and the second electrode pattern layer 160 may be formed in the resistive layer 120.

[0042] In the structure of the nonvolatile memory device 1 of the present embodiment, when a set voltage is applied, the electric field may be concentrated on the pattern edge portions 150A and 160A of the first electrode pattern layer 150 and the second electrode pattern layer 160. Therefore, the oxygen vacancies 125 in the region of the resistive layer 120 adjacent to the pattern edge portions 150A and 160A may be more actively aggregated or combined with each other, so that Figure 4The first trigger filament 125t1 and the second trigger filament 125t2 are formed as shown. The first trigger filament 125t1 and the second trigger filament 125t2 may be formed to contact the first electrode pattern layer 150 and the second electrode pattern layer 160, respectively.

[0043] In addition, the oxygen vacancies 125 can continuously aggregate or bind to the first trigger filament 125t1 and the second trigger filament 125t2, so that the connecting filament 125c can grow. The connecting filament 125c connects the first trigger filament 125t1 and the second trigger filament 125t2, so that the conductive filament 10 can form a continuous and connected filament. The conductive filament 10 that electrically connects the first electrode pattern layer 150 and the second electrode pattern layer 160 reduces the resistance of the resistive layer 120. Even after the set voltage and the gate voltage are removed, the conductive filament 10 remains inside the resistive layer 120, so that the resistive layer 120 can be written and maintained in a low resistance state.

[0044] In one embodiment, the first trigger filament 125t1 and the second trigger filament 125t2 formed in the pattern edge portions 150A and 160A where the electric field is concentrated may have a higher concentration of oxygen vacancies 125 than the connecting filament 125c. Therefore, the diameter of each of the first trigger filament 125t1 and the second trigger filament 125t2 may be greater than the diameter of the connecting filament 125c.

[0045] In some embodiments, the concentration of oxygen vacancies 125 introduced into the filament formation region by the first gate voltage may determine the diameter of the conductive filament 10. As the concentration of the induced oxygen vacancies 125 increases, the number of oxygen vacancies 125 that are aggregated or combined due to the applied set voltage may increase. Therefore, the diameter of the conductive filament 10 formed by the set voltage may be increased. In addition, as the diameter of the conductive filament 10 increases, the resistance value of the resistive layer 120 may be reduced. As described above, by utilizing the characteristic that the resistance value of the resistive layer 120 varies according to the width of the conductive filament 10, multiple resistance values ​​may be written in the resistive layer 120. As a result, a non-volatile memory device that stores multiple signal information in the resistive layer 120 may be implemented using a structure capable of forming a conductive filament having a variable diameter.

[0046] In addition, reference will be made to Figure 5 14. The reset operation according to another embodiment of the present disclosure is described below. A second gate voltage may be applied to the gate electrode layer 140. The second gate voltage may include a bias voltage having a positive polarity. In addition, when the second gate voltage is applied, a reset voltage may be applied between the first electrode pattern layer 150 and the second electrode pattern layer 160. The reset voltage may have a different polarity from the set voltage.

[0047] According to one embodiment, the oxygen vacancies 125 of the conductive filaments 10 in the resistive switching layer 120 can be decomposed by a reset voltage. In some embodiments, the reset voltage can generate Joule heat in the conductive filaments 10, and the Joule heat can decompose the oxygen vacancies 125 from the conductive filaments 10. In addition, the oxygen vacancies 125 available from the decomposition can be discharged from the filament formation region by a bias voltage having a positive polarity of the second gate voltage. That is, the decomposed oxygen vacancies 125 can move away from the region of the resistive switching layer 120 adjacent to the first surface LS120 and toward the region of the resistive switching layer 120 adjacent to the second surface US120.

[0048] In one embodiment, the decomposition of the conductive filament 10 generated by the reset voltage may occur more actively in the connecting filament 125c, which has a relatively low concentration of aggregated or bound oxygen vacancies 125. Therefore, the first trigger filament 125t1 and the second trigger filament 125t2, which have a relatively high concentration of aggregated or bound oxygen vacancies 125, may be retained for a longer duration in the pattern edge portions 150A and 160A of the first electrode pattern layer 150 and the second electrode pattern layer 160, compared to the bound oxygen vacancies 125 of the connecting filament 125c.

[0049] As described above, as at least a portion of the conductive filament 10 degrades, the resistance of the resistive layer 120 may increase. Therefore, when the conductive filament is disconnected, the internal resistance state of the resistive layer 120 may be changed from a low resistance state to a high resistance state. Even after the second gate voltage and the reset voltage are removed, the degree of disconnection of the conductive filament 10 is maintained, so that the resistive layer 120 can maintain a high resistance state.

[0050] According to the above-described embodiments of the present disclosure, when a set operation is performed on the nonvolatile memory device 1, a first trigger filament 125t1 and a second trigger filament 125t2 may be formed in the resistive switching layer 120 adjacent to the pattern edge portions 150A and 160A (which are electric field concentration portions). Then, a connecting filament 125c is formed to connect the first trigger filament 125t1 and the second trigger filament 125t2, so that a complete and connected conductive filament 10 may be formed. As a result, the density and distribution of the conductive filament 10 may be effectively limited by controlling the positions of the first trigger filament 125t1 and the second trigger filament 125t2. In addition, by stably forming the first trigger filament 125t1 and the second trigger filament 125t2 in the pattern edge portions 150A and 160A, a set operation error and a reset operation error of the nonvolatile memory device 1 may be prevented from occurring. That is, the connection state or disconnection state of the conductive filament 10 is structurally stable using the trigger filaments, so that the retention and durability of the signal information may be improved.

[0051] In other embodiments, the conductive filaments 10 of the nonvolatile memory device 1 may be formed with movable metal ions 125 distributed inside the resistive switching layer 120. As an embodiment, when the resistive switching layer 120 includes positive metal ions 125, the phenomenon of generating or disconnecting the conductive filaments in the resistive switching layer 120 may be respectively described in the above reference. Figures 2 to 4 The setting operation described above refers to Figure 5 The same operation as described for the reset operation is caused.

[0052] In another embodiment, when the resistive layer 120 includes negative metal ions 125, a first gate voltage including a bias voltage having a positive polarity may be applied to the gate electrode layer 140. Therefore, the negative metal ions 125 may move to the filament formation region of the resistive layer 120 adjacent to the first surface LS120. Subsequently, when the first gate voltage is applied, a set voltage may be applied between the first electrode pattern layer 150 and the second electrode pattern layer 160 to form a conductive filament in the resistive layer 120. The set voltage in this embodiment may have the same configuration as the above. Figure 4 In addition, when performing the reset process, a second gate voltage including a bias voltage having a negative polarity may be applied to the gate electrode layer 140. In addition, when applying the second gate voltage, a reset voltage may be applied between the first electrode pattern layer 150 and the second electrode pattern layer 160. Therefore, the reset voltage of this embodiment may have the same polarity as that of the above reference. Figure 5 The reset voltages of the described embodiments have different polarities. Therefore, the negative metal ions 125 decomposed from the conductive filaments by the reset voltage can be effectively discharged and moved away from the filament formation area.

[0053] Figure 6 is a cross-sectional view schematically showing a nonvolatile memory device according to a comparative example. Figure 6 , the nonvolatile memory device 1000 may include a first electrode layer 1100 and a second electrode layer 1200 facing each other along the z-direction. In addition, the nonvolatile memory device 1000 may include a resistive layer 1300 disposed between the first electrode layer 1100 and the second electrode layer 1200. Because the first electrode layer 1100 and the second electrode layer 1200 are disposed to face each other along the z-direction, when a set voltage is applied, a plurality of conductive filaments 1400 may be randomly grown between the resistive layer 1300 and the interface between the first electrode layer 1100 and the second electrode layer 1200. That is, in the case of the comparative example, it may be relatively difficult to control the density and distribution of the conductive filaments 1400. In contrast, in the embodiments of the present disclosure, as Figure 4As shown, the first electrode pattern layer 150 and the second electrode pattern layer 160 do not face each other and have a resistive switching layer therebetween. In addition, in the embodiment of the present disclosure, the first trigger filament 125t1 and the second trigger filament 125t2 formed in the pattern edge portions 150A and 160A can determine the starting position of the conductive filament 10. Therefore, the density and distribution of the conductive filament 10 can be effectively controlled.

[0054] Figure 7 is a cross-sectional view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure. Figure 7 , the nonvolatile memory device 2 may include: a substrate 101; a resistive layer 220 disposed on the substrate 101; a gate insulating layer 230 disposed on the resistive layer 220; a gate electrode layer 240 disposed on the gate insulating layer 230; and a first electrode pattern layer 250 and a second electrode pattern layer 260 disposed on the substrate 101 to contact different portions of the resistive layer 220. In addition, the nonvolatile memory device 2 may further include a device insulating layer 105, which electrically insulates the first electrode pattern layer 250 and the second electrode pattern layer 260 from the substrate 101. In addition, the nonvolatile memory device 2 may further include an interlayer insulating layer 110, which is disposed between the first electrode pattern layer 250 and the second electrode pattern layer 260 on the device insulating layer 105.

[0055] The device insulating layer 105 may be disposed on the substrate 101. The first electrode pattern layer 250 and the second electrode pattern layer 260 may be disposed on the device insulating layer 105 to be spaced apart from each other in the x direction. The first electrode pattern layer 250 and the second electrode pattern layer 260 may have edge portions 250A and 260A, respectively. The configurations of the first electrode pattern layer 250 and the second electrode pattern layer 260 and the edge portions 250A and 250B may be the same as those described above with reference to Figures 1 to 5 The configurations of the first and second electrode pattern layers 150 and 160 and the pattern edge portions 150A and 160A are substantially the same.

[0056] The interlayer insulating layer 110 may be disposed in a lateral direction from the first electrode pattern layer 250 and the second electrode pattern layer 260. The interlayer insulating layer 110 may electrically insulate the first electrode pattern layer 250 and the second electrode pattern layer 260. The interlayer insulating layer 110 may include an insulating material. The insulating material may be, for example, an oxide, a nitride, or an oxynitride. In one embodiment, the upper surfaces of the interlayer insulating layer 110 and the first electrode pattern layer 250 and the second electrode pattern layer 260 may be located at the same level on the z-axis.

[0057] The resistive layer 220 may be disposed on the first electrode pattern layer 250, the second electrode pattern layer 260 and the interlayer insulating layer 110. The resistive layer 220 may include a first surface LS220 and a second surface US220 opposite to the first surface LS220. The first surface LS220 of the resistive layer 220 may contact the first electrode pattern layer 250, the second electrode pattern layer 260 and the interlayer insulating layer 110. The resistive layer 220 may be configured as described above with reference to Figure 1 The structures of the resistive switching layers 120 of the non-volatile memory devices 1 are substantially the same.

[0058] The gate insulating layer 230 may be disposed on the second surface US220 of the resistive layer 220. The gate insulating layer 230 may be disposed in contact with the second surface US220. In addition to the structural configuration, the gate insulating layer 230 may be similar to the above reference Figure 1 The gate insulating layer 130 of the nonvolatile memory device 1 is the same. For example, the gate insulating layer 230 may have the same material as the gate insulating layer 130. In addition, the gate insulating layer 230 may have the same function as the gate insulating layer 130.

[0059] A gate electrode layer 240 may be provided on the gate insulating layer 230. The gate electrode layer 240 may be similar to the above-mentioned Figure 1 The gate electrode layer 140 of the nonvolatile memory device 1 described above is substantially the same. For example, the gate electrode layer 240 may have the same material as the gate electrode layer 140. In addition, the gate electrode layer 240 may have the same function as the gate electrode layer 140.

[0060] In the following, reference will be made to Figures 8 to 11 A method of operating the nonvolatile memory device 2 is described. Figures 8 to 10 2 is a diagram illustrating a setting operation of the nonvolatile memory device 2 according to one embodiment of the present disclosure. Fig.11 2 is a diagram illustrating a reset operation of the nonvolatile memory device 2 according to an embodiment of the present disclosure.

[0061] See also Figure 8 , can provide the above combination Figure 7 The nonvolatile memory device 2 described herein. The resistive switching layer 220 may have oxygen vacancies or movable metal ions 225. In one embodiment, the oxygen vacancies or movable metal ions 225 may be uniformly distributed inside the resistive switching layer 220. Hereinafter, as an example, the resistive switching layer 220 includes oxygen vacancies having a positive polarity. In another embodiment, when the resistive switching layer 220 includes the movable metal ions 125, substantially the same operating method may be applied.

[0062] See also Fig. 9, a first gate voltage including a bias voltage having a positive polarity may be applied to the gate electrode layer 240. By applying the first gate voltage, the oxygen vacancies 225 inside the resistive layer 220 may move to a filament formation region adjacent to the first surface LS220. The filament formation region may refer to an inner region of the resistive layer 220 adjacent to the interlayer insulating layer 110 and adjacent to the first gate electrode pattern layer 250 and the second gate electrode pattern layer 260.

[0063] According to one embodiment, the concentration or size of oxygen vacancies 225 moving to the filament formation region may be controlled by controlling the magnitude of the first gate voltage. The concentration of oxygen vacancies 225 may determine the diameter of the conductive filament formed in the operation described below.

[0064] See also Fig.10 When the first gate voltage is applied to the gate electrode layer 240 , a set voltage may be applied between the first electrode pattern layer 250 and the second electrode pattern layer 260 . As a result, a conductive filament 20 electrically connecting the first electrode pattern layer 250 and the second electrode pattern layer 260 may be formed in the resistive layer 220 .

[0065] In one embodiment, when a set voltage is applied, an electric field may be concentrated on the pattern edge portions 250A and 250B of the first electrode pattern layer 250 and the second electrode pattern layer 260, so that the first trigger filament 225t1 and the second trigger filament 225t2 may be formed in the filament formation region of the resistive layer 220 adjacent to the pattern edge portions 250A and 260A. The first trigger filament 225t1 and the second trigger filament 225t2 may be formed to contact the first electrode pattern layer 250 and the second electrode pattern layer 260. In addition, the connecting filament 225c may be grown from the first trigger filament 225t1 and the second trigger filament 225t2, respectively, and they may be combined with each other to form a continuous and connected conductive filament 20. By forming the conductive filament 20, the resistance of the resistive layer 220 may be reduced. Even after the first gate voltage and the set voltage are removed, the conductive filament 20 remains, so that the internal resistance state of the resistive layer 120 may be written and maintained in a low resistance state.

[0066] The method for forming the conductive filament 20 and the conductive filament 20 formed thereby can be the same as that described above with reference to Figures 2 to 4 The method of forming the conductive filaments 10 and the conductive filaments 10 formed thereby are substantially the same.

[0067] In addition, reference will be made to Fig.11The reset operation according to another embodiment of the present disclosure is described below. A second gate voltage having a negative bias voltage may be applied to the gate electrode layer 240. When the second gate voltage is applied, a reset voltage may be applied between the first electrode pattern layer 250 and the second electrode pattern layer 260. The reset voltage may have the same value as that in the above reference. Fig.10 The setting operation is described for different polarities of the setting voltage.

[0068] According to one embodiment, the oxygen vacancies 225 of the conductive filament 20 in the resistive layer 220 can be decomposed by the energy provided by the reset voltage. As an example, the energy can be electrical energy or heat energy generated by the electrical energy. In addition, the oxygen vacancies 225 obtained by the decomposition can be discharged from the filament formation region by the second gate voltage. As the oxygen vacancies 225 decompose, at least a portion of the conductive filament 20 can be disconnected. As a result, the resistance of the resistive layer 220 can be increased. Therefore, when the conductive filament is disconnected, the internal resistance state of the resistive layer 220 can be changed from a low resistance state to a high resistance state. Even after the second gate voltage and the reset voltage are removed, the disconnected state of the conductive filament 20 is written and maintained, so that the resistive layer 220 can maintain a high resistance state.

[0069] Fig.12 2 is a cross-sectional view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure. Fig.12 , the nonvolatile memory device 3 may include: a substrate 101, a resistive layer 320 disposed on the substrate 101; a gate insulating layer 330 disposed on the resistive layer 320; a gate electrode layer 340 disposed on the gate insulating layer 330; and a first electrode pattern layer 350 and a second electrode pattern layer 360, which are respectively disposed on the substrate 101 and are disposed to contact different portions of the resistive layer 320. In addition, the nonvolatile memory device 3 may further include a device insulating layer 105 to electrically insulate the first electrode pattern layer 350 and the second electrode pattern layer 360 from the substrate 101. In addition, the nonvolatile memory device 3 may further include an interlayer insulating layer 110 disposed between the first electrode pattern layer 350 and the second electrode pattern layer 360 on the device insulating layer 105.

[0070] The nonvolatile memory device 3 may have the same Figure 7 The nonvolatile memory device 2 described above has substantially the same configuration except for the resistive switching layer 320. That is, the gate insulating layer 330, the gate electrode layer 340, the first electrode pattern layer 350 and the second electrode pattern layer 360 may be constructed in the same manner as described above with reference to FIG. Figure 7 The gate insulating layer 230 , the gate electrode layer 240 , the first electrode pattern layer 250 and the second electrode pattern layer 260 are substantially the same.

[0071] In one embodiment, the resistive layer 320 may include a first resistive material layer 320a and a second resistive material layer 320b sequentially disposed on the first electrode pattern layer 350 and the second electrode pattern layer 360 and the interlayer insulating layer 110. The first resistive material layer 320a may contact the first electrode pattern layer 350 and the second electrode pattern layer 360 and the interlayer insulating layer 110, and the second resistive material layer 320b may contact the gate insulating layer 330.

[0072] The first resistive material layer 320a and the second resistive material layer 320b may include a variable resistive material, respectively. The variable resistive material may include oxygen vacancies or movable metal ions. The metal ions may be cations or anions. The variable resistive material may be composed of the above reference Figure 1 The variable resistance materials of the resistance switching layer 120 of the non-volatile memory device 1 are substantially the same.

[0073] The first resistance material layer 320a and the second resistance material layer 320b may include different variable resistance materials, respectively. Compared with the second resistance material layer 320b, the first resistance material layer 320a may have a lower oxygen vacancy concentration or a lower movable metal ion concentration. The first resistance material layer 320a may be a higher resistor than the second resistance material layer 320b. In addition, the first resistance material layer 320a may be thinner and have a smaller thickness than the second resistance material layer 320b.

[0074] Fig.13 and Fig.14 3 is a view illustrating a set operation and a reset operation of a nonvolatile memory device 3 according to an embodiment of the present disclosure. For ease of description, an example of implementing a resistive switching layer 320 provided with oxygen vacancies 325 having positive charges is used, but the embodiment is not limited thereto. In other embodiments, for example, the resistive switching layer 320 includes movable metal ions 325, and the movable metal ions 325 can be used in substantially the same manner as will be described below.

[0075] See also Fig.13 In the setting operation, a first gate voltage including a bias voltage having a positive polarity may be applied to the gate electrode layer 340. In addition, when the first gate voltage is applied to the gate electrode layer 340, a setting voltage may be applied between the first electrode pattern layer 350 and the second electrode pattern layer 360. Therefore, an electric field due to the setting voltage may be formed inside the resistive layer 320.

[0076] Here, the electric field generated by the set voltage may be concentrated on the pattern edge portions 350A and 360A of the first electrode pattern layer 350 and the second electrode pattern layer 360. In addition, since the first resistive material layer 320a is a higher resistor than the second resistive material layer 320b, when the set voltage is applied to the first resistive material layer 320a and the second resistive material layer 320b, a relatively large voltage may be applied to the first resistive material layer 320a. As a result, the first trigger filament 325t1 and the second trigger filament 325t2 may be formed in the first resistive material layer 320a adjacent to the pattern edge portions 350A and 360A, respectively.

[0077] The first trigger filament 325t1 and the second trigger filament 325t2 may be formed to contact the first electrode pattern layer 350 and the second electrode pattern layer 360. In addition, a connecting filament 325c connected to the first trigger filament 325t1 and the second trigger filament 325t2 may be formed in the second resistive material layer 320b. The connecting filament 325c may connect the first trigger filament 325t1 and the second trigger filament 325t2 to form a continuous and connected conductive filament 30.

[0078] See also Fig.14 , a second gate voltage including a bias voltage having a negative polarity may be applied to the gate electrode layer 340. In addition, when the second gate voltage is applied, a reset voltage may be applied between the first electrode pattern layer 350 and the second electrode pattern layer 360. The reset voltage may have a different polarity from the set voltage.

[0079] According to one embodiment, the oxygen vacancies 325 of the conductive filaments 30 in the resistive layer 320 can be decomposed by the Joule heat generated by the reset voltage. The decomposition of the oxygen vacancies 325 from the conductive filaments 30 can occur in the connecting filaments 325c of the second resistive material layer 320b at a relatively high frequency. In addition, due to the applied second gate voltage, the decomposed oxygen vacancies 325 can be discharged and moved away from the filament formation area. With the decomposition of the oxygen vacancies 325, at least a portion of the conductive filaments 30 may be disconnected. As a result, the resistance of the resistive layer 320 can be increased. Therefore, the internal resistance state of the resistive layer 320 can be changed from a low resistance state to a high resistance state.

[0080] Fig.15 is a cross-sectional view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure. Fig.15, the nonvolatile memory device 4 may include: a substrate 101; a resistive layer 420 disposed on the substrate 101; a gate insulating layer 430 disposed on the resistive layer 420; a gate electrode layer 440 disposed on the gate insulating layer 430; and a first electrode pattern layer 450 and a second electrode pattern layer 460, which are respectively disposed on the substrate 101 to contact different parts of the resistive layer 420. In addition, the nonvolatile memory device 4 may further include a device insulating layer 105, which is used to electrically insulate the first electrode pattern layer 450 and the second electrode pattern layer 460 from the substrate 101. In addition, the nonvolatile memory device 4 may further include an interlayer insulating layer 110, which is disposed between the first electrode pattern layer 450 and the second electrode pattern layer 460 on the device insulating layer 105.

[0081] The nonvolatile memory device 4 may have the same Fig.12 The nonvolatile memory device 3 is substantially the same in structure as described above, except for the resistive switching layer 420. That is, the gate insulating layer 430, the gate electrode layer 440, the first electrode pattern layer 450 and the second electrode pattern layer 460 can be constructed in the same manner as described above with reference to FIG. Fig.12 The gate insulating layer 330 , the gate electrode layer 340 , the first electrode pattern layer 350 and the second electrode pattern layer 360 are substantially the same.

[0082] In one embodiment, the resistive layer 420 may include a first resistive material layer 420a and a second resistive material layer 420b sequentially disposed on the first electrode pattern layer 450 and the second electrode pattern layer 460 and the interlayer insulating layer 110. The first resistive material layer 420a may contact the first electrode pattern layer 450 and the second electrode pattern layer 460 and the interlayer insulating layer 110, and the second resistive material layer 420b may contact the gate insulating layer 430.

[0083] The first resistive material layer 420a and the second resistive material layer 420b may each include a variable resistive material. The variable resistive material may include oxygen vacancies or movable metal ions 425. The metal ions may be cations or anions. The variable resistive material may be formed with the above reference Figure 1 The variable resistance materials of the resistance switching layer 120 of the non-volatile memory device 1 are substantially the same.

[0084] In one embodiment, each of the first resistive material layer 420a and the second resistive material layer 420b may include the same variable resistive material. Here, the first resistive material layer 420a may have a lower oxygen vacancy 425 concentration or a lower movable metal ion 425 concentration compared to the second resistive material layer 420b. Therefore, the first resistive material layer 420a may be a resistor having a higher resistance than the second resistive material layer 420b. In addition, the first resistive material layer 420a may be thinner and have a thickness smaller than that of the second resistive material layer 420b.

[0085] In a manufacturing method according to an embodiment, a first resistive material layer 420a and a second resistive material layer 420b may be formed on a first electrode pattern layer 450 and a second electrode pattern layer 460 and on an interlayer insulating layer 110 using the same source material. Here, a first resistive material layer 420a including an oxide having a high oxygen vacancy concentration may be formed by providing a relatively low oxygen concentration during the manufacturing process. Subsequently, a second resistive material layer 420b may be formed by increasing the concentration of injected oxygen during the manufacturing process, and the second resistive material layer 420b includes an oxide having a relatively low oxygen vacancy concentration. In some embodiments, the oxygen vacancies 425 inside the first resistive material layer 420a and the second resistive material layer 420b may be formed to have a concentration gradient. That is, the concentration of the oxygen vacancies 425 of the first resistive material layer 420a and the second resistive material layer 420b may be increased from the lower surface LS420 of the first resistive material layer 420a to the upper surface US420 of the second resistive material layer 420b.

[0086] In a manufacturing method according to another embodiment, the first resistive material layer 420a and the second resistive material layer 420b can be formed on the first electrode pattern layer 450 and the second electrode pattern layer 460 and the interlayer insulating layer 110 using the same source material. Here, a relatively low concentration of movable metal ions 425 can be injected to form the first resistive material layer 420a. Subsequently, the concentration of the movable metal ions 425 to be injected can be increased to form the second resistive material layer 420b. In some embodiments, the movable metal ions 425 inside the first resistive material layer 420a and the second resistive material layer 420b can be formed to have a concentration gradient. That is, the concentration of the movable metal ions 425 distributed inside the first resistive material layer 420a and the second resistive material layer 420b can be increased from the lower surface LS420 of the first resistive material layer 420a to the upper surface US420 of the second resistive material layer 420b.

[0087] Fig.16 and Fig.174 is a diagram illustrating a set operation and a reset operation of a nonvolatile memory device 4 according to an embodiment of the present disclosure. For ease of description, an example of a resistive switching layer 42 having positively charged oxygen vacancies 425 will be described as an embodiment, but the embodiment is not limited thereto. In other embodiments, for example, a resistive switching layer 420 including movable metal ions 425 may be used in substantially the same manner.

[0088] See also Fig.16 In the setting operation, a first gate voltage including a bias voltage having a positive polarity may be applied to the gate electrode layer 440. In addition, when the first gate voltage is applied to the gate electrode layer 440, a setting voltage may be applied between the first electrode pattern layer 450 and the second electrode pattern layer 460.

[0089] Here, the electric field generated by the set voltage may be concentrated on the pattern edge portions 450A and 460A of the first electrode pattern layer 450 and the second electrode pattern layer 460, respectively. In addition, since the first resistive material layer 420a is a resistor having a higher resistance than the second resistive material layer 420b, when the set voltage is applied to the first resistive material layer 420a and the second resistive material layer 420b, a relatively high voltage may be applied to the first resistive material layer 420a. As a result, the first trigger filament 425t1 and the second trigger filament 425t2 may be formed in the first resistive material layer 420a adjacent to the pattern edge portions 450A and 460A, respectively.

[0090] Subsequently, a connecting filament 425c connected to the first trigger filament 425t1 and the second trigger filament 425t2 may be formed in the second resistive material layer 420b. The connecting filament 425c connects the first trigger filament 425t1 and the second trigger filament 425t2 to form a continuous and connected conductive filament 40.

[0091] See also Fig.17 , a second gate voltage including a bias voltage having a negative polarity may be applied to the gate electrode layer 440. In addition, when the second gate voltage is applied, a reset voltage may be applied between the first electrode pattern layer 450 and the second electrode pattern layer 460. The reset voltage may have a different polarity from the set voltage.

[0092] According to one embodiment, the oxygen vacancies 425 of the conductive filaments 40 in the resistive layer 420 can be decomposed by the Joule heat generated by the reset voltage. The decomposition of the oxygen vacancies 425 from the conductive filaments 40 can occur in the connecting filaments 425c of the second resistive material layer 420b at a relatively high frequency. In addition, by applying a second gate voltage, the decomposed oxygen vacancies 425 can be discharged and moved away from the filament formation area. As the oxygen vacancies 425 decompose, at least a portion of the conductive filaments 40 can be disconnected. As a result, the resistance of the resistive layer 420 can be increased. Therefore, the internal resistance state of the resistive layer 420 can be changed from a low resistance state to a high resistance state and stored in the memory cell.

[0093] In other embodiments, the above reference Fig.12 The resistive switching layer 320 and the above reference Fig.15 The structure of the resistive switching layer 420 can be applied to the above reference Figure 1 The resistive switching layer 120. That is, the resistive switching layer 120 may include a first resistive material layer in contact with the first electrode pattern layer 150, the second electrode pattern layer 160 and the gate insulating layer 130, and a second resistive material layer disposed on the first resistive material layer. Compared with the second resistive material layer, the first resistive material layer may be a resistor with a higher resistance. Therefore, a trigger filament may be formed in the first resistive material layer, and a connecting filament may be formed in the second resistive material layer.

[0094] The embodiments of the inventive concept have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept disclosed in the accompanying claims.

Claims

1. A nonvolatile memory device, comprising: substrate; A resistive switching layer, which is arranged on the substrate; A gate insulating layer, which is disposed on the resistive switching layer; a gate electrode layer, disposed on the gate insulating layer; as well as A first electrode pattern layer and a second electrode pattern layer, which are respectively disposed on the substrate and are disposed to contact different portions of the resistive switching layer, The resistive layer includes a first resistive material layer in contact with the first electrode pattern layer and the second electrode pattern layer, and a second resistive material layer disposed on the first resistive material layer. wherein the first resistive material layer has a lower concentration of oxygen vacancies or a lower concentration of mobile metal ions than the second resistive material layer, Wherein, the resistive switching layer includes conductive filaments. Wherein, the conductive filaments include: a first trigger filament and a second trigger filament, wherein the first trigger filament and the second trigger filament are disposed in the first resistance material layer, are separated from each other, and are in contact with the first electrode pattern layer and the second electrode pattern layer, respectively; A connecting filament is disposed in the second resistance material layer and connects the first trigger filament and the second trigger filament to each other in a transverse direction. 2 . The nonvolatile memory device according to claim 1 , wherein the conductive filament is formed in the resistive switching layer when a set voltage is applied to electrically connect the first electrode pattern layer and the second electrode pattern layer.

3. The nonvolatile memory device according to claim 2, wherein: The first trigger filament and the second trigger filament are disposed adjacent to respective edge portions of the first electrode pattern layer and the second electrode pattern layer.

4. The nonvolatile memory device according to claim 1, wherein: The resistive layer has a first surface and a second surface opposite to the first surface, and Wherein, the gate insulation layer and the first electrode pattern layer and the second electrode pattern layer are arranged to contact the first surface.

5. The nonvolatile memory device according to claim 1, wherein: The resistive layer has a first surface and a second surface opposite to the first surface. Wherein, the gate insulating layer is arranged to contact the first surface, and Wherein, the first electrode pattern layer and the second electrode pattern layer are arranged to contact the second surface.

6. The nonvolatile memory device according to claim 1, wherein: Each of the first resistive material layer and the second resistive material layer includes substantially the same variable resistive material.

7. The nonvolatile memory device according to claim 1, wherein: The first resistive material layer has a higher resistance than the second resistive material layer.

8. A non-volatile memory device, comprising: substrate; A gate electrode layer disposed on the substrate; a gate insulating layer disposed on the substrate and arranged to surround the gate electrode layer; a first electrode pattern layer and a second electrode pattern layer disposed on the substrate and respectively disposed on opposite sides of the gate electrode layer; and a resistive switching layer, which is disposed on the gate insulating layer and on the first electrode pattern layer and the second electrode pattern layer, Wherein, the resistive switching layer includes oxygen vacancies and movable metal ions. The resistive layer includes a first resistive material layer in contact with the first electrode pattern layer and the second electrode pattern layer, and a second resistive material layer disposed on the first resistive material layer. wherein the first resistive material layer has a lower concentration of oxygen vacancies or a lower concentration of mobile metal ions than the second resistive material layer, Wherein, the resistive switching layer includes conductive filaments. Wherein, the conductive filaments include: a first trigger filament and a second trigger filament, wherein the first trigger filament and the second trigger filament are disposed in the first resistance material layer, are separated from each other, and are in contact with the first electrode pattern layer and the second electrode pattern layer, respectively; A connecting filament is disposed in the second resistance material layer and connects the first trigger filament and the second trigger filament to each other in a transverse direction.

9. The nonvolatile memory device according to claim 8, wherein: The resistive layer is configured to contact the gate insulating layer and the first electrode pattern layer and the second electrode pattern layer, and Wherein, the first electrode pattern layer and the second electrode pattern layer are arranged to contact the gate insulating layer on opposite sides of the gate electrode layer. 10 . The nonvolatile memory device according to claim 8 , wherein the conductive filament is formed in the resistive switching layer when a set voltage is applied to electrically connect the first electrode pattern layer and the second electrode pattern layer to each other.

11. The nonvolatile memory device according to claim 10, wherein: The first trigger filament and the second trigger filament are disposed adjacent to respective edge portions of the first electrode pattern layer and the second electrode pattern layer.

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