A low trigger voltage scr device and a method for manufacturing the same

Abstract

The application discloses a low-trigger-voltage SCR device and a preparation method thereof, and belongs to the field of semiconductor protection devices, and comprises the following steps: forming an epitaxial layer on the surface of a substrate; sequentially forming P-type doped regions, N-type doped regions, P-type doped regions and N-type doped regions in the epitaxial layer; respectively forming a first N-type injection region, a second N-type injection region, a third N-type injection region, a first P-type injection region, a second P-type injection region, a fourth N-type injection region, a third P-type injection region, a fifth N-type injection region and a fourth P-type injection region, and the second P-type injection region is coupled with the first N-type doped region and the second P-type doped region; forming an isolation structure in the epitaxial layer; depositing a dielectric layer on the surface of the epitaxial layer, and respectively forming contact holes corresponding to each injection region; depositing metal in the contact holes, and forming metal wires. The technical scheme has the beneficial effects of low trigger voltage, strong electrostatic discharge capacity, high stability and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor protection devices, specifically to an electrostatic discharge protection device, and more particularly to a low-trigger-voltage SCR device and its fabrication method. Background Technology

[0002] Silicon controlled rectifiers (SCRs) are widely used in power devices. Because they can switch between high and low resistance states, they can be used as power switches. They are also commonly used for electrostatic discharge (ESD) protection, possessing excellent static discharge capabilities. Compared to diodes, transistors, and field-effect transistors, their positive feedback mechanism gives SCRs advantages such as strong current discharge capability, high discharge efficiency per unit area, low on-resistance, strong robustness, and high protection levels. This allows for high ESD protection levels to be achieved with a relatively small chip area on a semiconductor planar process.

[0003] The trigger voltage refers to the minimum voltage required for a silicon controlled rectifier (SCR) device to turn on. Generally, ordinary SCR devices have relatively high trigger voltages, which may exceed the voltage limit of circuits operating at lower voltages. Therefore, for circuits operating at lower voltages, to protect them from damage before the SCR turns on and discharges current, SCR devices with the lowest possible trigger voltage should be used. Thus, there is an urgent need to design a low-trigger-voltage SCR device and its fabrication method to meet practical application requirements. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, a low-trigger-voltage SCR device and its fabrication method are provided, which has a low trigger voltage, strong electrostatic discharge capability, and good stability and reliability.

[0005] The technical problem solved by this invention can be achieved by the following technical solutions:

[0006] This invention provides a low-trigger-voltage SCR device, comprising:

[0007] A substrate;

[0008] An epitaxial layer is formed on the upper surface of the substrate, the epitaxial layer comprising:

[0009] A first P-type doped region, wherein the first P-type doped region includes a first N-type implantation region and a second N-type implantation region;

[0010] A first N-type doped region, wherein the first N-type doped region includes a third N-type implantation region and a first P-type implantation region;

[0011] A second P-type doped region, wherein the second P-type doped region includes a fourth N-type implantation region and a third P-type implantation region;

[0012] The second N-type doped region includes a fifth N-type implantation region and a fourth P-type implantation region;

[0013] The second P-type implantation region is coupled to the first N-type doped region and the second P-type doped region;

[0014] An isolation structure is provided, which extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer to the substrate, wherein the first P-type doped region is isolated by the isolation structure.

[0015] A dielectric layer is formed on the upper surface of the epitaxial layer;

[0016] Multiple metal layers are formed above each N-type implantation region and each P-type implantation region, respectively;

[0017] Multiple metal wires are used to connect and lead out the first N-type injection region, the third N-type injection region, the first P-type injection region, the fifth N-type injection region, and the fourth P-type injection region to serve as the anode of the device; the fourth N-type injection region and the third P-type injection region are connected and led out to serve as the cathode of the device; and the second N-type injection region and the second P-type injection region are connected.

[0018] Preferably, the resistivity of the epitaxial layer is greater than the resistivity of the substrate.

[0019] Preferably, the implanted element in the first P-type doped region is boron, the ion implantation dose is 5E12 to 5E13 per square centimeter, and the implantation energy is 60 to 100 keV;

[0020] The implanted element in the second P-type doped region is boron, with an ion implantation dose of 5E14 to 8E14 per square centimeter and an implantation energy of 40 to 60 keV;

[0021] The implanted element in the first N-type doped region and the second N-type doped region is phosphorus, the ion implantation dose is 5E13 to 1E14 per square centimeter, and the implantation energy is 60 to 80 keV.

[0022] Preferably, the implanted element in each of the N-type implantation regions is phosphorus or arsenic, the ion implantation dose is 1E15 to 1E16 per square centimeter, the implantation energy is 80 to 100 keV, and thermal annealing is performed after ion implantation at a temperature of 850°C to 950°C for 30 to 60 minutes.

[0023] Preferably, the distance between the fourth N-type implantation region and the first N-type doped region, and the distance between the fourth N-type implantation region and the second N-type doped region, do not exceed 6 μm.

[0024] Preferably, the distance between the first N-type injection region and the second N-type injection region does not exceed 5 μm.

[0025] Preferably, the implanted element in each P-type implantation region is boron or boron difluoride, the ion implantation dose is 1E15 to 1E16 per square centimeter, the implantation energy is 40 to 80 keV, and thermal annealing is performed after ion implantation at a temperature of 950 to 1050°C for 10 to 30 seconds.

[0026] Preferably, the distance between the P-type injection regions is not less than 2 μm.

[0027] The present invention also provides a method for fabricating a low-trigger-voltage SCR device, for fabricating the low-trigger-voltage SCR device as described above, comprising:

[0028] Step S1: Provide a substrate and grow an epitaxial layer on the surface of the substrate;

[0029] Step S2: A first P-type doped region, a first N-type doped region, a second P-type doped region, and a second N-type doped region are sequentially formed in the epitaxial layer;

[0030] Step S3: A first N-type implantation region and a second N-type implantation region are formed in the first P-type doped region, a third N-type implantation region is formed in the first N-type doped region, a fourth N-type implantation region is formed in the second P-type doped region, and a fifth N-type implantation region is formed in the second N-type doped region.

[0031] Step S4: A first P-type implantation region is formed in the first N-type doped region, a second P-type implantation region is formed in the epitaxial layer, a third P-type implantation region is formed in the second P-type doped region, and a fourth P-type implantation region is formed in the second N-type doped region, wherein the second P-type implantation region is coupled to the first N-type doped region and the second P-type doped region.

[0032] Step S5: An isolation structure is formed in the epitaxial layer, and the isolation structure extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer to the substrate, wherein the first P-type doped region is isolated by the isolation structure.

[0033] Step S6A: A dielectric layer is deposited on the upper surface of the epitaxial layer, and corresponding contact holes are formed above each N-type injection region and P-type injection region.

[0034] In step S7A, metal deposition is performed in each of the contact holes to form metal interconnects, so that the first N-type injection region, the third N-type injection region, the first P-type injection region, the fifth N-type injection region, and the fourth P-type injection region are connected and led out as the anode of the device, the fourth N-type injection region and the third P-type injection region are connected and led out as the cathode of the device, and the second N-type injection region and the second P-type injection region are connected.

[0035] The present invention also provides a method for fabricating a low-trigger-voltage SCR device, for fabricating the low-trigger-voltage SCR device as described above, comprising:

[0036] Step S1: Provide a substrate and grow an epitaxial layer on the surface of the substrate;

[0037] Step S2: A first P-type doped region, a first N-type doped region, a second P-type doped region, and a second N-type doped region are sequentially formed in the epitaxial layer;

[0038] Step S3: A first N-type implantation region and a second N-type implantation region are formed in the first P-type doped region, a third N-type implantation region is formed in the first N-type doped region, a fourth N-type implantation region is formed in the second P-type doped region, and a fifth N-type implantation region is formed in the second N-type doped region.

[0039] Step S4: A first P-type implantation region is formed in the first N-type doped region, a second P-type implantation region is formed in the epitaxial layer, a third P-type implantation region is formed in the second P-type doped region, and a fourth P-type implantation region is formed in the second N-type doped region, wherein the second P-type implantation region is coupled to the first N-type doped region and the second P-type doped region.

[0040] Step S5: An isolation structure is formed in the epitaxial layer, and the isolation structure extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer to the substrate, wherein the first P-type doped region is isolated by the isolation structure.

[0041] Step S6B: A dielectric layer is deposited on the upper surface of the epitaxial layer, and a polysilicon layer is formed in the dielectric layer. The polysilicon layer is located between the second N-type implantation region and the third N-type implantation region, and corresponding contact holes are formed above each N-type implantation region and P-type implantation region, as well as at both ends of the polysilicon layer.

[0042] In step S7B, metal deposition is performed in each of the contact holes to form metal interconnects, so that the first N-type implantation region, the third N-type implantation region, the first P-type implantation region, the fifth N-type implantation region, and the fourth P-type implantation region are connected and led out as the anode of the device, the fourth N-type implantation region and the third P-type implantation region are connected and led out as the cathode of the device, and the second N-type implantation region, the polysilicon layer, and the second P-type implantation region are connected.

[0043] The beneficial effects of the technical solution of this invention are as follows:

[0044] The SCR device provided by this invention has a low trigger voltage, strong ESD discharge capability, good stability and high reliability; multiple parallel conduction paths can release current simultaneously, which is beneficial for evenly distributing ESD events and enhancing the electrostatic discharge capability. Attached Figure Description

[0045] Figure 1 This is a schematic flowchart of a method for fabricating a low-trigger-voltage SCR device according to the present invention.

[0046] Figure 2 This is a schematic diagram of step S1 in the fabrication method of a low-trigger-voltage SCR device according to the present invention;

[0047] Figure 3 This is a schematic diagram of step S2 in the fabrication method of a low-trigger-voltage SCR device in this invention;

[0048] Figure 4 This is a schematic diagram of step S3 in the fabrication method of a low-trigger-voltage SCR device in this invention;

[0049] Figure 5 This is a schematic diagram of step S4 in the fabrication method of a low-trigger-voltage SCR device in this invention.

[0050] Figure 6 This is a schematic diagram of step S5 in the fabrication method of a low-trigger-voltage SCR device in this invention;

[0051] Figure 7 This is a schematic diagram of step S6A of the method for fabricating a low-trigger-voltage SCR device in this invention;

[0052] Figure 8 This is a schematic diagram of a specific embodiment of the low-trigger-voltage SCR device prepared in this invention;

[0053] Figure 9 This is an equivalent circuit diagram of a specific embodiment of a low-trigger-voltage SCR device in this invention;

[0054] Figure 10 This is a schematic flowchart of a specific embodiment two of the fabrication method of a low trigger voltage SCR device in this invention;

[0055] Figure 11 This is a schematic diagram of a specific embodiment of the low-trigger-voltage SCR device prepared in this invention.

[0056] Figure 12 This is an equivalent circuit diagram of a specific embodiment two of the SCR device with low trigger voltage in this invention.

[0057] Figure label:

[0058] 01. Anode; 02. Cathode; 1. Substrate; 2. Epitaxial layer; 31. First P-type doped region; 32. Second P-type doped region; 41. First N-type doped region; 42. Second N-type doped region; 51. First N-type implanted region; 52. Second N-type implanted region; 53. Third N-type implanted region; 54. Fourth N-type implanted region; 55. Fifth N-type implanted region; 61. First P-type implanted region; 62. Second P-type implanted region; 63. Third P-type implanted region; 64. Fourth P-type implanted region; 7. Isolation structure; 8. Dielectric layer; 81. Contact hole; 9. Metal; 10. Polysilicon layer; Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0061] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0062] Example 1:

[0063] This invention provides an SCR device with a low trigger voltage, such as... Figure 8 As shown, it includes:

[0064] Substrate 1;

[0065] An epitaxial layer 2 is formed on the upper surface of the substrate 1, and the epitaxial layer 2 includes:

[0066] A first P-type doped region 31, which includes a first N-type implantation region 51 and a second N-type implantation region 52;

[0067] A first N-type doped region 41, which includes a third N-type implantation region 53 and a first P-type implantation region 61;

[0068] A second P-type doped region 32, which includes a fourth N-type implantation region 54 and a third P-type implantation region 63;

[0069] The second N-type doped region 42 includes a fifth N-type implantation region 55 and a fourth P-type implantation region 64.

[0070] The second P-type implantation region 62 is coupled to the first N-type doped region 41 and the second P-type doped region 32.

[0071] The isolation structure 7 extends longitudinally from the upper surface of the epitaxial layer 2 through the epitaxial layer into the substrate 1, and the first P-type doped region 31 is isolated by the isolation structure 7.

[0072] A dielectric layer 8 is formed on the upper surface of the epitaxial layer 2;

[0073] Multiple metal layers 9 are formed above each N-type implantation region and P-type implantation region, respectively;

[0074] Multiple metal wires are used to connect and lead out the first N-type injection region 51, the third N-type injection region 53, the first P-type injection region 61, the fifth N-type injection region 55 and the fourth P-type injection region 64 as the anode of the device, the fourth N-type injection region 54 and the third P-type injection region 63 are connected and led out as the cathode of the device, and the second N-type injection region 52 and the second P-type injection region 62 are connected.

[0075] Example 2:

[0076] This invention provides a method for fabricating a low-trigger-voltage SCR device, belonging to the field of semiconductor protection devices, such as... Figure 1 As shown, the specific steps include the following:

[0077] Step S1, as follows Figure 2 As shown, a substrate 1N-sub of a first conductivity type is provided, and an epitaxial layer 2P-epi of a second conductivity type is grown on the surface of the substrate 1.

[0078] Wherein, the first conductivity type is N-type or P-type, that is, if the conductivity type of substrate 1 is N-type, then the conductivity type of epitaxial layer 2 is P-type; if the conductivity type of substrate 1 is P-type, then the conductivity type of epitaxial layer 2 is N-type. In this invention, N-type substrate 1 and P-type epitaxial layer 2 are used as an example.

[0079] In step S1, firstly, an N-type silicon wafer is selected as substrate 1. In a specific embodiment, substrate 1 is made of a high-resistivity material. Preferably, in this embodiment, the resistivity of the material used for substrate 1 is [0.1Ω*cm, 1Ω*cm].

[0080] A P-type epitaxial layer 2 is grown on the surface of substrate 1 using a high-temperature epitaxial process. The thickness of epitaxial layer 2 is [10μm, 15μm]. The resistivity of epitaxial layer 2 is greater than that of substrate 1. In this embodiment, the resistivity of epitaxial layer 2 is [50Ω*cm, 100Ω*cm]. Using epitaxial layer 2 with high resistivity can help reduce the capacitance of the device and can be applied to high-speed signal ports.

[0081] Step S2, as follows Figure 3 As shown, a first P-type doped region 31PW1, a first N-type doped region 41NW1, a second P-type doped region 32, and a second N-type doped region 42 are sequentially formed in the epitaxial layer 2.

[0082] In step S2, a first P-type doped region 31 is defined using photolithography, followed by ion implantation; a second P-type doped region 32 is then defined using photolithography, followed by another ion implantation; finally, a first N-type doped region 41 and a second N-type doped region 42 are defined using photolithography, followed by another ion implantation. After ion implantation, the regions are placed in a furnace tube and subjected to a high-temperature propulsion process, causing the first P-type doped region 31PW1, the first N-type doped region 41NW1, the second P-type doped region 32, and the second N-type doped region 42 to diffuse to a certain junction depth. Preferably, the junction depth of the second P-type doped region 32 is less than the junction depth of the second N-type doped region 42, and the second P-type doped region 32 is adjacent to the second N-type doped region 42.

[0083] Furthermore, the first P-type doped region 31, the first N-type doped region 41, the second P-type doped region 32, and the second N-type doped region 42 are well regions formed sequentially in the P-type epitaxial layer 2, that is, the first P-type doped region 31 and the second P-type doped region 32 are P-type well regions formed in the epitaxial layer 2, and the first N-type doped region 41 and the second N-type doped region 42 are N-type well regions formed in the epitaxial layer 2.

[0084] In a preferred embodiment, the implanted element of the first P-type doped region 31 is boron, the ion implantation dose is 5E12 to 5E13 per square centimeter, and the implantation energy is 60 to 100 keV.

[0085] Preferably, the implanted element in the second P-type doped region 32 is boron, the ion implantation dose is 5E14 to 8E14 per square centimeter, and the implantation energy is 40 to 60 keV;

[0086] Preferably, the implanted element in the first N-type doped region 41 and the second N-type doped region 42 is phosphorus, the ion implantation dose is 5E13 to 1E14 per square centimeter, and the implantation energy is 60 to 80 keV.

[0087] Furthermore, after ion implantation, a high-temperature drive-up process is used to achieve a junction depth of 2–6 μm for the first P-type doped region 31, the second P-type doped region 32, the first N-type doped region 41, and the second N-type doped region 42. The drive-up temperature is 1050°C–1150°C, and the drive-up time is 30–120 minutes. Preferably, multiple high-temperature drive-ups can be performed according to the product requirements of the fabricated low-trigger-voltage SCR device.

[0088] Step S3, as follows Figure 4 As shown, a first N-type implantation region 51 and a second N-type implantation region 52 are formed in the first P-type doped region 31, a third N-type implantation region 53 is formed in the first N-type doped region 41, a fourth N-type implantation region 54 is formed in the second P-type doped region 32, and a fifth N-type implantation region 55 is formed in the second N-type doped region 42.

[0089] In step S3, N+ selective implantation is performed on the surface of the doped region using photolithography and ion implantation processes to form an implantation region. Then, the region is annealed in a furnace tube to repair implantation damage.

[0090] In a preferred embodiment, the implanted element in each N-type implantation region is phosphorus or arsenic, the ion implantation dose is 1E15 to 1E16 per square centimeter, the implantation energy is 80 to 100 keV, and rapid thermal annealing is performed after ion implantation at a temperature of 850°C to 950°C for 30 to 60 minutes.

[0091] In a preferred embodiment, the distance between the fourth N-type implantation region 54 formed in the second P-type doped region 32 and the first N-type doped region 41 does not exceed 6 μm. Similarly, preferably, the distance between the fourth N-type implantation region 54 and the second N-type doped region 42 also does not exceed 6 μm.

[0092] In a preferred embodiment, the distance between the two N-type implantation regions formed in the first P-type doped region 31 does not exceed 5 μm, that is, the distance between the first N-type implantation region 51 and the second N-type implantation region 52 does not exceed 5 μm.

[0093] Step S4, as follows Figure 5 As shown, a first P-type implantation region 61 is formed in the first N-type doped region 41, a second P-type implantation region 62 is formed in the epitaxial layer 2, a third P-type implantation region 63 is formed in the second P-type doped region 32, and a fourth P-type implantation region 64 is formed in the second N-type doped region 42, wherein the second P-type implantation region 62 is coupled to the first N-type doped region 41 and the second P-type doped region 32;

[0094] In step S4, P+ selective implantation is performed on the surface of the doped region to form an implantation region through photolithography and ion implantation processes, followed by rapid thermal annealing to repair implantation damage.

[0095] In a preferred embodiment, the implanted element in each P-type implantation region is boron or boron difluoride, the ion implantation dose is 1E15 to 1E16 per square centimeter, the implantation energy is 40 to 80 keV, and rapid thermal annealing is performed after ion implantation at a temperature of 950 to 1050°C for 10 to 30 seconds.

[0096] In a preferred embodiment, the injection region at the junction of the first N-type doped region 41 and the second P-type doped region 32, namely the second P-type injection region 62, serves as the access point for the injection current.

[0097] In a preferred embodiment, the distance between each P-type injection region is not less than 2 μm.

[0098] Step S5, as follows Figure 6 As shown, an isolation structure 7 is formed in the epitaxial layer 2, and the isolation structure 7 extends longitudinally from the upper surface of the epitaxial layer 2 through the epitaxial layer 2 into the substrate 1, and the first P-type doped region 31 is isolated by the isolation structure 7.

[0099] In step S5, a deep trench is etched in the epitaxial layer 2 and filled with a dielectric to form an isolation structure 7. The isolation structure 7 is a deep trench isolation (DTI). The DTI extends vertically through the epitaxial layer 2 to the substrate 1. The formed deep trench isolation can improve the device integration density.

[0100] Step S6A, as follows Figure 7 As shown, a dielectric layer 8 is deposited on the upper surface of the epitaxial layer 2, and corresponding contact holes 81 are formed above each N-type injection region and P-type injection region, respectively.

[0101] In a preferred embodiment, a dielectric layer 8 is formed by dielectric deposition on the upper surface of the device prepared in step S5. The dielectric layer 8 can be an oxide layer, a borosilicate glass, or a multilayer insulating film composite layer. Subsequently, a plurality of contact holes 81 are formed by photolithography and etching processes. Each contact hole 81 corresponds to each injection region and is located on the upper surface of each injection region.

[0102] Step S7A, as follows Figure 8As shown, metal 9 is deposited in each contact hole 81 on the above surface, and then metal interconnects are formed by photolithography and metal etching, so that the first N-type injection region 51, the third N-type injection region 53, the first P-type injection region 61, the fifth N-type injection region 55 and the fourth P-type injection region 64 are connected and led out as the anode 01 of the device, the fourth N-type injection region 54 and the third P-type injection region 63 are connected and led out as the cathode 02 of the device, and the second N-type injection region 52 and the second P-type injection region 62 are connected.

[0103] Example 3:

[0104] This embodiment is the equivalent circuit of Embodiment 2, such as... Figure 9 As shown, it includes:

[0105] A diode D1 has its anode connected to a first port and its cathode connected to a second port, wherein the first port is the anode O1 of the device and the second port is the cathode O2 of the device.

[0106] A first transistor Q1, the emitter of the first transistor Q1 is connected to the first port, and the base of the first transistor Q1 is connected to the first port through a first resistor R-Nw;

[0107] A second transistor Q2 is connected to the collector of the first transistor Q1, the collector of the second transistor Q2 is connected to the base of the first transistor Q1, and the emitter of the second transistor Q2 is connected to the second port.

[0108] A transient diode (TVS) includes a first electrode and a second electrode. The first electrode is connected to a first port, and the second electrode is directly connected to the base of the second transistor (TVS).

[0109] First, an N-type silicon wafer is selected as substrate 1. In a specific embodiment, substrate 1 is made of a high-resistivity material. Preferably, in this embodiment, the resistivity of the material used for substrate 1 is [0.1Ω*cm, 1Ω*cm].

[0110] A P-type epitaxial layer 2 is grown on the surface of substrate 1 using a high-temperature epitaxial process. The thickness of epitaxial layer 2 is [10μm, 15μm]. The resistivity of epitaxial layer 2 is greater than that of substrate 1. In this embodiment, the resistivity of epitaxial layer 2 is [50Ω*cm, 100Ω*cm]. Using epitaxial layer 2 with high resistivity can help reduce the capacitance of the device and can be applied to high-speed signal ports.

[0111] Then, diode D1, first transistor Q1, second transistor Q2, transient diode TVS, and first resistor R-Nw are formed in epitaxial layer 2.

[0112] In a preferred embodiment, the first transistor Q1 is a PNP transistor, formed by the first N-type doped region 41, the third N-type injection region 53, the first P-type injection region 61, and the second P-type injection region 62; the second transistor Q2 is an NPN transistor, formed by the first N-type doped region 41, the third N-type injection region 53, the second P-type injection region 62, the second P-type doped region 32, and the fourth N-type injection region 54; the transient diode TVS is a low avalanche breakdown or punch-through breakdown base floating transistor formed by the first N-type injection region 51, the first P-type doped region 31, and the second N-type injection region 52; the first resistor R-Nw is the parasitic resistance of the second N-type doped region 42; and the diode D1 is a diode formed by the second P-type doped region 32 and the second N-type doped region 42.

[0113] In this embodiment, the first P-type doped region 31 has a high doping concentration, and the breakdown voltage of the TVS formed between the first N-type implanted region 51 and the second N-type implanted region 52 inside it is much smaller than the breakdown voltage of NW1 / P+. The breakdown voltage of the first P-type doped region 31 is within 5V; while the second P-type doped region 32, the first N-type doped region 41, and the second N-type doped region 42 have low doping concentrations, and their breakdown voltages are generally above 20V.

[0114] When the anode 01 of the thyristor device encounters an electrostatic discharge (ESD) event, the voltage rises instantaneously, and the transient diode TVS breaks down first. The current reaches the second P-type injection region 62 at the junction of the first N-type doped region 41 and the second P-type doped region 32, which is the entry point of the injected current. The current flows through the second P-type injection region 62, the second P-type doped region 32, and the third P-type injection region 63 to reach the cathode 02. The ESD voltage continues to increase, and the current flows to the cathode 02 through R_PW1. Since the second P-type doped region 32 has a low doping concentration, its parasitic resistance is relatively large. Even a small current passing through the parasitic resistance of the second P-type doped region 32 can make the voltage difference across it reach more than 0.7V, that is, the emitter junction (first P-type doped region and N+ injection region) of the second transistor Q2 is forward biased. Since the collector junction of the second transistor Q2 is itself in a reverse biased state, the second transistor Q2 is turned on. After the second transistor Q2 is turned on, a base current is generated, that is, the current is generated at the junction of the first N-type doped region 41, the second P-type injection region 62, the fourth N-type injection region 54, and the second P-type doped region 32. The current path is from the first N-type doped region 41, the second P-type injection region 62, the second P-type doped region 32 to the fourth N-type injection region 54. After that, the first transistor Q1 will also be turned on. The SCR device of the present invention enters positive feedback and is in a high negative resistance conduction state, thereby effectively protecting the subsequent circuit.

[0115] In a preferred embodiment, the trigger voltage of the thyristor device is mainly determined by the breakdown voltage of the transient diode TVS. Since the first P-type doped region 31 has a very high doping concentration and the N+ implanted region also has a very high doping concentration, the breakdown voltage of the PN junction between the first N-type implanted region 51, the first P-type doped region 31, and the second N-type implanted region 52 is very low. By precisely controlling the doping concentration through ion implantation, the breakdown voltage can be controlled within 5V. Therefore, the thyristor device has an extremely low trigger voltage, which can protect more circuits with lower operating voltages.

[0116] In a preferred embodiment, when the anode 01 of the thyristor device encounters a negative surge, the negative surge can reach the cathode 02 through the diode D1, thereby releasing the negative surge.

[0117] As a preferred embodiment, the thyristor device adopts a repeating unit structure with multiple conduction paths in parallel, which can release current simultaneously and is conducive to the uniform distribution of ESD events. Therefore, it has strong ESD discharge capability, excellent stability and high reliability.

[0118] Example 4:

[0119] This invention also provides a method for fabricating an SCR device with a low trigger voltage, such as... Figure 10 As shown, it includes:

[0120] Step S1, as follows Figure 2 As shown, a substrate 1 of a first conductivity type is provided, and an epitaxial layer 2 of a second conductivity type is grown on the surface of the substrate 1;

[0121] Step S2, as follows Figure 3 As shown, a first P-type doped region 31, a first N-type doped region 41, a second P-type doped region 32, and a second N-type doped region 42 are sequentially formed in the epitaxial layer 2.

[0122] Step S3, as follows Figure 4 As shown, a first N-type implantation region 51 and a second N-type implantation region 52 are formed in the first P-type doped region 31, a third N-type implantation region 53 is formed in the first N-type doped region 41, a fourth N-type implantation region 54 is formed in the second P-type doped region 32, and a fifth N-type implantation region 55 is formed in the second N-type doped region 42.

[0123] Step S4, as follows Figure 5 As shown, a first P-type implantation region 61 is formed in the first N-type doped region 41, a second P-type implantation region 62 is formed in the epitaxial layer 2, a third P-type implantation region 63 is formed in the second P-type doped region 32, and a fourth P-type implantation region 64 is formed in the second N-type doped region 42, wherein the second P-type implantation region 62 is coupled to the first N-type doped region 41 and the second P-type doped region 32;

[0124] Step S5, as follows Figure 6 As shown, an isolation structure 7 is formed in the epitaxial layer 2, and the isolation structure 7 extends longitudinally from the upper surface of the epitaxial layer 2 through the epitaxial layer 2 into the substrate 1, and the first P-type doped region 31 is isolated by the isolation structure 7.

[0125] Step S6B, as follows Figure 11 As shown, a dielectric layer 8 is deposited on the upper surface of the epitaxial layer 2, and a polysilicon layer 10 is formed in the dielectric layer 8. The polysilicon layer 10 is located between the second N-type implantation region 52 and the third N-type implantation region 53, and corresponding contact holes 81 are formed above each N-type implantation region and P-type implantation region, as well as at both ends of the polysilicon layer 10.

[0126] Step S7B, as follows Figure 10 As shown, metal 9 is deposited in each contact hole 81 to form metal interconnects, so that the first N-type injection region 51, the third N-type injection region 53, the first P-type injection region 61, the fifth N-type injection region 55 and the fourth P-type injection region 64 are connected and led out as the anode 01 of the device, the fourth N-type injection region 54 and the third P-type injection region 63 are connected and led out as the cathode 02 of the device, and the second N-type injection region 52, the polysilicon layer 10 and the second P-type injection region 62 are connected.

[0127] In Embodiment 3, the specific implementation methods of steps S1-S5 are the same as those in Embodiment 1. For example, the conductivity type, implanted ion elements of each doped region and each implanted region, implantation energy, and processes used can all be the same, and will not be repeated here. Based on Embodiment 1, this embodiment adds a polysilicon layer 10 as a current-limiting resistor. Contact holes 81 are formed at both ends of the polysilicon layer 10 through photolithography and etching processes, so that one end of the current-limiting resistor is connected to the second N-type implanted region 52 through a metal interconnect, and the other end of the current-limiting resistor is connected to the second P-type implanted region 62 through a metal interconnect. In a preferred embodiment, the resistance value of the polysilicon layer 10 is [100Ω, 200Ω].

[0128] Example 5:

[0129] This embodiment is the equivalent circuit of Embodiment 3, such as... Figure 12 As shown, it includes:

[0130] A diode D1 has its anode O1 connected to a first port and its cathode connected to a second port.

[0131] A first transistor Q1, the emitter of the first transistor Q1 is connected to the first port, and the base of the first transistor Q1 is connected to the first port through a first resistor R-Nw;

[0132] A second transistor Q2 is connected to the collector of the first transistor Q1, the collector of the second transistor Q2 is connected to the base of the first transistor Q1, and the emitter of the second transistor Q2 is connected to the second port.

[0133] A transient diode (TVS) includes a first electrode and a second electrode. The first electrode is connected to a first port, and the second electrode is connected to the base of a second transistor through a second resistor R-poly.

[0134] Specifically, based on Example 2, a second resistor R-poly is added as a current-limiting resistor, and the resistance value of the second resistor R-poly is [100Ω, 200Ω].

[0135] The beneficial effects of the technical solution of this invention are as follows:

[0136] The SCR device provided by this invention has a low trigger voltage, strong ESD discharge capability, good stability and high reliability; multiple parallel conduction paths can release current simultaneously, which is beneficial for evenly distributing ESD events and enhancing the electrostatic discharge capability.

[0137] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-trigger-voltage SCR device, characterized in that, include: A substrate; An epitaxial layer is formed on the upper surface of the substrate, the epitaxial layer comprising: A first P-type doped region, the first P-type doped region including a first N-type implantation region and a second N-type implantation region, the distance between the first N-type implantation region and the second N-type implantation region not exceeding 5 μm; A first N-type doped region, wherein the first N-type doped region includes a third N-type implantation region and a first P-type implantation region; A second P-type doped region, wherein the second P-type doped region includes a fourth N-type implantation region and a third P-type implantation region; The second N-type doped region includes a fifth N-type implantation region and a fourth P-type implantation region; The second P-type implantation region is coupled to the first N-type doped region and the second P-type doped region; An isolation structure is provided, which extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer to the substrate, wherein the first P-type doped region is isolated by the isolation structure. A dielectric layer is formed on the upper surface of the epitaxial layer; Multiple metal layers are formed above each N-type implantation region and each P-type implantation region, respectively; Multiple metal wires are used to connect and lead out the first N-type injection region, the third N-type injection region, the first P-type injection region, the fifth N-type injection region, and the fourth P-type injection region to serve as the anode of the device; the fourth N-type injection region and the third P-type injection region are connected and led out to serve as the cathode of the device; and the second N-type injection region and the second P-type injection region are connected.

2. The SCR device with low trigger voltage according to claim 1, characterized in that, The resistivity of the epitaxial layer is greater than that of the substrate.

3. The SCR device with low trigger voltage according to claim 1, characterized in that, The implanted element in the first P-type doped region is boron, the ion implantation dose is 5E12~5E13 per square centimeter, and the implantation energy is 60~100 keV; The implanted element in the second P-type doped region is boron, with an ion implantation dose of 5E14~8E14 per square centimeter and an implantation energy of 40~60 keV; The implanted element in the first N-type doped region and the second N-type doped region is phosphorus, the ion implantation dose is 5E13~1E14 per square centimeter, and the implantation energy is 60~80 keV.

4. The SCR device with low trigger voltage according to claim 1, characterized in that, The implanted element in each of the N-type implantation regions is phosphorus or arsenic, the ion implantation dose is 1E15~1E16 per square centimeter, the implantation energy is 80~100 keV, and thermal annealing is performed after ion implantation at a temperature of 850℃~950℃ for 30~60 minutes.

5. The SCR device with low trigger voltage according to claim 1, characterized in that, The distance between the fourth N-type implantation region and the first N-type doped region, and the distance between the fourth N-type implantation region and the second N-type doped region, shall not exceed 6 μm.

6. The SCR device with low trigger voltage according to claim 1, characterized in that, The implanted element in each of the P-type implantation regions is boron or boron difluoride, the ion implantation dose is 1E15~1E16 per square centimeter, the implantation energy is 40~80 keV, and thermal annealing is performed after ion implantation at a temperature of 950~1050℃ for 10~30 seconds.

7. The SCR device with low trigger voltage according to claim 1, characterized in that, The distance between the P-type injection regions is not less than 2 μm.

8. A method for fabricating an SCR device with low trigger voltage, characterized in that, For fabricating the low trigger voltage SCR device as described in any one of claims 1-7, comprising: Step S1: Provide a substrate and grow an epitaxial layer on the surface of the substrate; Step S2: A first P-type doped region, a first N-type doped region, a second P-type doped region, and a second N-type doped region are sequentially formed in the epitaxial layer; Step S3: A first N-type implantation region and a second N-type implantation region are formed in the first P-type doped region, a third N-type implantation region is formed in the first N-type doped region, a fourth N-type implantation region is formed in the second P-type doped region, and a fifth N-type implantation region is formed in the second N-type doped region. Step S4: A first P-type implantation region is formed in the first N-type doped region, a second P-type implantation region is formed in the epitaxial layer, a third P-type implantation region is formed in the second P-type doped region, and a fourth P-type implantation region is formed in the second N-type doped region, wherein the second P-type implantation region is coupled to the first N-type doped region and the second P-type doped region. Step S5: An isolation structure is formed in the epitaxial layer, and the isolation structure extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer to the substrate, wherein the first P-type doped region is isolated by the isolation structure. Step S6A: A dielectric layer is deposited on the upper surface of the epitaxial layer, and corresponding contact holes are formed above each N-type injection region and P-type injection region. In step S7A, metal deposition is performed in each of the contact holes to form metal interconnects, so that the first N-type injection region, the third N-type injection region, the first P-type injection region, the fifth N-type injection region, and the fourth P-type injection region are connected and led out as the anode of the device, the fourth N-type injection region and the third P-type injection region are connected and led out as the cathode of the device, and the second N-type injection region and the second P-type injection region are connected.

9. A method for fabricating a low-trigger-voltage SCR device, characterized in that, For fabricating the low trigger voltage SCR device as described in any one of claims 1-7, comprising: Step S1: Provide a substrate and grow an epitaxial layer on the surface of the substrate; Step S2: A first P-type doped region, a first N-type doped region, a second P-type doped region, and a second N-type doped region are sequentially formed in the epitaxial layer; Step S3: A first N-type implantation region and a second N-type implantation region are formed in the first P-type doped region, a third N-type implantation region is formed in the first N-type doped region, a fourth N-type implantation region is formed in the second P-type doped region, and a fifth N-type implantation region is formed in the second N-type doped region. Step S4: A first P-type implantation region is formed in the first N-type doped region, a second P-type implantation region is formed in the epitaxial layer, a third P-type implantation region is formed in the second P-type doped region, and a fourth P-type implantation region is formed in the second N-type doped region, wherein the second P-type implantation region is coupled to the first N-type doped region and the second P-type doped region. Step S5: An isolation structure is formed in the epitaxial layer, and the isolation structure extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer to the substrate, wherein the first P-type doped region is isolated by the isolation structure. Step S6B: A dielectric layer is deposited on the upper surface of the epitaxial layer, and a polysilicon layer is formed in the dielectric layer. The polysilicon layer is located between the second N-type implantation region and the third N-type implantation region, and corresponding contact holes are formed above each N-type implantation region and P-type implantation region, as well as at both ends of the polysilicon layer. In step S7B, metal deposition is performed in each of the contact holes to form metal interconnects, so that the first N-type implantation region, the third N-type implantation region, the first P-type implantation region, the fifth N-type implantation region, and the fourth P-type implantation region are connected and led out as the anode of the device, the fourth N-type implantation region and the third P-type implantation region are connected and led out as the cathode of the device, and the second N-type implantation region, the polysilicon layer, and the second P-type implantation region are connected.

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