Vertical nitride semiconductor transistor device

Abstract

A normally-off vertical nitride semiconductor transistor device with little threshold voltage deviation comprises: a drift layer including a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film comprises at least a first insulating film located on the channel region side, a second insulating film located on the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, the second insulating film having a charge trap whose energy level is located inside the band gap of both the first insulating film and the third insulating film, and the threshold voltage is adjusted by the charge accumulated in the charge trap, and the threshold voltage is used to block the flowing current by substantially eliminating the conduction carriers in the channel region using the voltage applied to the gate electrode. In addition, a charge accumulation electrode is provided between the channel region and the gate electrode, and the threshold voltage is adjusted by the charge accumulated in the charge accumulation electrode.

Description

Technical Field

[0001] The present invention relates to a vertical nitride semiconductor transistor device, and in particular to a vertical nitride semiconductor field effect transistor device having a field effect type gate and suitable for application in high-power switching elements. Background Art

[0002] GaN, AlN, InN or semiconductors containing mixed crystals thereof, which are nitride semiconductors, have a wide band gap and the conduction electrons have a high carrier mobility, so they are suitable for high-voltage and high-output electronic devices. In particular, in a vertical field effect transistor (Vertical Field Effect Transistor) made using nitride semiconductors, the electron current flowing out of the source passes through a thick drift layer with a low doping concentration arranged at the bottom of the source region and flows into the drain. Therefore, the withstand voltage relative to the drain voltage when turned off is high. Moreover, since the source and drain are arranged vertically, the current flowing per unit area is high and the on-resistance is low, so it is suitable for use as a high-power switch (power switch) element. Figure 17 (a) is a cross-sectional view of a vertical nitride semiconductor field effect transistor as a first existing example (patent document 1). First, a drift layer 1101 is formed on a substrate 1100. GaN, SiC, Si, etc. with n-type conductivity are used in the substrate 1100. The epitaxial growth of nitride semiconductors in the c-axis direction can easily obtain good crystallinity. Therefore, the substrate 1100 preferably uses a single crystal substrate having a crystal plane orientation that can obtain epitaxial growth in the c-axis direction. For example, when using a GaN substrate or a SiC substrate with a hexagonal crystal structure, the crystal plane orientation of the substrate is set to the c-axis direction. When using a GaN substrate, a substrate with a Ga surface that is particularly easy to grow epitaxially is used. In addition, when using a Si substrate, if a substrate with a crystal plane orientation of (111) is used, epitaxial growth of nitride semiconductors in the c-axis direction can be obtained. A buffer layer may also be inserted between the substrate 1100 and the drift layer 1101 for the purpose of improving the crystallinity of the drift layer 1101 during epitaxial growth. In addition, the drift layer 1101 can be made of n-type GaN, n-type AlGaN, or AlGaN with a composition tilt. A barrier layer 1102, a first nitride semiconductor layer 1104, and a second nitride semiconductor layer 1105 are provided on the drift layer 1101. The barrier layer 1102 is provided for the purpose of blocking the flow of conduction electrons, and an opening 1103 that does not block the flow of conduction electrons is provided in a part of the surface. There are various methods for making the opening 1103. For example, the barrier layer 1102 may be formed on the entire surface of the drift layer 1101, and the barrier layer 1102 in the opening 1103 may be removed by wet etching or dry etching, and then the first nitride semiconductor layer 1104 and the second nitride semiconductor layer 1105 may be grown to fill the opening 1103. In this case, for the barrier layer 1102, p-type GaN, p-type AlGaN, a high-resistance nitride semiconductor doped with a dopant for forming a deep trap level, an insulating film, or a stacked structure thereof, etc., which are epitaxially grown on the drift layer 1101, are used.Alternatively, after the drift layer 1101 is grown, a p-type dopant may be selectively introduced into the portion other than the opening by ion implantation, and activated by a subsequent thermal process, thereby forming a barrier layer 1102 including a p-type layer. Alternatively, after the drift layer 1101, the barrier layer 1102 including a p-type nitride semiconductor, the first nitride semiconductor layer 1104, and the second nitride semiconductor layer 1105 are sequentially epitaxially grown, an n-type dopant may be selectively ion implanted into the opening 1103, and activated by a subsequent thermal process, thereby inverting the barrier layer 1102 in the opening 1103 to an n-type. The second nitride semiconductor layer 1105 includes at least a nitride semiconductor having a larger band gap than at least a portion of the nitride semiconductor of the first nitride semiconductor layer 1104. For example, GaN is used as the first nitride semiconductor layer 1104, and AlGaN is used as the second nitride semiconductor layer 1105. Thus, a conductive layer 1111 and a conductive layer 1112 containing a two-dimensional electron gas are formed on the first nitride semiconductor layer 1104 side of the interface between the second nitride semiconductor layer 1105 and the first nitride semiconductor layer 1104. A gate insulating film 1106 is formed on the second nitride semiconductor layer 1105. As its material, aluminum oxide, silicon oxide, silicon nitride, hafnium oxide, zirconium oxide or other gate insulating materials known in the art, or a laminated film thereof, is used. A gate electrode 1107 is formed on the gate insulating film 1106. In addition, a source electrode 1109 is formed in contact with the second nitride semiconductor layer 1105, and a drain electrode 1110 is formed on the back side of the substrate 1100. In addition, when a p-type nitride semiconductor is used in the barrier layer 1102, a main body electrode 1108 may also be provided in order to fix the potential. As an electrode material, for example, Pd, Pt, Ni, etc. are used. The source electrode 1109 is formed so as to be electrically connected to the main body electrode 1108 at the same time. As the electrode material, for example, a multilayer film composed of a lower layer of Ti and an upper layer of Al is used. In addition, the source electrode 1109 can also be formed before the gate electrode 1107 is formed. For example, after the second nitride semiconductor layer 1105 is formed, the main electrode 1108 and the source electrode 1109 are first formed, and then the gate insulating film 1106 is deposited, and then the gate electrode 1107 is formed. The drain electrode 1110 on the back side can also be formed before the other electrodes are formed. The main electrode 1108 is provided to fix the potential of the blocking layer 1102, but the main electrode 1108 may not be provided.

[0003] Next, the operating principle of the vertical nitride semiconductor transistor shown in FIG. 17(a) as the first prior art example is described. Due to the presence of the barrier layer 1102, the conduction electrons flowing into the semiconductor layer from the source electrode 1109 do not flow directly toward the substrate, but pass through the conductive layer 1112 (indicated by a thin dotted line in FIG. 17(a)) and a portion of the conductive layer 1111 (indicated by a thick dotted line in FIG. 17(a)), and flow into the drift layer 1101 through the opening 1103 along the direction of the arrow 1113 indicating the flow of the conduction electrons. Thereafter, the conduction electrons pass through the drift layer 1101 and the substrate 1100 and reach the drain electrode 1110. At this time, the number of conduction electrons in the conductive layer 1111 directly below can be changed by the field effect of the voltage applied to the gate electrode 1107, thereby changing the flow of electrons. Hereinafter, the conductive region in the current path between the source and the drain where the number of conduction electrons can be changed by the field effect of the gate electrode is referred to as the channel region. In FIG. 17( a), the channel region 1114 is represented by a dotted ellipse. The gate voltage that blocks the current by substantially eliminating the conduction electrons in the conductive layer 1111 constituting the channel region 1114 is called the threshold voltage. In the vertical nitride semiconductor field effect transistor shown in the present prior art, the threshold voltage is usually a negative value. The switching element is turned on by applying a voltage above the threshold voltage to the gate electrode. At this time, the conduction electrons reach the opening 1103 via the high-mobility conductive layer 1112 containing the two-dimensional electron gas and the conductive layer 1111 in the channel region, so that a switch element with low resistance in the on state, i.e., low on-resistance, can be obtained. On the other hand, in the off state, as a high-power switch, the withstand voltage relative to the drain voltage is important. In a vertical transistor, the withstand voltage can be increased by increasing the thickness of the drift layer 1101 and reducing the n-type dopant concentration of the drift layer 1101. However, the resistance of the conduction electrons passing through the drift layer will increase, so the on-resistance will increase. Therefore, the thickness and doping concentration of the drift layer 1101 should be optimized in consideration of the withstand voltage and the on-resistance.

[0004] FIG17(b) is a cross-sectional view of a vertical nitride semiconductor transistor as a second prior art example. In the second prior art example, an n-type nitride semiconductor layer 1130 is provided between the drift layer 1101 and the substrate 1100, and the drain electrode 1110 is provided on the upper surface of the n-type nitride semiconductor layer 1130 in contact with the n-type nitride semiconductor layer 1130, rather than being provided on the back side of the substrate 1100. Therefore, the substrate 1100 does not need to be an n-type substrate, and a high-resistance substrate can also be used. The rest is the same as the first prior art example shown in FIG17(a). In the second prior art example, since the drain electrode 1110 is present on the surface, an additional area is required when making a switching element, and the on-resistance per unit area becomes higher than that of the first prior art example. In the following, the prior art examples and the embodiments of the present invention only describe the case where the drain electrode is provided on the back side of the substrate.

[0005] Fig.18 FIG. 1 is a cross-sectional structure of a vertical nitride semiconductor transistor as a third prior art example (Non-Patent Document 1). A drift layer 1101 is formed on a substrate 1100, and a barrier layer 1202 is formed thereon. The manufacturing process of the transistor described in FIG. 17(a) is substantially the same, but the opening 1203 is formed by etching away unnecessary portions after forming the barrier layer 1202 on the entire surface. Fig.18 As shown, the first nitride semiconductor layer 1204 and the second nitride semiconductor layer 1205 are then grown along the side of the opening portion having an inclination. Here, the second nitride semiconductor layer 1205 includes at least a nitride semiconductor having a larger band gap than at least a portion of the nitride semiconductor of the first nitride semiconductor layer 1204, which is the same as the first prior art example illustrated in FIG. 17( a). For example, GaN is used as the first nitride semiconductor layer 1204, and AlGaN is used as the second nitride semiconductor layer 1205. Among them, since the first nitride semiconductor layer 1204 and the second nitride semiconductor layer 1205 are grown along the side of the opening portion 1203, the conductive layer 1211 formed on the side of the first nitride semiconductor layer 1204 at the interface between the second nitride semiconductor layer 1205 and the first nitride semiconductor layer 1204 is also formed along the inner side of the opening portion 1203 including the side. Next, a gate insulating film 1206 is formed, and a gate electrode 1207 is formed thereon to cover the inner surface of the opening. The body electrode 1108, the source electrode 1109, and the drain electrode 1110 are formed in the same manner as in the first conventional example described in FIG.

[0006] Next, as a third prior art example, Fig.1817 (a) and the like. The operating principle of the vertical nitride semiconductor transistor shown in FIG. 17 (a) is explained. The channel region 1214 includes a portion of the conductive layer 1211 formed in the inclined portion of the opening 1203. The conduction electrons flow from the source electrode 1109 through the conductive layer 1212, the channel region 1214 and into the drift layer 1101, and then through the substrate 1100 to reach the drain electrode 1110. In addition, the number of conduction electrons in the conductive layer 1211 including the channel region 1214 can be changed by the field effect of the voltage applied to the gate electrode 1207, thereby adjusting the current. The threshold voltage for substantially eliminating the conduction electrons in the channel region 1214 to block the current can be set to a negative voltage or a positive voltage that is smaller than the prior art example of FIG. 17 (a). This is based on the following reasons. As described in the first paragraph of the background technology, in the first prior art example of FIG. 17 (a), the crystal plane orientation of the nitride semiconductor layer grown on the substrate is the c-axis direction. The c-plane is a so-called polarization plane. Under the influence of spontaneous polarization and piezoelectric polarization occurring along the c-axis in the substrate direction, the conductive layer 1111 is spontaneously formed without external voltage application. Therefore, in order to substantially eliminate the conduction electrons in the conductive layer 1111, a large negative voltage needs to be applied to the gate electrode 1107. In other words, the threshold voltage has a large negative value. In contrast, Fig.18 In the third prior art example shown, the crystal plane orientations of the first semiconductor layer 1204 and the second semiconductor layer 1205 formed on the side of the opening 1203 deviate from the c-axis direction. Therefore, the spontaneous polarization and the piezoelectric polarization are weakened, and the number of carriers induced in the conductive layer 1211 formed on the side portion is less than that of the conductive layer 1111 of FIG. 17 (a) when no voltage is applied from the outside. This is the reason why the threshold voltage is shifted in the positive direction compared with the first prior art example of FIG. 17 (a) (non-patent document 2). However, the shift amount of the threshold voltage is sensitive to the inclination angle of the side portion, and further, the threshold voltage is also largely dependent on the details of the formation process of the opening 1203, the first nitride semiconductor layer 1204, the second nitride semiconductor layer 1205, and the gate insulating film 1206. Therefore, according to the report, the threshold voltage has a large negative value (non-patent document 1).

[0007] Fig.19This is a cross-sectional structure of a vertical nitride semiconductor transistor as a fourth prior art example (non-patent document 3). The manufacturing process of the substrate 1100 and the drift layer 1101 of the first prior art example illustrated in FIG. 17( a) is the same until the drift layer 1301 is grown on the substrate 1300. Then, a p-type nitride semiconductor layer 1302 and an n-type nitride semiconductor layer 1303 are formed in sequence. The p-type nitride semiconductor layer 1302 is used as a p-type main region. In a preferred example, GaN is used in the p-type nitride semiconductor layer 1302 and the n-type nitride semiconductor layer 1303. After the n-type nitride semiconductor layer 1303 is formed, a groove 1304 penetrating to the drift layer 1301 is formed by wet etching or dry etching. Then, a gate insulating film 1305 is formed in a manner covering the side and bottom surfaces of the groove 1304. In addition, in order to improve the characteristics of the interface between the gate insulating film and the nitride semiconductor, before forming the gate insulating film 1305, a thin nitride semiconductor layer such as GaN can also be grown in a manner covering the inner wall of the groove 1304 (non-patent document 4). Then, the gate electrode 1306 is formed in a manner covering the inner surface of the groove 1304. Furthermore, a main electrode 1307 electrically connected to the p-type nitride semiconductor layer 1302 is formed. As an electrode material, for example, Pd, Pt, Ni, etc. are used. Then, a source electrode 1308 is formed. As an electrode material, for example, a multilayer film composed of a lower layer of Ti and an upper layer of Al is used. The source electrode 1308 is electrically connected to the main electrode 1307 and the n-type nitride semiconductor layer 1303. Furthermore, a drain electrode 1309 is formed on the back side of the substrate 1300, thereby completing the vertical nitride semiconductor transistor. In addition, the formation of the main electrode 1307 and the source electrode 1308 can be performed before the formation of the gate electrode 1306. For example, after the formation of the n-type nitride semiconductor layer 1303, the main electrode 1307 and the source electrode 1308 can be formed first, and then the formation of the groove 1304, the deposition of the gate insulating film 1305, and the formation of the gate electrode 1306 can be performed in sequence. The drain electrode 1309 on the back side can also be formed before the formation of other electrodes. The main electrode 1307 is provided to fix the potential of the p-type nitride semiconductor layer 1302 used as the p-type main region, and can also be omitted.

[0008] Next, as a fourth prior art example, Fig.1917( a) and 17( b) illustrate the operation principle of the vertical nitride semiconductor transistor shown in FIG. 1302. Due to the presence of the p-type nitride semiconductor layer 1302, the conduction electrons flowing from the source electrode 1308 into the n-type nitride semiconductor layer 1303 do not flow directly toward the substrate, but flow toward the groove 1304 along the arrow 1311 indicating the flow of the conduction electrons. On the other hand, the p-type nitride semiconductor layer 1302 functions as a p-type body region, and the inverted conductive layer 1310 formed along the side surface inside the groove 1304 constitutes a channel region 1314. The conduction electrons flow from the n-type nitride semiconductor layer 1303 through the channel region 1314 and into the drift layer 1301 along the arrow 1312 indicating the flow of the electrons. Furthermore, the conduction electrons pass through the drift layer 1301 and the substrate 1300 and reach the drain electrode 1309. The design of the drift layer 1301 may be performed in the same manner as that described in the first conventional example of FIG. 17( a). On the other hand, the number of conduction electrons induced in the conductive layer 1310 forming the channel region can be changed by applying a voltage to the gate electrode 1306. When the gate voltage is below a certain threshold voltage, it becomes an off state, and when the gate voltage is above the threshold voltage, it becomes an on state, thereby obtaining an on / off action as a switch. In the on state, the mobility of the conduction electrons flowing in the conductive layer 1310 is reduced due to the influence of the unevenness or defects at the interface between the conductive layer 1310 and the gate insulating film 1305. Therefore, compared with the first existing example of Figure 17 (a), the current is lower and the on resistance is higher. On the other hand, the conductive layer 1312 is formed as a plane roughly orthogonal to the c-plane, so the influence of polarization is small, and unlike the first existing example of Figure 17 (a), the threshold voltage is usually a positive value.

[0009] [Prior art literature]

[0010] [Patent Document]

[0011] [Patent Document 1] Chowdhury et al. US 9,590,088 B2

[0012] [Non-patent literature]

[0013] [Non-patent document 1] Dong Ji et al., Institute of Electrical and Electronics Engineers (IEEE) Electron Device Letters, Vol. 39, No. 6, June 2018, p. 863.

[0014] [Non-patent document 2] Daisuke Shibata et al., International Electron Device Meeting 2016, p. 248.

[0015] [Non-patent document 3] Ray Li et al., Institute of Electrical and Electronics Engineers (IEEE) Electron Device Letters, Vol. 37, No. 11, November 2016, p. 1466.

[0016] [Non-Patent Document 4] Chirag Gupta et al., Institute of Electrical and Electronics Engineers (IEEE) Electron Device Letters, Vol. 38, No. 3, March 2017, p. 353. Summary of the invention

[0017] [Problems to be solved by the invention]

[0018] The threshold voltage of the vertical nitride semiconductor transistor of the first and second prior art examples is usually a negative voltage. That is, as a switching element, it is a so-called normally on in which the switch is turned on when no voltage is applied to the gate electrode. A switch composed of a normally on transistor will turn on the switch when the control voltage applied to the gate electrode is lost due to malfunction or failure, so there is a high risk of the entire device such as the power supply being destroyed, which is not preferred from the perspective of safety. Regarding the threshold voltage of the vertical nitride semiconductor transistor of the third prior art example, since the crystal plane orientation of the nitride semiconductor layer in the channel part is tilted from the c-axis, the influence of the polarization charge becomes smaller, and it is expected to shift in the direction of the positive voltage. However, the threshold voltage actually obtained depends largely on the structure or manufacturing process, and is a negative voltage in most cases. Or even if it becomes a positive voltage and becomes normally off, it is difficult to obtain a threshold voltage of more than 3V, which is usually required from the perspective of safety, in applications such as power supplies. In addition, the threshold voltage caused by the process varies greatly, and it is difficult to obtain a switching element with consistent characteristics. In the vertical nitride semiconductor transistor of the fourth conventional example, a normally-off transistor having a positive voltage of about 3 V can be obtained. However, since the inverted conductive layer 1310 forming the channel is formed on the side of the opening 1304 formed by etching, the threshold voltage varies greatly due to the process, and it is difficult to obtain a switch element with uniform characteristics because the semiconductor surface is damaged by etching and it is difficult to form a gate insulating film 1305 of good quality on the side inside the opening 1304.

[0019] An object of the present invention is to provide a normally-off vertical nitride semiconductor transistor having a sufficiently large positive voltage and a threshold voltage with little deviation.

[0020] [Technical means to solve the problem]

[0021] The vertical nitride semiconductor transistor device provided by the first invention of the present application for solving the above-mentioned problem includes: a drift layer composed of a nitride semiconductor; a channel region composed of a nitride semiconductor and electrically connected to the drift layer; a source electrode electrically contacting the side of the channel region opposite to the drift layer; a drain electrode electrically contacting the drift layer; a gate insulating film close to the channel region; and a gate electrode arranged on the side of the gate insulating film opposite to the channel region. The gate insulating film includes at least a first insulating film located on the channel region side, a second insulating film closer to the gate electrode side than the first insulating film, and a third insulating film closer to the gate electrode side than the second insulating film, wherein the second insulating film has a charge trap whose energy level is located inside the band gap of both the first insulating film and the third insulating film. The threshold voltage is adjusted by the charge accumulated in the charge trap, and the threshold voltage is used to block the current flowing between the source electrode and the drain electrode by substantially eliminating the conduction carriers in the channel region by the voltage applied to the gate electrode.

[0022] In a preferred embodiment of the vertical nitride semiconductor transistor device provided by the first invention of the present application, the threshold voltage is adjusted to a positive voltage by the charges accumulated in the charge traps.

[0023] In a preferred form of the vertical nitride semiconductor transistor device provided by the first invention of the present application, a blocking layer for blocking the current is provided on the drift layer, a first nitride semiconductor layer is provided on the blocking layer, and a second nitride semiconductor layer is provided on the first nitride semiconductor layer. The second nitride semiconductor layer at least includes a nitride semiconductor having a larger band gap than at least a part of the nitride semiconductor of the first nitride semiconductor layer, the channel region includes at least a part of the conductive layer formed on the first nitride semiconductor layer side at the interface between the second nitride semiconductor layer and the first nitride semiconductor layer, the blocking layer has an opening, the first nitride semiconductor layer is electrically connected to the drift layer via the opening, and the current between the source electrode and the drain electrode substantially flows via the opening.

[0024] In another preferred form of the vertical nitride semiconductor transistor device provided by the first invention of the present application, a third nitride semiconductor layer having a conductivity type opposite to that of the drift layer is provided on the drift layer, and a fourth nitride semiconductor layer is provided on the third nitride semiconductor layer, and the fourth nitride semiconductor layer has substantially the same conductivity type as that of the drift layer by doping or polarization charge. The source electrode is electrically connected to the fourth nitride semiconductor layer. A groove is formed that penetrates the fourth nitride semiconductor layer and the third nitride semiconductor layer and reaches the drift layer. At least a portion of the gate insulating film is formed directly or via a thin nitride semiconductor layer on the side of the third nitride semiconductor layer in the inner surface of the groove. An inverted conductive layer is formed on one side of the third nitride semiconductor layer at an interface formed between the side of the third nitride semiconductor layer and the gate insulating film directly or via the thin nitride semiconductor layer. At least a portion of the gate electrode is formed on a side of the gate insulating film opposite to the inverted conductive layer, and the channel region includes at least a portion of the inverted conductive layer.

[0025] The vertical nitride semiconductor transistor device provided by the second invention of the present application for solving the above-mentioned problem includes: a drift layer composed of a nitride semiconductor; a channel region composed of a nitride semiconductor and electrically connected to the drift layer; a source electrode electrically contacting the side of the channel region opposite to the drift layer; a drain electrode electrically contacting the drift layer; a fourth insulating film close to the channel region; a charge storage electrode provided on the side of the fourth insulating film opposite to the channel region; a fifth insulating film provided on the side of the charge storage electrode opposite to the fourth insulating film; and a gate electrode provided on the side of the fifth insulating film opposite to the charge storage electrode. The threshold voltage is adjusted by the charge stored in the charge storage electrode, and the threshold voltage is used to block the current flowing between the source electrode and the drain electrode by substantially eliminating the conduction carriers in the channel region by the voltage applied to the gate electrode.

[0026] In a preferred embodiment of the vertical nitride semiconductor transistor device provided by the second invention of the present application, the charge storage electrode includes a plurality of electrodes which are arranged laterally and are electrically insulated.

[0027] In a preferred embodiment of the vertical nitride semiconductor transistor device provided by the second invention of the present application, the threshold voltage is adjusted to a positive voltage by the charge accumulated in the charge accumulation electrode.

[0028] In a preferred form of the vertical nitride semiconductor transistor device provided by the second invention of the present application, in the on state, the capacitance value of the first capacitor formed between the channel region and the charge storage electrode is smaller than the capacitance value of the second capacitor formed between the gate electrode and the charge storage electrode.

[0029] In a preferred form of the vertical nitride semiconductor transistor device provided by the second invention of the present application, there is a charge injection electrode that forms a third capacitor with the charge storage electrode, and the accumulation of the charge to the charge storage electrode is performed by a current flowing through the third capacitor.

[0030] In a preferred form of the vertical nitride semiconductor transistor device provided by the second invention of the present application, a sixth insulating film is formed on at least a portion of the charge injection electrode, and the charge storage electrode is formed on at least a portion of the sixth insulating film. The sixth insulating film is used as a capacitive coupling film to form the third capacitor between the charge storage electrode and the charge injection electrode.

[0031] In a preferred embodiment of the vertical nitride semiconductor transistor device provided by the second invention of the present application, the capacitance value of the third capacitor is smaller than the capacitance value of the second capacitor.

[0032] In a preferred form of the vertical nitride semiconductor transistor device provided by the second invention of the present application, a blocking layer for blocking the current is arranged on the drift layer, a first nitride semiconductor layer is arranged on the blocking layer, and a second nitride semiconductor layer is arranged on the first nitride semiconductor layer, the second nitride semiconductor layer at least includes a nitride semiconductor having a band gap larger than that of at least a part of the nitride semiconductor of the first nitride semiconductor layer, the channel region includes at least a part of the conductive layer formed on the first nitride semiconductor layer side of the interface between the second nitride semiconductor layer and the first nitride semiconductor layer, the blocking layer has an opening portion, the first nitride semiconductor layer is electrically connected to the drift layer via the opening portion, and the current between the source electrode and the drain electrode substantially flows via the opening portion.

[0033] In another preferred form of the vertical nitride semiconductor transistor device provided by the second invention of the present application, a third nitride semiconductor layer having a conductivity type opposite to that of the drift layer is provided on the drift layer, a fourth nitride semiconductor layer is provided on the third nitride semiconductor layer, the fourth nitride semiconductor layer having substantially the same conductivity type as that of the drift layer by doping or polarization of charges, and the source electrode is electrically connected to the fourth nitride semiconductor layer. A trench is formed that penetrates the fourth nitride semiconductor layer and the third nitride semiconductor layer and reaches the drift layer, and at least a portion of the fourth insulating film is formed directly or via a thin nitride semiconductor layer on the side of the third nitride semiconductor layer in the inner surface of the trench. An inverted conductive layer is formed on one side of the third nitride semiconductor layer at an interface formed directly or via the thin nitride semiconductor layer between the side of the third nitride semiconductor layer and the fourth insulating film. At least a portion of the charge storage electrode is formed on the side of the fourth insulating film opposite to the inverted conductive layer. The channel region includes at least a portion of the inverted conductive layer.

[0034] In the second invention of the present application, when the charge is accumulated in the charge accumulation electrode by the current flowing through the third capacitor, a voltage is applied to the gate electrode, whereby the charge injection amount can be easily controlled.

[0035] When the vertical nitride semiconductor transistor device provided by the second invention of the present application is sealed in a package, the gate electrode, the drain electrode, and the source electrode can be connected to external pins respectively, and the charge injection electrode is not connected to the external pin. Alternatively, the charge injection electrode and the gate electrode can be connected to the same external pin.

[0036] In a preferred embodiment of the vertical nitride semiconductor transistor device provided by the first invention and the second invention of the present application, the first nitride semiconductor layer is composed of GaN, and the second nitride semiconductor layer is composed of Al. x Ga 1-x N (0<x≤1). x Ga 1-x The conductive layer induced in the interface of N has high electron mobility, so a vertical nitride semiconductor transistor device with excellent on-resistance, which is one of the important characteristics of a switch, can be obtained.

[0037] In a preferred embodiment of the vertical nitride semiconductor transistor device provided by the first invention and the second invention of the present application, at least the bottommost layer of the gate insulating film in contact with the nitride semiconductor layer is composed of aluminum oxide. Aluminum oxide is not easy to generate interface trap energy levels at the interface with the nitride semiconductor layer, so when a positive voltage is applied to the gate electrode to increase the number of conduction carriers in the channel region to increase the flowing current, it is not easily affected by the interface trap energy levels at the interface between the nitride semiconductor in the channel region and the gate insulating film. As a result, a vertical nitride semiconductor transistor device with excellent on-resistance, which is one of the important characteristics of a switch, can be obtained.

[0038] [Effects of the Invention]

[0039] As described above, according to the present invention, a normally-off vertical nitride semiconductor transistor device having a positive threshold voltage and little variation in threshold voltage can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a first embodiment of the first invention of the present application;

[0041] Figure 2 It means in Figure 1 A table showing dimensions and material properties assumed in a two-dimensional device simulation of a vertical nitride semiconductor transistor device provided by the first embodiment of the first invention of the present application;

[0042] Figure 3 Yes means through Figure 1 and Figure 2 A diagram showing the depth dependence of the conduction band energy in the drift layer obtained by two-dimensional device simulation of the vertical nitride semiconductor transistor device provided by the first embodiment of the first invention of the present application;

[0043] Figure 4 Yes means Figure 1 and Figure 2 A diagram showing the drain voltage dependence of the drain current of the vertical nitride semiconductor transistor device provided by the first embodiment of the first invention of the present application in a state before negative charges are accumulated in the charge accumulation insulating film;

[0044] Figure 5 Yes means Figure 1 and Figure 2 A diagram showing the gate voltage dependence of the drain current of the vertical nitride semiconductor transistor device provided by the first embodiment of the first invention of the present application;

[0045] Figure 6 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a second embodiment of the first invention of the present application;

[0046] Figure 7 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a third embodiment of the first invention of the present application;

[0047] Figure 8 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a fourth embodiment of the first invention of the present application;

[0048] Fig. 9 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a fifth embodiment of the first invention of the present application;

[0049] Fig.10 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a first embodiment of the second invention of the present application;

[0050] Fig.11 is an equivalent circuit diagram showing capacitors between nodes of a vertical nitride semiconductor transistor device provided by a first embodiment of the second invention of the present application;

[0051] Fig.12 1 is a plan view, an AA' cross-sectional view and a BB' cross-sectional view showing a vertical nitride semiconductor transistor device provided by a second embodiment of the second invention of the present application;

[0052] Fig.13 is an equivalent circuit diagram showing capacitors between nodes of a vertical nitride semiconductor transistor device provided by a second embodiment of the second invention of the present application;

[0053] Fig.14 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a third embodiment of the second invention of the present application;

[0054] Fig.15 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a fourth embodiment of the second invention of the present application;

[0055] Fig.16 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by a fifth embodiment of the second invention of the present application;

[0056] FIG17(a) is a cross-sectional view showing a vertical nitride semiconductor transistor device as a first conventional example;

[0057] FIG17( b) is a cross-sectional view showing a vertical nitride semiconductor transistor device as a second conventional example;

[0058] Fig.18 is a cross-sectional view showing a vertical nitride semiconductor transistor device as a third conventional example;

[0059] Fig.19 FIG. 1 is a cross-sectional view showing a vertical nitride semiconductor transistor device as a fourth conventional example.

[0060] Description of Reference Numerals

[0061] 100, 400, 600, 800, 1100, 1300: substrate

[0062] 101, 401, 601, 801, 1101, 1301: drift layer

[0063] 102, 302, 602, 702, 1102, 1202: barrier layer

[0064] 103, 303, 603, 703, 1103, 1203: Opening

[0065] 104, 304, 503, 604, 704, 903, 1104: first nitride semiconductor layer

[0066] 105, 305, 504, 605, 705, 904, 1105: second nitride semiconductor layer

[0067] 106, 206, 306, 406: first insulating film

[0068] 107, 207, 307: Second insulating film

[0069] 108, 208, 308, 408: Third insulating film

[0070] 109, 209, 309, 409, 609, 809, 1107, 1207, 1306: Gate electrodes

[0071] 110, 410, 610, 810, 1108, 1307: Main electrode

[0072] 111, 411, 611, 811, 1109, 1308: source electrode

[0073] 112, 412, 612, 812, 1110, 1309: drain electrode

[0074] 113, 114, 213, 214, 313, 314, 413, 513, 514, 613, 614, 713, 714, 813, 913, 914, 1111, 1112, 1211, 1212, 1310: conductive layer

[0075] 115, 215, 414, 415, 515, 615, 715, 814, 815, 915, 1113, 1213, 1311, 1312: Arrows representing the flow of conduction electrons

[0076] 116, 216, 316, 416, 516: Fixed charge

[0077] 117, 217, 317, 417, 517, 617, 717, 817, 917, 1114, 1214, 1314: Channel area

[0078] 118: Width (a)

[0079] 119: Width (b)

[0080] 120: Distance (c)

[0081] 205: Second nitride semiconductor layer / nitride semiconductor layer

[0082] 218, 616, 716, 816: Field insulation film

[0083] 315: Arrows / arrows representing the flow of conduction electrons

[0084] 402, 802: third nitride semiconductor layer

[0085] 403, 803: fourth nitride semiconductor layer

[0086] 405, 505, 805, 905, 1304: Groove

[0087] 407: Second insulating film / insulating film

[0088] 606, 706, 806: Fourth insulating film

[0089] 607, 707, 807: Electrodes for charge storage

[0090] 608, 708, 808: Fifth insulating film

[0091] 619: Sixth insulating film

[0092] 620: Electrode for charge injection

[0093] 621: Edge

[0094] 630: First capacitor

[0095] 631: Second capacitor

[0096] 632: The third capacitor

[0097] 1106, 1206, 1305: Gate insulating film

[0098] 1130, 1303: n-type nitride semiconductor layer

[0099] 1204: First nitride semiconductor layer / first semiconductor layer

[0100] 1205: Second nitride semiconductor layer / second semiconductor layer

[0101] 1302: p-type nitride semiconductor layer DETAILED DESCRIPTION

[0102] Figure 1, a cross-sectional view of a vertical nitride semiconductor transistor device provided by the first embodiment of the first invention of the present application is shown. In this embodiment and other embodiments of the present invention, all of them describe the case where conduction electrons are used as conduction carriers. A drift layer 101 is epitaxially grown on a substrate 100. The substrate 100 may use GaN, SiC, Si, etc. of n-type conductivity. In the case of epitaxially growing a nitride semiconductor, good crystallinity can be obtained by growing the nitride semiconductor along the c-axis direction. Therefore, the substrate 100 preferably uses a single crystal substrate having a crystal plane orientation that allows epitaxial growth in the c-axis direction. For example, in the case of using a GaN substrate or a SiC substrate having a hexagonal crystal structure, a single crystal substrate having a crystal plane orientation of the substrate in the c-axis direction is used. In the case of using a GaN substrate, it is preferred to use a substrate with a Ga face as the surface, which is particularly easy for epitaxial crystal growth. In the case of using a Si substrate, if a substrate with a crystal plane orientation of (111) is used, epitaxial growth of a nitride semiconductor in the c-axis direction can be obtained. A buffer layer may be inserted between the substrate 100 and the drift layer 101 for the purpose of improving the crystallinity of the drift layer 101 during epitaxial growth. In addition, the drift layer 101 may be made of n-type GaN, n-type AlGaN, or AlGaN with a composition gradient. A barrier layer 102, a first nitride semiconductor layer 104, and a second nitride semiconductor layer 105 are provided on the upper part of the drift layer 101. The barrier layer 102 is provided for the purpose of blocking the flow of conduction electrons, but an opening 103 that does not block the flow of electrons is provided in a part thereof. There are various methods for making the opening 103. For example, the barrier layer 102 may be formed on the entire surface of the drift layer 101, and a portion of the opening 103 may be removed by wet etching or dry etching, and then the first nitride semiconductor layer 104 may be grown to fill the opening 103. In this case, for the barrier layer 102, p-type GaN, p-type AlGaN, a high-resistance nitride semiconductor doped with a dopant for forming a deep trap energy level, an insulator, or a stacked structure thereof, which is epitaxially grown on the drift layer 101, is used. Alternatively, after the drift layer 101 is grown, a p-type dopant may be selectively introduced into the surface portion other than the opening by ion implantation, and activated by a subsequent thermal process, thereby forming the barrier layer 102 including a p-type layer. Alternatively, after the drift layer 101, the barrier layer 102 including a p-type nitride semiconductor, the first nitride semiconductor layer 104, and the second nitride semiconductor layer 105 are sequentially epitaxially grown, an n-type dopant may be selectively ion implanted into the opening 103, and activated by a subsequent thermal process, thereby inverting the barrier layer 102 in the opening 103 to an n-type. The second nitride semiconductor layer 105 includes at least a nitride semiconductor having a larger band gap than at least a portion of the nitride semiconductor of the first nitride semiconductor layer 104.For example, GaN is used as the first nitride semiconductor layer 104, and AlGaN is used as the second nitride semiconductor layer 105. Thus, a conductive layer 113 (containing a two-dimensional electron gas) is formed on the first nitride semiconductor layer 104 side of the interface between the second nitride semiconductor layer 105 and the first nitride semiconductor layer 104. Figure 1 ) and the conductive layer 114 ( Figure 1 The channel region 117 is shown by a thin dashed line. Figure 1 Indicated by a dotted ellipse. For the purpose of promoting electron conduction from the channel region 117 to the drift layer 101 via the opening 103, n-type dopants may also be doped in the first nitride semiconductor layer 104. Subsequently, a first insulating film 106, a second insulating film 107, and a third insulating film 108, each of which includes a single layer or a stacked film, are sequentially deposited on the second nitride semiconductor layer 105. At this time, the second insulating film 107 is selected in a material and a film forming method in such a way that the following charge traps are included in the film: the energy level of the charge trap is located inside the band gap of at least a part of the insulating film of the first insulating film 106 and inside the band gap of at least a part of the insulating film of the third insulating film. For example, as the second insulating film, silicon nitride, hafnium oxide, and zirconium oxide formed by plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition (PECVD)) or atomic layer deposition (ALD) are used. On the other hand, in the first insulating film 106 and the third insulating film 108, for example, silicon oxide, aluminum oxide or a stacked film thereof is used. The film forming method can use the same method as the second insulating film 107. Then, the gate electrode 109 is formed on the third insulating film 108. On the second nitride semiconductor layer 105, a source electrode 111 is formed in a manner to obtain a good electrical connection with low resistance relative to the conductive layer 114. As an electrode material, for example, a multilayer film consisting of a lower layer of Ti and an upper layer of Al is used. In addition, when a p-type nitride semiconductor is used in the barrier layer 102, a main electrode 110 may also be provided to fix the potential. As an electrode material, for example, Pd, Pt, Ni, etc. are used. The source electrode 111 is formed so as to be electrically connected to the main electrode 110 at the same time. The drain electrode 112 is formed on the back side of the substrate 100. In addition, the source electrode 111 may be formed before the gate electrode 109 is formed. For example, after forming the second nitride semiconductor layer 105, the main electrode 110 and the source electrode 111 may be formed first, and then the first insulating film 106, the second insulating film 107, and the third insulating film 108 may be deposited, and then the gate electrode 109 may be formed. The drain electrode 112 on the back side may also be formed before other electrodes are formed.

[0103] about Figure 1The first embodiment of the first invention of the present application shown in FIG. 17( a ) can be regarded as replacing the gate insulating film 1106 in the first prior art example shown in FIG. 17( a ) with a stacked film including the first insulating film 106 , the second insulating film 107 and the third insulating film 108 . Therefore, the operation principle of the transistor is basically the same as the first prior art example shown in FIG. 17( a ), and the conduction electrons flowing out from the source electrode 111 flow through the conductive layer 114 in the channel region 117 including the conductive layer 113 , and then flow into the drift layer along the arrow 115 indicating the flow of the conduction electrons, and then reach the drain electrode 112 through the substrate 100 . On the other hand, the feature of this embodiment is that fixed charges 116 can be accumulated in the second insulating film 107 . The potential energy of the second insulating film 107 can be changed in accordance with the sign and amount of the accumulated charge. For example, when negative charges are accumulated, the potential energy relative to the electrons is increased, and accordingly, the gate voltage dependency of the drain current is shifted toward the positive gate voltage direction as a whole. By accumulating a sufficient amount of negative charge, the threshold voltage for substantially eliminating the conduction electrons in the channel region 117 to block the current between the source electrode and the drain electrode can be set to a positive value, thereby achieving a normally-off operation that is difficult to achieve in the first prior art example. On the other hand, when GaN is used as the first nitride semiconductor layer 104 and AlGaN is used as the second nitride semiconductor layer 105, the thickness of the second nitride semiconductor layer 105 is set to about 0.01 microns or more, which will induce a sufficient amount of conduction electrons in the conductive layer 114 to reduce the resistance of the region from the source electrode to the gate electrode. For the AlN mixed crystal ratio of the second nitride semiconductor layer 105, that is, appropriately adjusting the chemical formula expressed as Al x Ga 1-x The value of x of N is such that AlGaN having a lattice constant different from that of GaN does not cause significant lattice relaxation. Typically, x is adjusted between 0.1 and 0.4.

[0104] When negative fixed charges are to be accumulated in the second insulating film 107, a voltage that is positive compared to the source electrode 111 can be applied to the gate electrode 109, so that electrons tunnel from the second nitride semiconductor layer 105 through the first insulating film 106 and flow into the second insulating film 107. For example, silicon nitride formed by PECVD is used as the second insulating film 107, and silicon oxide is used as the first insulating film 106 and the third insulating film 108. In this case, the silicon nitride formed by PECVD contains a plurality of charge traps whose energy levels are located inside the band gap of silicon oxide, and the electrons tunneling through the first insulating film 106 are captured by the charge traps. Since the trap energy level in the silicon nitride film is located at an energy deeper than the conduction band of silicon oxide, the trapped charges are hardly released again, but are retained as fixed charges 116. In addition, when negative charges are accumulated in the second insulating film 107 by this method, the thickness of the first insulating film 106 needs to be reduced in order to obtain sufficient tunneling of electrons. However, if it is too thin, the accumulated negative charge will be released again due to tunneling. Usually, the thickness of the first insulating film 106 is set in the range of 5nm to 20nm. On the other hand, in order to prevent the charge accumulated in the second insulating film 107 from being released again due to tunneling, the third insulating film 108 is made thicker, but if it is too thick, the coupling capacitance between the gate electrode 109 and the channel region 117 will be weakened, the change in the number of conduction electrons in the channel region 117 caused by the gate voltage will become smaller, and the change in current will become smaller, so the characteristics of the transistor will deteriorate. Usually, the thickness of the third insulating film 108 is set in the range of 10nm to 40nm.

[0105] As another method of accumulating the negative fixed charge 116 in the second insulating film 107, a voltage more negative than the source electrode 111 may be applied to the gate electrode 109 to allow electrons to tunnel from the gate electrode 109 through the third insulating film 108 and be injected into the second insulating film 107. In this case, the thickness of the third insulating film is adjusted to promote tunneling.

[0106] Next, the characteristics of the vertical nitride semiconductor transistor device provided by the first embodiment of the first invention of the present application will be described. Figure 2 Yes means Figure 1 Table of device dimensions and material types in the two-dimensional device simulation of the vertical nitride semiconductor transistor device shown in FIG. The drift layer 101 includes an n-type GaN layer with a thickness of 2 μm and a doping concentration of 1×10 15 cm -3 In addition, the barrier layer 102 includes a p-type GaN layer with a thickness of 0.4 μm and a doping concentration of 1×10 17 cm -3 In addition, the first nitride semiconductor layer 104 includes a GaN layer with a thickness of 0.2 μm and a doping concentration of 1×10 15 cm-3 The second nitride semiconductor layer 105 includes an AlGaN layer with a thickness of 0.01 μm and an AlN mixed crystal ratio (expressed as Al x Ga 1-x N) is 0.3, and no dopant is doped. Regarding the gate insulating film, the first insulating film 106 and the third insulating film 108 are silicon oxide, and the second insulating film 107 is silicon nitride. The thickness is 0.01 micron. Regarding the lateral size, the width (a) 118 of the opening 103 is set to 2 microns. The channel region 117 corresponds to the conductive layer 113 outside the opening 103, and its width (b) 119 is set to 1 micron. In addition, the distance (c) 120 between the gate electrode 109 and the source electrode 111 is set to 1 micron. In addition, the main electrode 110 is not included in the two-dimensional device simulation.

[0107] Next, the simulation results are described. Figure 3 The depth dependence of the conduction band energy in the drift layer 101 below the opening 103 is shown. The gate is in the on state. In addition, the source electrode 111 is grounded, and the voltage of the drain electrode 112 is 10 V. It can be seen that the potential changes gently in the depth direction in the drift layer. Figure 4 The drain voltage dependency of the drain current is shown. No fixed charge is accumulated in the second insulating film 107. The gate voltage is changed from -5 V to 4 V in 1 V increments, and the drain voltage is scanned at each gate voltage. Figure 4 The drain current on the vertical axis is the current that the transistor device maintains when Figure 1 The current value per unit mm when extending in a direction perpendicular to the paper surface in the state of the cross-sectional structure shown in the figure. The on-resistance and on-current desired as a switching element are obtained. Figure 5 The characteristic is when the drain voltage is fixed at 10V and the gate voltage is scanned. The figure shows three curves, but they represent the case of changing the negative fixed charge 116 accumulated in the second insulating film 107. Assuming that the negative fixed charge 116 is accumulated in the second insulating film 107 below the gate electrode 109 in a uniformly distributed manner in both the vertical and horizontal directions, Figure 5 The curve represents the negative charge density per unit volume from the left to the right, which is 0, 1×10 19 cm -3 , 2×10 19 cm -3 As the amount of negative charge accumulated in the second insulating film increases, the current-voltage characteristic shifts toward the positive gate voltage side, and when the negative charge density is 2×10 19 cm -3 When , the threshold voltage for blocking the drain current becomes 3.4V. As a high-power switch with a threshold voltage exceeding 3V, the desired normally-off characteristics can be achieved.

[0108] exist Figure 1 In a preferred form of the first embodiment of the first invention of the present application shown, a stacked film composed of aluminum oxide as the lower layer and silicon oxide as the upper layer is used as the first insulating film 106. Aluminum oxide is not easy to generate interface trap energy levels at the interface with the nitride semiconductor layer, so when a positive voltage is applied to the gate electrode to increase the number of conduction electrons in the channel region to increase the flowing current, it is not easily affected by the interface trap energy levels existing at the interface between the nitride semiconductor in the channel region and the first insulating film. As a result, a vertical nitride semiconductor transistor device with excellent on-resistance, which is one of the important characteristics of a switch, can be obtained.

[0109] Figure 61 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by the second embodiment of the first invention of the present application. The process is the same as the first embodiment of the first invention of the present application until a drift layer 101, a barrier layer 102, an opening 103, a first nitride semiconductor layer 104, and a second nitride semiconductor layer 205 are formed on a substrate 100. Thereafter, a field insulating film 218 is deposited, and the field insulating film 218 of the gate electrode forming portion is removed, and then the second nitride semiconductor layer 205 is etched to reduce the thickness. For the field insulating film 218, aluminum oxide, silicon oxide, silicon nitride, or a multilayer film thereof can be used. Subsequently, a first insulating film 206, a second insulating film 207, and a third insulating film 208 are deposited in sequence, and finally a gate electrode 209 is formed. In the transistor device of this embodiment, since the second nitride semiconductor layer 205 in the gate electrode forming portion is thinned and the influence of the polarized charge is weakened, the number of conduction electrons induced in the conductive layer 213 is reduced, and the threshold voltage before the fixed charge is accumulated in the second insulating film 207 becomes a negative voltage smaller than that of the first embodiment of the first invention of this application. Therefore, the amount of negative fixed charge 216 accumulated in the second insulating film 207 in order to make the threshold voltage a positive voltage to obtain the desired normally-off characteristics can be reduced. On the other hand, by maintaining the original thickness of the second nitride semiconductor layer between the gate electrode 209 and the source electrode 111, the number of conduction electrons induced in this portion of the conductive layer 214 does not decrease, so that the electrical connection from the source electrode 111 to the channel region 217 can be obtained with low resistance. The material and film forming method of the second insulating film 207 are selected in such a way that the film contains the following charge traps: the energy level of the charge traps is located inside the band gap of at least a part of the first insulating film 206 and inside the band gap of at least a part of the third insulating film 208, which is the same as the first embodiment of the first invention of the present application. In addition, after the nitride semiconductor layer 205 of the opening part of the field insulating film 218 is etched, the remaining field insulating film 218 is removed, and then the first insulating film 206, the second insulating film 207, and the third insulating film 208 are deposited. In addition, the main electrode 110 and the source electrode 111 may be formed before the gate electrode 209 is formed, for example, the main electrode 110 is formed first, and then the field insulating film 218 is deposited, and the source electrode 111 is formed after the field insulating film 218 of the source electrode forming part is removed, and then the second nitride semiconductor layer 205 is etched after the field insulating film 218 of the gate electrode forming part is removed, and then the gate part process is performed until the gate electrode 209 is formed.

[0110] Figure 7: is a cross-sectional view of a vertical nitride semiconductor transistor device provided by the third embodiment of the first invention of the present application. In this embodiment, a p-type nitride semiconductor layer or a high-resistance nitride semiconductor layer grown on the drift layer 101 is used for the barrier layer 302, and an opening 303 with an inclination is formed by etching, and then a first nitride semiconductor layer 304 and a second nitride semiconductor layer 305 are grown on the upper surface of the opening 303 including the inclination, and then a first insulating film 306, a second insulating film 307, and a third insulating film 308 are sequentially deposited thereon, and then a gate electrode 309 is formed thereon in a manner covering the entire surface of the opening 303. The rest is the same as the first embodiment of the first invention of the present application. In this embodiment, at least a portion of the conductive layer 313 is formed on the inclination of the opening 303. The conductive layer 313 of the inclination forms a channel region 317, and the conduction electrons flowing out from the source electrode flow from the conductive layer 314 through the channel region 317 and along the arrow 315 into the drift layer 101. As described in the third prior art example, when the crystal plane orientation of the stacked structure of the nitride semiconductor deviates from the c-axis direction, the generated polarization weakens. Therefore, when compared before the fixed charge is accumulated in the second insulating film 307, the threshold voltage becomes a negative voltage smaller than the first embodiment of the first invention of the present application. Therefore, the amount of negative fixed charge 316 accumulated in the second insulating film 307 in order to make the threshold voltage a sufficiently large positive voltage to obtain the desired normally-off characteristics can be reduced. In addition, in the case where the deviation of the threshold voltage becomes a problem, the deviation can be reduced by adjusting the amount of charge accumulated in the second insulating film 307 for each transistor. The second insulating film 307 selects the material and the film forming method in such a way that the following charge traps are included in the film: the energy level of the charge trap is located inside the band gap of the first insulating film 306 and inside the band gap of the third insulating film 308, which is the same as the first embodiment of the first invention of the present application.

[0111] Figure 81 is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by the fourth embodiment of the first invention of the present application. A drift layer 401 is epitaxially grown on a substrate 400. So far, it is the same as the first embodiment of the first invention of the present application. Then, a third nitride semiconductor layer 402 having a p-type conductivity and a fourth nitride semiconductor layer 403 having an n-type conductivity are grown on the drift layer 401. In a preferred example, GaN is used as the third nitride semiconductor layer 402 and the fourth nitride semiconductor layer 403. Then, a groove 405 is formed that penetrates the fourth nitride semiconductor layer 403 and the third nitride semiconductor layer 402 and reaches the drift layer 401. Then, a first insulating film 406, a second insulating film 407, and a third insulating film 408 are sequentially deposited in a manner covering the inside of the groove 405. The types, properties, and deposition methods of the insulating films are as described in the first embodiment of the first invention of the present application. In addition, in order to improve the characteristics of the interface between the insulating film and the nitride semiconductor, a thin nitride semiconductor layer such as a GaN layer may be grown inside the groove 405, and then the first insulating film 406, the second insulating film 407, and the third insulating film 408 are deposited in sequence. Typically, the thickness of the thin nitride semiconductor layer is selected in the range of 1 nm to 20 nm. Subsequently, a gate electrode 409 is formed in a manner covering the inner surface of the groove 405. A main body electrode 410 is provided in a manner electrically contacting the third nitride semiconductor layer 402 used as a main body region. Then, a source electrode 411 is provided in a manner electrically contacting the fourth nitride semiconductor layer 403 and the main body electrode 410. The main body electrode 410 may be provided for the purpose of fixing the main body region to the same potential as the source electrode, but it may not be provided. The drain electrode 412 is provided on the back side of the substrate 400. In addition, the source electrode 411 may be formed before the gate electrode 409 is formed. For example, after forming the fourth nitride semiconductor layer 403, the main electrode 410 and the source electrode 411 may be formed first, and then the trench 405 may be formed, and then the first insulating film 406, the second insulating film 407, and the third insulating film 408 may be deposited, and the gate electrode 409 may be formed. The drain electrode 412 on the back side may also be formed before the other electrodes are formed.

[0112] about Figure 8 The fourth embodiment of the first invention of the present application shown can be regarded as Fig.19 The gate insulating film 1305 in the fourth conventional example shown in FIG. 1 is replaced with a stacked film including a first insulating film 406, a second insulating film 407, and a third insulating film 408. Therefore, the operating principle of the transistor is basically the same as that of FIG. Fig.19As in the fourth conventional example shown in FIG. 1 , the conduction electrons flowing out from the source electrode 411 flow in the fourth nitride semiconductor layer 403 along the direction of the groove along the arrow 414 indicating the flow of the conduction electrons, and then flow into the drift layer 401 along the direction of the arrow 415 indicating the flow of the conduction electrons via the channel region 417 including the inverted conductive layer 413, and then reach the drain electrode 412 through the substrate 400. Figure 8 In the fourth embodiment of the first invention of the present application shown, the threshold voltage can be adjusted by accumulating fixed charges 416 in the second insulating film 407 to eliminate the conduction electrons in the channel region 417, thereby blocking the current between the source electrode 411 and the drain electrode 412. In particular, negative fixed charges 416 can be accumulated in the second insulating film 407 to make the threshold voltage positive. Alternatively, in the case where the threshold voltage before charge accumulation is already positive, it can be adjusted to a desired threshold voltage by accumulating negative charges or positive charges. Alternatively, the threshold voltage deviation before accumulation can be reduced by adjusting the accumulated charge for each transistor. A positive voltage relative to the source electrode 411 can be applied to the gate electrode 409, so that electrons are injected from the conductive layer 413 into the second insulating film 407 via tunneling through the first insulating film 406, and fixed charges 416 can be accumulated in the second insulating film 407. For example, when silicon nitride deposited by PECVD is used as the second insulating film 407, and silicon oxide is used as the first insulating film 406 and the third insulating film 408, the PECVD silicon nitride film includes a plurality of charge traps whose energy level is located inside the band gap of silicon oxide, and the electrons tunneling through the first insulating film 406 are captured by the charge traps. Once the trapped charges are located at an energy level deeper than the conduction band of the first insulating film 406 and the third insulating film 408 including silicon oxide, they are hardly released again, but are retained as fixed charges. Alternatively, by applying a negative voltage to the gate electrode 409 relative to the source electrode 411, electrons can be injected from the gate electrode 409 into the second insulating film 407 by tunneling through the third insulating film 408. In this case, the thickness of the third insulating film 408 is reduced to promote tunneling. When the accumulation of positive fixed charges in the insulating film 407 is carried out by hole injection, this can be achieved by hole tunneling from the third nitride semiconductor layer 402 or the gate electrode 409, and the hole tunneling is controlled by selecting appropriate materials and thicknesses of the first insulating film 406 and the third insulating film 408 and adjusting the voltage applied to the gate electrode 409 and the source electrode 411.

[0113] Fig. 9: is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by the fifth embodiment of the first invention of the present application. The difference between this embodiment and the fourth embodiment of the first invention of the present application is that after the third nitride semiconductor layer 402 having a p-type conductivity is grown, a nitride semiconductor layer including two layers of a first nitride semiconductor layer 503 and a second nitride semiconductor layer 504 is formed as a layer equivalent to the fourth nitride semiconductor layer. Here, as in the first embodiment of the first invention of the present application, the second nitride semiconductor layer 504 at least includes a nitride semiconductor having a larger band gap than at least a part of the nitride semiconductor of the first nitride semiconductor layer 503. For example, GaN is used as the first nitride semiconductor layer 503, and AlGaN is used as the second nitride semiconductor layer 504. Thus, a conductive layer 514 containing a two-dimensional electron gas is formed on the first nitride semiconductor layer 503 side of the interface between the second nitride semiconductor layer 504 and the first nitride semiconductor layer 503. The nitride semiconductor layer composed of the first nitride semiconductor layer 503 and the second nitride semiconductor layer 504 can induce conduction electrons in the conductive layer 514 by the effect of polarization charge even when n-type doping is not performed, so that n-type conductivity can be substantially obtained. However, in order to promote the electron current toward the channel region 517 including the inverted conductive layer 513, n-type dopants can be doped in the first nitride semiconductor layer 503. In the transistor of this embodiment, the conduction electrons flowing out from the source electrode 411 flow into the drift layer 401 via the conductive layer 514 and the channel region 517 in the direction of the arrow 515 indicating the flow of the conduction electrons.

[0114] Fig.10: is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by the first embodiment of the second invention of the present application. A drift layer 601 is epitaxially grown on a substrate 600. The substrate 600 may use GaN, SiC, Si, etc. of n-type conductivity. In the case of epitaxially growing a nitride semiconductor, good crystallinity can be obtained by growing the nitride semiconductor along the c-axis direction. Therefore, the substrate 600 preferably uses a single crystal substrate having a crystal plane orientation that allows epitaxial growth in the c-axis direction. For example, in the case of using a GaN substrate or a SiC substrate having a hexagonal crystal structure, a single crystal substrate having a crystal plane orientation of the substrate in the c-axis direction is used. In the case of using a GaN substrate, it is preferred to use a substrate having a Ga face as the surface, which is particularly easy for epitaxial crystal growth. In addition, in the case of using a Si substrate, if a substrate having a crystal plane orientation of (111) is used, epitaxial growth of a nitride semiconductor in the c-axis direction can be obtained. A buffer layer may also be inserted between the substrate 600 and the drift layer 601 for the purpose of improving the crystallinity of the drift layer 601 during epitaxial growth. In addition, the drift layer 601 may be made of n-type GaN, n-type AlGaN, or AlGaN with a composition gradient. A barrier layer 602, a first nitride semiconductor layer 604, and a second nitride semiconductor layer 605 are provided on the upper part of the drift layer 601. The barrier layer 602 is provided for the purpose of blocking the flow of conduction electrons, but an opening 603 that does not block the flow of conduction electrons is provided in a part thereof. There are various methods for making the opening 603. For example, the barrier layer 602 may be formed on the entire surface of the drift layer 601, and a part of the opening 603 may be removed by wet etching or dry etching, and then the first nitride semiconductor layer 604 and the second nitride semiconductor layer 605 may be grown to fill the opening 603. In this case, for the barrier layer 602, p-type GaN, p-type AlGaN, a high-resistance nitride semiconductor doped with a dopant for forming a deep trap level, an insulating film, or a stacked structure thereof, etc., which are epitaxially grown on the drift layer 601, are used. Alternatively, after the drift layer 601 is grown, a p-type dopant may be selectively introduced into the surface portion other than the opening by ion implantation, and activated by a subsequent thermal process, thereby forming a barrier layer 602 including a p-type layer. Alternatively, after the drift layer 601, the barrier layer 602 including a p-type nitride semiconductor, the first nitride semiconductor layer 604, and the second nitride semiconductor layer 605 are sequentially epitaxially grown, an n-type dopant may be selectively ion implanted into the opening 603, and activated by a subsequent thermal process, thereby inverting the barrier layer 602 in the opening 603 to an n-type. The second nitride semiconductor layer 605 includes at least a nitride semiconductor having a larger band gap than at least a portion of the nitride semiconductor of the first nitride semiconductor layer 604. For example, GaN is used as the first nitride semiconductor layer 604, and AlGaN is used as the second nitride semiconductor layer 605.Thus, a conductive layer 613 ( ) containing a two-dimensional electron gas is formed on the first nitride semiconductor layer 604 side of the interface between the second nitride semiconductor layer 605 and the first nitride semiconductor layer 604 . Fig.10 ) and the conductive layer 614 ( Fig.10 The channel region 617 is shown by a thin dashed line. Fig.10 In the figure, it is represented by a dotted ellipse. In order to promote the conduction of electrons from the channel region 617 to the drift layer 601 through the opening 603, n-type dopants may also be doped in the first nitride semiconductor layer 604. The above process is the same as the first embodiment of the first invention of the present application. Then, a field insulating film 616 is deposited on the second nitride semiconductor layer 605, and the field insulating film 616 of the gate electrode forming portion is removed. Then, a fourth insulating film 606 is deposited, and a charge storage electrode 607 is formed thereon. At this time, it is ideal as follows Fig.10 As shown, the charge storage electrode 607 is formed in a manner of being mounted on the portion where the field insulating film 616 exists, so that the area of ​​the upper part of the charge storage electrode is larger than the area of ​​the lower part. Then, the fifth insulating film 608 is deposited on the charge storage electrode 607. The periphery of the charge storage electrode 607 is covered by the fourth insulating film 606 and the fifth insulating film 608, so that it becomes an electrically floating state. In the fourth insulating film and the fifth insulating film, a conventionally known insulating material can be used, such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film or a stacked film thereof. In addition, as the charge storage electrode 607, not only a metal layer but also polysilicon doped with dopants can be used. In this case, phosphorus, arsenic, boron, etc. are used as dopants. Then, a gate electrode 609 is formed on the fifth insulating film 608 so as to form a capacitor together with the charge storage electrode. A source electrode 611 is formed on the second nitride semiconductor layer 605 so as to obtain a good electrical connection with low resistance relative to the conductive layer 614. As an electrode material, for example, a multilayer film composed of a lower layer of Ti and an upper layer of Al is used. In addition, when a p-type nitride semiconductor is used in the barrier layer 602, a main electrode 610 may also be provided to fix the potential. As an electrode material, for example, Pd, Pt, Ni, etc. are used. The source electrode 611 is formed so as to be in electrical contact with the main electrode 610 at the same time. The drain electrode 612 is formed on the back side of the substrate 600. In addition, the formation of the main electrode 610 and the source electrode 611 can be performed before the gate electrode 609 is formed. For example, after the second nitride semiconductor layer 605 is grown, the main electrode 610 can be formed first, and then the field insulating film 616 can be deposited, and the field insulating film 616 used to form the source electrode is removed to form the source electrode 611, and then the field insulating film 616 used to form the gate electrode is removed, and then the gate part process is performed until the gate electrode 609 is formed. The drain electrode 612 on the back side can also be formed before the other electrodes are formed.

[0115] Next, the operating principle of the vertical nitride semiconductor transistor device provided by the first embodiment of the second invention of the present application is described. As in the first embodiment of the first invention of the present application, the conduction electrons flowing out from the source electrode flow into the drift layer 601 from the conductive layer 614 and the channel region 617 through the opening 603 as shown by the arrow 615 indicating the flow of the conduction electrons, and then reach the drain electrode 612 through the substrate 600. On the other hand, the voltage applied to the gate electrode 609 is transmitted to the channel region 617 through the charge storage electrode 607 by capacitive coupling, so that the number of conduction electrons in the region can be changed. The gate voltage when the number of conduction electrons in the channel region 617 is substantially zero and the current flowing between the source electrode 611 and the drain electrode 612 is blocked is the threshold voltage, but the value of the voltage can be changed according to the charge accumulated in the charge storage electrode 607. For example, when negative charges are accumulated in the charge storage electrode 607, the potential energy of the charge storage electrode 607 relative to the electrons is increased. As a result, the gate voltage dependency of the drain current shifts toward the positive gate voltage direction as a whole. If a sufficient amount of negative charge is provided, a normally-off operation with a positive threshold voltage can be realized.

[0116] Next, the method of accumulating negative charges to the charge accumulation electrode 607 of the first embodiment of the second invention of the present application is described. A voltage that is positive compared to the source electrode 611 can be applied to the gate electrode 609, so that electrons tunnel from the second nitride semiconductor layer 605 through the fourth insulating film 606 and are injected into the charge accumulation electrode 607. In this case, it is necessary to reduce the thickness of the fourth insulating film 606 in order to obtain sufficient tunneling current. However, if it is too thin, the accumulated negative charges are released again due to tunneling. Usually, the thickness of the fourth insulating film 606 is set in the range of 5nm to 20nm. On the other hand, in order to prevent the charges accumulated in the charge accumulation electrode 607 from being released again due to tunneling, the thickness of the fifth insulating film 608 is made thicker, but if it is too thick, the coupling capacitance between the gate electrode 609 and the charge accumulation electrode 607 will be weakened, the change in the number of conduction electrons in the channel region 617 caused by the gate voltage will become smaller, and the amount of change in the current will become smaller, so the characteristics of the transistor will deteriorate. Typically, the thickness of the fifth insulating film 608 is set to be in the range of 10 nm to 40 nm.

[0117] As another method of accumulating negative charges in the charge storage electrode 607, a voltage that is negative compared to the source electrode 611 may be applied to the gate electrode 609 so that electrons tunnel from the gate electrode 609 through the fifth insulating film 608. In this case, the thickness of the fifth insulating film 608 is reduced to promote tunneling. In addition, by designing the thickness of the fourth insulating film 606 and the fifth insulating film 608, etc., so that the outflow of electrons from the charge storage electrode 607 to the second nitride semiconductor layer 605 becomes dominant, it is also possible to accumulate positive charges in the charge storage electrode 607. Furthermore, by designing, it is also possible to make the outflow of electrons from the charge storage electrode 607 to the gate electrode 609 dominant when a voltage that is positive compared to the source electrode is applied to the gate electrode 609, thereby accumulating positive charges in the charge storage electrode.

[0118] Fig.11 6 is a diagram showing capacitors between nodes in the first embodiment of the second invention of the present application. The first capacitor 630 is a coupling capacitor between the conductive layer 613 and the charge storage electrode 607. The conductive layer 613 forms a channel region 617, and the number of conduction electrons changes according to the voltage applied to the gate electrode 609. When conduction electrons are accumulated in the conductive layer 613, that is, the switch is in the on state, and when the conduction electrons in the conductive layer 613 are exhausted and the switch is in the off state, Fig.11 The capacitance value of the first capacitor 630 is different, being larger in the on state and smaller in the off state. On the other hand, the second capacitor 631 is a coupling capacitor between the charge storage electrode 607 and the gate electrode 609. Here, the case where the switch is in the on state is described. In the on state, the value of the first capacitor 630 becomes larger, but ideally the second capacitor 631 is larger. Thus, the dependence of the number of conduction electrons induced in the channel region 617 on the voltage applied to the gate electrode 609, i.e., the gate voltage, can be increased. Fig.10 In the first embodiment of the second invention of the present application shown in the figure, the charge storage electrode 607 is formed in a manner that is bridged over the portion where the field insulating film 616 exists, so that the area of ​​the second capacitor 631 is larger than the area of ​​the first capacitor 630. Therefore, even when the insulating films with the same dielectric constant and thickness are used for the fourth insulating film 606 and the fifth insulating film 608, the second capacitor 631 can be made larger than the first capacitor 630 in proportion to the area, and a transistor device with excellent characteristics as a switch can be obtained. In addition, in order to make the second capacitor 631 larger than the first capacitor 630, the dielectric constant of the fifth insulating film 608 can be made larger than that of the fourth insulating film 606.

[0119] Fig.12, a cross-sectional view and a plan view of a vertical nitride semiconductor transistor device provided by the second embodiment of the second invention of the present application are shown. The cross-sectional view shows both the A-A' cross-section and the BB' cross-section. The difference from the first embodiment of the second invention of the present application is that a charge injection electrode 620 is provided which is capacitively coupled to the charge storage electrode 607 via an insulating film. Hereinafter, this capacitor is referred to as a third capacitor 632. For example, Fig.12As shown in the BB' cross-sectional view, the charge injection electrode 620 is formed at the lower part of the charge storage electrode 607 across the sixth insulating film 619. In this case, the third capacitor 632 is formed by using the sixth insulating film 619 as a capacitive coupling film, and the first capacitor 630 is formed by using the stacked film of the fourth insulating film 606 and the sixth insulating film 619 as a capacitive coupling film. If the thickness of the sixth insulating film 619 is reduced, the electron injection into the charge storage electrode 607 by tunneling through the third capacitor 632 will become easy. On the other hand, the thickness of the capacitive coupling film of the first capacitor 630 can be adjusted by the thickness of the fourth insulating film 606. When making the charge injection electrode 620 and the third capacitor 632, various variations can be considered. For example, the charge injection electrode 620 can be formed on the field insulating film 616 without forming the sixth insulating film, and the fourth insulating film can be formed thereon, so that the first capacitor 630 and the third capacitor 632 are both made by using the fourth insulating film as a capacitive coupling film. In this case, the thickness of the capacitive coupling film of the third capacitor 632 becomes thicker, but the third capacitor 632 can be provided with an edge portion 621 as shown in the figure, and tunneling between the two electrodes is promoted by concentrating the electric field at the edge portion, so that electron injection can be performed relatively easily. Alternatively, a charge injection electrode 620 can be formed on the upper portion of the charge storage electrode 607. In this case, for example, if a sixth insulating film 620 is formed on the upper portion of the charge storage electrode 607 after the charge storage electrode 607 is formed, and a charge injection electrode 620 is further formed thereon, a third capacitor 632 using the sixth insulating film 620 as a capacitive coupling film can be obtained. Subsequently, a fifth insulating film 608 is formed, and a gate electrode 609 is formed thereon. While the sixth insulating film having a portion where the gate electrode 609 is formed is retained, the second capacitor 631 uses a laminated film of the fifth insulating film 608 and the sixth insulating film 619 as a capacitive coupling film. Alternatively, after the sixth insulating film 619 for forming the portion of the gate electrode 609 is removed, the fifth insulating film 608 may be formed, and the gate electrode 609 may be formed thereon. In this case, the second capacitor 631 uses only the fifth insulating film 608 as a capacitive coupling film. In either method, the types and thicknesses of the capacitive coupling films of the first capacitor 630, the second capacitor 631, and the third capacitor 632 are optimized according to their respective uses. For example, the thickness of the capacitive coupling film of the third capacitor 632 facilitates charge injection through tunneling. In the case where tunneling promotion caused by electric field concentration in the edge portion is not used, the thickness of the insulating film is generally set to a range of 5 nm to 20 nm. On the other hand, the thickness of the capacitive coupling films of the first capacitor 630 and the second capacitor 631 is preferably relatively thick, generally set to a range of 10 nm to 40 nm.In addition, if the charge injection electrode 620 is also formed on the upper part of the charge storage electrode 607, if the charge injection electrode 620 is formed in a manner covering the edge portion such as the end portion of the upper surface of the charge storage electrode 607, the tunneling promotion effect of the edge portion can be utilized.

[0120] exist Fig.12 In the embodiment, the charge storage electrode 607 is a separate finger-shaped object, and the transistor device as a whole preferably includes a plurality of separate charge storage electrodes 607. Therefore, even if the charge stored in the charge storage electrode 607 leaks due to a local defect or damage and the threshold voltage changes, the influence is limited to the individual charge storage electrode 607, so that the increase of the drain leakage current in the off state can be suppressed as much as possible as a whole. Fig.12 In the embodiment, each finger includes one charge storage electrode 607, but each finger may be further subdivided so that each finger includes a plurality of charge storage electrodes 607. In addition, regarding the pad for supplying power to the charge injection electrode 620, a common pad may be provided for all the charge injection electrodes 620, or the charge injection electrodes 620 may be separately connected to a plurality of pads.

[0121] Fig.13 FIG. 4 shows an equivalent circuit of capacitors between nodes in the second embodiment of the second invention of the present application. In the equivalent circuit of capacitors between nodes in this embodiment, Fig.11 The first embodiment of the second invention of the present application shown in the figure adds a third capacitor 632. In order to improve the characteristics when the switch is turned on, it is ideal to make the second capacitor 631 larger than the first capacitor 630 when the switch is turned on. For this purpose, for example, it is preferred to make the area of ​​the second capacitor 631 larger than the area of ​​the first capacitor 630, which is the same as the first embodiment of the second invention of the present application. For example, Fig.12 As shown in the A-A' cross-sectional view and the BB' cross-sectional view, by forming the charge storage electrode 607 in a manner that is bridged over the portion where the field insulating film 616 exists, the area of ​​the second capacitor 631 formed between the charge storage electrode 607 and the gate electrode 609 can be made larger than the area of ​​the first capacitor 630 formed between the charge storage electrode 607 and the conductive layer 613, thereby even if the dielectric films used for the first capacitor 630 and the second capacitor 631 have the same dielectric constant and thickness, the capacitance value of the second capacitor 631 can be made large.

[0122] Next, about Fig.13The capacitance value of the third capacitor 632 shown in FIG. 1 is described in conjunction with the method of accumulating charges in the charge accumulating electrode 607. In the second embodiment of the second invention of the present application, the accumulation of negative charges in the charge accumulating electrode 607 is performed by applying a voltage that is negative compared to the gate electrode 609 to the charge injection electrode 620. At this time, since the charge accumulating electrode 607 is capacitively coupled to the gate electrode 609 through the second capacitor 631, a voltage is applied to the third capacitor 632 between the charge injection electrode 620 and the charge accumulating electrode 607, and electrons tunnel through the capacitive coupling film from the charge injection electrode 620 and flow into the charge accumulating electrode 607. When it is desired to store positive charges in the charge storage electrode 607, if a voltage that is more positive than the gate electrode 609 is applied to the charge injection electrode 620, electrons flow from the charge storage electrode 607 to the charge injection electrode 620 by tunneling through the capacitive coupling film of the third capacitor 632, and as a result, positive charges are accumulated in the charge storage electrode 607. In either method, the accumulation of charges in the charge storage electrode 607 is performed by the current flowing through the third capacitor 632. Here, the case of accumulating negative charges in the charge storage electrode 607 is described in more detail. When a negative voltage is applied to the charge injection electrode 620 compared to the gate electrode 609, the capacitance coupling between the gate electrode 609 and the charge storage electrode 607 becomes stronger by making the capacitance value of the second capacitor 631 greater than the capacitance value of the third capacitor 632, and a larger voltage is applied between the third capacitor 632, that is, the charge injection electrode 620 and the charge storage electrode 607, so that the electrons from the charge injection electrode 620 to the charge storage electrode 607 by tunneling can be promoted. The accumulation of charges to the charge storage electrode 607 can be carried out by fixing the potential of the source electrode. For example, the source electrode 611 is grounded together with the gate electrode 609, and a negative voltage is applied to the charge injection electrode 620. The threshold voltage of the transistor before the accumulation of negative charges is usually a negative value, and the transistor is in the on state, so the capacitance value of the first capacitor 630 is large. Therefore, the potential of the charge storage electrode 607 is strongly fixed by the capacitive coupling of the second capacitor 631 and the first capacitor 630, so most of the voltage applied to the charge injection electrode 620 is applied to the third capacitor 632, which promotes the injection of electrons into the charge storage electrode 607 by tunneling.

[0123] Fig.14: is a cross-sectional view showing a vertical nitride semiconductor transistor device provided by the third embodiment of the second invention of the present application. In this embodiment, a p-type nitride semiconductor layer or a high-resistance nitride semiconductor layer grown on the drift layer 601 is used as a barrier layer 702, and an opening portion 703 having an inclination is formed by etching, and then a first nitride semiconductor layer 704 and a second nitride semiconductor layer 705 are grown on the upper surface of the opening portion 703 including the inclination portion, and then a field insulating film 716 is deposited on the second nitride semiconductor layer 705, and the field insulating film 716 of the gate electrode forming portion is removed. Then, a fourth insulating film 706 is deposited, and a charge storage electrode 707 is formed thereon. At this time, it is desirable to form the charge storage electrode 707 in a manner that is bridged over the portion where the field insulating film 716 exists, thereby expanding the area of ​​the upper portion of the charge storage electrode 707. Then, a fifth insulating film 708 is deposited on the charge storage electrode 707. The rest is the same as the first embodiment of the second invention of the present application. In this embodiment, at least a portion of the conductive layer 713 is formed at the inclined portion of the opening 703. The conductive layer 713 at the inclined portion forms a channel region 717, and the conduction electrons flowing out from the source electrode flow from the conductive layer 714 through the channel region 717 and into the drift layer 601 along the arrow 715 indicating the flow of the conduction electrons. As described in the third prior art example, when the crystal plane orientation of the stacked structure of the nitride semiconductor deviates from the c-axis direction, the generated polarization weakens. Therefore, when compared before the charge is accumulated in the charge accumulation electrode, the threshold voltage for substantially eliminating the conduction electrons in the channel region 717 to block the current between the source electrode 611 and the drain electrode 612 is a negative voltage smaller than that of the first embodiment of the second invention of the present application. Therefore, the amount of negative charge that needs to be stored in the charge accumulation electrode 707 in order to obtain the desired normally-off characteristics can be reduced. The method of accumulating negative and positive charges in the charge accumulation electrode 707 can be the same as the negative charge accumulation method described above in the first embodiment of the second invention of the present application. Alternatively, when a current injection electrode is used as in the second embodiment of the second invention of the present application, the charge accumulation method can be performed in the same manner as the above-mentioned second embodiment of the second invention of the present application.

[0124] Fig.15A cross-sectional view of a vertical nitride semiconductor transistor device provided by the fourth embodiment of the second invention of the present application is shown. A drift layer 801, a third nitride semiconductor layer 802 having a p-type conductivity, and a fourth nitride semiconductor layer 803 having an n-type conductivity are sequentially grown on a substrate 800. So far, it is the same as the fourth embodiment of the first invention of the present application. Then, after a field insulating film 816 is deposited and an opening is formed in the gate electrode forming portion, the opening is used as a mask to form a trench 805 that penetrates the fourth nitride semiconductor layer 803 and the third nitride semiconductor layer 802 and reaches the drift layer 801. Then, a fourth insulating film 806 is formed in a manner covering the inside of the trench 805. For the purpose of improving the characteristics of the interface between the insulating film and the nitride semiconductor, the fourth insulating film 806 may also be formed after a thin nitride semiconductor layer, such as a GaN layer, is grown inside the trench 805. Furthermore, a charge storage electrode 807 is formed inside the groove 803, and a fifth insulating film 808 is formed, and a gate electrode 809 is formed thereon. A main body electrode 810 is provided in electrical contact with the third nitride semiconductor layer 802, and a source electrode is provided in electrical contact with the fourth nitride semiconductor layer 803 and the main body electrode 810. In addition, a drain electrode is provided in electrical contact with the substrate 800 from the back. In addition, as described in the first embodiment of the second invention of the present application, the main body electrode 810 and the source electrode 811 can be formed before the gate electrode 809 is formed. The materials of the fourth insulating film 806, the fifth insulating film 808, and the charge storage electrode 807 are also the same as those of the first embodiment of the second invention of the present application.

[0125] exist Fig.15 In the vertical nitride semiconductor transistor device provided by the fourth embodiment of the second invention of the present application, similarly to the fourth embodiment of the first invention of the present application, the conduction electrons flowing out from the source electrode 811 flow in the fourth nitride semiconductor layer 803 in the groove direction along the arrow 814 indicating the flow of the conduction electrons, and then flow into the drift layer 801 in the direction of the arrow 815 indicating the flow of the conduction electrons via the channel region 817 including the inverted conductive layer 813, and then reach the drain electrode 812 through the substrate 800. On the other hand, Fig.15 In the fourth embodiment of the second invention of the present application, by accumulating charges in the charge accumulation electrode 807, the threshold voltage for blocking the current between the source electrode 811 and the drain electrode 812 by substantially eliminating the conduction electrons in the channel region 817 can be adjusted. In particular, negative charges can be accumulated in the charge accumulation electrode 807 to make the threshold voltage positive. Alternatively, in the case where the threshold voltage before charge accumulation is already positive, the threshold voltage can be adjusted to a desired value by accumulating negative charges or positive charges. Alternatively, the threshold voltage variation can be reduced by adjusting the accumulated charge for each transistor.

[0126] The accumulation of negative charges in the charge storage electrode 807 can be accomplished by electrons tunneling from the conductive layer 813, the fourth nitride semiconductor layer 803, or the drift layer 801 through the fourth insulating film 806 and flowing into the charge storage electrode 807, and this can be achieved by applying a positive voltage to the gate electrode 809 relative to the source electrode 811. If the fifth insulating film 808 is thin enough, electrons can also flow from the gate electrode 809 to the charge storage electrode 807 by tunneling through the fifth insulating film 808, thereby accumulating negative charges in the charge storage electrode 807, and this can be achieved by applying a negative voltage to the gate electrode 809 relative to the source electrode 811. On the other hand, the accumulation of positive charges in the charge storage electrode 807 can be performed by designing the thickness of the fourth insulating film 806 and the fifth insulating film 808 so that, when a negative voltage is applied to the gate electrode 809 compared to the source electrode 811, the tunneling of electrons from the charge storage electrode 807 to the third nitride semiconductor layer 802 or the tunneling of holes from the third nitride semiconductor layer 802 to the charge storage electrode 807 becomes dominant. Alternatively, the accumulation of positive charges in the charge storage electrode 807 can be performed by designing the thickness of the fourth insulating film 806 and the fifth insulating film 808 so that, when a positive voltage is applied to the gate electrode 809 compared to the source electrode 811, the tunneling of electrons from the charge storage electrode 807 to the gate electrode 809 becomes dominant.

[0127] As another method of accumulating charge in the charge accumulating electrode 807, a charge injecting electrode may be provided as in the second embodiment of the second invention of this application, and the charge accumulating method described in the second embodiment of the second invention of this application may be performed in the same manner.

[0128] As in the first and second embodiments of the second invention of this application, Fig.15 As shown, the charge storage electrode 807 is formed so as to bridge the portion where the field insulating film 816 exists, thereby increasing the area of ​​the capacitor formed between the charge storage electrode 807 and the gate electrode 809, which is beneficial for improving the characteristics of the transistor as a switch.

[0129] Fig.16The cross-sectional view of the vertical nitride semiconductor transistor device provided by the fifth embodiment of the second invention of the present application is shown. The difference between this embodiment and the fourth embodiment of the second invention of the present application is that after the third nitride semiconductor layer 802 having a p-type conductivity is grown, a nitride semiconductor layer consisting of two layers, a first nitride semiconductor layer 903 and a second nitride semiconductor layer 904, is formed as a layer equivalent to the fourth nitride semiconductor layer. Here, as in the first embodiment of the second invention of the present application, the second nitride semiconductor layer 904 at least includes a nitride semiconductor having a larger band gap than at least a part of the nitride semiconductor of the first nitride semiconductor layer 903. For example, GaN is used as the first nitride semiconductor layer 903, and AlGaN is used as the second nitride semiconductor layer 904. Thus, a conductive layer 914 containing a two-dimensional electron gas is formed on the first nitride semiconductor layer 903 side of the interface between the second nitride semiconductor layer 904 and the first nitride semiconductor layer 903. The nitride semiconductor layer composed of the first nitride semiconductor layer 903 and the second nitride semiconductor layer 904 can induce conduction electrons in the conductive layer 914 by the effect of polarization charge even when not doped with n-type dopants, and can substantially obtain n-type conductivity, but in order to promote the electron current toward the channel region 917 including the inverted conductive layer 913, n-type dopants can also be doped in the first nitride semiconductor layer 903. In the transistor of this embodiment, the conduction electrons flowing out from the source electrode 811 flow into the drift layer 801 via the conductive layer 914 and the channel region 917 along the direction of the arrow 915 indicating the flow of the conduction electrons.

[0130] In the above embodiments, the case where GaN and AlGaN are used as nitride semiconductors is described, but other nitride semiconductors, such as InN, InGaN, InAlN and other nitride semiconductors containing In, may also be used. Alternatively, a stacked structure of nitride semiconductors of different materials or compositions may also be used. In particular, in the first, second, third, and fifth embodiments of the first invention of the present application and the first, second, third, and fifth embodiments of the second invention of the present application, the material and composition may be selected in such a way that the main part of the first nitride semiconductor layer is formed of a nitride semiconductor with a small band gap, and the main part of the second nitride semiconductor layer is formed of a nitride semiconductor with a large band gap.

[0131] In the first, second, third, and fifth embodiments of the first invention of the present application and the first, second, third, and fifth embodiments of the second invention of the present application, for example, the first nitride semiconductor layer may be GaN, and the second nitride semiconductor layer may be a two-layer structure with AlGaN as the lower layer and GaN as the upper layer. AlGaN has a larger band gap than GaN as the first nitride semiconductor and functions as the main part, while the upper GaN serves as a protective film to prevent Al atoms that are easily oxidized from being exposed to the surface.

[0132] [Industrial Applicability]

[0133] The vertical nitride semiconductor transistor device of the present invention can be effectively used mainly as a power switch used in a power circuit, etc. In addition, by the threshold voltage adjustment method provided by the present invention, a desired normally-off operation can be realized as a switch.

Claims

1. A vertical nitride semiconductor transistor device, comprising: a drift layer composed of a nitride semiconductor; A channel region composed of a nitride semiconductor and electrically connected to the drift layer; a source electrode electrically contacting a side of the channel region opposite to the drift layer; a drain electrode, in electrical contact with the drift layer; a fourth insulating film, close to the channel region; a charge storage electrode disposed on a side of the fourth insulating film opposite to the channel region; a fifth insulating film provided on a side of the charge storage electrode opposite to the fourth insulating film; as well as a gate electrode provided on a side of the fifth insulating film opposite to the charge storage electrode, adjusting a threshold voltage by the charge accumulated in the charge accumulating electrode, the threshold voltage being used to substantially eliminate conduction carriers in the channel region by a voltage applied to the gate electrode, thereby blocking a current flowing between the source electrode and the drain electrode, The vertical nitride semiconductor transistor device is characterized in that it also includes: The charge injection electrode forms a third capacitor with the charge storage electrode, and the charge is stored in the charge storage electrode by a current flowing through the third capacitor, wherein A sixth insulating film is provided on at least a portion of the charge injection electrode, and the charge storage electrode is formed on at least a portion of the sixth insulating film, and the third capacitor is formed between the charge storage electrode and the charge injection electrode using the sixth insulating film as a capacitive coupling film.

2. The vertical nitride semiconductor transistor device according to claim 1, characterized in that: The charge storage electrode includes a plurality of electrodes arranged laterally and electrically insulated.

3. The vertical nitride semiconductor transistor device according to claim 1, wherein: The threshold voltage is adjusted to a positive voltage by the charge accumulated in the charge accumulation electrode.

4. The vertical nitride semiconductor transistor device according to claim 1, wherein: In an on state, a capacitance value of a first capacitor formed between the channel region and the charge storage electrode is smaller than a capacitance value of a second capacitor formed between the gate electrode and the charge storage electrode.

5. The vertical nitride semiconductor transistor device according to claim 4, characterized in that: The capacitance value of the third capacitor is smaller than the capacitance value of the second capacitor.

6. The vertical nitride semiconductor transistor device according to claim 1, wherein: Also includes: a blocking layer, disposed on the drift layer for the purpose of blocking the current; A first nitride semiconductor layer is disposed on the barrier layer; as well as a second nitride semiconductor layer, disposed on the first nitride semiconductor layer, The second nitride semiconductor layer includes at least a nitride semiconductor having a larger band gap than at least a part of the nitride semiconductor of the first nitride semiconductor layer. A conductive layer is formed on the first nitride semiconductor layer side of an interface between the second nitride semiconductor layer and the first nitride semiconductor layer, The channel region includes at least a portion of the conductive layer, The barrier layer has an opening, The first nitride semiconductor layer is electrically connected to the drift layer via the opening. The current between the source electrode and the drain electrode substantially flows through the opening portion.

7. The vertical nitride semiconductor transistor device according to claim 6, characterized in that: The first nitride semiconductor layer includes at least a GaN layer, and the second nitride semiconductor layer includes at least an Al x Ga 1-x N,0<x≤1.

8. The vertical nitride semiconductor transistor device according to claim 1, wherein: Also includes: a third nitride semiconductor layer, disposed on the drift layer and having a conductivity type opposite to that of the drift layer; as well as a fourth nitride semiconductor layer, disposed on the third nitride semiconductor layer, and having substantially the same conductivity type as the drift layer through doping or polarization charge, The source electrode is electrically connected to the fourth nitride semiconductor layer, A trench is formed which penetrates the fourth nitride semiconductor layer and the third nitride semiconductor layer and reaches the drift layer. At least a portion of the fourth insulating film is formed on the side surface of the third nitride semiconductor layer in the inner surface of the trench directly or via a thin nitride semiconductor layer. An inverted conductive layer is formed on one side of the side of the third nitride semiconductor layer at an interface formed between the side of the third nitride semiconductor layer and the fourth insulating film directly or via the thin nitride semiconductor layer. At least a portion of the charge storage electrode is formed on a side of the fourth insulating film opposite to the inverted conductive layer. The channel region includes at least a portion of the inverted conductive layer.

9. The vertical nitride semiconductor transistor device according to claim 1, wherein: The fourth insulating film and the fifth insulating film each include at least one of silicon oxide and aluminum oxide.

10. The vertical nitride semiconductor transistor device according to claim 1, wherein: The gate electrode, the source electrode, and the drain electrode are independently connected to external pins of a package, and the charge injection electrode is not connected to the external pins of the package.

11. The vertical nitride semiconductor transistor device according to claim 1, wherein: The charge injection electrode and the gate electrode are connected to the same external pin of the package.

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