Electrostatic discharge blocking circuit

Abstract

The present application provides an electrostatic discharge protection circuit, which includes an internal circuit, a Schottky diode and an electrostatic discharge release element. The Schottky diode is coupled between a specific node and the internal circuit. The electrostatic discharge release element is coupled between the specific node and a power supply terminal. When an electrostatic discharge event occurs at the specific node, the electrostatic discharge release element is turned on to release an electrostatic discharge current from the specific node to the power supply terminal. The present application can protect an integrated circuit.

Description

Technical Field

[0001] This invention relates to an electrostatic discharge isolation circuit, and more particularly to an electrostatic discharge isolation circuit having an electrostatic discharge release element. Background Technology

[0002] Electrostatic discharge (ESD) events in integrated circuits refer to the release of high-voltage electrostatic charges through the integrated circuit chip. Although the amount of such electrostatic charge is usually small, the instantaneous energy released due to the high voltage is considerable, and if not handled properly, it can often cause the integrated circuit to burn out.

[0003] Therefore, ESD has become a crucial reliability consideration in semiconductor products. Two commonly known ESD tests are Human Body Model (HBM) and Machine Model (MM). Commercially available integrated circuits must possess a certain level of HBM and MM tolerance to be sold; otherwise, they are highly susceptible to damage from accidental ESD events. Consequently, developing an efficient ESD protection device / component to protect integrated circuits remains a subject of ongoing discussion and research in the industry. Summary of the Invention

[0004] This invention provides an electrostatic discharge isolation circuit, including an internal circuit, a Schottky diode, and an electrostatic discharge release element. The Schottky diode is coupled between a specific node and the internal circuit. The electrostatic discharge release element is coupled between the specific node and a power supply terminal. When an electrostatic discharge event occurs at the specific node, the electrostatic discharge release element conducts to release an electrostatic discharge current from the specific node to the power supply terminal.

[0005] This invention can protect integrated circuits. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the electrostatic discharge isolation circuit of the present invention.

[0007] Figure 2 This is a possible embodiment of the electrostatic discharge isolation circuit of the present invention.

[0008] Figure 3 This is another embodiment of the electrostatic discharge isolation circuit of the present invention.

[0009] Figure 4 This is another embodiment of the electrostatic discharge isolation circuit of the present invention.

[0010] Figure 5 This is another embodiment of the electrostatic discharge isolation circuit of the present invention.

[0011] Attached icon number

[0012] 100: Electrostatic discharge resistance isolation circuit

[0013] 110: Internal Circuitry

[0014] 120, 411, 511: Schottky diodes

[0015] 130: Electrostatic discharge release element

[0016] PT -1 PT2: Power supply terminal

[0017] ND: Specific node

[0018] VPP1, VPP2: Voltage

[0019] VDD, VSS: Operating voltage

[0020] 211: Access Circuit

[0021] 212: Storage Array

[0022] 313, 414, 514: P-type transistors

[0023] 312: Bipolar Transistor

[0024] 413: Output stage

[0025] 513: Input level

[0026] 311, 314, 315, 412, 415, 512, 515: N-type transistors Detailed Implementation

[0027] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0028] Figure 1 This is a schematic diagram of the electrostatic discharge isolation circuit of the present invention. As shown in the figure, the electrostatic discharge isolation circuit 100 includes an internal circuit 110, a Schottky diode 120, and an electrostatic discharge release element 130. The internal circuit 110 is coupled to the cathode of the Schottky diode 120 and the power supply terminal PT.-1 Between. A Schottky diode 120 is coupled between a specific node ND and the internal circuit 110 to block an electrostatic discharge current from the specific node ND into the internal circuit 110. In this schematic diagram, the anode of the Schottky diode 120 is coupled to the specific node ND, and its cathode is coupled to the internal circuit 110. An electrostatic discharge release element 130 is coupled between the specific node ND and the power supply terminal PT1 to release the electrostatic discharge current.

[0029] When an electrostatic discharge (ESD) event occurs at a specific node ND and the power supply terminal PT1 is coupled to ground, the ESD isolation circuit 100 enters a protection mode. In protection mode, the ESD release element 130 conducts to release an ESD current from the specific node ND to the power supply terminal PT1. In this schematic diagram, because the Schottky diode 120 has a high AC resistance, it does not conduct in the initial stage of the ESD event to block the ESD current from entering the internal circuit 110. Furthermore, because the trigger voltage of the ESD release element 130 is lower than the total trigger voltage of the Schottky diode 120 plus the internal circuit 110, the path of the ESD release element 130 conducts earlier than the path of the Schottky diode 120.

[0030] When no electrostatic discharge (ESD) event occurs, the ESD isolation circuit 100 operates in a normal mode. In normal mode, because the Schottky diode 120 has low DC resistance, it can quickly conduct when a specific node ND receives an external signal or voltage, thereby transmitting the signal or voltage of the specific node ND to the internal circuit 110. In this schematic diagram, the internal circuit 110 operates according to the signal or voltage of the specific node ND. The present invention does not limit the architecture of the internal circuit 110. Any circuit requiring ESD protection can be used as the internal circuit 110.

[0031] Figure 2 This is a possible embodiment of the electrostatic discharge isolation circuit of the present invention. In this embodiment, a specific node ND serves as an input node to provide a signal or voltage to the internal circuit 110. In one possible embodiment, the specific node ND receives and provides voltage VPP1 or VPP2 to the internal circuit 110. Additionally, the internal circuit 110 is further coupled to a power supply terminal PT2. The power supply terminal PT2 is used to receive the operating voltage VDD. In this example, the power supply terminal PT1 is used to receive the operating voltage VSS. The operating voltage VDD is greater than the operating voltage VSS. In some embodiments, the operating voltage VSS may be negative.

[0032] The internal circuit 110 starts operating based on the operating voltages VDD and VSS. In this embodiment, the operating voltages VDD and VSS are used as the operating voltages of the internal circuit 110, so the operating voltages VDD and VSS must each be stable at a fixed value. For example, the operating voltage VDD may be maintained at 3.3V, while the operating voltage VSS may be maintained at 0V. When the operating voltages VDD and VSS are unstable, the internal circuit 110 may not function properly.

[0033] The voltage of a specific node ND does not remain at a fixed value relative to the operating voltages VDD and VSS. For example, during a first period (such as a write period), the voltage of a specific node ND is equal to voltage VPP1, and during a second period (such as a read period), the voltage of a specific node ND is equal to voltage VPP2. In one possible embodiment, voltage VPP1 is greater than voltage VPP2.

[0034] The present invention does not limit the architecture of the internal circuit 110. In one possible embodiment, the internal circuit 110 is a one-time programmable memory (OTP memory) and has an access circuit 211 and a storage array 212.

[0035] Access circuit 211 is used to access memory array 212. The present invention does not limit the architecture of access circuit 211. In one possible embodiment, access circuit 211 performs a write operation on memory array 212 based on voltage VPP1 to write the value 1 or the value 0 to memory array 212. In another possible embodiment, access circuit 211 performs a read operation on memory array 212 based on voltage VPP2 to retrieve data stored in memory array 212.

[0036] The memory array 212 has multiple memory cells (not shown). The invention does not limit the structure of the memory cells. In one possible embodiment, each memory cell of the memory array 212 has at least one transistor, and each transistor has a floating gate. During a write operation, the access circuit 211 provides a voltage VPP1 to the corresponding memory cell to accumulate charge on the floating gate of the memory cell. In this example, when the floating gate of the memory cell has sufficient charge, it indicates that the memory cell stores a first value (such as 1 or 0). When the floating gate of the memory cell has no charge, it indicates that the memory cell stores a second value (such as 0 or 1).

[0037] In another possible embodiment, each memory cell of the memory array 212 has at least one transistor. In this example, the access circuit 211 may use a voltage VPP1 to break down the gate oxide layer of the transistor corresponding to the memory cell. When the gate oxide layer of the transistor in the memory cell is broken down, it indicates that the memory cell stores a first value. When the gate oxide layer of the transistor in the memory cell is not broken down, it indicates that the memory cell stores a second value.

[0038] In other embodiments, each memory cell of the memory array 212 has at least one fuse. In this example, the access circuit 211 may use voltage VPP1 to blow the fuse of the corresponding memory cell. When the fuse of the transistor in the memory cell is blown, it indicates that the memory cell stores a first value. When the fuse of the transistor in the memory cell is not blown, it indicates that the memory cell stores a second value.

[0039] When an electrostatic discharge (ESD) event occurs at a specific node ND and the power supply terminal PT1 is coupled to ground, the ESD release element 130 is turned on to release the ESD current from the specific node ND to the power supply terminal PT1. In this embodiment, since the Schottky diode 120 blocks the ESD current from flowing into the internal circuit 110, damage to the access circuit 211 and the memory array 212 can be avoided.

[0040] Figure 3 This is another possible embodiment of the electrostatic discharge isolation circuit of the present invention. In this embodiment, a specific node ND serves as a power supply terminal to receive the operating voltage VDD. The internal circuit 110 starts operating based on the operating voltages VDD and VSS. In one possible embodiment, the internal circuit 110 includes a P-type transistor 313, and N-type transistors 314 and 315.

[0041] The source of P-type transistor 313 is coupled to the cathode of Schottky diode 120. The drain of P-type transistor 313 is coupled to the drain of N-type transistor 314. The source of N-type transistor 314 is coupled to power supply terminal PT1. The gate of N-type transistor 314 is coupled to the gate of P-type transistor 313 and the drain of N-type transistor 315. The gate and source of N-type transistor 315 are coupled to power supply terminal PT1.

[0042] When an electrostatic discharge (ESD) event occurs at a specific node ND and the power supply terminal PT1 is coupled to ground, the high AC impedance of the Schottky diode 120 can block the ESD current from entering the internal circuit 110, preventing the ESD current from damaging the P-type transistor 313, N-type transistors 314 and 315. Furthermore, since the forward voltage of the ESD release element 130 is lower than the total forward voltage of the Schottky diode 120 plus the internal circuit 110, the path of the ESD release element 130 turns on earlier than that of the Schottky diode 120, thus releasing the ESD current from the specific node ND to the power supply terminal PT1 via the ESD release element 130.

[0043] In this embodiment, the electrostatic discharge (ESD) release element 130 includes an N-type transistor 311. The drain of the N-type transistor 311 is coupled to a specific node ND, and its gate and source are coupled to a power supply terminal PT1. When an ESD event occurs at the specific node ND, the parasitic bipolar transistor 312 of the N-type transistor 311 is turned on, thereby turning on the N-type transistor 311, allowing the ESD current to flow from the specific node ND into the power supply terminal PT1.

[0044] Figure 4 This is another embodiment of the electrostatic discharge isolation circuit of the present invention. In this embodiment, a specific node ND serves as an output node for outputting the signal of the internal circuit 110. Since the internal circuit 110 may output a negative voltage, the electrostatic discharge isolation circuit 100 further includes a Schottky diode 411. In other embodiments, if the level of the signal or voltage output by the internal circuit 110 only varies between a positive level and a grounded level (e.g., 0V), the Schottky diode 411 can be omitted.

[0045] In this embodiment, Schottky diode 411 is connected in parallel with Schottky diode 120. As shown, the cathode of Schottky diode 120 is coupled to the anode of Schottky diode 411 and the output stage 413. The anode of Schottky diode 120 and the cathode of Schottky diode 411 are coupled to a specific node ND. When the internal circuit 110 outputs a positive level, Schottky diode 411 is turned on. Therefore, the level of the specific node ND is positive. However, when the internal circuit 110 outputs a negative voltage, Schottky diode 120 is turned on. Therefore, the level of the specific node ND is negative.

[0046] This invention does not limit the architecture of the internal circuit 110. Any circuit capable of outputting a signal or voltage can serve as the internal circuit 110. In this embodiment, the internal circuit 110 includes an output stage 413. The output stage 413 is based on a control signal S. C Output operating voltage VDD or VSS. For example, when the control signal S... CWhen the first level is set (e.g., a high level), output stage 413 outputs an operating voltage VSS. In one possible embodiment, the operating voltage VSS is a negative voltage or a ground voltage. When the control signal S... C When the output stage 413 is at a second level (e.g., a lower level), it outputs an operating voltage VDD. In one possible embodiment, the operating voltage VDD is a positive voltage.

[0047] In this embodiment, the output stage 413 includes a P-type transistor 414 and an N-type transistor 415. The source of the P-type transistor 414 is coupled to the power supply terminal PT2. The gate of the P-type transistor 414 is coupled to the gate of the N-type transistor 415 and receives the control signal S. C The drain of N-type transistor 415 is coupled to the drain of P-type transistor 414. The source of N-type transistor 415 is coupled to power supply terminal PT1.

[0048] When no electrostatic discharge event occurs, the electrostatic discharge isolation circuit 100 operates in a normal mode. In normal mode, when power supply terminals PT1 and PT2 receive operating voltages VSS and VDD respectively, output stage 413 operates according to control signal S. C Output operating voltage VSS or VDD. For example, when the control signal S... C When P-type transistor 414 is turned on, it outputs an operating voltage VDD. Therefore, the voltage at a specific node ND is approximately equal to the operating voltage VDD. However, when the control signal S... C When N-type transistor 415 is turned on, it outputs an operating voltage VSS. Therefore, the voltage at a specific node ND is approximately equal to the operating voltage VSS.

[0049] When an electrostatic discharge (ESD) event occurs at a specific node ND and the power supply terminal PT1 is coupled to ground, the ESD release element 130 is turned on to release the ESD current from the specific node ND to the power supply terminal PT1. In this embodiment, the ESD release element 130 includes an N-type transistor 412. Due to the characteristics of the N-type transistor 412 and... Figure 3 The characteristics of the N-type transistor 311 are similar, so they will not be described in detail here.

[0050] Figure 5 This is another embodiment of the operating circuit of the present invention. In this embodiment, a specific node ND serves as an input node to provide a signal or voltage to the internal circuit 110. Since the level of the signal or voltage received by the specific node ND may be positive or negative, in this embodiment, the electrostatic discharge isolation circuit 100 further includes a Schottky diode 511.

[0051] Schottky diode 511 is connected in parallel with Schottky diode 120. As shown, the cathode of Schottky diode 120 is coupled to the anode of Schottky diode 511 at input stage 513, and the anode of Schottky diode 120 is coupled to the cathode of Schottky diode 511 at a specific node ND. When the specific node ND receives a positive signal or voltage, Schottky diode 120 conducts to transmit the signal or voltage of the specific node ND to internal circuit 110. However, when the specific node ND receives a negative signal or voltage, Schottky diode 511 conducts to transmit the negative signal or voltage to internal circuit 110.

[0052] This invention does not limit the architecture of the internal circuit 110. Any circuit capable of receiving external signals or voltages can serve as the internal circuit 110. In this embodiment, the internal circuit 110 includes an input stage 513. The input stage 513 operates according to the voltage of a specific node ND. For example, when the level of the signal or voltage at the specific node ND is equal to a first level (e.g., a positive level), the input stage 513 outputs an operating voltage VSS. When the level of the signal or voltage at the specific node ND is equal to a second level (e.g., a negative level), the input stage 513 outputs an operating voltage VDD. In other embodiments, the input stage 513 also outputs an operating voltage VDD when the level of the signal or voltage at the specific node ND is equal to a ground level (e.g., 0V). In some embodiments, the Schottky diode 511 may be omitted when the signal or voltage at the specific node ND changes between a positive level and a ground level.

[0053] In this embodiment, the input stage 513 includes a P-type transistor 514 and an N-type transistor 515. The source of the P-type transistor 514 is coupled to the power supply terminal PT2. The gate of the P-type transistor 514 is coupled to the gate of the N-type transistor 515 and to the cathode of the Schottky diode 120. The drain of the N-type transistor 515 is coupled to the drain of the P-type transistor 514. The source of the N-type transistor 515 is coupled to the power supply terminal PT1. In other embodiments, the drain of the N-type transistor 515 is not coupled to the drain of the P-type transistor 514. In this example, the drain of the N-type transistor 515 is used to output the operating voltage VSS, while the drain of the P-type transistor 514 is used to output the operating voltage VDD.

[0054] When an electrostatic discharge (ESD) event occurs at a specific node ND and the power supply terminal PT1 is coupled to ground, the ESD release element 130 is turned on to release the ESD current from the specific node ND to the power supply terminal PT1. In this embodiment, the ESD release element 130 includes an N-type transistor 512. Due to the characteristics of the N-type transistor 512 and... Figure 3 The characteristics of the N-type transistor 311 are similar, so they will not be described in detail here.

[0055] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized or overly formal expressions.

[0056] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods of the present invention can be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention is determined by the claims.

Claims

1. An electrostatic discharge isolation circuit, characterized in that, include: One internal circuit; A first Schottky diode is coupled between a specific node and the internal circuit. A second Schottky diode is connected in parallel with the first Schottky diode; as well as An electrostatic discharge release element is coupled between the specific node and a first power supply terminal; When an electrostatic discharge (ESD) event occurs at a specific node, the ESD release element is activated to release an ESD current from the specific node to the first power supply terminal. The internal circuit is further coupled to a second power supply terminal. When no ESD event occurs, the voltage at the second power supply terminal is equal to a first operating voltage, and the voltage at the first power supply terminal is equal to a second operating voltage. The internal circuit operates according to the first and second operating voltages. The cathode of the first Schottky diode and the anode of the second Schottky diode are coupled to the internal circuit, and the anode of the first Schottky diode and the cathode of the second Schottky diode are coupled to the specific node.

2. The electrostatic discharge isolation circuit as described in claim 1, characterized in that, The internal circuit is a one-time programmable memory. When the one-time programmable memory performs a write operation, the voltage of the specific node is equal to a first voltage. When the one-time programmable memory performs a read operation, the voltage of the specific node is equal to a second voltage. The first voltage is greater than the second voltage.

3. The electrostatic discharge isolation circuit as described in claim 1, characterized in that, The internal circuitry includes an output stage that provides the first operating voltage or the second operating voltage to the specific node.

4. The electrostatic discharge isolation circuit as described in claim 1, characterized in that, The internal circuitry includes an input stage to which the first Schottky diode transmits the signal for the specific node.

5. The electrostatic discharge isolation circuit as described in claim 4, characterized in that, The cathode of the first Schottky diode and the anode of the second Schottky diode are coupled to the input stage, and the anode of the first Schottky diode and the cathode of the second Schottky diode are coupled to the specific node.

6. The electrostatic discharge isolation circuit as described in claim 1, characterized in that, When the electrostatic discharge event triggers the electrostatic discharge release element, the first Schottky diode is not conducting.

7. The electrostatic discharge isolation circuit as described in claim 1, characterized in that, The electrostatic discharge device is an N-type transistor with a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the specific node, and the second terminal and the control terminal are coupled to the first power supply terminal.

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