Non-power-of-two memory configuration

Abstract

Systems, devices, and methods for managing non-power-of-two memory configurations are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem having a non-power-of-two number of active memory channels. The control unit simplifies the ratio of the number of active memory channels to the total number of physical memory channels to the ratio of a first number to a second number. If a first subset of physical address bits of a received memory request is greater than or equal to the first number, the control unit calculates a third number that is equal to a modulo operation of the second subset of physical address bits with respect to the first number, and uses the concatenation of the third number and the third subset of physical address bits to select a memory channel for issuing the received memory request.

Description

Background Art

[0001] Description of Related Technology

[0002] Modern processors and systems on a chip (SoC) include a variety of circuits and components for fast and efficient computing. The energy of data movement between the processor and the memory is a large part of the total chip energy consumed during program execution. The memory configuration typically has a number of memory channels that are powers of two. This allows the address space to be mapped in a simple manner and allows data to be transferred between the processing unit and the memory device of the memory subsystem in an efficient burst. As used herein, a "power of two memory configuration" is defined as a memory subsystem with a certain number of memory channels, wherein the number is equal to a power of two. Examples of powers of two include 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, etc.

[0003] However, in some cases, a computing system will have a non-power-of-two memory configuration. As used herein, a "non-power-of-two memory configuration" is defined as a memory subsystem having a number of active memory channels, where the number is not equal to a power of two. It should be noted that for a "non-power-of-two memory configuration," a memory subsystem may actually have a number of physical memory channels, where the number is equal to a power of two, but the number of resident memory slots is equal to a non-power-of-two number. In some cases, a physical memory slot is unoccupied or occupied by a non-functioning memory module or device. The physical memory channels that are connected to an occupied memory slot through a functioning and available memory device are referred to as "active memory channels." BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of one implementation of a computing system.

[0006] Figure 2 is a diagram of one implementation of an address space mapping between clients and physical memory addresses for a power-of-two memory configuration.

[0007] Figure 3 is a diagram of one implementation of an address space map for a system with a non-power-of-two memory configuration.

[0008] Figure 4 is a diagram of another implementation of an address space map for a system with a non-power-of-two memory configuration.

[0009] Figure 5is a block diagram of one implementation of a memory subsystem with a memory controller.

[0010] Figure 6 is a block diagram of another implementation of a memory subsystem.

[0011] Figure 7 One implementation of pseudo code for selecting a memory channel and converting a physical memory address to a normalized address is shown.

[0012] Figure 8 is a generalized flow chart illustrating one implementation of a method for determining the type of mapping scheme and address translation scheme to use for a memory request.

[0013] Figure 9 is a generalized flow chart illustrating one implementation of a method of selecting a memory channel for a given physical address for a non-power-of-two memory configuration.

[0014] Figure 10 Another implementation of pseudo code for selecting a memory channel and converting a physical memory address to a normalized address is shown. DETAILED DESCRIPTION

[0015] In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, one of ordinary skill in the art will recognize that various implementations may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid obscuring the methods described herein. It should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the size of some elements may be enlarged relative to other elements.

[0016] Various systems, devices, and methods for managing non-power-of-two memory configurations are disclosed herein. A computing system includes at least one or more clients, a control unit, and a memory subsystem having a non-power-of-two number of active memory channels. In one implementation, the control unit simplifies the ratio of the number of active memory channels to the total number of physical memory channels to the ratio of a first number to a second number. If the value (i.e., size) of a first subset of physical address bits of a received memory request is greater than or equal to the first number, the control unit calculates a third number based on a modulo operation of the first number by the second subset of physical address bits (or a value corresponding to a subset of physical address bits), and the control unit uses the binary representation of the third number and the concatenation of the third subset of physical address bits to select a memory channel for issuing the received memory request. The value corresponding to the address bits can be a value based on a mathematical transformation of the address bits or other value. In one implementation, the first subset of physical address bits is the physical address bits that determine whether the received memory request targets an inactive memory channel. The control unit then completes the memory request for the selected memory channel. In a conventional addressing scheme, a first subset of physical address bits of a received memory request being greater than or equal to a first number indicates that the memory request will target an inactive memory channel. By selecting a memory channel for issuing a memory request in this manner, an address space is divided across a non-power-of-two number of active memory channels in a manner that allows efficient access to the memory subsystem by one or more clients.

[0017] Additionally, in one implementation, if the value of the first subset of physical address bits of the received memory request is greater than or equal to the first number, the control unit calculates a fourth number that is equal to the first subset of physical address bits shifted upward by a fifth number, where the fifth number is calculated based on the size of the address space of the memory subsystem. As is known in the art, each upward shift produces a value equal to the previous binary value multiplied by two. Additionally, if the value of the first subset of physical address bits of the received memory request is greater than or equal to the first number, the control unit calculates the first subset of normalized address bits to be equal to the second subset of physical address bits, with the high order bits replaced by the first subset of physical address bits. Further, if the value of the first subset of physical address bits of the received memory request is greater than or equal to the first number, the control unit calculates the second subset of normalized address bits to be equal to the concatenation of the fourth subset of physical address bits and the fifth subset of physical address bits. Furthermore, if the value of the first subset of physical address bits of the received memory request is greater than or equal to the first number, the control unit completes the memory request for the normalized address on the selected memory channel, wherein the normalized address includes the first subset of normalized address bits and the second subset of normalized address bits.

[0018] Now refer to Figure 1 , shows a block diagram of one implementation of a computing system 100. In one implementation, computing system 100 includes at least processors 105A through 105N, an input / output (I / O) interface 120, a bus 125, one or more memory controllers 130, a network interface 135, one or more memory devices 140, a display controller 150, and a display 155. In other implementations, computing system 100 includes other components and / or computing system 100 is arranged differently. Processors 105A through 105N represent any number of processors included in system 100.

[0019] In one implementation, processor 105A is a general-purpose processor, such as a central processing unit (CPU). In one implementation, processor 105N is a data-parallel processor with a highly parallel architecture. Data-parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and the like. In some implementations, processors 105A to 105N include multiple data-parallel processors. In one implementation, processor 105N is a GPU that provides pixels to display controller 150 to be driven to display 155.

[0020] The one or more memory controllers 130 represent any number and type of memory controllers accessible by the processors 105A to 105N. The one or more memory controllers 130 are coupled to any number and type of memory devices 140. The one or more memory devices 140 represent any number and type of memory devices. For example, the types of memory in the one or more memory devices 140 include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0021] I / O interface 120 represents any number and type of I / O interfaces (e.g., Peripheral Component Interconnect (PCI) bus, PCI Extended (PCI-X), PCIE (PCI Express) bus, Gigabit Ethernet (GBE) bus, Universal Serial Bus (USB)). Various types of peripheral devices (not shown) are coupled to I / O interface 120. Such peripheral devices include, but are not limited to, a display, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc. Network interface 135 is used to receive and send network messages across a network.

[0022] In various implementations, computing system 100 is any of a computer, laptop, mobile device, gaming console, server, streaming device, wearable device, or various other types of computing systems or devices. Note that the number of components of computing system 100 varies depending on the implementation. For example, in other implementations, there are Figure 1 It should also be noted that in other implementations, the computing system 100 includes Figure 1 Other components not shown in FIG. In addition, in other implementations, the computing system 100 is configured to Figure 1 The different ways of structuring are shown in .

[0023] Now turn Figure 2 , shows a diagram of one implementation of an address space map 200 for a power-of-two memory configuration. In one implementation, clients 205A-205D access data in memory across a power-of-two number of memory channels 210A-210D using a 256-byte stride. For discussion purposes, assume that clients 205A-205D typically access data in bursts of 1 kilobyte (KB) within a memory channel, which is an efficient way to access memory for mapping 200. In systems with power-of-two memory configurations, the math for spanning addressing to achieve efficient bursts is simple. The memory burst region is highlighted with a bold outline around the first four blocks in the column representing memory channel 210A below client 205A. In one implementation, clients 205A-205D are rendering backends. In other implementations, clients 205A-205D are other types of graphics engines. In yet other implementations, clients 205A-205D are other types of non-graphics engines. In other implementations, other numbers of clients besides four may be mapped to memory channels 210A-210D.

[0024] Map 200 illustrates one implementation of the mapping between clients 205A-205D, physical memory addresses, and memory channels 210A-210D for a power-of-two memory configuration. In one implementation, each client 205A-205D has a one-to-one mapping to a corresponding memory channel 210A-210D. For the purposes of this implementation, it is assumed that the memory address space is mapped into blocks of 256 bytes. In other implementations, the memory address space is mapped into blocks of other sizes. For example, in one implementation, the four blocks highlighted for addresses 0x0, 0x400, 0x800, and 0xC00 for client 205A represent an efficient access burst by client 205A to a single memory channel 210A. Mapping each client 205A-205D to a separate memory channel 210A-210D is a simple configuration that enables efficient access to memory. However, as will be shown in subsequent figures, non-power-of-two memory configurations often result in inefficient memory access.

[0025] Now refer to Figure 3 , shows a diagram of one implementation of an address space map 300 for a system having a non-power-of-two memory configuration. The mapping 300 of clients 305A to 305D to memory channels 310A to 310C shows a typical implementation for a prior art system having a non-power-of-two memory configuration. The mapping of data blocks to memory channels 310A to 310C is represented by Figure 3 310A. The shading of the blocks shown to the right of is indicated. Thus, transparent blocks without shading are mapped to memory channel 310A, blocks with dots are mapped to memory channel 310B, and blocks with diagonal lines are mapped to memory channel 310C. This mapping 300 results in inefficient access to memory channels 310A to 310C by clients 305A to 305D. For example, the highlighted blocks for memory channel 310A illustrate how the first 1 kilobyte of data is mapped to memory channel 310A. Consequently, the first 1 kilobyte of data mapped to memory channel 310A cannot be accessed in an efficient burst.

[0026] Now turn Figure 4 , a diagram showing another implementation of an address space map 400 for a system having a non-power-of-two memory configuration. Figure 3Mapping 400 is an improved mapping compared to mapping 300. The improvement of mapping 400 refers to the ability of each client 405A to 405D to perform accesses to the same memory channel across four blocks. Since there are three memory channels 410A to 410C in the exemplary system configuration, each memory channel 410A to 410C is alternately mapped to client 405D for four consecutive blocks. Similar to mapping 300, the mapping 400 of data blocks to memory channels 410A to 410C is composed of Figure 4 The different shading of the blocks shown on the right is indicated.

[0027] As shown in map 400, after clients 405A to 405C are mapped to three memory channels 410A to 410C in four-block chunks, client 405D is mapped to memory channel 410A for four chunks at addresses 0x300, 0x700, 0xB00, and 0xF00. The next set of four-block chunks are then mapped from clients 405A to 405C to memory channels 410A to 410C in a regular pattern. Client 405D is then mapped to memory channel 410B for four chunks at addresses 0x1300, 0x1700, 0x1B00, and 0x1F00. Finally, after the next set of four blocks are mapped to memory channels 410A to 410C for clients 405A to 405C in a conventional pattern, client 405D is mapped to memory channel 410C for the next four blocks at addresses 0x2300, 0x2700, 0x2B00, and 0x2F00. While client 405D continues this mapping pattern by alternating between memory channels 410A to 410C, clients 405A to 405C continue to be mapped to memory channels 410A to 410C, respectively, on a one-to-one basis. This pattern continues for the remainder of the memory address space. It should be noted that mapping 400 represents an example of an effective mapping for three memory channels and four clients. It should be understood that mapping 400 can be adjusted for use with other systems having other numbers of clients and / or other numbers of memory channels that are not powers of two.

[0028] Now refer to Figure 5, shows a block diagram of one implementation of a memory subsystem 500 having a memory controller 505. In one implementation, the memory controller 505 includes at least registers 520 and a remapping unit 525. It should be noted that the memory controller 505 also includes other components and / or circuits, which are not shown to avoid obscuring the drawing. In one implementation, the register 520 includes values indicating the number of active memory channels 520A, the total number of memory channels 520B, the number of clients 520C, and the step size 520D. In other implementations, the register 520 includes other numbers and / or types of values. In other implementations, the values 520A to 520D are stored in other locations.

[0029] In one implementation, the remapping unit 525 receives the physical address 510 and converts the physical address 510 into a normalized address 530. In one implementation, the remapping is performed based on the number of active memory channels 540A to 540N indicated by the register 520. This remapping helps achieve greater efficiency when accessing the memory devices 550A to 550N via the memory channels 540A to 540N. It should be noted that the remapping unit 525 may also be referred to as a "control unit" herein. The memory channels 540A to 540N represent any number "N" of memory channels, where "N" is an integer power that is not two. Each memory channel 540A to 540N is connected to a corresponding memory module 550A to 550N. Each memory module 550A to 550N is implemented using any suitable type of memory technology (e.g., DRAM) and any number of memory devices.

[0030] Now turn Figure 6, shows a block diagram of another implementation of the memory subsystem 600. In one implementation, the control unit 605 includes at least registers 620 and a remapping unit 625. It should be noted that the control unit 605 also includes other components and / or circuits, which are not shown to avoid obscuring the drawing. In one implementation, the control unit 605 is located within the input / output (I / O) architecture. In other implementations, the control unit 605 is located elsewhere. In one implementation, the remapping unit 625 receives the physical address 610 of a memory request and converts the physical address 610 into a normalized address 630 based on the number of active memory channels 640A to 640N. The remapping is performed based on the number of active memory channels 640A to 640N indicated by registers 620. This remapping helps achieve greater efficiency when accessing the memory modules 650A to 650N via the memory channels 640A to 640N. Memory channels 640A-640N represent any number "N" of memory channels, where "N" is a non-integer power of two.

[0031] Now refer to Figure 7 , shows one implementation of pseudocode 700 for selecting a memory channel and converting a physical memory address to a normalized address. For the purposes of pseudocode 700, it is assumed that there are three active memory channels in the memory subsystem. Or in other words, for pseudocode 700, it is assumed that the numerator of the ratio of the number of active memory channels to the total number of physical memory channels in the memory subsystem, after simplification, is three. Therefore, in this implementation, the first line of pseudocode 700 checks whether physical address bits [11:10] are equal to 3, where 3 is the number of active memory channels. In one implementation, the term "active memory channel" is defined as an active memory channel that is connected to a fully populated, fully functional memory module or memory device. On the other hand, an "inactive memory channel" is defined as a memory channel that is coupled to less than a fully populated memory module.

[0032] The first line of pseudocode 700 sets mod_ID bits [1:0] to either the modulo 3 operation of physical address bits [43:16] or physical address bits [11:10], depending on whether physical address bits [11:10] are equal to 3. In the second line of pseudocode 700, channel ID bits [3:0] are set to the concatenation of mod_ID bits [1:0] and physical address bits [9:8]. Channel ID bits [3:0] select the memory channel on which the received memory request is routed, with a maximum number of 16 memory channels for this particular implementation. In other implementations, the number of channel ID bits may vary depending on the maximum number of memory channels supported.

[0033] Depending on whether physical address bits [11:10] are equal to 3, upper_bits[43:16] of the bit array stores the value three shifted up by the variable (addr_space–2) or 0. In one implementation, the variable addr_space is equal to the total amount of addressable physical memory in the system expressed in given units, where the given units are specified as a particular size. In one implementation, the given unit size is 64KB. In other implementations, the given unit size is any of a variety of other sizes. Bits [43:12] of the normalized address are set equal to the result of a bitwise OR operation between upper_bits[43:16] of the bit array and physical address bits [43:16]. Bits [11:0] of the normalized address are set equal to the concatenation of physical address bits [15:12] and physical address bits [7:0]. It should be understood that the exemplary pseudocode 700 indicates code that may be used in one particular implementation. The sizes of the various bit arrays used within the pseudo-code 700 and the sizes of the specific bits within the physical addresses may vary for other implementations. The sizes of the various bit arrays used and the sizes of the specific bits within the physical addresses may vary depending on the total address space, stride size, block size, number of active memory channels, number of physical memory channels, etc.

[0034] Now turn Figure 8 , shows one implementation of a method 800 for determining the type of mapping scheme and address translation scheme to be used for a memory request. For discussion purposes, the steps and Figure 9 However, it should be noted that in various implementations of the described method, one or more of the described elements may be performed simultaneously, in a different order than shown, or omitted entirely. Other additional elements may also be performed as needed. Any of the various systems or devices described herein may be configured to implement method 800.

[0035] The control unit retrieves a memory configuration value from a register, wherein the memory configuration value indicates whether the system has a number of memory channels that is not a power of two (block 805). In one implementation, block 805 is performed when the system is powered on. In other implementations, the memory configuration value is stored in a location other than a register.

[0036] If the value is a first value indicating that the number of memory channels is a non-power-of-two number (conditional block 810, "yes" branch), the control unit maps the memory request to the memory channel using the first mapping (block 815). Also, if the system has a non-power-of-two memory configuration, the control unit converts the physical address to a normalized address using the first translation scheme (block 820). Figure 9An example of the first mapping and the first conversion scheme is described in further detail in the discussion associated with method 900 of .

[0037] If the value is a second value indicating that the number of memory channels is a power of two (conditional block 810, "no" branch), the control unit maps the memory request to the memory channel using a second mapping, wherein the second mapping is different from the first mapping (block 825). Furthermore, if the system has a power of two memory configuration, the control unit converts the physical address to a normalized address using a second translation scheme, wherein the second translation scheme is different from the first translation scheme (block 830). An example of the first mapping and the first translation scheme is shown in FIG. Figure 2 After blocks 820 and 830, the control unit forwards the memory request to the memory on the memory channel indicated by the selected mapping scheme and having the normalized address converted from the physical address using the selected translation scheme (block 835). After block 835, method 800 ends.

[0038] Now refer to Figure 9 , shows one implementation of a method 900 for selecting a memory channel for a given physical address for a non-power-of-two memory configuration. The control unit determines the number of active memory channels from the total number of physical memory channels (block 905). For example, for some memory subsystems, not all physical memory channels may be occupied and / or active. It should be noted that "active memory channels" may also be referred to as "resident memory channels." In one implementation, the control unit is located within the memory controller. In other implementations, the control unit is located elsewhere.

[0039] The control unit reduces the ratio of the number of active memory channels to the total number of physical memory channels to the ratio of the first number to the second number (block 910). Simplifying the ratio involves dividing each number by the greatest common factor. The ratio is reduced when the number in the ratio is the smallest possible integer. For example, if there are 6 active memory channels and 8 physical memory channels, the control unit will reduce the ratio to 3 to 4. If the ratio cannot be reduced, the first number is equal to the number of active memory channels, and the second number is equal to the total number of physical memory channels. It should be noted that blocks 905 to 910 can be performed in advance, such as during system startup. Therefore, depending on the implementation, blocks 905 to 910 can be performed as part of method 900 or separately from method 900.

[0040] At a later point in time, the control unit receives a memory request (block 915). In response to receiving the memory request, the control unit determines whether a first subset of the physical address bits of the memory request is greater than or equal to a first number (block 920). In one implementation, the first subset of the physical address bits is at least a portion of the bits that determine a mapping between a physical address and a memory channel. If the first subset of the bits is greater than or equal to the first number (conditional block 925, "yes" branch), the control unit calculates a third number that is equal to a modulo operation of the second subset of the physical address bits with respect to the first number (block 930). In other words, the third number is equal to the remainder after dividing the value represented by the second subset of the physical address bits by the first number. In one implementation, the second subset of the physical address bits is physical address bits [43:16]. In other implementations, the second subset of the physical address bits is another range of physical address bits depending on the block size, stride size, total address space size, and / or other factors. In another implementation, the modulo operation in block 930 is performed on a transformation of the physical address bits rather than on the original physical address bits. As used herein, "transformation" of physical address bits refers to a shift of the address bits, a mapping of the address bits to alternative values, or some other mathematical transformation of the address bits.

[0041] The control unit then uses the third number concatenated with the third subset of physical address bits to select a memory channel for the memory request (block 935). Note that the control unit uses the third number instead of the first subset of physical address bits. The first subset of physical address bits would be used to select a memory channel in a conventional manner. In one implementation, the third subset of physical address bits is physical address bits [9:8]. Furthermore, the control unit calculates a fourth number that is equal to the first subset of physical address bits shifted up (i.e., left) by a fifth number, where the fifth number is calculated based on the size of the address space (block 940). In other words, the first subset of physical address bits is shifted left by a number of bits that is equal to the fifth number. Effectively, this results in the first subset of bits being multiplied by two raised to the power of the fifth number. In another implementation, the control unit calculates the fourth number as a transformation equal to the first subset of physical address bits shifted up by the fifth number. Next, the control unit calculates the first subset of normalized address bits to be equal to the second subset of physical address bits, with the upper bits replaced by the first subset of physical address bits (block 945). The control unit then calculates the second subset of normalized address bits to be equal to the concatenation of the fourth subset of physical address bits and the fifth subset of physical address bits (block 950). In one implementation, the fourth subset of physical address bits is physical address bits [15:12], and the fifth subset of physical address bits is physical address bits [7:0]. In another implementation, the fourth subset of physical address bits is physical address bits [15:13]. In other implementations, the fourth and fifth subsets of physical address bits are other ranges of physical address bits, depending on the block size, stride size, total address space size, and other factors.

[0042] If the first subset of bits is less than the first number (conditional block 925, "no" branch), the control unit selects a memory channel using conventional methods and generates a normalized address for the physical address of the memory request (block 955). Following blocks 950 and 955, the memory controller accesses the memory on the selected memory channel using the normalized address to fulfill the memory request (block 960). Following block 960, method 900 ends.

[0043] Now turn Figure 10, shows another implementation of pseudocode 1000 for selecting a memory channel and converting a physical memory address to a normalized address. For the purposes of pseudocode 1000, it is assumed that there are five active memory channels out of the eight physical memory channels in the memory subsystem. In other words, for pseudocode 1000, it is assumed that the numerator of the ratio of the number of active memory channels to the total number of physical memory channels in the memory subsystem is five and the denominator is eight after simplification. Therefore, in this implementation, the first line of pseudocode 1000 checks whether physical address bits [12:10] are greater than or equal to 5, where 5 is the number of active memory channels.

[0044] The first line of pseudocode 1000 sets the remap_ID bits [2:0] equal to 3 times the physical address bits [43:16] plus the sum of the physical address bits [12:10] modulo 5. The second line of pseudocode 1000 sets the mod_ID bits [2:0] equal to either the remap_ID bits [2:0] or the physical address bits [12:10], depending on whether the physical address bits [12:10] are greater than or equal to 5. In the third line of pseudocode 1000, the channel ID bits [4:0] are set equal to the concatenation of the mod_ID bits [2:0] and the physical address bits [9:8]. The channel ID bits [4:0] select which memory channel the received memory request is routed on, with a maximum number of memory channels being 32 for this particular implementation. In other implementations, the number of channel ID bits may vary depending on the maximum number of memory channels supported.

[0045] The upper_bits[43:16] of the bit array are set equal to the value of the physical address bits [12:10] shifted up by the variable (addr_space–3). The lower_bits[43:16] of the bit array are set equal to the output of a bitwise AND operation between 1 and the value of the physical address bits [43:16] shifted up by the variable (addr_space–3). Depending on whether the physical address bits [12:10] are greater than or equal to 5, bits [43:11] of the normalized address are set equal to the result of a bitwise OR operation between the upper_bits of the bit array and the lower_bits of the bit array, or equal to the physical address bits [43:16]. Bits [10:0] of the normalized address are set equal to the concatenation of physical address bits [15:13] and physical address bits [7:0]. It should be understood that the exemplary pseudocode 1000 is indicative of code that may be used in one particular implementation. The sizes of the various bit arrays used within the pseudo-code 1000 and the sizes of the specific bits within the physical addresses may vary for other implementations. The sizes of the various bit arrays used and the sizes of the specific bits within the physical addresses may vary depending on the total address space, stride size, block size, number of active memory channels, number of physical memory channels, etc.

[0046] In various implementations, program instructions of a software application are used to implement the methods and / or mechanisms described herein. For example, program instructions that can be executed by a general-purpose processor or a special-purpose processor are envisioned. In various implementations, such program instructions are represented by a high-level programming language. In other implementations, the program instructions are compiled from the high-level programming language into a binary form, an intermediate form, or other form. Alternatively, program instructions describing the behavior or design of the hardware are written. Such program instructions are represented by a high-level programming language such as C. Alternatively, a hardware design language (HDL) such as Verilog is used. In various implementations, the program instructions are stored on any one of a variety of non-transitory computer-readable storage media. During use, a computing system can access the storage medium to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors configured to execute the program instructions.

[0047] It should be emphasized that the above implementations are merely non-limiting examples of implementations. Once the above disclosure is fully understood, various changes and modifications will become apparent to those skilled in the art. The following claims are intended to be interpreted as encompassing all such changes and modifications.

Claims

1. A system comprising: One or more clients; as well as a memory subsystem having a first ratio of active memory channels to total memory channels, wherein the memory subsystem has a non-power-of-two number of active memory channels; The memory subsystem includes a control unit configured to: simplifying the first ratio to a second ratio of the first number to the second number; receiving a memory request from one of the one or more clients; In response to determining that a first subset of physical address bits of the memory request have a value greater than or equal to the first number: calculating a third number based on a value corresponding to a modulo operation of the first number with respect to a second subset of physical address bits; selecting a memory channel from a plurality of memory channels using a concatenation of the third number and a third subset of physical address bits; as well as The memory request for the selected memory channel is completed.

2. The system of claim 1 , wherein in response to determining that the first subset of physical address bits of the memory request has a value greater than or equal to the first number, the control unit is further configured to: calculating a fourth number based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem; calculating a first subset of normalized address bits to be equal to said second subset of physical address bits with the upper bits replaced by said first subset of physical address bits; computing a second subset of normalized address bits equal to the concatenation of the fourth subset of physical address bits and the fifth subset of physical address bits; and The memory request is completed to a normalized address on the selected memory channel, wherein the normalized address includes the first subset of normalized address bits and the second subset of normalized address bits.

3. The system of claim 2, wherein the memory subsystem has a non-power-of-two number of active memory channels.

4. The system of claim 3, wherein the first subset of physical address bits is adjacent to the third subset of physical address bits.

5. The system of claim 4, wherein the fourth subset of physical address bits is adjacent to the first subset of physical address bits.

6. The system of claim 5, wherein the third subset of physical address bits is adjacent to the fifth subset of physical address bits.

7. The system of claim 1, wherein the plurality of clients are graphics engines, and wherein the memory requests are generated as part of an application for rendering pixels to be displayed on a display.

8. A method comprising: determining, by a control unit of the first device, a number of active memory channels from a total number of physical memory channels in the memory subsystem; simplifying the ratio of the number of active memory channels to the total number of physical memory channels to the ratio of the first number to the second number; In response to determining that a first subset of physical address bits of the received memory request is greater than or equal to the first number: calculating a third number based on a value corresponding to a modulo operation of the first number with respect to a second subset of physical address bits; selecting a memory channel from a plurality of memory channels using a concatenation of the third number and a third subset of physical address bits; as well as The memory request for the selected memory channel is completed.

9. The method of claim 8, wherein in response to determining that the first subset of physical address bits of the memory request is greater than or equal to the first number, the method further comprises: calculating a fourth number based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem; calculating a first subset of normalized address bits to be equal to said second subset of physical address bits with the upper bits replaced by said first subset of physical address bits; calculating a second subset of normalized address bits equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; as well as The memory request is completed to a normalized address on the selected memory channel, wherein the normalized address includes the first subset of normalized address bits and the second subset of normalized address bits.

10. The method of claim 9, wherein the memory subsystem has a non-power-of-two number of active memory channels.

11. The method of claim 10, wherein the first subset of physical address bits is adjacent to the third subset of physical address bits.

12. The method of claim 11, wherein the fourth subset of physical address bits is adjacent to the first subset of physical address bits.

13. The method of claim 12, wherein the third subset of physical address bits is adjacent to the fifth subset of physical address bits.

14. The method of claim 8, further comprising generating the memory request as part of an application for rendering pixels to be displayed on a display.

15. A device comprising: control unit; as well as a memory subsystem comprising a plurality of memory channels; The control unit is configured as follows: determining a number of active memory channels from a total number of physical memory channels in the memory subsystem; simplifying the ratio of the number of active memory channels to the total number of physical memory channels to the ratio of the first number to the second number; In response to determining that a first subset of physical address bits of the received memory request is greater than or equal to the first number: calculating a third number, the third number being a modulo operation of the first number based on a second subset of physical address bits; selecting one of the plurality of memory channels using a concatenation of the third number and a third subset of physical address bits; as well as The memory request for the selected memory channel is completed.

16. The apparatus of claim 15 , wherein in response to determining that the first subset of physical address bits of the memory request is greater than or equal to the first number, the control unit is further configured to: calculating a fourth number based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem; calculating a first subset of normalized address bits to be equal to said second subset of physical address bits with the upper bits replaced by said first subset of physical address bits; computing a second subset of normalized address bits equal to the concatenation of the fourth subset of physical address bits and the fifth subset of physical address bits; and The memory request is completed to a normalized address on the selected memory channel, wherein the normalized address includes the first subset of normalized address bits and the second subset of normalized address bits.

17. The apparatus of claim 16, wherein the memory subsystem has a non-power-of-two number of active memory channels.

18. The apparatus of claim 17, wherein the first subset of physical address bits is adjacent to the third subset of physical address bits.

19. The apparatus of claim 18, wherein the fourth subset of physical address bits is adjacent to the first subset of physical address bits.

20. The apparatus of claim 19, wherein the third subset of physical address bits is adjacent to the fifth subset of physical address bits.

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