A power transistor coupled to a plurality of sense transistors

Abstract

An electronic device comprises: a first semiconductor die (102); a power transistor (104) integrated in the first semiconductor die, the power transistor comprising a first gate (104g), a first terminal (104s) and a second terminal (104d); a first sensing transistor (106) integrated in the first semiconductor die, the first sensing transistor comprising a second gate (106g), a third terminal (106s) and a fourth terminal (106d), the second gate being coupled to the first gate and the fourth terminal being coupled to the second terminal; a first resistor (106R) having a first temperature coefficient; a second sensing transistor (108) integrated in the first semiconductor die, the second sensing transistor comprising a third gate (108g), a seventh terminal (108s) and an eighth terminal (108d), the third gate being coupled to the first gate and the eighth terminal being coupled to the second terminal; and a second resistor (108R) having a second temperature coefficient.

Description

Background Art

[0001] Some electronic devices include a measurement system that calculates a high amplitude signal (eg, 10 A) using a low amplitude signal (eg, 10 mA) derived from the high amplitude signal. Summary of the invention

[0002] In at least one example, an electronic device includes a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor including a first gate, a first terminal, and a second terminal; a first sensing transistor integrated in the first semiconductor die, the first sensing transistor including a second gate, a third terminal, and a fourth terminal, the second gate being coupled to the first gate, and the fourth terminal being coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor having a first temperature coefficient, the first resistor including a fifth terminal and a sixth terminal, wherein the third terminal is coupled to the fifth terminal; a second sensing transistor integrated in the first semiconductor die, the second sensing transistor including a third gate, a seventh terminal, and an eighth terminal, the third gate being coupled to the first gate, and the eighth terminal being coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor having a second temperature coefficient, the second resistor including a ninth terminal and a tenth terminal, wherein the seventh terminal is coupled to the ninth terminal.

[0003] In at least another example, an electronic fuse (eFuse) includes: a controller; a first transistor configured to conduct a load current between a first terminal and a second terminal of the first transistor, wherein the first terminal is coupled to the controller at a first node; a second transistor coupled to the first transistor at a second terminal, wherein a third terminal of the second transistor is coupled to the controller at a second node via a first resistor, the first resistor having a first temperature coefficient; and a third transistor coupled to the first transistor at the second terminal, wherein a fourth terminal of the third transistor is coupled to the controller at a third node via a second resistor, the second resistor having a second temperature coefficient, wherein the controller is configured to generate a first sensing current and a second sensing current, the first sensing current being related to / a function of the first temperature coefficient, and the second sensing current being related to / a function of the second temperature coefficient.

[0004] In at least another example, a method includes: measuring, by a controller, a first sensing current and a second sensing current, wherein the first sensing current is received via a first sensing transistor and the second sensing current is received via a second sensing transistor, wherein the first transistor and the second transistor are coupled to a power transistor, wherein the first transistor is coupled to the controller via a first resistor and the second sensing transistor is coupled to the controller via a second resistor; calculating, by the controller, a desired sensing current value using the first sensing current and the second sensing current; and calculating, by the controller, a load current flowing through the power transistor using the desired sensing current value. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 Illustrative electronic devices in various examples are shown.

[0006] FIG. 2( a ) shows an illustrative controller unit of an electronic device in various examples.

[0007] FIG. 2( b ) shows another illustrative controller unit of an electronic device in various examples.

[0008] Figure 3 Illustrative methods for calculating sense current in various examples are shown. DETAILED DESCRIPTION

[0009] Some power circuits employ power transistors, which in some cases provide a current (hereinafter referred to as load current) to a load. The load current is a large current (e.g., 10A), which needs to be measured in some power system applications, such as electronic fuses (eFuse). It is preferred to measure this large current indirectly, rather than directly measuring the load current using, for example, an ammeter. Indirect measurement can be accomplished by coupling a sensing transistor (which is relatively small in size (e.g., a smaller channel width) relative to the size of the power transistor) to the power transistor in such a way that when the power transistor is turned on, the sensing transistor has a drain-source current (also referred to herein as sensing current) indicating the load current of the power transistor. Thus, by measuring (or in other words, sensing) the sensing current, an indirect measurement of a load current having a magnitude much greater than the sensing current can be performed. This indirect measurement is facilitated by using a sensing transistor of a different size from the power transistor. The size can be selected so that the load current is related to the sensing current by a multiplier factor. In some cases, the multiplier factor is referred to as a sensing ratio. After sensing the sensing current, the sensing ratio can be multiplied by the sensing current to calculate the load current. A measurement circuit coupled to the power transistor and the sense transistor may be employed to measure (or sense) the sense current and calculate the load current.

[0010] The sensing ratio can be expressed as the ratio of the resistances along the current flow paths of the sensing transistor and the power transistor, respectively. The resistance experienced by the current in the sensing transistor and the power transistor includes parasitic resistances introduced due to the conductive properties of the materials used to manufacture the power transistor and the sensing transistor. In addition, these parasitic resistances are different along the two current flow paths. Since resistance is a function of temperature, the parasitic resistances of both the power transistor and the sensing transistor vary with temperature, but at different rates, which introduces errors in the sensing ratio and further introduces errors in the measurement / calculation of the load current. In other words, since the parasitic resistances of the two transistors vary differently with temperature, the sensing ratio changes, thereby introducing errors in the measured load current value as the sensing current varies with temperature. In addition, the relationship between the sensing current and the load current can vary depending on the gate-source (VGS) bias provided to the power transistor.

[0011] In order to mitigate the effects of parasitic resistance and / or gate bias on the sense current of a power circuit including a sense transistor and a power transistor, in some examples, at least two sense transistors are coupled to the power transistor. Each of the at least two sense transistors is coupled to a different resistor (hereinafter referred to as a compensation resistor) at its respective source terminal. These compensation resistors at least partially compensate for the errors introduced in the sense current due to temperature and gate-to-source bias variations. In at least some examples, the temperature coefficients of the compensation resistors are different. In some examples, as further described below, the load current of the power transistor can be calculated at least in part using a known temperature coefficient value of the compensation resistor and a sense current measured from the sense transistor. Compensation resistors with different temperature coefficients can be manufactured by using one element (e.g., metal) or by mixing different elements (e.g., polysilicon and metal). In some examples, one compensation resistor includes polysilicon, while another compensation resistor includes metal. In other examples, one compensation resistor may include both metal and polysilicon, while another compensation resistor may include metal. In other examples, various other combinations of one or more elements may be used to manufacture compensation resistors with different temperature coefficients. In at least some examples, the value of the temperature coefficient can be quantified.

[0012] Reference now Figure 1, an illustrative electronic device 100 is shown. The electronic device 100 includes a power transistor 104 integrated on a semiconductor die 102. The electronic device 100 also includes sense transistors 106, 108 integrated on the semiconductor die 102. In one example, the power transistor 104 and the sense transistors 106, 108 are n-type metal oxide semiconductor field effect transistors (nMOSFET or nMOS). In such an example, the power transistor 104 includes a drain terminal 104d, a source terminal 104s, and a gate terminal 104g. The sense transistor 106 includes a drain terminal 106d, a source terminal 106s, and a gate terminal 106g. The sense transistor 108 includes a drain terminal 108d, a source terminal 108s, and a gate terminal 108g. The drain terminals 104d, 106d, and 108d are coupled to each other at a node 111.

[0013] In some examples, the power transistor 104 includes a large number (e.g., about 1000) of transistor cells integrated in the semiconductor die 102 and coupled together in parallel, so that the power transistor 104 has a relatively large drain-source current when turned on. As described above, in some examples, the sense transistors 106, 108 are manufactured on the same semiconductor die 102 and are manufactured in the same process flow as the power transistor 104. The size of the sense transistors 104, 106 is much smaller than the power transistor 104. In some embodiments, the sense transistors 106, 108 include transistor cells integrated in the semiconductor die 102 and coupled together in parallel, but the number of parallel-connected transistor cells constituting the sense transistors 106, 108 is much smaller than the number of parallel-connected transistor cells constituting the power transistor 104. In operation, when both the sense transistors 106 , 108 and the power transistor 104 are turned on, the respective drain-source currents (ie, sense currents) of the sense transistors 106 , 108 are much smaller than the drain-source current of the power transistor 104 .

[0014] From a manufacturing and fabrication perspective, in some examples, power transistor 104 and sense transistors 106, 108 share a region of silicon forming their drain terminals, such as drain terminals 104d, 106d, and 108d in semiconductor die 102, thereby effectively coupling their respective drain terminals together. This coupled drain terminal is represented as drain terminal 110. For some examples where the power transistor and sense transistor are nMOS transistors, this shared region of silicon can be referred to as a drain region in semiconductor die 102. Resistor 105 and resistor 107 represent the parasitic (and / or distributed) resistance of drain terminal 110. Let R SUB1 and R SUB2The two parasitic resistors R SUB1 +R SUB2 The sum of is the total parasitic resistance of the drain terminal 110. In other words, Figure 1 The circuit of FIG. 1 shows drain terminals 106 d , 108 d of sense transistors 106 , 108 , respectively, connected to node 111 , indicating that resistor 105 represents a parasitic resistance R common to both power transistor 104 and sense transistors 106 , 108 . SUB2 The resistor 114 represents a parasitic resistance associated with the source terminal 104 s of the power transistor 104 .

[0015] Resistor 106R has a first terminal 135 coupled to source terminal 106d of sense transistor 106 and a second terminal 136 coupled to first node 120 of sub-controller 150 as part of controller 132. In some examples, controller 132 includes other additional circuitry ( Figure 1 In some examples, the controller unit 132 includes a processing unit (in Figure 1 2(a)) and a storage device (e.g., RAM (random access memory), ROM (read only memory)), which may include any suitable type of non-transitory computer-readable medium storing machine-executable instructions. When executed by the processing unit, the machine-executable instructions cause the processing unit to perform one or more actions attributed to the controller unit 132 herein. The controller unit 132 includes a first sensing current I , which is respectively coupled to the transistors 106 and 108 and is configured to respectively sense / measure the first sensing current I SNS1 and the second sensing current I SNS2 2 , controller 132 is integrated on second semiconductor die 118. In some examples, controller 132 is integrated on semiconductor die 102.

[0016] The sub-controller 150 includes a node 138 coupled to a terminal 112 of the power transistor 104. The terminal 112 is coupled to the source terminal 104s via a resistor 114. The sub-controller 150 is coupled to the resistor 106R to provide a virtual connection from the resistor 106R to the terminal 112 of the power transistor 104. The sub-controller 150 includes an operational amplifier 124 including a first input port 139 coupled to the terminal 112 of the power transistor 104, a second input port 140 coupled to the second terminal 136 of the resistor 106R, and an output port 141. The sub-controller 150 also includes a pass transistor 128 having a gate terminal 128g, a source terminal 128s, and a drain terminal 128d. The gate terminal 128g is coupled to the output port 141 of the operational amplifier 124, and the source terminal 128s is coupled to the terminal 136 of the resistor 106R. The sub-controller 150 includes a negative feedback arrangement in which the sub-controller 150 is coupled to the resistor 106R and the terminal 112 of the power transistor 104 to maintain a first voltage at the first node 120 substantially equal to a second voltage at the node 138. The sub-controller 150 causes only a negligible amount of current to flow from the second terminal 136 of the resistor 106R to the terminal 112 of the power transistor 104, thereby providing a virtual connection between the nodes 138 and 120.

[0017] Similar to resistor 106R, resistor 108R has a first terminal 133 coupled to source terminal 108s of sense transistor 108 and a second terminal 134 coupled to first node 122 of sub-controller 160, which is part of controller 132 as described above. Sub-controller 160 includes node 144 coupled to terminal 112 of power transistor 104. Sub-controller 160 is coupled to resistor 108R to provide a virtual connection from resistor 108R to terminal 112 of power transistor 104. Sub-controller 160 includes operational amplifier 126 including first input port 146 coupled to terminal 112 of power transistor 104, second input port 148 coupled to second terminal 124 of resistor 108R, and output port 151. Sub-controller 160 further includes pass transistor 130 having gate terminal 130g, source terminal 130s, and drain terminal 130d. The gate terminal 130g is coupled to the output port 151 of the operational amplifier 126, and the source terminal 130s is coupled to the terminal 134 of the resistor 108R. The sub-controller 160 includes a negative feedback arrangement in which the sub-controller 160 is coupled to the resistor 108R and the terminal 112 of the power transistor 104 to maintain a first voltage at the first node 122 substantially equal to a second voltage at the node 144. The sub-controller 160 causes only a negligible amount of current to flow from the second terminal 134 of the resistor 108R to the terminal 112 of the power transistor 104, thereby providing a virtual connection between the nodes 144 and 122.

[0018] Resistors 106R, 108R are integrated on semiconductor die 102. Resistors 106R, 108R have different temperature coefficients. For example, resistor 106R can be manufactured by using one element (e.g., metal) or by mixing different elements (e.g., polysilicon and metal). The temperature coefficient of resistor 106R can be expressed as TC 106 On the other hand, resistor 108R may be fabricated using a different combination of one or more elements such that the resulting temperature coefficient of resistor 108R is different from the temperature coefficient of resistor 106R. The temperature coefficient of resistor 108R may be represented by TC 108 Indicates that the temperature coefficient TC 106 and TC 108unequal. In at least some examples, resistors 106R, 108R are designed to have resistances that compensate for the effects of parasitic resistance on the drain-source current of computing transistor 104. In at least some examples, these temperature coefficient values ​​can be quantized and stored in a memory of controller unit 132. In some cases, the stored value of the temperature coefficient may need to be corrected because the temperature coefficient may change over time or for some other reason. In such a case, controller unit 132 can be configured to automatically correct the temperature coefficient value by at least partially using equation 1 described below.

[0019] The load current is the product of the sense ratio and the sense current, and as mentioned above, the sense ratio is the ratio of the resistance seen by the sense current to the resistance seen by the load current. Therefore, the sense current Isns can be expressed as Among them I L is the load current, R L is the resistance seen by the load current, and R S is the resistance seen by the sense current. These resistances can be expressed as quadratic functions of temperature, leading to the following expression for the sense current: I sns =I snso (1+TC1 sns ΔT+TC2 sns ΔT 2 ). Here, I snso is the desired sensing current (or in other words, the temperature-independent sensing current), ΔT is the change in temperature, and TCl sns and TC2 sns are the linear and quadratic temperature coefficients of the expected sensed current, respectively. In some cases, the true sensed ratio is stored in the controller unit 132, and the sensed current is adjusted (or in some examples, automatically corrected) for temperature changes.

[0020] As described above, sub-controller 150 causes only a negligible amount of current to flow from second terminal 136 of resistor 106R to terminal 112 of power transistor 104, thereby providing a virtual connection between nodes 138 and 120. Similarly, sub-controller 160 causes only a negligible amount of current to flow from second terminal 134 of resistor 108R to terminal 112 of power transistor 104, thereby providing a virtual connection between node 138 (or node 144) and node 122. In other words, the voltage potential at node 120 and the voltage potential at node 138 are substantially similar; and the voltage potential at node 122 and the voltage potential at node 144 are substantially similar. Referring now to the operation of electronic device 100, when transistor 104 is turned on (by a gate signal sent via controller unit 132), a load current flows out of transistor 104 (depending on the drain-to-source voltage). Transistors 106, 108 are coupled to transistor 104 so that a current mirroring the load current flows out of transistors 106, 108. Since operational amplifiers 124 and 126 have very high input impedances, the sense current flowing through transistors 106 and 108 continues to flow unattenuated through pass transistors 128 and 130, respectively, as shown in FIG. SNS1 and ISNS2 . The pass transistors 128, 130 are biased so that the transistors 128, 130 operate in the saturation region and therefore the current flowing through them depends only on their respective gate voltages. Since a negative feedback arrangement is used in the sub-controllers 150, 160, disturbances that may cause the potential at the nodes 120, 122 to be different from the potential at the nodes 138, 144, respectively, are compensated by the operational amplifiers 124, 126, respectively. In other words, if the mirror image of the current between the power transistor 104 and the sense transistors 106, 108 is distorted, it is compensated for by an equivalent adjustment in the output of the operational amplifiers 124, 126, which are coupled to the gates of the pass transistors 128, 130, respectively. This results in automatic correction of the voltage at the nodes 120, 122 and the sense current I, respectively. SNS1 ,I SNS2 .

[0021] In some of the above examples, transistors 104, 106, 108 are all n-type metal oxide semiconductor field effect transistors (nMOSFETs). In other examples, transistors 104, 106, 108 are all p-type metal oxide semiconductor field effect transistors (pMOSFETs). In some examples, transistors 106, 108 are vertical nMOSFETs. However, the examples are not limited to vertical transistors and may include lateral transistors. Figure 1In the example shown, the pass transistors 128, 130 are p-type metal oxide semiconductor field effect transistors (pMOSFETs). In other examples, the transistors 128, 130 are n-type metal oxide semiconductor field effect transistors (nMOSFETs).

[0022] Referring now to FIG. 2( a ), an illustrative controller unit 132 is shown. The controller unit 132 facilitates calculation of a desired sense current, which in turn facilitates calculation of a drain-to-source current of a power transistor. In one example, the controller unit 132 includes a processing unit (hereinafter referred to as a “processor”) 205, a memory unit (hereinafter referred to as a “memory”) 210 coupled to the processor 205. A current measurement unit 206 is coupled to the processor 205. In some examples, the memory 210 includes a RAM (random access memory) and a ROM (read-only memory)). In some examples, the memory 210 includes any suitable type of non-transitory computer-readable medium storing machine-executable instructions. The machine-executable instructions, when executed by the processor 205, cause the processor 205 to perform one or more actions attributed to the controller unit 132 herein. The sub-controllers 150 and 160 are coupled to the current measurement unit 206 via conductors 202 and 201 , respectively. In some examples, the current measurement unit 206 includes one or more resistors of known values ​​that are configured to convert the sense current I SNS1 ,I SNS2 Converted to voltage V SNS1 and V SNS2 These voltages may be further digitized using an analog-to-digital converter - the output of which may be processed in the controller unit 132 .

[0023] The processor 205 is configured to calculate the desired sensing current I SNS0 , and then calculate the drain-to-source current of transistor 104. Now refer to Figure 3 , shows the method for calculating the desired sensing current I SNS0 The method 300 begins with step 305, which includes measuring a first sensing current I SNS1 and the second sensing current I SNS2 This is done by the current measurement unit 206 present in the controller unit 132. After the current measurement, the measured value may be transmitted to the processor 205, or in some examples, stored in the memory 210. The method 300 then moves to step 310, which includes calculating the desired sensing current I SNS0 In some examples, the calculation is performed using a current-temperature relationship that defines the first current and the second current as:

[0024] I sns1 =Isns0 (1+TC1 sns1 ΔT+TC2 sns1 ΔT 2} (1)

[0025] I sns2 =I sns0 (1+TC1 sns2 ΔT+TC2 sns2 ΔT 2 ) (2), where I SNS1 ,I SNS2 is the sensed current value received from the sub-controllers 150, 160; I SNS0 is the desired sense current value; TC1 sns1 、TC1 sns2 TC2 is the linear temperature coefficient value of the sensing current associated with 106 and 108 respectively; sns1 、TC2 sns2 is the quadratic temperature coefficient value of the sense current associated with 106 and 108, respectively; and ΔT is the temperature change value. ΔT and I SNS0 The values ​​are unknown. Both quadratic relations defined above have three known variables (e.g., TC1 in Eq. sns1 、TC2 sns1 and I SNS1 ; and TC1 in Equation 2 sns2 、TC2 sns2 and I SNS2 ) and two unknown variables. Known variable TC1 snsl 、TC2 sns1 、TCl sns2 、TC2 sns2 may be stored in the memory 210. ΔT may be calculated by the processor 205 using Equation 3 depicted below:

[0026]

[0027] And I SNS0 The value can be calculated using Equation 4 depicted below:

[0028]

[0029] After calculating the desired current sense I SNS0 Thereafter, the method 300 moves to step 315, which includes calculating the drain-to-source current of the transistor 104. This is done by using a predefined sensing ratio and a desired current sensing I SNS0 For example, assuming the sense ratio is defined by “SR”, the drain-to-source current of transistor 104 is SR x I SNS0In some examples, the method 300 then moves to step 320, which includes comparing the drain-to-source current value to a threshold value. If the drain-to-source current value is above the threshold value, the controller unit 132 performs an action based on the comparison. For example, in an eFuse application, the controller unit 132 may be configured to shut off the flow of current in an electrical system where the flow of current is equal to or greater than a rated value (e.g., a threshold value).

[0030] Some examples of the controller unit 132 may include analog circuitry to generate a desired sensing current I SNS0 , which in turn can be used to calculate the drain-to-source current of transistor 104. Referring now to FIG. 2(b), an illustrative controller unit 132 is shown that includes a weighted averaging technique to calculate the desired sense current I SNS0 . In some examples, such a technique includes resistors 215, 220 having resistances R1, R2, respectively. Such a technique may further include additional resistors 221, 221 coupled to resistors 215, 220 at nodes 217, 218, respectively. The resistance of resistors 221, 222 may be higher than resistors R1, R2, so that resistors R1, R2 are used as weights in a weighted averaging technique. Resistors 221, 222 are coupled at node 219, which is further coupled to an operational amplifier 232 via conductor 230. Operational amplifier 232 includes a feedback resistor 244. In the example depicted in FIG2(b), the negative terminal of operational amplifier 232 is coupled to a ground source (or virtual ground source) via terminal 225 and / or resistor 233. The output V of operational amplifier 232 out It can be calculated by the following weighted average equation: V out =R1I SNS1 +R2I SNS2 . The output V out Further digitization may be performed using an analog-to-digital converter, and the digitized data may be processed in a processor (not explicitly depicted) similar to processor 205 .

[0031] In the foregoing discussion and claims, the term "including" is used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to..." In addition, the term "coupled" is intended to mean an indirect or direct connection. An element or feature "configured to" perform a task or function may be configured (e.g., programmed or structurally designed) by the manufacturer at the time of manufacture to perform the function and / or may be configurable (or reconfigurable) by the user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of hardware components, and the interconnection of the device, or a combination thereof. In addition, in the foregoing discussion, the use of the phrase "ground" or similar terms is intended to include frame ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of the specification. Unless otherwise specified, "approximately," "about," or "substantially" before a value refers to + / -10% of the value.

[0032] The above discussion is intended to illustrate principles and various embodiments. Once the above description is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the appended claims be interpreted as including all such variations and modifications.

Claims

1. An electronic device, comprising: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sensing transistor integrated in the first semiconductor die, the first sensing transistor comprising a second gate, a third terminal, and a fourth terminal, the second gate being coupled to the first gate, and the fourth terminal being coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor having a first temperature coefficient, the first resistor comprising a fifth terminal and a sixth terminal, wherein the third terminal is coupled to the fifth terminal; a second sensing transistor integrated in the first semiconductor die, the second sensing transistor comprising a third gate, a seventh terminal and an eighth terminal, the third gate being coupled to the first gate, and the eighth terminal being coupled to the second terminal; as well as A second resistor is integrated in the first semiconductor die, the second resistor having a second temperature coefficient, the second resistor including a ninth terminal and a tenth terminal, wherein the seventh terminal is coupled to the ninth terminal.

2. The electronic device according to claim 1, wherein: The first terminal is the source of the power transistor; The second terminal is a drain of the power transistor; The third terminal is a source of the first sensing transistor; The fourth terminal is a drain of the first sensing transistor; The seventh terminal is a source of the second sensing transistor; as well as The eighth terminal is a drain of the second sensing transistor.

3. The electronic device according to claim 2, wherein: The power transistor, the first sensing transistor and the second sensing transistor are all n-type metal oxide semiconductor field effect transistors, namely, nMOSFETs.

4. The electronic device according to claim 2, wherein: The power transistor, the first sensing transistor and the second sensing transistor are all p-type metal oxide semiconductor field effect transistors, namely, pMOSFETs.

5. The electronic device according to claim 1, further comprising a controller unit, the controller unit comprising: a first node coupled to the sixth terminal of the first resistor; a second node coupled to the tenth terminal of the second resistor; and A third node is coupled to the first terminal of the power transistor.

6. The electronic device according to claim 5, further comprising: A second semiconductor die, wherein the controller unit is integrated in the second semiconductor die.

7. The electronic device according to claim 5, wherein: The controller is configured to provide a virtual connection from the sixth terminal to the first terminal and a virtual connection from the tenth terminal to the first terminal. 8 . The electronic device of claim 5 , the controller being configured to maintain a first voltage at the first node that is substantially equal to a second voltage at the second node and a third voltage at the third node.

9. The electronic device according to claim 5, wherein: The controller is configured to generate a first sensing current and a second sensing current, and is further configured to calculate a desired sensing current value using the first sensing current and the second sensing current, wherein the desired sensing current is a scaled-down version of a current flowing between the first terminal and the second terminal.

10. The electronic device according to claim 1, wherein: The first temperature coefficient and the second temperature coefficient are different in magnitude.

11. An electronic fuse, comprising: Controller; a first transistor configured to conduct a load current between a first terminal and a second terminal of the first transistor, wherein the first terminal is coupled to the controller at a first node; a second transistor coupled to the first transistor at the second terminal, wherein a third terminal of the second transistor is coupled to the controller at a second node via a first resistor, the first resistor having a first temperature coefficient; and a third transistor coupled to the first transistor at the second terminal, wherein a fourth terminal of the third transistor is coupled to the controller at a third node via a second resistor, the second resistor having a second temperature coefficient, The controller is configured to generate a first sensing current and a second sensing current, wherein the first sensing current is a function of the first temperature coefficient and the second sensing current is a function of the second temperature coefficient.

12. The electronic fuse according to claim 11, wherein: The controller is configured to calculate a desired current value using the first sensed current and the second sensed current.

13. The electronic fuse according to claim 12, wherein: The controller is configured to shut down the electrical system if the controller determines that the expected current value is greater than a predefined value.

14. The electronic fuse according to claim 11, wherein: The first transistor, the second transistor and the third transistor are all n-type metal oxide semiconductor field effect transistors, namely, nMOSFETs.

15. The electronic fuse according to claim 11, wherein: The first transistor, the second transistor and the third transistor are all p-type metal oxide semiconductor field effect transistors, namely, pMOSFETs.

16. The electronic fuse according to claim 11, wherein: The controller is configured to provide a virtual connection from the first terminal to the third terminal and a virtual connection from the first terminal to the fourth terminal. 17 . The electronic fuse of claim 11 , the controller configured to maintain a first voltage at the first node that is substantially equal to a second voltage at the second node and a third voltage at the third node.

18. A method for a power transistor, comprising: measuring, by a controller, a first sense current and a second sense current, wherein the first sense current is received via a first sense transistor, the first sense current corresponding to a first indication of a load current flowing through the power transistor, and the second sense current is received via a second sense transistor, the second sense current corresponding to a second indication of the load current, wherein drain terminals of the first sense transistor and the second sense transistor are coupled to a drain terminal of the power transistor, wherein the first sense transistor is coupled to a first node of the controller via a first resistor, and the second sense transistor is coupled to a second node of the controller via a second resistor; calculating, by the controller, a desired sense current value using the first sense current and the second sense current; and The load current flowing through the power transistor is calculated by the controller using the desired sense current value.

19. The method according to claim 18, further comprising: comparing, by the controller, the load current with a threshold; as well as Based on the load current being greater than or equal to the threshold, shutting down the electrical system is caused.

20. The method according to claim 18, wherein: The first resistor has a first temperature coefficient and the second resistor has a second temperature coefficient, and wherein the first temperature coefficient and the second temperature coefficient are different.

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