Display device and method of manufacturing the same

Abstract

The display device includes a pixel circuit layer. A first electrode and a second electrode are disposed on the pixel circuit layer and are spaced apart from each other. A first insulating layer is disposed on the pixel circuit layer, the first electrode, and the second electrode. A conductive pattern is disposed on the first insulating layer and is electrically insulated from the first electrode and the second electrode. A levee is disposed on the conductive pattern. A light emitting element is disposed on the first insulating layer between the first electrode and the second electrode and is electrically coupled to the first electrode and the second electrode.

Description

Technical Field

[0001] Various embodiments of the present disclosure are directed to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting element using a material having a reliable inorganic crystal structure and manufacturing a light-emitting device using the light-emitting element has been developed. For example, a technology for constructing a light source of a light-emitting device using an ultra-small light-emitting element having a small size corresponding to a range from a nanometer-level size to a micrometer-level size has been developed. Such a light-emitting device can be used in various electronic devices such as display devices and lighting devices. Summary of the invention

[0003] Technical issues

[0004] The light emitting elements may be supplied onto the substrate through an inkjet scheme or the like, and the light emitting elements supplied to the respective emission regions may not be mixed with each other by banks provided to define the respective emission regions to which the light emitting elements are supplied.

[0005] Various embodiments of the present disclosure are directed to a display device including a bank having enhanced characteristics.

[0006] Various embodiments of the present disclosure are directed to a method of manufacturing a display device including a bank through a simpler process.

[0007] Technical Solution

[0008] According to aspects of the present disclosure, a display device according to an embodiment of the present disclosure may include: a pixel circuit layer; a first electrode and a second electrode, which are arranged on the pixel circuit layer and are spaced apart from each other; a first insulating layer, which is arranged on the pixel circuit layer, the first electrode and the second electrode; a conductive pattern, which is arranged on the first insulating layer and is electrically insulated from the first electrode and the second electrode; a dam, which is arranged on the conductive pattern; and a light-emitting element, which is arranged on the first insulating layer between the first electrode and the second electrode and is electrically coupled to the first electrode and the second electrode.

[0009] In an embodiment, an angle between a sidewall of the bank and an upper surface of the first insulating layer may be in a range of 70° to 90°.

[0010] In an embodiment, the bank may completely overlap the conductive pattern, and a sidewall of the bank may be located in the same plane as a plane of the sidewall of the conductive pattern.

[0011] In an embodiment, the bank may include a groove in a boundary surface thereof bordering the conductive pattern, the groove being formed in a sidewall of the bank. A portion of the bank adjacent to the boundary surface may have an inverted tapered shape.

[0012] In an embodiment, the bank may overlap the conductive pattern.On a boundary surface between the bank and the conductive pattern, a first width of the bank may be greater than a second width of the conductive pattern.

[0013] In an embodiment, the conductive pattern may include a conductive material removed by wet etching.

[0014] In an embodiment, the conductive pattern may include a transparent conductive material.

[0015] In an embodiment, the bank may include a light shielding material configured to block light incident from the light emitting element.

[0016] In an embodiment, the display device may further include: a first bank pattern disposed between the first electrode and the pixel circuit layer; and a second bank pattern disposed between the second electrode and the pixel circuit layer. The light emitting element may be disposed between the first bank pattern and the second bank pattern. The thickness of the bank may be greater than the thickness of the first bank pattern.

[0017] In embodiments, the conductive pattern may not overlap the first bank pattern and the second bank pattern.

[0018] In an embodiment, the display device may further include: a first contact electrode, which is arranged on the first end of each light emitting element and a region of the first electrode, and is configured to electrically connect the first end to the first electrode; and a second contact electrode, which is arranged on the second end of each light emitting element and a region of the second electrode, and is configured to electrically connect the second end to the second electrode.

[0019] In an embodiment, the conductive pattern, the first contact electrode, and the second contact electrode may be disposed on the same plane.

[0020] In an embodiment, a thickness of the conductive pattern may be different from a thickness of the first contact electrode.

[0021] In an embodiment, the pixel circuit layer may include a first emission region, a second emission region, and a third emission region separated from each other by a dam. The light-emitting element may include a first light-emitting element disposed in the first emission region, a second light-emitting element disposed in the second emission region, and a third light-emitting element disposed in the third emission region. The first light-emitting element, the second light-emitting element, and the third light-emitting element may emit light of different colors.

[0022] In an embodiment, each of the light emitting elements may include a rod-shaped light emitting diode having a size ranging from nanometer scale to micrometer scale.

[0023] According to aspects of the present disclosure, a display device according to an embodiment of the present disclosure may include: a pixel circuit layer; a first electrode and a second electrode, which are arranged on the pixel circuit layer and are spaced apart from each other; a first insulating layer, which is arranged on the pixel circuit layer, the first electrode and the second electrode; a dam, which is formed on the first insulating layer; a conductive pattern, which is arranged to overlap with the dam and is electrically insulated from the first electrode and the second electrode; and a light-emitting element, which is arranged on the first insulating layer between the first electrode and the second electrode and is electrically coupled to the first electrode and the second electrode.

[0024] According to aspects of the present disclosure, a method for manufacturing a display device according to an embodiment of the present disclosure may include: preparing a pixel circuit layer; forming a first electrode and a second electrode spaced apart from each other on the pixel circuit layer; forming a first insulating layer on the pixel circuit layer, the first electrode and the second electrode; forming a light-shielding layer on the first insulating layer; patterning the light-shielding layer using a mask; and forming a dam by etching the light-shielding layer exposed by the mask.

[0025] In an embodiment, the step of forming a light shielding layer on the first insulating layer may include: forming a conductive layer on the first insulating layer; and forming the light shielding layer on the conductive layer.

[0026] In an embodiment, the step of forming the bank may include: dry etching the light shielding layer exposed through the mask; and wet etching the portion of the conductive layer exposed through the mask and the mask.

[0027] In an embodiment, the mask and the conductive layer may include the same material.

[0028] Beneficial Effects

[0029] In the display device and the method of manufacturing the same according to the embodiment of the present disclosure, the bank may be formed by a dry etching process, so that the bank having a desired etching profile angle and a desired thickness may be easily formed.

[0030] In addition, in the display device and the method for manufacturing the display device according to the embodiment of the present disclosure, the conductive pattern (or conductive layer) is formed under the dam, so that during the dry etching process, the lower structure (for example, the first insulating layer and the first and second electrodes) can be prevented from being damaged, and the residue of the dam can be removed. Therefore, defects caused by the residue (for example, a short circuit defect attributable to the residue or an alignment defect of the light-emitting element) can be prevented from being caused. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a and Figure 1b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0034] Figure 4 is a plan view of a display device according to an embodiment of the present disclosure.

[0035] Figure 5a to Figure 5c It is shown Figure 4 A circuit diagram of an example of a sub-pixel included in a display device.

[0036] Figure 6 It is shown Figure 4 A plan view of an example of a pixel included in a display device.

[0037] Figure 7 It is shown along Figure 6 A cross-sectional view of an example of a sub-pixel taken along line II'.

[0038] Figure 8a and Figure 8b It is shown Figure 7 An enlarged cross-sectional view of an example of a first region.

[0039] Figures 9a to 9c It is shown along Figure 6 A cross-sectional view of another example of a sub-pixel taken along line II'.

[0040] Fig.10 It is shown along Figure 6 A cross-sectional view of an example of a pixel taken along line II-II'.

[0041] Figures 11a to 11e It shows the manufacturing Figure 7 A cross-sectional view of an example of a sub-pixel process.

[0042] Fig.12a It is shown Figure 6 Electron microscope image of an example of pixel comparison.

[0043] Figure 12b It is shown Figure 6 An electron microscope image of an example of pixels.

[0044] Fig.13a and Fig.13b is to show that the light emitting element is Figure 7 A cross-sectional view of an example of a process for aligning sub-pixels in FIG.

[0045] Figures 14a to 14c It shows the manufacturing Figure 7 A cross-sectional view of an example of a sub-pixel process.

[0046] Figures 15a to 15d It is shown along Figure 6 A cross-sectional view of another example of a sub-pixel taken along line II'.

[0047] Figures 16a to 16d It shows the manufacturing Fig.15a A cross-sectional view of an example of a sub-pixel process. DETAILED DESCRIPTION

[0048] Since the embodiments of the present disclosure can be variously modified in many different forms, reference will now be made in detail to the various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below. However, the present disclosure is not limited to the following embodiments and can be modified into various forms.

[0049] In the accompanying drawings, some elements that are not directly related to the features of the present disclosure may be omitted to clearly explain the present disclosure. In addition, the sizes, proportions, etc. of some elements in the accompanying drawings may be slightly exaggerated. It should be noted that throughout the accompanying drawings, the same reference numerals are used to indicate the same or similar elements, and repeated descriptions will be omitted.

[0050] It will be understood that, although the terms "first", "second", etc. may be used here to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, it is explained that there are stated features, wholes, steps, operations, elements, components and / or combinations thereof, but it is not excluded that there are or add one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first component such as a layer, film, region or plate is disposed on a second component, the first component can not only be directly on the second component, but a third component can be placed between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions according to the viewing angle or direction.

[0051] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings to describe the present disclosure in detail so that a person skilled in the art with ordinary knowledge in the technical field to which the present disclosure belongs can easily practice the present disclosure. In addition, as long as there is no specific mention in a sentence, a singular form may also include a plural form.

[0052] Figure 1a and Figure 1b 1 and 2 are perspective views and cross-sectional views respectively showing a light emitting element according to an embodiment of the present disclosure. Figure 1a and Figure 1b , a rod-type light emitting element LD having a cylindrical shape is shown in FIG. 1 , but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0053] Reference Figure 1a and Figure 1b , the light emitting element LD may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be composed of a stacked body formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 in one direction.

[0054] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. The light emitting element LD may have a first end and a second end with respect to the one direction.

[0055] In an embodiment, one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on a first end of the light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on a second end of the light emitting element LD.

[0056] In the embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. Here, the term "rod-like shape" includes a rod-like shape and a strip-like shape (such as a cylindrical shape and a prism shape) that are longer in the longitudinal direction than in the width direction (i.e., have an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0057] In the embodiment, the light emitting element LD may have a small size corresponding to the nanometer level or the micrometer level (for example, a diameter D and / or a length L corresponding to the nanometer level or the micrometer level). However, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (for example, a display device using a light emitting device using the light emitting element LD as a light source).

[0058] The first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material for forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0059] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0060] If an electric field of a predetermined voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD can emit light by combining electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source of various light emitting devices and a light source of a pixel of a display device.

[0061] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer including any semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material for forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0062] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer circumferential surface of the active layer 12, and may also surround a region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting element LD with respect to the longitudinal direction, for example, the two surfaces (i.e., the top surface and the bottom surface) of the cylinder may be exposed instead of covering them.

[0063] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF may be formed of various well-known insulating materials.

[0064] In an embodiment, the light emitting element LD may further include additional other components in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0065] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0066] Reference Figure 2a and Figure 2b The light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive semiconductor layer 13 .

[0067] Reference Figure 3a and Figure 3b The light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive semiconductor layer 11 .

[0068] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a conductive metal oxide, and for example, Cr, Ti, Al, Au, Ni and their oxides or alloys, ITO, IZO, and ITZO may be used alone or in combination with each other. The electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0069] In an embodiment, the insulating film INF may at least partially surround the outer circumferential surface of the electrode layers 14 and 15, or may not surround the outer circumferential surface. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities (for example, at least one region of each of the electrode layers 14 and 15 may be exposed). However, this is not limited to this, and the insulating film INF may not be provided.

[0070] If the insulating film INF is provided on the surface of the light emitting element LD (for example, provided on the surface of the active layer 12), the active layer 12 can be prevented from being short-circuited with at least one electrode (for example, at least one of the contact electrodes bonded to the opposite ends of the light emitting element LD, etc.). Therefore, the electrical stability of the light emitting element LD can be ensured.

[0071] In addition, the insulating film INF can be formed on the surface of the light emitting element LD, thereby minimizing surface defects of the light emitting element LD and improving the life and efficiency of the light emitting element LD. In addition, the insulating film INF is formed on the surface of the light emitting element LD, thereby preventing an undesirable short circuit between the light emitting elements LD even if a plurality of light emitting elements LD are arranged close to each other.

[0072] In an embodiment, the light emitting element LD may be manufactured by a surface treatment process (e.g., coating). For example, when a plurality of light emitting elements LD are mixed with a fluid solution to be supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed in the solution without being unevenly aggregated in the solution. Here, the emission region is a region where light is emitted by the light emitting element LD. The emission region may be distinguished from a non-emission region where no light is emitted.

[0073] The light-emitting device including the above-mentioned light-emitting element LD can be used in various devices including a display device that requires a light source. For example, a plurality of ultra-small light-emitting elements LD can be arranged in each pixel area of ​​the display panel to form a light-emitting unit for each pixel. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to the display device. For example, the light-emitting element LD can also be used in various devices (such as lighting devices) that require a light source.

[0074] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (particularly, a display panel PNL provided in the display device) is shown as a reference. Figures 1a to 3b The light emitting element LD described above is an example of a device as a light source. According to the embodiment, Figure 4 The structure of the display panel PNL is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit component (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0075] Reference Figure 4, the display panel PNL may include a base layer SUB1 (or substrate) and pixels PXL disposed on the base layer SUB1. In detail, the display panel PNL and the base layer SUB1 may include a display area DA configured to display an image and a non-display area NDA formed in a predetermined area except the display area DA.

[0076] In an embodiment, the display area DA may be disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed along the periphery of the display panel PNL in a manner of surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0077] The base layer SUB1 may form a base of the display panel PNL. For example, the base layer SUB1 may form a base of a lower panel (eg, a lower plate of the display panel PNL).

[0078] In an embodiment, the base layer SUB1 may be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. For example, the base layer SUB1 may be a rigid substrate made of glass or tempered glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer SUB1 may be a transparent substrate, but is not limited thereto. For example, the base layer SUB1 may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0079] One area on the substrate layer SUB1 is defined as a display area DA in which the pixels PXL are disposed, and another area of ​​the substrate layer SUB1 is defined as a non-display area NDA. For example, the substrate layer SUB1 may include a display area DA including a plurality of pixel areas in which the pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits coupled to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0080] The pixel PXL may include at least one light emitting element LD driven by a corresponding scan signal and a corresponding data signal (eg, according to Figures 1a to 3b ). For example, the pixel PXL may include a plurality of rod-type light emitting diodes, each of which has a small size ranging from nanometer to micrometer, which are combined in parallel with each other. The plurality of rod-type light emitting diodes may form the light source of each pixel PXL.

[0081] In addition, the pixel PXL may include a plurality of sub-pixels. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel for emitting red light, the second sub-pixel SPX2 may be a green sub-pixel for emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel for emitting blue light. However, the color, type, and / or number of sub-pixels forming each pixel PXL are not particularly limited. For example, the color of light emitted from each sub-pixel may be changed in various ways. Although in Figure 4 2 shows an embodiment in which the pixels PXL are arranged in a stripe shape in the display area DA, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in various known pixel array forms.

[0082] In an embodiment, the pixel PXL (or each of the sub-pixels) may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure is not particularly limited. For example, the pixel PXL may be formed by a pixel having various known active structures or passive structures of a light-emitting display device.

[0083] Figure 5a to Figure 5c It is shown Figure 4 A circuit diagram of an example of a sub-pixel included in a display device. Figure 5a to Figure 5c Each shows Figure 4 Any one of the first sub-pixel SPX1, the second sub-pixel SPX2 and the third sub-pixel SPX3 shown in FIG. Figure 5a to Figure 5c Different embodiments of sub-pixels SPX that may be provided in an active display device (eg, an active light emitting display device) are shown.

[0084] For example, Figure 5a to Figure 5c The sub-pixel SPX shown in each of the above may be arranged in Figure 4 Any one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 in the light-emitting display panel PNL. The structures of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be substantially the same or similar to each other. Figure 5a to Figure 5c In the present invention, the first sub-pixel SPX1, the second sub-pixel SPX2 and the third sub-pixel SPX3 will be collectively referred to as sub-pixels SPX.

[0085] Reference Figure 5a , the sub-pixel SPX may include a light emitting unit LSU and a pixel circuit PXC configured to drive the light emitting unit LSU.

[0086] In an embodiment, the light emitting unit LSU may include a plurality of light emitting elements LD coupled in parallel to each other between a first power supply VDD and a second power supply VSS. The first power supply VDD and the second power supply VSS may have different potentials. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, at least during the emission period of the sub-pixel SPX, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or more.

[0087] although Figure 5a The light emitting elements LD are shown to be coupled in parallel between the first power supply VDD and the second power supply VSS in the same direction (e.g., in the forward direction), but the present disclosure is not limited thereto. For example, some of the light emitting elements LD may be coupled to each other in the forward direction between the first power supply VDD and the second power supply VSS, and other light emitting elements LD may be coupled to each other in the reverse direction. In an embodiment, at least one sub-pixel SPX may include only a single light emitting element LD.

[0088] In an embodiment, the respective first terminals of the light emitting elements LD may be commonly coupled to the corresponding pixel circuits PXC through the first electrodes and may be commonly coupled to the first power supply VDD through the pixel circuits PXC. The respective second terminals of the light emitting elements LD may be commonly coupled to the second power supply VSS through the second electrodes.

[0089] The light emitting unit LSU may emit light having brightness corresponding to the driving current supplied thereto through the corresponding pixel circuit PXC. Thus, a predetermined image may be displayed on the display area DA.

[0090] The pixel circuit PXC may be coupled to the scan line Si and the data line Dj of the corresponding sub-pixel SPX. For example, if the sub-pixel SPX is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0091] The first transistor (or driving transistor) T1 may be coupled between the first power source VDD and the first electrode of the light emitting unit LSU. The gate electrode of the first transistor T1 is coupled to the first node N1. The first transistor T1 may control a driving current to be supplied to the light emitting unit LSU in response to a voltage of the first node N1.

[0092] The second transistor (or switching transistor) T2 may be coupled between the data line Dj and the first node N1. A gate electrode of the second transistor T2 may be coupled to the scan line Si.

[0093] When a scan signal having a gate-on voltage (e.g., a low voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically couple the first node N1 to the data line Dj. During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal may be transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal may be charged into the storage capacitor Cst.

[0094] A first electrode of the storage capacitor Cst may be coupled to the first power source VDD, and a second electrode of the storage capacitor Cst may be coupled to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period, and maintain the charged voltage until a data signal of a subsequent frame is supplied.

[0095] although Figure 5a It is shown that all transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0096] For example, Figure 5b As shown in FIG. 1 , both the first transistor T1 and the second transistor T2 can be formed by N-type transistors. Except that the connection positions of some circuit elements have changed according to the change of the type of transistor, Figure 5b The construction and operation of the sub-pixel SPX shown in FIG. Figure 5a The construction and operation of the sub-pixel SPX are substantially the same. Therefore, Figure 5b Detailed description of the sub-pixel SPX.

[0097] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a well-known pixel circuit, which may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a well-known pixel circuit. Figure 5c The embodiment shown in FIG. 1 is constructed in the same manner.

[0098] Reference Figure 5c, the pixel circuit PXC can be coupled not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the sub-pixel SPX arranged on the i-th row of the display area DA can also be coupled to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be coupled not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC can also be coupled to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0099] The first transistor T1 is coupled between the first power source VDD and the first electrode of the light emitting unit LSU. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current to be supplied to the light emitting unit LSU in response to a voltage of the first node N1.

[0100] The second transistor T2 may be coupled between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the second transistor T2 may be turned on to electrically couple the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj may be transmitted to the first transistor T1.

[0101] The third transistor T3 may be coupled between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be coupled to the corresponding scan line Si. When a scan signal of a gate-on voltage is supplied from the scan line Si, the third transistor T3 may be turned on to connect the first transistor T1 in the form of a diode.

[0102] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to a previous scan line (e.g., the i-1th scan line Si-1). When a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be the minimum voltage of the data signal or less.

[0103] The fifth transistor T5 may be coupled between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be coupled to the corresponding emission control line (e.g., the i-th emission control line Ei). The fifth transistor T5 may be turned off when an emission control signal having a gate cut-off voltage (e.g., a high voltage) is supplied to the emission control line Ei, and may be turned on in other cases.

[0104] The sixth transistor T6 may be coupled between the first transistor T1 and the first electrode (e.g., the second node N2) of the light emitting unit LSU. The gate electrode of the sixth transistor T6 may be coupled to the corresponding emission control line (e.g., the i-th emission control line Ei). The sixth transistor T6 may be turned off when an emission control signal of a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.

[0105] The seventh transistor T7 may be connected between the first electrode of the light emitting unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 may be coupled to any one of the scan lines of the subsequent stage (for example, coupled to the i+1th scan line Si+1). When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light emitting unit LSU.

[0106] The storage capacitor Cst may be coupled between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0107] although Figure 5c It is shown that the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC are formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor. In this case, the voltage level of the control signal (e.g., the scan signal and / or the data signal) used to control at least one of the first transistor T1 to the seventh transistor T7 may be changed.

[0108] In addition, the structure of the sub-pixel SPX that can be applied to the present disclosure is not limited to Figure 5a to Figure 5cIn the embodiment shown in FIG. 1 , the sub-pixel SPX may have various well-known structures. For example, the pixel circuit PXC included in the sub-pixel SPX may be formed by a well-known pixel circuit, which may have various structures and / or be operated by various driving schemes. In an embodiment of the present disclosure, the sub-pixel SPX may be constructed in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode and the second electrode of the light-emitting unit LSU may be directly coupled to the scan line Si, the data line Dj, the power line, and / or the control line.

[0109] Figure 6 It is shown Figure 4 A plan view of an example of a pixel included in a display device. Figure 6 The structure of the pixel PXL is shown focusing on the display element layer in which the light emitting element LD of the pixel PXL is provided.

[0110] Reference Figures 4 to 6 The pixel PXL is formed in a pixel area PXA defined on the base layer SUB1. The pixel area PXA may include sub-pixel areas SPA corresponding to a plurality of sub-pixels SPX constituting the pixel PXL.

[0111] For example, the pixel area PXA may include a first sub-pixel area SPA1 in which a first sub-pixel SPX1 is formed, a second sub-pixel area SPA2 in which a second sub-pixel SPX2 is formed, and a third sub-pixel area SPA3 in which a third sub-pixel SPX3 is formed. Each of the first sub-pixel area SPA1, the second sub-pixel area SPA2, and the third sub-pixel area SPA3 may include at least one pair of first and second electrodes ELT1 and ELT2 and an emission area EMA in which at least one light emitting element LD coupled between the first and second electrodes ELT1 and ELT2 is disposed. In an embodiment, each emission area EMA may be defined by a dam BNK surrounding the emission area EMA.

[0112] In an embodiment, the first subpixel SPX1 may include a first electrode ELT1 and a second electrode ELT2 disposed at positions spaced apart from each other in a first subpixel region SPA1 corresponding to the first subpixel SPX1, and at least one first light emitting element LD1 coupled between the first electrode ELT1 and the second electrode ELT2. For example, the first subpixel SPX1 may include a plurality of first light emitting elements LD1 coupled in parallel to each other between the first electrode ELT1 and the second electrode ELT2.

[0113] In an embodiment, the second subpixel SPX2 may include a first electrode ELT1 and a second electrode ELT2 disposed at positions spaced apart from each other in a second subpixel region SPA2 corresponding to the second subpixel SPX2, and at least one second light emitting element LD2 coupled between the first electrode ELT1 and the second electrode ELT2. For example, the second subpixel SPX2 may include a plurality of second light emitting elements LD2 coupled in parallel to each other between the first electrode ELT1 and the second electrode ELT2.

[0114] In an embodiment, the third subpixel SPX3 may include a first electrode ELT1 and a second electrode ELT2 disposed at positions spaced apart from each other in a third subpixel region SPA3 corresponding to the third subpixel SPX3, and at least one third light emitting element LD3 coupled between the first electrode ELT1 and the second electrode ELT2. For example, the third subpixel SPX3 may include a plurality of third light emitting elements LD3 coupled in parallel to each other between the first electrode ELT1 and the second electrode ELT2.

[0115] In an embodiment, the structures of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be substantially the same or similar to each other. For convenience, hereinafter, any one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 will be collectively referred to as a sub-pixel SPX, wherein the region in which the sub-pixel SPX is formed will be collectively referred to as a sub-pixel region SPA, at least one first light-emitting element LD1, the second light-emitting element LD2, or the third light-emitting element LD3 disposed in the sub-pixel region SPA will be collectively referred to as a light-emitting element LD, and the structure of the sub-pixel SPX will be described in detail.

[0116] In an embodiment, the subpixel SPX may include at least one pair of first electrodes ELT1 and second electrodes ELT2 arranged at positions spaced apart from each other in the subpixel area SPA, a first embankment pattern PW1 and a first contact electrode CNE1 overlapping a region of the first electrode ELT1, a second embankment pattern PW2 and a second contact electrode CNE2 overlapping a region of the second electrode ELT2, and at least one light emitting element LD (for example, a plurality of light emitting elements coupled in parallel to each other) coupled between the first electrode ELT1 and the second electrode ELT2.

[0117] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other in each sub-pixel area SPA, so that at least portions of the first electrode ELT1 and the second electrode ELT2 face each other. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed in parallel with each other at positions spaced apart from each other by a predetermined distance relative to the first direction DR1 in the emission area EMA, and each electrode may extend in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto. For example, the shapes and / or mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0118] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single layer or a multi-layer structure. For example, the first electrode ELT1 may have a multi-layer structure including a first reflective electrode REF1 and a first conductive cover layer CPL1. The second electrode ELT2 may have a multi-layer structure including a second reflective electrode REF2 and a second conductive cover layer CPL2.

[0119] In addition, each of the first reflective electrode REF1 and the second reflective electrode REF2 may have a single-layer or multi-layer structure. For example, each first reflective electrode REF1 may include at least one reflective conductive layer, and optionally further include at least one transparent conductive layer disposed above and / or below the reflective conductive layer. Similarly, each second reflective electrode REF2 may include at least one reflective conductive layer, and optionally further include at least one transparent conductive layer disposed above and / or below the reflective conductive layer.

[0120] In an embodiment, the first electrode ELT1 may be coupled to the first connection electrode CNL1. For example, the first electrode ELT1 may be integrally coupled to the first connection electrode CNL1. For example, the first electrode ELT1 may be formed by at least one branch bifurcated from the first connection electrode CNL1. In the case where the first electrode ELT1 and the first connection electrode CNL1 are integrally formed with each other, the first connection electrode CNL1 may be considered as a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first electrode ELT1 and the first connection electrode CNL1 may be formed separately and electrically coupled to each other through at least one contact hole, a through hole, etc., not shown.

[0121] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions in the sub-pixel area SPA. For example, when the first connection electrode CNL1 extends in the first direction DR1, the first electrode ELT1 may extend in the second direction DR2 crossing the first direction DR1.

[0122] In an embodiment, the first connection electrode CNL1 may have a single-layer or multi-layer structure. For example, the first connection electrode CNL1 may include a 1_1 connection electrode CNL1_1 integrally combined with the first reflective electrode REF1 and a 1_2 connection electrode CNL1_2 integrally combined with the first conductive cover layer CPL1. In an embodiment, the first connection electrode CNL1 may have the same cross-sectional structure (or stacking structure) as that of the first electrode ELT1, but the present disclosure is not limited thereto.

[0123] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be coupled to the pixel circuit PXC of each sub-pixel SPX through the first contact hole CH1 , for example, Figure 5a to Figure 5c . In an embodiment, the first contact hole CH1 may be disposed outside the emission area EMA of each sub-pixel SPX. For example, the first contact hole CH1 may be disposed around the corresponding emission area EMA so that the first contact hole CH1 overlaps the embankment BNK. In this case, the first contact hole CH1 is covered by the embankment BNK, so that the pattern can be prevented from being reflected in the emission area EMA. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one first contact hole CH1 may be disposed in the emission area EMA.

[0124] In an embodiment, the pixel circuit PXC may be disposed under the light emitting element LD disposed in the corresponding sub-pixel area SPA. For example, each pixel circuit PXC may be formed in a pixel circuit layer (or a pixel element layer including circuit elements such as transistors) under the light emitting element LD and coupled to the first electrode ELT1 through the first contact hole CH1.

[0125] In an embodiment, the second electrode ELT2 may be coupled to the second connection electrode CNL2. For example, the second electrode ELT2 may be integrally coupled to the second connection electrode CNL2. For example, the second electrode ELT2 may be formed by at least one branch bifurcated from the second connection electrode CNL2. In the case where the second electrode ELT2 and the second connection electrode CNL2 are integrally formed with each other, the second connection electrode CNL2 may be considered as a region of the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the second electrode ELT2 and the second connection electrode CNL2 may be formed separately and electrically coupled to each other through at least one contact hole, a through hole, etc., not shown.

[0126] In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions in the sub-pixel area SPA. For example, when the second connection electrode CNL2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 crossing the first direction DR1.

[0127] In an embodiment, the second connection electrode CNL2 may have a single-layer or multi-layer structure. For example, the second connection electrode CNL2 may include a 2_1st connection electrode CNL2_1 integrally combined with the second reflective electrode REF2 and a 2_2nd connection electrode CNL2_2 integrally combined with the second conductive cover layer CPL2. In an embodiment, the second connection electrode CNL2 may have a cross-sectional structure (stacked structure) the same as that of the second electrode ELT2, but the present disclosure is not limited thereto.

[0128] In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be coupled to a second power supply VSS. For example, the second electrode ELT2 and the second connection electrode CNL2 may be coupled to the second power supply VSS through a second contact hole CH2 and a power line (not shown) coupled thereto. In an embodiment, the second contact hole CH2 may be disposed outside the emission area EMA of each sub-pixel SPX. For example, the second contact hole CH2 may be disposed around the corresponding emission area EMA so that the second contact hole CH2 overlaps the embankment BNK. In this case, the second contact hole CH2 may be covered by the embankment BNK so that the pattern may be prevented from being reflected in the emission area EMA. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one second contact hole CH2 may be disposed in the emission area EMA.

[0129] In an embodiment, a region of a power line for supplying a second power source VSS may be provided in a pixel circuit layer below the light emitting element LD. For example, the power line is provided in a pixel circuit layer below the light emitting element LD and is coupled to the second electrode ELT2 through a second contact hole CH2. However, the present disclosure is not limited to the aforementioned structure, and the position of the power line may be changed in various ways.

[0130] In an embodiment, the first embankment pattern PW1 may be disposed under the first electrode ELT1 and overlap with a region of the first electrode ELT1. The second embankment pattern PW2 may be disposed under the second electrode ELT2 and overlap with a region of the second electrode ELT2. The first embankment pattern PW1 and the second embankment pattern PW2 may be disposed at positions spaced apart from each other in the emission area EMA, and the regions of the first electrode ELT1 and the second electrode ELT2 may protrude upward. For example, the first electrode ELT1 may be disposed on the first embankment pattern PW1 and protrude the first embankment pattern PW1 in the height direction (or thickness direction) of the base layer SUB1. The second electrode ELT2 may be disposed on the second embankment pattern PW2 and protrude the second embankment pattern PW2 in the height direction of the base layer SUB1.

[0131] In an embodiment, at least one light emitting element LD (for example, a plurality of light emitting elements LD) may be arranged between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX. For example, at least one first light emitting element LD1 may be disposed between the first electrode ELT1 and the second electrode ELT2 of the first sub-pixel SPX1. At least one second light emitting element LD2 may be disposed between the first electrode ELT1 and the second electrode ELT2 of the second sub-pixel SPX2. At least one third light emitting element LD3 may be disposed between the first electrode ELT1 and the second electrode ELT2 of the third sub-pixel SPX3. For example, in each sub-pixel area SPA, a plurality of light emitting elements LD may be combined in parallel with each other in an area where the first electrode ELT1 and the second electrode ELT2 are disposed to face each other.

[0132] although Figure 6 The light emitting elements LD are shown to be arranged between the first electrode ELT1 and the second electrode ELT2 in the first direction DR1 (eg, in the horizontal direction), but the arrangement direction of the light emitting elements LD is not limited thereto. For example, at least one of the light emitting elements LD may be positioned in a diagonal direction.

[0133] In an embodiment, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may emit light having the same color or different colors. For example, each first light emitting element LD1 may be a red light emitting diode configured to emit red light. Each second light emitting element LD2 may be a green light emitting diode configured to emit green light. Each third light emitting element LD3 may be a blue light emitting diode configured to emit blue light.

[0134] For example, all of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be formed of a blue light emitting diode configured to emit blue light. In this case, in order to form a full-color pixel PXL, a light conversion layer and / or a color filter for converting the color of light emitted from the corresponding sub-pixel SPX may be provided on at least some of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0135] Each of the light emitting elements LD is electrically coupled between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX. For example, the first end EP1 of each of the light emitting elements LD may be electrically coupled to the first electrode ELT1 of the sub-pixel SPX, and the second end EP2 of each of the light emitting elements LD may be electrically coupled to the second electrode ELT2 of the corresponding sub-pixel SPX.

[0136] In an embodiment, the first end of each of the light emitting elements LD may be electrically coupled to the corresponding first electrode ELT1 through at least one contact electrode (e.g., the first contact electrode CNE1) rather than being directly disposed on the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first end EP1 of the light emitting element LD may be in direct contact with the corresponding first electrode ELT1 and electrically coupled to the first electrode ELT1.

[0137] Similarly, the second end EP2 of each of the light emitting elements LD can be electrically coupled to the corresponding second electrode ELT2 through at least one contact electrode (e.g., the second contact electrode CNE2), rather than being directly disposed on the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the second end EP2 of each of the light emitting elements LD can be in direct contact with the second electrode ELT2 and electrically coupled to the second electrode ELT2.

[0138] In an embodiment, each of the light emitting elements LD may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size corresponding to, for example, a nanometer level or a micrometer level. For example, each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be formed of an ultra-small rod-type light emitting diode having a size corresponding to a nanometer level or a micrometer level, such as Figures 1a to 3b However, the type of light emitting element LD that can be applied to the present disclosure is not limited thereto. For example, the light emitting element LD can be formed by a growth scheme and can be a light emitting diode having a core-shell structure having a size corresponding to, for example, nanometer to micrometer scale.

[0139] In an embodiment, the light emitting element LD may be prepared in a dispersed form in a predetermined solution and then supplied to the emission area EMA of each sub-pixel SPX by an inkjet printing scheme or a slit coating scheme. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to the emission area EMA. Here, if a predetermined voltage is supplied to the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD is self-aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD has been aligned, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting element LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, since the first contact electrode CNE1 and the second contact electrode CNE2 are formed on the first end EP1 and the second end EP2 of the light emitting element LD, the light emitting element LD may be reliably bonded between the first electrode ELT1 and the second electrode ELT2.

[0140] In an embodiment, the first contact electrode CNE1 may be formed on the first end EP1 of the light emitting element LD and at least one region of the first electrode ELT1 corresponding to the first end EP1, whereby the first end EP1 of the light emitting element LD may be physically and / or electrically coupled to the first electrode ELT1. Similarly, the second contact electrode CNE2 may be formed on the second end EP2 of the light emitting element LD and at least one region of the second electrode ELT2 corresponding to the second end EP2, whereby the second end EP2 of the light emitting element LD may be physically and / or electrically coupled to the second electrode ELT2.

[0141] The light emitting elements LD disposed in the sub-pixel area SPA may be aggregated, thereby forming a light source of the corresponding sub-pixel SPX. For example, if a driving current flows through at least one sub-pixel SPX during each frame period, the light emitting element LD coupled in the forward direction between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX may emit light having a brightness corresponding to the driving current.

[0142] In an embodiment, the emission area EMA may be surrounded by a bank BNK. For example, the display device may include a bank BNK disposed between the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 to surround the emission area EMA of each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3.

[0143] In an embodiment, the bank BNK may be disposed or formed on a conductive layer or a conductive pattern. The conductive pattern may prevent a residue of the bank BNK from remaining in the emission area EMA or the like.

[0144] Figure 7 It is shown along Figure 6 A cross-sectional view of an example of a sub-pixel taken along line II'. Figure 8a and Figure 8b It is shown Figure 7 FIG. 1 is an enlarged cross-sectional view of an example of a first area A1 .

[0145] In an embodiment, Figure 7 1 and 2 show any sub-pixel region SPA formed in the display panel PNL. In an embodiment, the cross-sectional structures of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be substantially the same or similar to each other. Figure 7 The first sub-pixel region SPA1 is shown Figure 6 The structure of each sub-pixel SPX will be fully described with reference to the cross section corresponding to the line II'.

[0146] Reference Figure 1a , Figure 1b , Figure 6 and Figure 7 , the pixel circuit layer PCL and the display element layer LDL may be sequentially disposed on the base layer SUB1 in each sub-pixel area SPA. In an embodiment, the pixel circuit layer PCL and the display element layer LDL may be formed in the entire display area DA of the display panel PNL.

[0147] In an embodiment, the pixel circuit layer PCL may include circuit elements constituting the pixel circuit PXC of the sub-pixel SPX. The display element layer LDL may include the light emitting element LD of the sub-pixel SPX.

[0148] For example, in the first sub-pixel region SPA1 on the substrate layer SUB1, a pixel circuit layer PCL including circuit elements constituting a pixel circuit PXC of a corresponding first sub-pixel SPX1 and a display element layer LDL including at least one light emitting element LD (for example, a plurality of first light emitting elements LD1) disposed in the first sub-pixel SPX1 may be disposed sequentially on one surface of the substrate layer SUB1. Similarly, in the second sub-pixel region SPA2 on the substrate layer SUB1, a pixel circuit layer PCL including circuit elements constituting a pixel circuit PXC of a corresponding second sub-pixel SPX2 and a display element layer LDL including a plurality of second light emitting elements LD2 disposed in the second sub-pixel SPX2 may be disposed sequentially on one surface of the substrate layer SUB1. Similarly, in the third sub-pixel region SPA3 on the substrate layer SUB1, a pixel circuit layer PCL including circuit elements constituting a pixel circuit PXC of a corresponding third sub-pixel SPX3 and a display element layer LDL including a plurality of third light emitting elements LD3 disposed in the third sub-pixel SPX3 may be disposed sequentially on one surface of the substrate layer SUB1.

[0149] In this way, the pixel circuit layer PCL and the display element layer LDL may be sequentially disposed in the display area DA on the base layer SUB 1. For example, the pixel circuit layer PCL may be formed on the surface of the base layer SUB 1, and the display element layer LDL may be formed on the surface of the base layer SUB 1 on which the pixel circuit layer PCL is formed.

[0150] In an embodiment, the pixel circuit layer PCL may include a plurality of circuit elements disposed in the display area DA. For example, the pixel circuit layer PCL may include a plurality of circuit elements formed in the sub-pixel area SPA to form a pixel circuit PXC of a corresponding sub-pixel SPX. For example, the pixel circuit layer PCL may include a plurality of transistors disposed in the sub-pixel area SPA, for example, Figure 5a and Figure 5b The first transistor T1 and the second transistor T2. Figure 7, but the pixel circuit layer PCL may include a storage capacitor Cst disposed in the sub-pixel area SPA, various signal lines (eg, Figure 5a and Figure 5b ) and various power lines coupled to the pixel circuit PXC and / or the light emitting element LD (e.g., a first power line PL1 configured to transmit a voltage of a first power source VDD and a voltage of a second power source VSS, respectively (see Figure 5a to Figure 5c ) and a second power line PL2).

[0151] In an embodiment, a plurality of transistors (e.g., a first transistor T1 and a second transistor T2) provided in the pixel circuit PXC may have substantially the same or similar cross-sectional structures. However, the present disclosure is not limited thereto. In an embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0152] In addition, the pixel circuit layer PCL may include a plurality of insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the base layer SUB1.

[0153] In an embodiment, the buffer layer BFL may prevent impurities from diffusing into the circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two or more layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0154] In an embodiment, each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Figure 7 It is shown that each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor provided in each sub-pixel area SPA may be formed integrally with the corresponding semiconductor layer SCL.

[0155] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer SUB1 on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0156] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0157] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0158] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode ET1 and the second transistor electrode ET2 and the semiconductor layer SCL and the gate electrode GE. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically coupled to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be coupled to the first region and the second region of the semiconductor layer SCL, respectively, through contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0159] In an embodiment, at least one transistor (eg, Figure 5a and Figure 5b Any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 shown in FIG. 4 may be electrically coupled to the first electrode ELT1 of the light emitting unit LSU disposed on the passivation layer PSV through the first contact hole CH1 passing through the passivation layer PSV.

[0160] In an embodiment, at least one signal line and / or power line coupled to the subpixel SPX may be disposed on the same layer as the layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, the second power line PL2 for supplying the voltage of the second power source VSS may be disposed on the same layer as the layer of the gate electrode GE of each of the first transistor T1 and the second transistor T2, and electrically coupled to the second electrode ELT2 disposed on the passivation layer PSV of the light emitting unit LSU through both the bridge pattern BRP disposed on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and through at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2, etc., etc. may be changed in various ways.

[0161] In an embodiment, the display element layer LDL may include a first embankment pattern PW1 and a second embankment pattern PW2, a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1 and a second contact electrode CNE2, and a third insulating layer INS3, which are sequentially arranged and / or formed on the pixel circuit layer PCL.

[0162] The first embankment pattern PW1 and the second embankment pattern PW2 may be disposed on the pixel circuit layer PCL. The first embankment pattern PW1 and the second embankment pattern PW2 may be disposed at positions spaced apart from each other in the emission area EMA. The first embankment pattern PW1 and the second embankment pattern PW2 may protrude in a height direction on the pixel circuit layer PCL. In an embodiment, the first embankment pattern PW1 and the second embankment pattern PW2 may have substantially the same height, but the present disclosure is not limited thereto.

[0163] In an embodiment, the first bank pattern PW1 may be disposed between the pixel circuit layer PCL and the first electrode ELT1. The first bank pattern PW1 may be disposed adjacent to the first end EP1 of the light emitting element LD. For example, one sidewall of the first bank pattern PW1 may be positioned adjacent to the first end EP1 of the light emitting element LD and disposed facing the first end EP1.

[0164] In an embodiment, the second bank pattern PW2 may be disposed between the pixel circuit layer PCL and the second electrode ELT2. The second bank pattern PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, one sidewall of the second bank pattern PW2 may be positioned adjacent to the second end EP2 of the light emitting element LD and disposed facing the second end EP2.

[0165] In an embodiment, each of the first bank pattern PW1 and the second bank pattern PW2 may have various shapes. Figure 7As shown in , each of the first embankment pattern PW1 and the second embankment pattern PW2 may have a cross-sectional shape of a trapezoid that decreases in width from its bottom to its top. In this case, each of the first embankment pattern PW1 and the second embankment pattern PW2 may have an inclined surface on at least one side. However, the shape of each of the first embankment pattern PW1 and the second embankment pattern PW2 is not limited thereto.

[0166] Each of the first bank pattern PW1 and the second bank pattern PW2 may include an insulating material including an inorganic material and / or an organic material. For example, the first bank pattern PW1 and the second bank pattern PW2 may include various inorganic insulating materials known to those skilled in the art (such as SiN x or SiO x ). Alternatively, the first bank pattern PW1 and the second bank pattern PW2 may include at least one organic layer and / or a photoresist layer including various known organic insulating materials, or may form a single-layer insulator or a multi-layer insulator including an organic / inorganic material combination. In other words, the materials of the first bank pattern PW1 and the second bank pattern PW2 may be changed variously.

[0167] In an embodiment, each of the first embankment pattern PW1 and the second embankment pattern PW2 may be used as a reflective member. For example, the first embankment pattern PW1 and the second embankment pattern PW2 together with the first electrode ELT1 and the second electrode ELT2 disposed on the first embankment pattern PW1 and the second embankment pattern PW2 may be used as a reflector to guide light emitted from each light emitting element LD in a desired direction, thereby enhancing the light efficiency of the pixel PXL.

[0168] The first electrode ELT1 and the second electrode ELT2 may be disposed on the first bank pattern PW1 and the second bank pattern PW2, respectively. The first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other in the emission area EMA.

[0169] In an embodiment, the first electrode ELT1 and the second electrode ELT2 respectively disposed on the first embankment pattern PW1 and the second embankment pattern PW2 may have shapes corresponding to the respective shapes of the first embankment pattern PW1 and the second embankment pattern PW2. For example, the first electrode ELT1 and the second electrode ELT2 may have inclined surfaces or curved surfaces corresponding to the first embankment pattern PW1 and the second embankment pattern PW2, respectively, and protrude in the height direction (or thickness direction) of the display element layer LDL.

[0170] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof), a conductive oxide (such as ITO, IZO, ZnO, or ITZO), and a conductive polymer (such as PEDOT); however, it is not limited thereto.

[0171] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer or multi-layer structure. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. Each of the first electrode ELT1 and the second electrode ELT2 may also selectively include at least one of at least one transparent electrode layer disposed on the upper and / or lower portion of the reflective electrode layer and at least one conductive cover layer covering the upper portion of the reflective electrode layer and / or the upper portion of the transparent electrode layer.

[0172] In an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof. However, the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ELT1 and the second electrode ELT2 including the reflective electrode layer may enable light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting elements LD to travel in the direction of displaying an image (e.g., in the forward direction). In particular, if the first electrode ELT1 and the second electrode ELT2 respectively have inclined surfaces or curved surfaces corresponding to the shapes of the first and second embankment patterns PW1 and PW2, and are respectively disposed to face the first and second ends EP1 and EP2 of the light emitting element LD, light emitted from the first and second ends EP1 and EP2 of each light emitting element LD can be reflected by the first and second electrodes ELT1 and ELT2, and thus more reliably travel in the forward direction of the display panel PNL (e.g., in the forward direction of the base layer SUB1). Therefore, the efficiency of light emitted from the light emitting element LD can be enhanced.

[0173] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ELT1 and the second electrode ELT2 are each formed of a multilayer structure of at least two or more layers, the voltage drop caused by the signal delay (RC delay) may be minimized. Therefore, the desired voltage may be effectively transmitted to the light emitting element LD.

[0174] In addition, if each of the first electrode ELT1 and the second electrode ELT2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, it is possible to prevent the reflective electrode layer of the first electrode ELT1 and the second electrode ELT2 from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive cover layer may be selectively included in the first electrode ELT1 and the second electrode ELT2, and the conductive cover layer may be omitted according to the embodiment. In addition, the conductive cover layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component provided on the first electrode ELT1 and the second electrode ELT2.

[0175] The first insulating layer INS1 may be disposed on one region of each of the first and second electrodes ELT1 and ELT2. For example, the first insulating layer INS1 may be formed to cover predetermined regions of the first and second electrodes ELT1 and ELT2, and may include openings to expose other predetermined regions of the first and second electrodes ELT1 and ELT2.

[0176] In an embodiment, the first insulating layer INS1 may be mainly formed to cover the entire surface of the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD is supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ELT1 and the second electrode ELT2 in the first contactor and the second contactor, as shown in FIG. Figure 7 Alternatively, the first insulating layer INS1 may be patterned in the form of a separate pattern partially disposed under the light emitting element LD after the supply and alignment of the light emitting element LD have been completed.

[0177] In other words, the first insulating layer INS1 may be disposed between the first electrode ELT1 and the light emitting element LD and between the second electrode ELT2 and the light emitting element LD, and may expose at least one region of each of the first electrode ELT1 and the second electrode ELT2. After forming the first electrode ELT1 and the second electrode ELT2, the first insulating layer INS1 may be formed to cover the first electrode ELT1 and the second electrode ELT2, so that the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged or metal precipitation can be prevented in subsequent processes. In addition, the first insulating layer INS1 may stably support each light emitting element LD.

[0178] The light emitting element LD may be supplied to the emission area EMA in which the first insulating layer INS1 is formed and aligned in the emission area EMA. For example, a plurality of light emitting elements LD may be supplied to the emission area EMA by an inkjet method or the like, and the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ELT1 and the second electrode ELT2.

[0179] The conductive pattern CDP may be disposed on the first insulating layer INS1. For example, the conductive pattern CDP may be formed between the sub-pixels SPX to surround the emission area EMA of each of the sub-pixels SPX. Therefore, the conductive pattern CDP may not overlap the first and second embankment patterns PW1 and PW2 disposed in the emission area EMA. The present disclosure is not limited thereto.

[0180] The conductive pattern CDP can prevent the lower structure (for example, the first insulating layer INS1, the first electrode ELT1, the second electrode ELT2, etc.) from being damaged when the embankment BNK is formed, and can be used to remove residues that may remain in the emission area EMA when the embankment BNK is formed. The conductive pattern CDP can allow the light emitting element LD to be properly aligned in the emission area EMA. For example, the conductive pattern CDP can offset the electric field formed between adjacent sub-pixels SPX, thereby preventing the light emitting element LD from being aligned near the outside of the sub-pixel SPX. Therefore, the light emitting element LD can be properly aligned in the emission area EMA of the sub-pixel SPX. The following will refer to Figures 11a to 11e Describe the function of the conductive pattern CDP.

[0181] The conductive pattern CDP may be electrically insulated from the first electrode ELT1 and the second electrode ELT2 by the first insulating layer INS1. The conductive pattern CDP may be disposed on the same layer as the first contact electrode CNE1 and the second contact electrode CNE2, and may be spaced apart from the first contact electrode CNE1 and the second contact electrode CNE2, and electrically insulated from the first contact electrode CNE1 and the second contact electrode CNE2 by the third insulating layer INS3. The conductive pattern CDP may be in an electrically insulated floating state. However, the present disclosure is not limited thereto. For example, the conductive pattern CDP may be coupled to a predetermined reference voltage source.

[0182] Although reference will be Figures 11a to 11e Description is made, but the conductive pattern CDP may be formed by a process different from that of the first contact electrode CNE1 and the second contact electrode CNE2. The conductive pattern CDP may have a material different from that of the first contact electrode CNE1 and the second contact electrode CNE2 and / or a cross-sectional structure (e.g., a stacked structure) different from that of the first contact electrode CNE1 and the second contact electrode CNE2. For example, the conductive pattern CDP may have a thickness different from that of the first contact electrode CNE1 and the second contact electrode CNE2 (e.g., smaller than that of the first contact electrode CNE1 and the second contact electrode CNE2). The thickness of the conductive pattern CDP may be or smaller, or The present disclosure is not limited thereto.

[0183] In an embodiment, the conductive pattern CDP may include at least one conductive material. The conductive pattern CDP may include a transparent conductive material. For example, the conductive pattern CDP may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), gallium indium zinc oxide (GIZO), zinc oxide (ZnO), or a mixture thereof. However, the conductive pattern CDP is not limited thereto. The conductive pattern CDP may be formed of various conductive materials that can be removed by wet etching, and its constituent materials are not particularly limited.

[0184] The bank BNK may be disposed on the conductive pattern CDP. For example, the bank BNK may be formed between the sub-pixels SPX to surround the corresponding emission areas EMA of the sub-pixels SPX, so that a pixel defining layer for defining the emission areas EMA of the sub-pixels SPX may be formed. The bank BNK may overlap the conductive pattern CDP. For example, in a plan view, the bank BNK may substantially completely overlap the conductive pattern CDP.

[0185] In an embodiment, the bank BNK may be formed to have a second height H2 greater than the first height H1 of the first bank pattern PW1 and the second bank pattern PW2. For example, the first height H1 of the first bank pattern PW1 and the second bank pattern PW2 may be approximately 2 μm, and the second height H2 of the bank BNK may be approximately 2.5 μm or greater, or 2.7 μm or greater. In other words, the second height H2 of the bank BNK may be equal to or greater than 1.2 times the first height H1 of the first bank pattern PW1 and the second bank pattern PW2, or greater than the first height H1 by 0.5 μm or more. The second height H2 of the bank BNK is not limited thereto.

[0186] In the step of supplying the light-emitting element LD to each emission area EMA, the bank BNK can be used as a dam structure, which is configured to prevent the solution mixed with the light-emitting element LD from being introduced into the emission area EMA of the adjacent sub-pixel SPX, or to control the amount of the solution so that a constant amount of solution is supplied to each emission area EMA.

[0187] The bank BNK may be formed to prevent light emitted from each emission area EMA from entering the adjacent emission area EMA and optically interfering. To this end, the bank BNK may be formed to prevent light emitted from the light emitting element LD of each sub-pixel SPX from passing through the bank BNK.

[0188] For example, the bank BNK may block or absorb light having a predetermined color and / or wavelength and emitted from the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3. In an embodiment, the bank BNK may include a color pigment (or color dye) having a color different from the color of the light emitted from the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3. The bank BNK may include a black dye.

[0189] For example, the bank BNK may be formed of at least one color bank layer including a light shielding material or a color filter material for blocking transmission of light having a predetermined color and / or wavelength and emitted from the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3. Thus, the bank BNK may serve as a light shielding layer configured to prevent light emitted from the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 from leaking into the adjacent emission area EMA.

[0190] In an embodiment of the present disclosure, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may emit light of different colors. For example, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may emit red light, green light, and blue light, respectively. In this case, the bank BNK may include a color filter material for blocking light having a red wavelength band, a green wavelength band, and a blue wavelength band.

[0191] Here, the bank BNK is not limited thereto. For example, in the case where all of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 emit blue light, the bank BNK may include a color filter material that blocks light having a blue wavelength band and allows light having other wavelength bands (e.g., light having a predetermined color different from blue and a wavelength band other than the blue wavelength band) to pass therethrough.

[0192] For example, the bank BNK may include a red-based color filter material for allowing light (e.g., red light) having a wavelength band relatively far from the blue wavelength band in the visible light region to selectively pass therethrough. However, the material of the bank BNK is not limited to the aforementioned materials. For example, the bank BNK may include a yellow-based color filter material. Alternatively, the bank BNK may include color filter materials of at least two colors. For example, the bank BNK may be formed of an orange bank including a combination of a red pigment and a yellow pigment.

[0193] In this way, if the bank BNK is formed to include a color filter material for blocking light having a predetermined color and emitted from the light emitting element LD of each sub-pixel SPX, the bank BNK can effectively prevent light from leaking between adjacent sub-pixels SPX. In addition, in the case where the bank BNK includes a color filter material, compared with the case of using a black matrix material such as carbon black, the residue of the bank BNK can be prevented from occurring.

[0194] In the embodiment, the bank BNK may have various cross-sectional shapes. Figure 8a and Figure 8b The cross-sectional shape of the bank BNK will be described.

[0195] Reference Figure 8a , the bank BNK may have a rectangular cross-sectional shape. In other words, the sidewall of the bank BNK may be substantially perpendicular to the upper surface of the first insulating layer INS1 (or the base layer SUB1). The angle ANG1 between the sidewall of the bank BNK and the upper surface of the first insulating layer INS1 may be substantially a right angle. Here, the substantially right angle may be an angle in the range of 80° to 90°. Although reference will be made to Figures 11a to 11eDescription is made, but the bank BNK can be formed by a dry etching operation instead of using an optical process (or a photolithography process). Therefore, the sidewall of the bank BNK can be substantially perpendicular to the upper surface of the first insulating layer INS1. In addition, by the dry etching operation, a bank BNK having a desired thickness can be easily formed without being limited by the optical process (the thicker the bank BNK, the more difficult it is to perform the exposure process and the development process).

[0196] The shape of the bank BNK is not limited thereto. Figure 8b , the bank BNK may have a trapezoidal cross-section that decreases in width upward. For example, the bank BNK may have an inclined surface that decreases in width upward in a region bordering the emission area EMA of each sub-pixel SPX. In this case, an angle ANG1 between a sidewall of the bank BNK and an upper surface of the first insulating layer INS1 may be 45° or more, for example, in the range of 70° to 90°.

[0197] For example, the bank BNK may have a curved surface decreasing in width upward in a region bordering the emission area EMA of the sub-pixel SPX. In other words, in embodiments, the bank BNK may have a shape decreasing in width upward, and its shape may be changed in various ways.

[0198] Since the bank BNK has a substantially rectangular cross-sectional shape or the sidewall of the bank BNK is substantially perpendicular to the upper surface of the first insulating layer INS1, it is possible to more effectively prevent light emitted from each emission area EMA from entering the adjacent emission area EMA and causing optical interference. In addition, a bank BNK having a desired shape and / or height (e.g., a height of 2.5 μm or more) can be more easily formed by a dry etching operation.

[0199] In an embodiment, the sidewall of the bank BNK may be disposed on the same plane as the sidewall of the conductive pattern CDP. Figure 8a and Figure 8b As shown in FIG. 4 , the sidewall of the bank BNK may correspond to the sidewall of the conductive pattern CDP.

[0200] In an embodiment, the bank BNK may completely overlap the conductive pattern CDP. Figure 8a As shown in , in the case where the angle ANG1 of the bank BNK is substantially a right angle, the bank BNK may completely overlap the conductive pattern CDP. In a plan view, the conductive pattern CDP may not be exposed by the bank BNK, or may be covered by the bank BNK.

[0201] In an embodiment, the bank BNK may include a groove (or undercut) UC1 formed in the sidewall on the boundary surface between the bank BNK and the conductive pattern CDP. In the case where the bank BNK is formed by a dry etching operation, the active gas (plasma) may be reflected and moved in the same manner as an eddy current on the boundary surface between the bank BNK and the conductive pattern CDP, thereby forming a groove UC1 in the sidewall of the bank BNK bordering the conductive pattern CDP. Therefore, the bank BNK may have a partially inverted tapered cross-sectional shape in the boundary surface bordering the conductive pattern CDP.

[0202] Likewise, the conductive pattern CDP may include a groove UC2 formed in the sidewall of the conductive pattern CDP in the boundary surface bordering the bank BNK. In the case where the conductive pattern CDP is formed by a wet etching process, the groove UC2 may be formed in the sidewall of the conductive pattern CDP bordering the bank BNK according to the etching selectivity of the conductive pattern CDP relative to the bank BNK used as a mask.

[0203] although Figure 8a It is shown that the sidewall of the bank BNK and the sidewall of the conductive pattern CDP are aligned with each other or continuous on the boundary surface of the bank BNK and the conductive pattern CDP, but the present disclosure is not limited thereto. Figure 8b As shown in , the sidewall of the bank BNK may be disposed on a plane different from the plane of the sidewall of the conductive pattern CDP, or may be discontinuous with the sidewall of the conductive pattern CDP. On the boundary surface between the bank BNK and the conductive pattern CDP, the first width of the bank may be greater than the second width of the conductive pattern. In other words, the shape on the boundary surface between the bank BNK and the conductive pattern CDP may be changed in various ways according to the etching selectivity of the conductive pattern CDP.

[0204] Refer again Figure 7 , the second insulating layer INS2 may be disposed on the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2, and may expose the first end EP1 and the second end EP2 of the light emitting element LD. For example, the second insulating layer INS2 may be disposed only partially on a predetermined region of the light emitting element LD without covering the first end EP1 and the second end EP2 of the light emitting element LD. The second insulating layer INS2 may be formed in an independent pattern in each emission area EMA, but the present disclosure is not limited thereto. In addition, as Figure 7 As shown in FIG. 1 , if there is a space between the first insulating layer INS1 and the light emitting element LD before forming the second insulating layer INS2 , the space may be filled with the second insulating layer INS2 . Therefore, the light emitting element LD may be supported more stably.

[0205] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2 and the first end EP1 and the second end EP2 of the light emitting element LD. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer, such as Figure 7 In this case, although the first contact electrode CNE1 and the second contact electrode CNE2 are formed by the same process using the same conductive material, the present disclosure is not limited thereto.

[0206] The first and second contact electrodes CNE1 and CNE2 may electrically couple the first and second ends EP1 and EP2 of the light emitting element LD to the first and second electrodes ELT1 and ELT2 , respectively.

[0207] For example, the first contact electrode CNE1 may be disposed on the first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 may be disposed on a region (e.g., a first contactor) of the first electrode ELT1 that is not covered by the first insulating layer INS1, so that the first contact electrode CNE1 contacts the first electrode ELT1. In addition, the first contact electrode CNE1 may be disposed on a first end EP1 of at least one light emitting element LD that is adjacent to the first electrode ELT1 (e.g., disposed on the corresponding first ends EP1 of the plurality of light emitting elements LD), so that the first contact electrode CNE1 may contact the first end EP1. In other words, the first contact electrode CNE1 may be disposed to cover the first end EP1 of the light emitting element LD and at least one region of the corresponding first electrode ELT1. Therefore, the first end EP1 of the light emitting element LD may be electrically coupled to the first electrode ELT1.

[0208] Likewise, the second contact electrode CNE2 may be disposed on the second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 may be disposed on a region (e.g., a second contactor) of the second electrode ELT2 that is not covered by the first insulating layer INS1, so that the second contact electrode CNE2 contacts the second electrode ELT2. In addition, the second contact electrode CNE2 may be disposed on a second end EP2 of at least one light emitting element LD that is adjacent to the second electrode ELT2 (e.g., disposed on the second ends EP2 of a plurality of light emitting elements LD), so that the second contact electrode CNE2 may contact the second end EP2. In other words, the second contact electrode CNE2 may be disposed to cover the second end EP2 of the light emitting element LD and at least one region of the corresponding second electrode ELT2. Therefore, the second end EP2 of the light emitting element LD may be electrically coupled to the second electrode ELT2.

[0209] The third insulating layer INS3 may be formed and / or disposed on one surface of the base layer SUB1 on which the first and second bank patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the bank BNK are formed, so that the third insulating layer INS3 may cover the first and second bank patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the bank BNK. The third insulating layer INS3 may include a thin film encapsulation layer including at least one inorganic layer and / or organic layer, but the present disclosure is not limited thereto. In some embodiments, at least one outer coating layer not shown may also be disposed on the third insulating layer INS3.

[0210] In an embodiment, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may have a single-layer or multi-layer structure and include at least one inorganic insulating material and / or organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include various well-known organic / inorganic insulating materials as well as SiN x , and the constituent material of each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 is not particularly limited. The first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include the same insulating material.

[0211] As reference Figures 7 to 8b As described above, since the display panel PNL (or the display device) includes the conductive pattern CDP, the lower structure can be prevented from being damaged by the etching operation (e.g., dry etching operation) for forming the bank BNK, and the residue in the emission area EMA can be removed during the process of forming the conductive pattern CDP. In addition, the display panel PNL (or the display device) includes the bank BNK having an etching profile angle that is substantially a right angle. Therefore, optical interference caused by light emitted from the emission area EMA being introduced into the adjacent emission area EMA can be more effectively prevented. In addition, in the case where the bank BNK is formed by a dry etching operation, the shape and / or height of the bank BNK (e.g., a height of 2.5 μm or more) can be more easily controlled, and the bank BNK can have a desired shape and / or height.

[0212] Despite Figures 7 to 8bIn the embodiment, the bank BNK and the conductive pattern CDP have been shown as components separated from each other, but the present disclosure is not limited thereto. For example, the bank BNK may have a double stack structure or a multi-stack structure (or a multi-layer structure) including a conductive pattern CDP and at least one color bank layer (or a black bank layer) formed on the conductive pattern CDP.

[0213] Figures 9a to 9c It is shown along Figure 6 A cross-sectional view of another example of a sub-pixel taken along line II'. Figures 9a to 9c Shown with Figure 7 The cross-section of the sub-pixel corresponding to the sub-pixel.

[0214] Reference Figure 7 and Figure 9a , Figure 9a The sub-pixel and Figure 7 The sub-pixels may differ in: Figure 9a The sub-pixel includes a first bank pattern PW1 and a second bank pattern PW2 each having a semicircular cross-sectional shape or a semi-elliptical cross-sectional shape. In addition to the first bank pattern PW1 and the second bank pattern PW2, Figure 9a The sub-pixel and Figure 7 The sub-pixels are substantially the same or similar, so repeated description will be omitted.

[0215] like Figure 9a As shown in , each of the first and second bank patterns PW1 and PW2 may have a cross-sectional shape of a trapezoid decreasing in width from the bottom to the top thereof. In this case, each of the first and second bank patterns PW1 and PW2 may have a curved surface on at least one side.

[0216] In other words, the shape of each of the first bank pattern PW1 and the second bank pattern PW2 may be changed in various ways without being particularly limited. In an embodiment, at least one of the first bank pattern PW1 and the second bank pattern PW2 may be omitted or repositioned. The first electrode ELT1 and the second electrode ELT2 may also have a semicircular or semi-elliptical cross-sectional shape in the region overlapping the first bank pattern PW1 and the second bank pattern PW2, for example, as shown in FIG. Figure 9a as shown in .

[0217] Reference Figure 7 and Figure 9b , Figure 9b The sub-pixel and Figure 7 The sub-pixels differ in that: Figure 9b The sub-pixel includes a first contact electrode CNE1 and a second contact electrode CNE2 disposed on different layers.

[0218] The first contact electrode CNE1 may be disposed in the sub-pixel region SPA in which the second insulating layer INS2 is disposed. In an embodiment, the first contact electrode CNE1 may be disposed on the first electrode ELT1 disposed in the corresponding sub-pixel region SPA, such that the first contact electrode CNE1 contacts one region of the first electrode ELT1. In addition, the first contact electrode CNE1 may be disposed on the first end EP1 of at least one light emitting element LD disposed in the corresponding sub-pixel region SPA, such that the first contact electrode CNE1 contacts the first end EP1. Due to the first contact electrode CNE1, the first end EP1 of at least one light emitting element LD disposed in the sub-pixel region SPA may be electrically coupled to the first electrode ELT1 disposed in the corresponding sub-pixel region SPA.

[0219] The fourth insulating layer INS4 may be disposed in the sub-pixel area SPA in which the first contact electrode CNE1 is disposed. In an embodiment, the fourth insulating layer INS4 may cover the second insulating layer INS2 and the first contact electrode CNE1 disposed in the corresponding sub-pixel area SPA.

[0220] In an embodiment, the fourth insulating layer INS4 may have a single-layer or multi-layer structure and include at least one inorganic insulating material and / or organic insulating material in a manner similar to that of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. For example, the fourth insulating layer INS4 may include various well-known organic / inorganic insulating materials as well as SiN x Furthermore, the fourth insulating layer INS4 may include an insulating material different from those of the first, second, and third insulating layers INS1, INS2, and INS3, or may include the same insulating material as at least some of the first, second, and third insulating layers INS1, INS2, and INS3.

[0221] The second contact electrode CNE2 may be disposed in each sub-pixel region SPA in which the fourth insulating layer INS4 is disposed. In an embodiment, the second contact electrode CNE2 may be disposed on the second electrode ELT2 disposed in the corresponding sub-pixel region SPA, such that the second contact electrode CNE2 contacts an area of ​​the second electrode ELT2. In addition, the second contact electrode CNE2 may be disposed on the second end EP2 of at least one light emitting element LD disposed in the corresponding sub-pixel region SPA, such that the second contact electrode CNE2 contacts the second end EP2. Due to the second contact electrode CNE2, the second end EP2 of at least one light emitting element LD disposed in each sub-pixel region SPA may be electrically coupled to the second electrode ELT2 disposed in the corresponding sub-pixel region SPA. Figure 9bIn the embodiment of the present invention, the second contact electrode CNE2 may overlap the second insulating layer INS2 and the fourth insulating layer INS4 on the light emitting element LD. For example, the fourth insulating layer INS4 may be disposed between the first contact electrode CNE1 and the second contact electrode CNE2 to insulate the first contact electrode CNE1 from the second contact electrode CNE2.

[0222] The third insulating layer INS3 can be formed and / or disposed on a surface of the base layer SUB1 on which the first and second embankment patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, and the first and second contact electrodes CNE1 and CNE2 are formed, so that the third insulating layer INS3 can cover the first and second embankment patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the embankment BNK.

[0223] Reference Figure 9b and Fig.9c , Fig.9c The sub-pixel and Figure 9b The sub-pixels may differ in: Fig.9c The sub-pixel includes a first bank pattern PW1 and a second bank pattern PW2 each having a semicircular cross-sectional shape or a semi-elliptical cross-sectional shape.

[0224] like Fig.9c As shown in , each of the first and second bank patterns PW1 and PW2 may have a cross-sectional shape of a trapezoid decreasing in width from the bottom to the top thereof. In this case, each of the first and second bank patterns PW1 and PW2 may have a curved surface on at least one side.

[0225] Fig.10 It is shown along Figure 6 For illustration purposes, Fig.10 Schematically shows the reference Figure 7 Some components such as the pixel circuit layer PCL (and the base layer SUB1) are not described in detail, and a detailed description thereof will be omitted.

[0226] Reference Figure 6 and Fig.10 , the emission area EMA of the first subpixel SPX1 , the emission area EMA of the second subpixel SPX2 , and the emission area EMA of the third subpixel SPX3 may be defined by the bank BNK (and the conductive pattern CDP).

[0227] The first light emitting element LD1 may be disposed in the emission area EMA of the first sub-pixel SPX1. The second light emitting element LD2 may be disposed in the emission area EMA of the second sub-pixel SPX2. The third light emitting element LD3 may be disposed in the emission area EMA of the third sub-pixel SPX3. Here, the first light emitting element LD1 may be a red light emitting diode configured to emit red light. The second light emitting element LD2 may be a green light emitting diode configured to emit green light. The third light emitting element LD3 may be a blue light emitting diode configured to emit blue light. In this case, the display panel PNL (or display device) may display a full-color image.

[0228] The bank BNK may block light emitted from the light emitting element LD of each sub-pixel SPX from passing through the bank BNK, thus preventing optical interference that may be caused by light emitted from each emission area EMA being introduced into an adjacent emission area EMA.

[0229] The light emitting elements LD may emit light having different colors from each other. The bank BNK may block optical interference between adjacent emission regions EMA. Therefore, a separate color filter, a black matrix, etc. may not be required. Therefore, the structure of the display panel PNL (or display device) may be simplified, and the thickness of the display panel PNL (or display device) may be reduced.

[0230] Figures 11a to 11e It shows the manufacturing Figure 7 A cross-sectional view of an example of a sub-pixel process. Figures 11a to 11e Some operations of the process of manufacturing sub-pixels before supplying light emitting elements are shown. Figures 11a to 11e Schematically shows Figure 7 The structure of the pixel circuit layer PCL based on some components thereof is described in detail in FIG, and a detailed description thereof will be omitted.

[0231] Reference Fig.11a , a pixel circuit layer PCL (or a substrate layer SUB1) can be prepared.

[0232] A first bank pattern PW1 and a second bank pattern PW2 may be formed on the pixel circuit layer PCL. Figure 7 As described, the first bank pattern PW1 and the second bank pattern PW2 may be disposed at positions spaced apart from each other in the emission area EMA.

[0233] The first electrode ELT1 and the second electrode ELT2 may be formed on the first bank pattern PW1 and the second bank pattern PW2, respectively. The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other. The first electrode ELT1 may overlap with and cover the first bank pattern PW1. The second electrode ELT2 may overlap with and cover the second bank pattern PW2.

[0234] A first insulating layer INS1 may be formed on the first and second electrodes ELT1 and ELT2 and the pixel circuit layer PCL. The first insulating layer INS1 may be disposed on the entire surface of the pixel circuit layer PCL to cover the first and second electrodes ELT1 and ELT2 and the pixel circuit layer PCL exposed by the first and second electrodes ELT1 and ELT2.

[0235] Reference Fig.11b , a conductive layer CDL may be formed on the first insulating layer INS1. The conductive layer CDL may be disposed on the entire surface of the first insulating layer INS1. The conductive layer CDL may include a reference Figure 7 The conductive pattern CDP may be formed by patterning the conductive layer CDL after supplying and aligning the light emitting element LD.

[0236] A light shielding layer PR (or a photoresist layer) may be formed on the conductive layer CDL. A light shielding material (or a photoresist) may be coated on the conductive layer CDL, and the light shielding layer PR may be formed by a hard baking process. The light shielding layer PR may include a reference Figure 7 The thickness of the light shielding layer PR can be determined by the coating thickness. In other words, the height of the bank BNK can be easily adjusted by adjusting the coating thickness.

[0237] Reference Fig.11c , a mask MASK may be formed on the light shielding layer PR. The mask MASK may be patterned by an optical process. The mask MASK may be set in a shape surrounding the emission area EMA and have the same shape as the reference Figure 7 The plan shapes of the described conductive patterns CDP and / or banks BNK are substantially the same plan shapes.

[0238] In an embodiment, the mask MASK may include the same material as that of the conductive layer CDL and have the same thickness as that of the conductive layer CDL. Similar to the conductive pattern CDP, the mask MASK may include a transparent conductive material and, for example, include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), gallium indium zinc oxide (GIZO), zinc oxide (ZnO), or a combination thereof. In addition, similar to the conductive pattern CDP, the thickness of the mask MASK may be or smaller or or smaller.

[0239] Reference Fig.11d , a portion of the light shielding layer PR exposed through the mask MASK (ie, a portion of the light shielding layer PR disposed in the emission area EMA) is removed by dry etching, thereby forming a bank BNK.

[0240] Since the conductive layer CDL is disposed under the light shielding layer PR, the first insulating layer INS1 and / or the first and second electrodes ELT1 and ELT2 in the emission area EMA may be prevented from being damaged by the dry etching operation.

[0241] like Fig.11d As shown in , the residue RES of the light shielding layer PR may exist in the emission area EMA. For reference, a black matrix material (such as carbon black) for patterning on glass (or bare glass) has been developed, so that if the layer below the light shielding layer PR is not formed of glass, a large amount of residue RES may be formed. Therefore, in the method of manufacturing a display device in an embodiment of the present disclosure, the residue RES in the emission area EMA can be removed by forming a separate conductive layer CDL under the light shielding layer PR and removing the conductive layer CDL after the dam BNK has been formed.

[0242] Reference Fig.11d and Fig.11e , the mask MASK and a portion of the conductive layer CDL exposed by the bank BNK (ie, a portion of the conductive layer CDL disposed in the emission area EMA) may be removed through a wet etching operation to form a conductive pattern CDP.

[0243] While removing the portion of the conductive layer CDL disposed in the emission area EMA, the residue RES of the light shielding layer PR may be removed.

[0244] As reference Figures 11a to 11e As described above, in the method for manufacturing a display device, since the conductive layer CDL is formed under the light shielding layer PR (or the bank BNK), the lower structure can be protected from the dry etching operation for forming the bank BNK. In addition, in the method for manufacturing a display device, the residue RES of the light shielding layer PR in the emission area EMA can be removed by removing the conductive layer CDL in the emission area EMA after the bank BNK has been formed. Therefore, defects caused by the residue RES (for example, a short circuit caused by the residue or defective alignment of the light emitting element LD) can be prevented from occurring.

[0245] Fig.12a It is shown Figure 6 Electron microscope image of an example of pixel comparison. Figure 12b It is shown Figure 6 An electron microscope image of an example of pixels.

[0246] Reference Fig.12a , showing a bank BNK formed of a black matrix material (such as carbon black) without including a reference Fig.11b A plan view of a pixel of a conductive layer CDL is described.

[0247] like Fig.12a As shown in FIG. 1 , a large amount of residue of the bank BNK (or the light shielding layer PR) may exist in the emission area EMA. The residue may cause a short defect in the sub-pixel SPX or cause a black dot defect, thereby deteriorating image quality.

[0248] Reference Figure 12b , showing that including through Figures 11a to 11e FIG. 1 is a plan view of a pixel of a bank BNK formed by a process of forming the bank BNK.

[0249] like Figure 12b As shown in FIG. 1 , there may be no residue of the bank BNK (or the light shielding layer PR) in the emission area EMA, or there may be no residue of the bank BNK (or the light shielding layer PR) in the emission area EMA. Fig.12a Compared with the amount of residue in the embodiment of the present invention, the amount of residue can be significantly reduced.

[0250] Fig.13a and Fig.13b is to show that the light emitting element is Figure 7 A cross-sectional view of an example of a process for aligning sub-pixels in FIG. Figures 14a to 14c It shows the manufacturing Figure 7 A cross-sectional view of an example of a sub-pixel process.

[0251] Fig.13a and Fig.13b A process of supplying and aligning light emitting elements during a process of manufacturing sub-pixels is shown. Figures 14a to 14c A portion of the process of manufacturing a sub-pixel after alignment of the light emitting elements is shown. Figures 13a to 14c Schematically shows Figure 7 The structure of the pixel circuit layer PCL based on some components thereof is described in detail in FIG, and a detailed description thereof will be omitted.

[0252] Reference Fig.13a , after forming the bank BNK (and the conductive pattern CDP), the light emitting element LD may be supplied to the emission area EMA or disposed in the emission area EMA. The light emitting element LD may be dispersed in a predetermined solution DRL (or solvent) and supplied to each emission area EMA by an inkjet scheme or the like. However, the scheme for supplying the light emitting element LD is not limited to the aforementioned scheme, and the light emitting element LD may be supplied to the emission area EMA in various other ways.

[0253] Thereafter, an alignment voltage is applied to the first and second electrodes ELT1 and ELT2 so that an electric field may be formed between the first and second electrodes ELT1 and ELT2 in the emission area EMA. Therefore, the light emitting element LD may be self-aligned between the first and second electrodes ELT1 and ELT2 in the emission area EMA.

[0254] A ground voltage (GND) may be applied to the first electrode ELT1, and an alternating voltage (AC) may be applied to the second electrode ELT2. Alternatively, an alternating voltage (AC) may be applied to the first electrode ELT1, and a ground voltage (GND) may be applied to the second electrode ELT2.

[0255] The step of supplying the light emitting element LD and the step of aligning the light emitting element LD may be performed sequentially or simultaneously. For example, the light emitting element LD may be aligned by supplying an alignment voltage to the first electrode ELT1 and the second electrode ELT2 of the emission area EMA while the light emitting element LD is supplied to the emission area EMA. For example, the light emitting element LD may be aligned by supplying an alignment voltage to the first electrode ELT1 and the second electrode ELT2 of the emission area EMA after the light emitting element LD is supplied to the emission area EMA. In other words, the order and / or scheme of the step of supplying the light emitting element LD and the step of aligning the light emitting element LD are not particularly limited.

[0256] Reference Fig.13b After the light emitting element LD has been aligned, the solvent DRL can be removed by a volatilization scheme or other schemes. In this way, the light emitting element LD can be reliably arranged between the first electrode ELT1 and the second electrode ELT2.

[0257] Reference Fig.14a The second insulating layer INS2 may be formed on the light emitting element LD, in particular, may be formed on the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2. The second insulating layer INS2 may fill the space between the first insulating layer INS1 and the light emitting element LD.

[0258] The first end EP1 and the second end EP2 of the light emitting element LD may be exposed by partially patterning the second insulating layer INS2. In addition, when the second insulating layer INS2 is patterned, the first insulating layer INS1 may be partially removed, such as Fig.14a In this case, the first electrode ELT1 and the second electrode ELT2 may be exposed.

[0259] Reference Fig.14b First and second contact electrodes CNE1 and CNE2 may be disposed on the first and second electrodes ELT1 and ELT2 and the first and second ends EP1 and EP2 of the light emitting element LD. The first and second contact electrodes CNE1 and CNE2 are disposed on the same layer using the same conductive material and by the same process.

[0260] The first and second contact electrodes CNE1 and CNE2 may electrically couple the first and second ends EP1 and EP2 of the light emitting element LD to the first and second electrodes ELT1 and ELT2 , respectively.

[0261] Reference Fig.14c A third insulating layer INS3 may be formed on a surface of the base layer SUB1 on which the first and second embankment patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the embankment BNK are formed, so that the third insulating layer INS3 may cover the first and second embankment patterns PW1 and PW2, the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the embankment BNK.

[0262] Although the reference Figures 14a to 14c A case where the first contact electrode CNE1 and the second contact electrode CNE2 are formed on the same layer through the same process has been described, but the present disclosure is not limited thereto. Figure 9b and Fig.9c As described above, after the second insulating layer INS2 is formed, the first contact electrode CNE1 , the fourth insulating layer INS4 , and the second contact electrode CNE2 may be sequentially formed.

[0263] Figures 15a to 15d It is shown along Figure 6 A cross-sectional view of another example of a sub-pixel taken along line II'. Figures 15a to 15d Shown with Figure 7 The cross-section of the sub-pixel corresponding to the sub-pixel.

[0264] Reference Figure 7 and Fig.15a , Fig.15a The sub-pixel and Figure 7 The sub-pixels differ in that: Fig.15a The sub-pixel includes a conductive pattern CDP disposed on the bank BNK. In addition to the bank BNK and the conductive pattern CDP, Fig.15a The sub-pixel and Figure 7 The sub-pixels are substantially the same or similar, and thus repeated descriptions will be omitted.

[0265] like Fig.15a As shown in FIG, the bank BNK may be directly disposed on the first insulating layer INS1. Figure 7 As described above, the bank BNK may be formed between the sub-pixels SPX to surround the corresponding emission areas EMA of the sub-pixels SPX, so that a pixel defining layer for defining the emission areas EMA of the sub-pixels SPX may be formed.

[0266] The conductive pattern CDP may be disposed on the bank BNK. The conductive pattern CDP may be formed between the sub-pixels SPX to surround the corresponding emission areas EMA of the sub-pixels SPX, and may overlap the bank BNK in a thickness direction and completely overlap the bank BNK.

[0267] The conductive pattern CDP may be used as a mask. The bank BNK may be formed by a dry etching operation. Figure 8a As described above, the bank BNK may have a rectangular cross-sectional shape, or the etching profile angle of the bank BNK may be substantially a right angle. However, the present disclosure is not limited thereto. Figure 8b As described above, the bank BNK may have a trapezoidal cross-sectional shape or a curved shape, and an etching profile angle thereof may be 45° or more, for example, in the range of 70° to 90°.

[0268] In an embodiment, the bank BNK may have a color filter material. Figure 7 As described above, in the case where the bank BNK includes a color filter material, the residue of the bank BNK can be prevented from occurring, compared with the case where a black matrix material such as carbon black is used.

[0269] The sub-pixel may include a first bank pattern PW1 and a second bank pattern PW2 having various shapes. Fig.15a and Fig.15c As shown in , each of the first bank pattern PW1 and the second bank pattern PW2 may have a trapezoidal cross-sectional shape that decreases upward in width. Fig.15b and Fig.15d As shown in FIG. 1 , each of the first bank pattern PW1 and the second bank pattern PW2 may have a semicircular cross-sectional shape or a semi-elliptical cross-sectional shape decreasing upward in width.

[0270] In addition, the sub-pixel may include a first contact electrode CNE1 and a second contact electrode CNE2 disposed on the same layer or different layers. Fig.15a and Fig.15b As shown in , the first contact electrode CNE1 and the second contact electrode CNE2 can be formed on the same layer by the same process. Fig.15c and Fig.15d As shown in FIG. , the first contact electrode CNE1 and the second contact electrode CNE2 may be sequentially formed on different layers through different processes.

[0271] As reference Figures 15a to 15dAs described above, the display panel PNL (or display device) includes a bank BNK having an etching profile angle that is substantially a right angle. Therefore, optical interference caused by light emitted from the emission area EMA being introduced into the adjacent emission area EMA can be more effectively prevented. In addition, in the case where the bank BNK is formed by a dry etching operation, the shape and / or height of the bank BNK (e.g., a height of 2.5 μm or more) can be more easily controlled.

[0272] Figures 16a to 16d It shows the manufacturing Fig.15a A cross-sectional view of an example of a sub-pixel process. Figures 16a to 16d Some operations of the process of manufacturing sub-pixels up to the alignment of light emitting elements are shown. Fig.11b In addition to the operation of the conductive layer CDL, Figures 16a to 16d Operation and reference Figures 11a to 11e The operations described are substantially the same or similar, so that repeated descriptions thereof will be skipped.

[0273] Figures 16a to 16d The structure of the above-mentioned pixel circuit layer PCL based on some components thereof is schematically illustrated, and a detailed description thereof will be omitted.

[0274] Reference Fig.16a , a first bank pattern PW1 and a second bank pattern PW2 may be formed on the pixel circuit layer PCL (or the base layer SUB1). A first electrode ELT1 and a second electrode ELT2 may be formed on the first bank pattern PW1 and the second bank pattern PW2, respectively. A first insulating layer INS1 may be formed on the first electrode ELT1, the second electrode ELT2, and the pixel circuit layer PCL.

[0275] Subsequently, a light shielding layer PR (or a photoresist layer) may be formed on the first insulating layer INS1 .

[0276] Reference Fig.16b , a conductive pattern CDP may be formed on the light shielding layer PR as a mask. The conductive pattern CDP may be disposed to surround the emission area EMA.

[0277] Reference Fig.16c , a portion of the light shielding layer PR exposed by the conductive pattern CDP (ie, a portion of the light shielding layer PR disposed in the emission area EMA) is removed by dry etching, whereby a bank BNK may be formed.

[0278] Although the residue RES of the light shielding layer PR may exist in the emission area EMA, the residue RES may be reduced because the light shielding layer PR is formed of a color filter material.

[0279] Reference Fig.16d, after forming the bank BNK (and the conductive pattern CDP), the light emitting element LD may be supplied to or disposed in the emission area EMA.

[0280] exist Fig.16d After the operation, you can use Figures 14a to 14c operation.

[0281] As reference Figures 16a to 16d As described above, in the method of manufacturing a display device, the bank BNK is formed by a dry etching process instead of using an optical process, so that the etching profile angle of the bank BNK can be controlled to be 45° or more or in the range of 70° to 90°. In addition, the thickness of the bank BNK can be easily controlled by adjusting the coating thickness of the light shielding layer PR.

[0282] As described above, the display device according to various embodiments of the present disclosure may include the bank BNK surrounding each emission area EMA in which at least one light emitting element LD is disposed.

[0283] In particular, in the embodiment of the present disclosure, the bank BNK is formed by a dry etching process instead of using an optical process, so that the bank BNK having a desired etching profile angle (e.g., 70° or more) and a desired thickness (e.g., 2.5 μm or more) can be easily formed. The bank BNK can prevent light from leaking from the emission area EMA in the lateral direction, so that a color mixing phenomenon can be prevented from occurring between adjacent sub-pixels SPX.

[0284] In addition, since the conductive pattern CDP (or the conductive layer CDL) is formed under the bank BNK, the lower structure (e.g., the first insulating layer INS1 and the first and second electrodes ELT1 and ELT2) can be prevented from being damaged during the dry etching process, and the residue of the bank BNK can be removed along with the formation of the conductive pattern CDP. Therefore, defects caused by the residue (e.g., a short-circuit defect attributable to the residue or an alignment defect of the light emitting element LD) can be prevented from being caused.

[0285] In an embodiment of the present disclosure, each sub-pixel SPX can form each light-emitting device. For example, the first sub-pixel SPX1 corresponding to the red sub-pixel can form a red light-emitting device, the second sub-pixel SPX2 corresponding to the green sub-pixel can form a green light-emitting device, and the third sub-pixel SPX3 corresponding to the blue sub-pixel can form a blue light-emitting device. The full-color pixel PXL including the first sub-pixel SPX1, the second sub-pixel SPX2 and the third sub-pixel SPX3 can form a full-color light-emitting device. In other words, the embodiments of the present disclosure are not limited to display devices, and can be widely applied to other types of devices that require a light source.

[0286] Although the spirit and scope of the present disclosure are described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and modifications may be made here without departing from the scope of the present disclosure defined by the claims.

[0287] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device, comprising: A pixel circuit layer including a plurality of transistors; A first electrode and a second electrode, disposed on the pixel circuit layer and spaced apart from each other; A first insulating layer, disposed on the pixel circuit layer, the first electrode and the second electrode; a conductive pattern, disposed on the first insulating layer and electrically insulated from the first electrode and the second electrode; a bank disposed on the conductive pattern; as well as A light emitting element is provided on the first insulating layer between the first electrode and the second electrode and is electrically coupled to the first electrode and the second electrode.

2. The display device according to claim 1, wherein: An angle between a sidewall of the bank and an upper surface of the first insulating layer is in a range of 70° to 90°.

3. The display device according to claim 2, wherein: The bank completely overlaps the conductive pattern, and Wherein, the sidewall of the bank is located in the same plane as the plane of the sidewall of the conductive pattern.

4. The display device according to claim 3, wherein: The bank includes a groove in a boundary surface thereof bordering the conductive pattern, the groove being formed in the side wall of the bank, and Wherein, a portion of the bank adjacent to the boundary surface has an inverted tapered shape.

5. The display device according to claim 2, wherein: The bank overlaps the conductive pattern, and Wherein, on a boundary surface between the bank and the conductive pattern, a first width of the bank is greater than a second width of the conductive pattern.

6. The display device according to claim 1, wherein: The conductive pattern includes a conductive material removed by wet etching.

7. The display device according to claim 6, wherein: The conductive pattern includes a transparent conductive material.

8. The display device according to claim 1, wherein: The bank includes a light shielding material configured to block light incident from the light emitting element.

9. The display device according to claim 1, further comprising: A first bank pattern is disposed between the first electrode and the pixel circuit layer; as well as A second bank pattern is disposed between the second electrode and the pixel circuit layer. The light emitting element is disposed between the first bank pattern and the second bank pattern, and The thickness of the bank is greater than the thickness of the first bank pattern.

10. The display device according to claim 9, wherein: The conductive pattern does not overlap the first bank pattern and the second bank pattern.

11. The display device according to claim 9, further comprising: a first contact electrode disposed on a first end of each of the light emitting elements and a region of the first electrode and configured to electrically connect the first end to the first electrode; as well as A second contact electrode is provided on the second end of each of the light emitting elements and a region of the second electrode and is configured to electrically connect the second end to the second electrode.

12. The display device according to claim 11, wherein: The conductive pattern, the first contact electrode, and the second contact electrode are disposed on the same plane.

13. The display device according to claim 12, wherein: The thickness of the conductive pattern is different from the thickness of the first contact electrode.

14. The display device according to claim 1, wherein: The pixel circuit layer includes a first emission region, a second emission region, and a third emission region separated from each other by the bank, wherein the light emitting element comprises a first light emitting element disposed in the first emission region, a second light emitting element disposed in the second emission region, and a third light emitting element disposed in the third emission region, and The first light-emitting element, the second light-emitting element and the third light-emitting element emit light of different colors.

15. The display device according to claim 1, wherein: Each of the light emitting elements includes a rod-shaped light emitting diode having a size ranging from a nanometer scale to a micrometer scale.

16. A display device, comprising: A pixel circuit layer including a plurality of transistors; A first electrode and a second electrode, disposed on the pixel circuit layer and spaced apart from each other; A first insulating layer, disposed on the pixel circuit layer, the first electrode and the second electrode; a bank formed on the first insulating layer; a conductive pattern disposed to overlap the bank and to be electrically insulated from the first electrode and the second electrode; as well as A light emitting element is provided on the first insulating layer between the first electrode and the second electrode and is electrically coupled to the first electrode and the second electrode.

17. A method for manufacturing a display device, the method comprising the following steps: forming a first electrode and a second electrode spaced apart from each other on a pixel circuit layer including a plurality of transistors; forming a first insulating layer on the pixel circuit layer, the first electrode and the second electrode; forming a light shielding layer on the first insulating layer; patterning the light shielding layer using a mask; as well as A bank is formed by etching the light shielding layer exposed through the mask.

18. The method according to claim 17, wherein: The step of forming the light shielding layer on the first insulating layer comprises: forming a conductive layer on the first insulating layer; and The light shielding layer is formed on the conductive layer.

19. The method according to claim 18, wherein: The steps of forming the bank include: performing dry etching on the light shielding layer exposed through the mask; and The portion of the conductive layer exposed by the mask and the mask are wet-etched.

20. The method according to claim 18, wherein: The mask and the conductive layer include the same material.

Images