Circuit arrangement comprising at least a delta-sigma modulator and a sample-and-hold element

Abstract

The invention relates to a circuit arrangement for an incremental delta-sigma modulator, the circuit arrangement comprising at least one incremental delta-sigma modulator and a sample-and-hold element, wherein the sample-and-hold element is arranged upstream of the incremental delta-sigma modulator and provides an input voltage to the incremental delta-sigma modulator in a charged state, wherein the sample-and-hold element has a capacitor for applying the input voltage to the incremental delta-sigma modulator, wherein a first switch is arranged upstream of the capacitor and a second switch is arranged downstream of the capacitor, wherein the first switch is opened when the second switch is closed in order to provide an input voltage of reduced magnitude, in particular attenuated, at the incremental delta-sigma modulator, or the second switch is opened when the first switch is closed in order to charge the capacitor of the sample-and-hold element. In addition, a method for operating a circuit arrangement for an incremental delta-sigma modulator is specified.

Description

Technical Field

[0001] The invention relates to a circuit arrangement comprising at least a delta-sigma modulator and a sample-and-hold element, and to a method for operating a circuit arrangement comprising at least a delta-sigma modulator and a sample-and-hold element. Background Art

[0002] An incremental delta-sigma modulator (IDSM) is a modified delta-sigma modulator (DSM) in which continuous AD conversion is not performed. The IDSM is reset after each AD conversion. The integrator is reset, for example, by switching on a switch such as in Figure 1 The reset of the IDSM enables multiplexing operation, in which analog signals from different input sources are converted into the digital domain by the IDSM. Multiplexing is not feasible in the classic DSM. It is known that single-bit as well as multi-bit implementations are feasible for DMS.

[0003] There are two locations in the IDSM where the "sample" is "taken", namely at the comparator in the IDSM and / or at the sampling and holding element, also called the S&H stage. In the single-bit sampling clock of the comparator of the known delta-sigma modulator, the bits are respectively transmitted from the comparator to the sampling filter. Correspondingly, in the multi-bit embodiment of the DSM, multiple bits are transmitted from the comparator to the sampling filter at the sampling clock of the comparator, wherein a multi-bit comparator is correspondingly present. The sampling clock of the S&H stage (such as in the ADC) is defined as the following clock, with the help of which the new voltage value is stored. The sampling clock also corresponds to the following clock, with the help of which a usable digital value, i.e. the voltage value converted into digital, is provided at the output of the sampling filter. The AD conversion lasts for one S&H sampling clock, but for multiple comparator sampling clocks, and the sampled voltage values ​​are respectively converted into digital.

[0004] In a typical case, a sample-and-hold element (also called Sample & Hold (S&H) stufe) is also used as the input stage, wherein the input voltage to be converted is stored on a capacitor and connected to the input of the IDSM by means of an active amplifier or an impedance converter (called active Buffer in English). The buffer is used in this case to make the stored input voltage unaffected by the input resistance. Alternatively, the storage capacitor can also be abandoned. The input voltage is then applied to the buffer during the entire AD conversion period.

[0005] A typical disadvantage of DSM and IDSM is that when the input signal approaches the so-called "full scale" value, i.e., when the maximum possible reset voltage is used, an increased noise is generated in the output signal. This leads to a significant increase in the variance when the input signal is high. The variance indicates the fluctuation of the output value in different AD conversions with the same input value of the input voltage. This is particularly problematic when the signal and the associated reference signal should be converted (double sampling) and the reference signal is close to the full scale signal. In this case, the real signal is usually continuously positive or negative with respect to the reference signal (unipolar measurement). In this case, the total noise of the calculated final value is always dominated by the noise of the reference value, even if the signal is in the middle range of the IDSM and a small noise component can be achieved there.

[0006] This has the result that a large range (approximately 40 to 50%) of the input signal range of the delta-sigma modulator cannot be meaningfully utilized due to the high noise. Summary of the invention

[0007] The object of the present invention is to provide an improved circuit arrangement for an incremental delta-sigma modulator, in particular, by means of which a large range of an input signal range, in particular of an incremental delta-sigma modulator, can be utilized in a meaningful manner.

[0008] This object is achieved by means of a circuit arrangement according to the invention for an incremental delta-sigma modulator and a method according to the invention for operating the circuit arrangement. Further embodiments of the improved circuit arrangement and of the proposed method are described below.

[0009] According to the invention, a circuit arrangement for an incremental delta-sigma modulator is proposed. The circuit arrangement comprises at least one incremental delta-sigma modulator and a particularly passive sampling and holding element, wherein the sampling and holding element is arranged upstream of the incremental delta-sigma modulator and provides an input voltage to the incremental delta-sigma modulator in a charged state, wherein the sampling and holding element has a capacitor for applying the input voltage to the incremental delta-sigma modulator, wherein a first switch is arranged upstream of the capacitor and a second switch is arranged downstream of the capacitor, wherein the first switch is opened when the second switch is closed in order to provide an input voltage with a reduced value, in particular decaying over time, at the delta-sigma modulator, or the second switch is opened when the first switch is closed in order to charge the capacitor of the sampling and holding element. The passive sampling and holding element is characterized in that it does not include an active amplifier. More precisely, the passive sampling and holding element has only a capacitor that is arranged between two switches. In the case of a passive sampling and holding element, the two switches (first switch and second switch) are switched so that at a point in time either the first switch is closed and the second switch is open, or the second switch is closed and the first switch is open. Passive sampling and holding elements are used in conjunction with incremental delta-sigma modulators as proposed. Known DSMs usually operate completely without sampling and holding elements (S&H stages). In general, it is conceivable to use passive sampling and holding elements with analog-to-digital converters. In this case, in order to avoid dead times during switching, the two switches are opened. As proposed, the time ends when the capacitor is charged and the integrator capacitance of the IDSM is reset. Dead times can thus be avoided. Alternatively, multiple S&H stages with IDSMs can also be used, wherein only one S&H stage is connected to the IDSM by means of its second switch. The "charging time" is then independent of the resetting of the IDSM. Dead times can thus also be avoided.

[0010] Preferably, the capacitor is configured so that the time constant of the discharge of the capacitor for the sample-and-hold element corresponds to the AD conversion. In particular, the AD conversion is provided as a number of bits / clock frequency, wherein the clock frequency is the clock frequency of the comparator. It is also conceivable that the time constant of the discharge of the capacitor for the sample-and-hold element is greater or less than the duration of the AD conversion. In particular, the time constant is given by the capacitance of the capacitor of the sample-and-hold element and the input resistance at the IDSM. This has the advantage that a large range of the input signal range of the incremental delta-sigma modulator can be meaningfully utilized. In particular, the variance of the incremental delta-sigma modulator is significantly smaller within the input range, in particular near the maximum input signal, than the incremental delta-sigma modulator known from the prior art.

[0011] Preferably, the charging of the capacitor takes place during the reset of the IDSM, in particular, the capacitor of the sampling and holding element has a time constant that is as small as possible with respect to the charging of the capacitor. Alternatively, multiple S&H stages can also be set in multiplexed operation during charging. Preferably, the time constant for discharging the capacitor corresponds to a time that is greater or less than the time of the AD conversion. Particularly preferably, the discharge of the capacitor in the IDSM takes place via the time constant of the AD conversion. In this case, the time constant is defined by the input resistance R of the IDSM and the capacitance C of the S&H stage. The length of the AD conversion is related to the system specifications. For example, the length of the AD conversion can be in the range of 1 μs and the sampling clock of the comparator is 100 MHz. That is, in this case, each AD conversion transmits less than 100 bits of the comparator to the sampling filter. In this case, less than 100 bits are transmitted because some clocks are required for reset and other control tasks.

[0012] It is also preferred that the incremental delta-sigma modulator is resettable after each AD conversion. Since the incremental delta-sigma modulator is resettable, the oscillation effect on the subsequent AD conversion caused by the previous AD conversion can be avoided. Each AD conversion can thus be regarded as independent of the previous AD conversion.

[0013] According to a preferred embodiment, the incremental delta-sigma modulator is an n-order modulator, where n is a natural number, in particular n=1, 2, 3, 4, 5 or 6. The order of the incremental delta-sigma modulator is related to the specifications of the modulator. In particular, the order of the delta-sigma modulator is determined by the number of integrators. In principle, a more accurate AD conversion can be achieved with a higher order when the number of comparators used is the same, or the same accuracy can be achieved when the comparator clock is less, thereby providing a faster modulator. However, at a higher order, the modulator becomes more complex, in particular, the modulator then has a larger spatial expansion. That is, the order of the incremental delta-sigma modulator is a trade-off between accuracy or speed and complexity or size.

[0014] Preferably, the sample-and-hold element is integrated in the incremental delta-sigma modulator or can be externally connected to the incremental delta-sigma modulator. Particularly preferably, the sample-and-hold element and the incremental delta-sigma modulator are arranged on a chip, in particular together with other components.

[0015] Furthermore, the incremental delta-sigma modulator preferably comprises a decimation filter, in particular at its output. The decimation filter particularly preferably comprises a lossy integrator. In the case of a lossy integrator, the weighting of the output bits in the decimation filter can be adjusted due to the reduced input voltage.

[0016] Preferably, the output bit at the end of the AD conversion has an increased bit value compared to the weighting at a static, ie constant, input voltage applied to the incremental delta-sigma modulator. The AD conversion here comprises, for example, less than 100 comparator clocks (ie <100 bits).

[0017] To adjust the weighting, the in particular digital integrator of the sampling filter of the incremental delta-sigma modulator is replaced by a so-called in particular digital lossy integrator in which in particular the limit frequency f C =1 / (2πRC) is defined by the time constant formed by the input resistance R of the incremental delta-sigma modulator and the capacitance C of the capacitor of the especially passive sampling and holding element. In the case of an ideal integrator, the gain is not limited. That is, a constant input value of ≠0 (after an infinite time) leads to an infinite output value. In the case of a lossy integrator, the gain is limited. This results in the lossy integrator behaving like an integrator at high input frequencies (integrator behavior) and like an amplifier at low frequencies (low-pass behavior). The transition between the integrator behavior and the low-pass behavior is defined by the boundary frequency.

[0018] Another aspect of the invention relates to a method for operating a circuit arrangement for an incremental delta-sigma modulator. The circuit arrangement comprises at least one incremental delta-sigma modulator and a sample-and-hold element, wherein the sample-and-hold element is arranged upstream of the input of the incremental delta-sigma modulator, in particular the circuit arrangement is designed as described, wherein the method comprises the following steps:

[0019] - providing an input voltage to an incremental delta-sigma modulator, in particular via a capacitor of a sample-and-hold element;

[0020] - using an input voltage of reduced magnitude in order to ensure the random nature of the output bit stream, where

[0021] - The capacitor is charged during the reset phase of the incremental delta-sigma modulator and is connected to the incremental delta-sigma modulator during switching.

[0022] In the proposed method, a passive sampling and holding element is used, wherein the applied input voltage changes, in particular decreases in magnitude over time. As long as the input voltage is transmitted to the IDSM, the charging of the sampling capacitor of the sampling and holding element is excluded. This is achieved by opening the first switch and closing the second switch (first switching state). However, once the sampling capacitor is charged, i.e. the first switch is closed, the second switch is opened (second switching state) to avoid supplying the input voltage to the incremental delta-sigma modulator. The capacitor of the sampling and holding element is also referred to as a sampling capacitor. The dead time or switching time between these two switching states of the first switch and the second switch is within the range of the comparator clock and can be ignored. The switching time can be easily implemented, in particular, via process control. However, shorter or longer switching times can also be considered. The switching time is unimportant when the resistance of the open switch is large enough so that the capacitor does not (excessively) discharge.

[0023] Preferably, the capacitor of the sampling and holding element is selected so that the time constant for the discharge of the capacitor of the sampling and holding element corresponds to the duration of the AD conversion. In particular, the AD conversion is given as the number of bits / clock frequency, wherein the clock frequency is the clock frequency of the comparator. In particular, the time constant is given by the capacitance of the capacitor of the sampling and holding element and the input resistance at the IDSM. This has the following advantages: the large range of the input signal range of the incremental delta-sigma modulator can be meaningfully utilized. In particular, the variance of the incremental delta-sigma modulator is significantly smaller in the input range, especially near the maximum input signal, than the incremental delta-sigma modulator known in the prior art. Preferably, the capacitor is charged during the reset of the IDSM, i.e., the charging of the capacitor is performed with the smallest possible time constant. Alternatively, multiple S&H stages can also be set in multiplexed operation during charging. In addition, preferably, the discharge of the capacitor in the IDSM is performed with the time constant of the AD conversion or with a time constant greater or less than the duration of the AD conversion. In this case, the time constant is defined by the capacitance C of the S&H stage and the input resistance R of the IDSM. The length of the AD conversion depends on the system specifications. For example, the length of the AD conversion can be in the range of 1 μs, while the sampling clock of the comparator is 100 MHz. That is, in this case, less than 100 bits of the AD conversion comparator are transferred to the sampling filter each time. In this case, less than 100 bits are transferred because some clocks are needed for reset and other control tasks.

[0024] It is also preferred that the weighting of the output bits is adjusted by means of the sampling filter, in particular the output bits at the end of the AD conversion are assigned an increased bit value compared to the weighting at a constant input voltage. When the input voltage drops to, for example, 90% of the maximum input voltage due to the discharge, the bit value of the comparator bit is increased to 1 / 90% (compared to the first generated bit, in which the capacitor is still charged to 100% of the sampled voltage).

[0025] To adjust the weighting, the integrator of the decimation filter is replaced by a so-called lossy integrator, in which in particular the limit frequency f C =1 / (2πRC) is defined by the time constant formed by the input resistor R and the capacitor C. The weighting is achieved by the lossy integrator in such a way that the weight of the first processed bit is reduced by the decaying impulse response of the lossy integrator.

[0026] Preferably, the digital output value is calculated as a weighted sum of the output bit stream. The weighting of the bits is defined in this case by the impulse response of the (digital) decimation filter. The last bit generated is weighted with the first value of the impulse response, the second to last bit is weighted with the second value, etc.

[0027] An essential aspect of the invention can be the use of a passive sample-and-hold stage or passive sample-and-hold element in order to feed an incremental delta-sigma modulator with an input voltage whose magnitude decreases over time. It is conceivable that the invention is also applicable to delta-sigma modulators. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It goes without saying that the described embodiments do not limit the scope of the claimed invention.

[0029] The accompanying drawings show:

[0030] Figure 1 A 3rd order IDSM with an active sample and hold stage (Sample & Hold stufe in English) is shown;

[0031] Figure 2 A typical decimation filter for a 3rd order IDSM is shown;

[0032] FIG3 shows the output signal and the variance for different input signals when using an active sample-and-hold element stage known from the prior art;

[0033] Figure 4 shows a typical output bit stream with an input signal of 90% full scale (FS);

[0034] Figure 5 shows an IDSM with the proposed passive sample-and-hold element stage;

[0035] Figure 6 Shown at an input signal with 90% FS and according to Figure 5 The variation curve of the voltage sampled during AD conversion in the case of a passive sample-and-hold element level;

[0036] Figure 7 Shown in use according to Figure 5 IDSM and according to Figure 6 The magnitude of the voltage decreases when a quasi-random bit stream is generated.

[0037] Figure 8 A decimation filter with a lossy integrator for an IDSM with a passive sample-and-hold element stage is shown;

[0038] Fig. 9 The output signal and the variance are shown for different input signals when using a passive sample-and-hold element stage according to the invention. DETAILED DESCRIPTION

[0039] Combine the following Figures 1 to 9 The present invention is described wherein Figure 1 , 3 and 4 show circuit arrangements known from the prior art ( Figure 1 ) and its measurable output signal or its variance ( Figure 3a , b) and a typical output bit stream ( Figure 4 ).

[0040] Figure 1 An embodiment known from the prior art of a circuit arrangement 10 for an incremental delta-sigma modulator (IDSM) 1 is shown. The IDSM 1 comprises a circuit arrangement 10 as shown in FIG. Figure 1 4, the three integrators 2 shown in FIG. 4 each also have a capacitor 3 and a switch 4. After the sample has been converted, ie after the AD conversion, the integrator 2 is reset. For simplicity, the zero position of the IDSM required for stability is not shown. The capacitor 3 of the integrator 2 is used as an analog memory, wherein the input voltage U 输入 Over time, the integral is obtained. In addition, the IDSM and each known form of DSM include an input resistor 5 and a comparator 6. In addition, the IDSM includes a feedback component 8. In the simplest case, the feedback component 8 consists of two voltage sources, which provide a positive or negative maximum signal. For example, it is conceivable to simply use GND and the supply voltage as a positive or negative maximum signal and a controlled switch, which applies one or another voltage to the resistor in relation to the output bit. In a multi-bit implementation, correspondingly more different voltage levels must be feasible. A filter 7, in particular a digital one, in particular a low-pass filter or an integrator is provided at the output of the IDSM. The circuit arrangement 10 also includes a sampling and holding element 9, which is connected upstream of the IDSM1. The sampling and holding element 9 provides an input voltage U at the input of the IDSM1. 输入 The sample-and-hold element 9 comprises in a known manner a switch 11 , a capacitor 12 and an active buffer 13 , whereby a constant input voltage U 2 can be provided at the input of the IDSM 1 . 输入 For the purposes of the present invention, a buffer is understood to be an amplifier or an impedance converter.

[0041] IDSM 1 is a modified version of the delta-sigma modulator, in which the input voltage U 输入 Continuous AD conversion. IDSM1 is reset after each AD conversion or IDSM1 can be reset after each AD conversion. When sampling the voltage, the sample is understood to be the instantaneous value of the voltage at the sampling time. The instantaneous value is then stored in the S&H stage on the capacitor. The reset of the integrator is shown according to Figure 1In the example of FIG. 1 , the switching takes place via the switch 4 across the integrating capacitor or capacitor 3. The resetting of the IDSM 1 enables a multiplexing operation in which analog signals from different input sources are converted into the digital domain by means of the IDSM.

[0042] As the input stage of the IDSM 1 , a sample-and-hold element 9 is usually used, which is also known as a Sample & Hold (S & H) stage, wherein the input voltage U to be converted is 输入 The input voltage U is stored on a capacitor 12 and connected to the input of the IDSM 1 by means of an active buffer 13. The buffer 13 is used to make the stored input voltage U 输入 The input voltage U 输入 It is then applied to buffer 13 during AD conversion.

[0043] Figure 2 A possible filter 7 is shown which can be used at the output of the IDSM 1, namely a decimation filter 7'. The advantage of the IDSM 1 over the DSM is the possibility of using a simpler digital decimation filter 7' for processing the bit stream. A typical decimation filter 7' for a 3rd order IDSM is shown in Figure 2 As shown in , it consists of three digital integrators 20. The number of integrators 20 determines the order of the filter 7, 7'. The integrator 20 can be implemented as an adder. As in the analog part of IDSM1, the adder is reset after each AD conversion. The digital output Out of the sampling filter 7' is calculated as Out=ΣΣΣBit N Instead of three integrators 20, a look-up table (LUT) and a single adder can also be substituted, since the influence of each bit on the digital output signal can be calculated beforehand.

[0044] 3 shows a typical output signal with the associated variance when using a known circuit arrangement 10 for an IDSM 1 with a known sample-and-hold element 9. A known disadvantage of DSMs and also IDSMs is that increased noise is generated in the digital output signal in the vicinity of the so-called full-scale value of the input signal. The full-scale value corresponds to the maximum possible reset voltage. Figure 3a The relationship between the normalized input signal and the normalized output value (Output) in the case of the 3rd order IDSM is shown, and Figure 3b shows the normalized input signal and ( Figure 3a The relationship between the variance of the digital output signal. Figure 3a The maximum positive input signal on the x-axis of , b has a value of +1 and the maximum negative input signal has a value of -1. Figure 3a The y-axis shows the normalized output signal, while Figure 3b The y-axis of φ shows the variance of the output signal (Output) when the same value is converted multiple times. The variance is also shown in a normalized manner.

[0045] It can be seen that in the case of high input signals, i.e. in the case of maximum positive voltage and in the case of minimum negative voltage, a significant increase in variance occurs. The variance indicates the fluctuation of the output value in the case of different AD conversions with the same, i.e. constant input value. However, this is problematic when the signal and the associated reference signal should be converted, which is also understood as double sampling. The reference signal is usually located near the full-scale signal and the real signal is always larger than the reference signal (unipolar measurement). In this case, the total noise of the calculated final signal is always dominated by the noise of the reference signal, even when the final signal is in the middle range of the IDSM and a small noise component can be achieved there. This results in: a large range of the input signal range (approximately 40 to 50%) cannot be meaningfully utilized due to the high noise.

[0046] Figure 4 The time-known variation of the (output) bit stream is shown for an input signal with 90% of the full scale (FS), i.e. for an input voltage of 90% of the maximum possible reset voltage. Normally, the bit stream of a DSM or IDSM1 has a quasi-random property. This random property is the basis for the design and calculation of the properties of the DSM. This random property no longer exists when the input signal is near the full scale value. Figure 4 The output bit stream is shown by way of example for an input signal with 90% FS. Almost all output bits have one value, namely 1, in this case.

[0047] Figure 5 An embodiment of the proposed circuit arrangement 10 for an incremental delta-sigma modulator 1 is shown. In order to ensure the quasi-random nature of the output bit stream even when the input signal is close to FS, an attenuated input signal (e.g. Figure 6 The attenuation of the input voltage U 输入 ). This achieves: As in Figure 5 As shown in FIG, the active buffer 13 between the sampling capacitor 12 and the input resistor 5 of IDSM1 is omitted (see FIG. Figure 1 ). Instead of the active buffer 13 ( Figure 1 ) According to the proposal, the switch 14 is integrated into the sample-and-hold element, so that the capacitor 12 is arranged between the switches 11 and 14. Instead of the known sample-and-hold element 9 ( Figure 1 ), according to the suggestion, the passive sample-and-hold element 9'( Figure 5 ) is used to feed the input voltage U to IDSM1输入 When using an active sample-and-hold element 9, a constant input voltage U is fed to the IDSM, whereas when using a passive sample-and-hold element 9' according to the proposal, an input voltage U that decays over time is fed to the IDSM1. 输入 The capacitor 12 is then charged to the input voltage U during the reset phase of the IDSM1, ie during the reset period. 输入 During the conversion, it is connected to the input resistor 5 of the IDSM 1. The sampling capacitor 12 is preferably selected so that the time constant formed by the sampling capacitor 12 and the input resistor 5 of the IDSM 1 corresponds to the conversion cycle time T, in particular the AD conversion time, which is defined as the number of bits / clock frequency.

[0048] By discharging the capacitor 12 during the AD conversion, the voltage U 输入 As in Figure 6 As shown in FIG. 1 , the voltage U across the capacitor 12 decreases from the initial value of the sampling. Because during the conversion, ie, the AD conversion, the voltage U across the capacitor 12 输入 Therefore, it is ensured that the bit stream generated by IDSM1 still has a quasi-random pattern after several clocks, such as Figure 7 As shown in .

[0049] Since the input signal U of IDSM1 输入 Now, the input signal U is varied in time, resulting from the reduction in the capacitor discharge, so the weighting of the output bits in the sampling filter 7' needs to be adjusted. 输入 At the end of AD conversion, the bit is reduced with the input signal U 输入 The bit value that needs to be increased compared to the constant weighting. To adjust the weighting, such as in Figure 8 As shown in Figure 2 One of the integrators 20 of the sampling filter 7') is replaced by a "lossy integrator" 21. The boundary frequency of the "lossy integrator" 21 is preferably defined in this case by the time constant formed by the input resistor 5 and the sampling capacitor 12, i.e. by f C =1 / (2πRC). Which integrator in the integrator 20 is replaced can be freely selected. Figure 2 As in the sampling filter 7' in Figure 8 It is also feasible to calculate the digital output value in the sampling filter 7" as a weighted sum of the bit stream.

[0050] When using a passive sample-and-hold element 9 ′ or a passive S&H stage 9 ′ and in particular adjusting the decimation filter 7 ″, it is achieved that the variance of the digital output values ​​in the vicinity of FS is significantly improved. Fig. 9 The variance of the digital output value is shown when using a passive sample-and-hold element 9' or a passive S&H stage 9'. The reduced variance in the case of input values ​​in the vicinity of the FS value enables the utilization of the entire input range. Due to the larger available range, an otherwise required oversizing of the IDSM can be avoided. In addition, a better optimization of the analog circuit components with respect to thermal noise and power consumption is possible. In addition, power and circuit area can be saved as well as development time by eliminating the active buffer 13.

Claims

1. A circuit arrangement (10) for an incremental delta-sigma modulator (1), the circuit arrangement (10) comprising at least one incremental delta-sigma modulator (1) and a sampling and holding element (9'), wherein the sampling and holding element (9') is arranged upstream of the incremental delta-sigma modulator (1) and provides an input voltage for the incremental delta-sigma modulator (1) in a charging state, wherein the sampling and holding element (9') has a capacitor (12) for applying the input voltage to the incremental delta-sigma modulator (1), wherein a first switch ( 11), and a second switch (14) is arranged downstream of the capacitor (12), wherein when the second switch (14) is closed, the first switch (11) is opened to provide a reduced input voltage at the incremental delta-sigma modulator (1), or when the first switch (11) is closed, the second switch (14) is opened to charge the capacitor (12) of the sample-and-hold element (9'), wherein the incremental delta-sigma modulator (1) comprises a sampling filter (7, 7', 7"), wherein the weighting of the output bits in the sampling filter (7, 7', 7") can be adjusted due to the reduced input voltage.

2. The circuit arrangement (10) of claim 1, wherein the input voltage whose magnitude is reduced is an attenuated input voltage.

3. The circuit arrangement (10) according to claim 1, wherein the capacitor (12) is configured such that a time constant of the discharge of the capacitor (12) with respect to the sample-and-hold element (9') corresponds to the duration of an AD conversion.

4. The circuit arrangement (10) as claimed in claim 1, wherein the incremental delta-sigma modulator (1) is resettable after each AD conversion.

5. The circuit arrangement (10) as claimed in claim 1, wherein the incremental delta-sigma modulator (1) is an n-th order modulator, wherein n is a natural number.

6. The circuit arrangement (10) as claimed in claim 1, wherein the sample-and-hold element (9') is integrated in the incremental delta-sigma modulator (1) or can be connected externally to the incremental delta-sigma modulator (1).

7. The circuit arrangement (10) as claimed in claim 1, wherein the incremental delta-sigma modulator (1) comprises a decimation filter (7, 7', 7") at its output.

8. The circuit arrangement (10) as claimed in claim 7, wherein the output bit at the end of the AD conversion has a bit value which is increased in weighting compared to the case when a static input voltage is applied to the incremental delta-sigma modulator (1).

9. The circuit arrangement (10) as claimed in claim 7, wherein for adjusting the weighting, the integrator (20) of the decimation filter (7, 7', 7") of the delta-sigma modulator (1) is replaced by a so-called lossy integrator.

10. The circuit arrangement (10) as claimed in claim 9, wherein in the lossy integrator a limit frequency f is defined by a time constant formed by an input resistor R (5) and a capacitor C (12). C =1 / (2πRC).

11. A method for operating a circuit arrangement (10) according to claim 1, the circuit arrangement comprising at least an incremental delta-sigma modulator (1) and a sample-and-hold element (9'), wherein the sample-and-hold element (9') is arranged upstream of the input of the incremental delta-sigma modulator (1), the method comprising the following steps: - Providing an input voltage (U) to the incremental delta-sigma modulator (1) 输入 ); - Use a reduced input voltage (U 输入 ) to ensure the random nature of the output bit stream, where - the capacitor (12) is charged during a reset phase of the delta-sigma modulator (1) and is connected to the delta-sigma modulator (1) during switching, - wherein the weighting of the output bits is adjusted by means of a decimation filter (7, 7', 7").

12. The method according to claim 11, wherein the sample-and-hold element (9') is passive.

13. The method according to claim 11, wherein the input voltage (U 输入 ) is provided by the capacitor (12) of the sample-and-hold element (9').

14. The method according to claim 11, wherein the capacitor (12) of the sample-and-hold element (9') is selected such that the time constant for the discharge of the capacitor (12) of the sample-and-hold element (9') corresponds to the duration of an AD conversion. 15 . The method according to claim 11 , wherein the output bits at the end of the AD conversion are assigned a bit value that is increased in weighting compared to the case of a constant input voltage.

16. The method according to claim 11, wherein for adjusting the weighting, the integrator (20) of the decimation filter (7, 7', 7") is replaced by a so-called lossy integrator (21).

17. The method according to claim 16, wherein the boundary frequency f is defined in the lossy integrator by a time constant formed by an input resistor (5) R and a capacitor (12) C. C =1 / (2πRC).

18. The method of claim 11, wherein the digital output value is calculated as a weighted sum of the output bit streams.

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