A circuit and control method for preventing semiconductor switch device from being turned on by mistake

Abstract

The present invention discloses a circuit and a control method for preventing a semiconductor switch device from being turned on by mistake. The circuit includes: an active clamping circuit, a control circuit, a power amplifier circuit and an interference suppression circuit; the control circuit is coupled to the input end of the power amplifier circuit; the output end of the power amplifier circuit is coupled to the gate of the semiconductor switch device; the first end of the active clamping circuit is connected to the first end of the semiconductor switch device, and the second end is connected to the input end of the power amplifier circuit. The active clamping circuit is configured to act within a preset time period from the moment when the voltage between the first end and the second end of the semiconductor switch device is greater than the preset voltage; the interference suppression circuit includes a controllable switch; the controllable switch is configured to be turned on after the action of the active clamping circuit is completed, so that the potential of the input end of the power amplifier circuit is clamped to a fixed potential. The present invention can effectively prevent the active clamping circuit from causing the switch device to be turned on by mistake due to the increase of the energy injected into the gate of the switch device.

Description

Technical Field

[0001] The present invention relates to a high-power circuit, in particular to a circuit and a control method for preventing a semiconductor switch device from being mistakenly turned on. Background Art

[0002] In high-power applications, the stray inductance of the circuit is unavoidable. When the power device is turned off, the electromotive force induced by the stray inductance is superimposed on the bus voltage, generating a large surge voltage at both ends of the power device. Without any protective measures, it may directly cause overvoltage damage to the power device. Therefore, it is necessary to adopt a corresponding voltage suppression strategy to protect the power device. The voltage suppression strategy mainly includes passive snubber circuits and active clamping circuits. Compared with passive snubber circuits, active clamping circuits have faster response speeds and lower switching losses, and are increasingly widely used in power electronic products.

[0003] At present, the traditional active clamping circuit is Figure 1 As shown, a Zener diode 101 and a Zener diode 102 are usually connected in series with other circuits between the collector 103 and the gate 104 or the gate drive circuit of an IGBT (Insulated Gate Bipolar Transistor). When the collector-emitter voltage exceeds the threshold voltage of the active clamp, the Zener diode 101 and the Zener diode 102 are reversely broken down, and charges are injected into the gate 104 or the gate drive circuit, so that the gate voltage of the IGBT is raised, and the impedance between the collector 103 and the emitter 105 is reduced, so that the charge can be discharged, thereby reducing the voltage between the collector and the emitter, and preventing the IGBT from being damaged by overvoltage.

[0004] Therefore, the purpose of setting up an active clamping circuit is to clamp the collector-emitter voltage of the IGBT to prevent the IGBT from being damaged by overvoltage. However, the signal feedback of the active clamping circuit requires time, that is, there is a certain delay time from the reverse breakdown of the voltage-stabilizing diode to the gate voltage being raised to the turn-on threshold voltage of the IGBT. During this delay time, the voltage between the collector and emitter of the IGBT will continue to rise until the gate voltage reaches above the turn-on threshold voltage. The voltage between the collector and emitter is limited. The fundamental reason is that the control loop lags behind the controlled object. In applications with small voltage margin, fast switching speed or large line stray inductance, the response speed of the traditional active clamping circuit will not meet the requirements of active clamping. It is usually necessary to connect a capacitor in parallel to the voltage-stabilizing diode of the traditional active clamping circuit. Its structure is as follows: Figure 2 As shown, the capacitor 106 connected in parallel to the Zener diode can increase the displacement current, so that the gate voltage reaches above the turn-on threshold voltage before the Zener diode breaks down, so as to achieve the purpose of clamping the voltage between the collector and the emitter in time.

[0005] However, connecting the capacitor 106 in parallel with the Zener diode 101 will introduce greater driving interference. The interference signal is injected into the gate of the IGBT through the active clamping circuit, which increases the energy of the gate of the IGBT and increases the risk of the IGBT being turned on by mistake.

[0006] As can be seen from the above, in situations where the power device switches quickly and has a small voltage margin, it is usually necessary to increase the energy injected into the gate of the IGBT through an active clamping circuit to obtain a better clamping effect, but this will also bring about a larger interference signal. The interference signal will affect the drive signal of the power device through the active clamping circuit, thereby causing the power device to be turned on by mistake, which not only affects the operating safety of the power device itself, but also affects the performance and stability of the entire system.

[0007] Therefore, how to prevent the active clamping circuit from increasing the energy injected into the gate of the power device and causing the power device to be turned on incorrectly is a problem to be solved. Summary of the invention

[0008] In order to solve the above problems, the present invention provides a circuit and a control method for preventing a semiconductor switch device from being turned on by mistake, which can effectively prevent an active clamping circuit from increasing the energy injected into the gate of the semiconductor switch device and causing the semiconductor switch device to be turned on by mistake.

[0009] In order to achieve the above object, the present invention provides a circuit for preventing a semiconductor switch device from being turned on by mistake, comprising: an active clamping circuit, a control circuit, a power amplifier circuit and an interference suppression circuit;

[0010] The control circuit is coupled to an input terminal of the power amplifier circuit;

[0011] The output end of the power amplifier circuit is coupled to the gate of the semiconductor switch device;

[0012] The first end of the active clamp circuit is connected to the first end of the semiconductor switch device, the second end of the active clamp circuit is connected to the input end of the power amplifier circuit, and the active clamp circuit is configured to operate within a preset time period from the moment when the voltage between the first end of the semiconductor switch device and the second end of the semiconductor switch device is greater than a preset voltage;

[0013] The interference suppression circuit includes a controllable switch; a first end of the interference suppression circuit is connected to the control circuit, a second end of the interference suppression circuit is connected to the input end of the power amplifier circuit, and a third end of the interference suppression circuit is connected to a fixed potential point; wherein the controllable switch is configured to be turned on after the action of the active clamping circuit is completed, so that the potential of the input end of the power amplifier circuit is clamped to a fixed potential.

[0014] The above-mentioned circuit for preventing the semiconductor switch device from being turned on by mistake further includes an input resistor and a driving resistor;

[0015] The input resistor is coupled between the control circuit and the input terminal of the power amplifier circuit;

[0016] The driving resistor is coupled between the output terminal of the power amplifier circuit and the gate of the semiconductor switch device.

[0017] In the above-mentioned circuit for preventing a semiconductor switch device from being mistakenly turned on, the controllable switch is configured to be turned off when the control circuit output is a high level or the gate voltage of the semiconductor switch device is greater than a preset gate voltage.

[0018] In the above-mentioned circuit for preventing the semiconductor switching device from being mistakenly turned on, the controllable switch is configured to be turned on when the action of the active clamping circuit is completed and the gate voltage of the semiconductor switching device is a preset gate voltage, and the preset gate voltage is less than the gate voltage threshold of the semiconductor switching device.

[0019] In the above-mentioned circuit for preventing a semiconductor switch device from being mistakenly turned on, the controllable switch is configured to be turned off within the preset time period during which the active clamping circuit is in operation.

[0020] In the above-mentioned circuit for preventing a semiconductor switch device from being turned on by mistake, the fourth terminal of the interference suppression circuit is coupled to the gate of the semiconductor switch device to receive the gate voltage of the semiconductor switch device.

[0021] In the above-mentioned circuit for preventing a semiconductor switch device from being turned on by mistake, the interference suppression circuit further includes a first diode, a second diode, a third diode, a first resistor and a first capacitor;

[0022] An anode of the first diode is coupled to a first end of the interference suppression circuit, and a cathode of the first diode is coupled to a gate of the controllable switch;

[0023] An anode of the second diode is coupled to the second end of the interference suppression circuit, and a cathode of the second diode is coupled to the first end of the controllable switch;

[0024] The first capacitor is coupled between the first end of the controllable switch and the gate of the controllable switch;

[0025] The first resistor and the third diode are connected in series and coupled between the gate of the controllable switch and the fourth end of the interference suppression circuit;

[0026] The second terminal of the controllable switch is coupled to a fixed potential point of the third terminal of the interference suppression circuit.

[0027] In the above-mentioned circuit for preventing a semiconductor switch device from being mistakenly turned on, the first capacitor is a parasitic capacitor between the first end of the controllable switch and the gate of the controllable switch.

[0028] In the above-mentioned circuit for preventing a semiconductor switching device from being mistakenly turned on, the gate of the controllable switch is connected to the first end of the interference suppression circuit, the first end of the controllable switch is connected to the second end of the interference suppression circuit, and the second end of the controllable switch is coupled to the third end of the interference suppression circuit; the control circuit is used to control the conduction or shutdown of the controllable switch according to the gate voltage of the semiconductor switching device and the control signal output by the control circuit.

[0029] In the above-mentioned circuit for preventing a semiconductor switch device from being turned on by mistake, the interference suppression circuit comprises a fourth diode, a fifth diode, a sixth diode, a second resistor and a second capacitor;

[0030] An anode of the fourth diode is coupled to the first end of the interference suppression circuit, and a cathode of the fourth diode is coupled to the gate of the controllable switch;

[0031] An anode of the fifth diode is coupled to the second end of the interference suppression circuit, and a cathode of the fifth diode is coupled to the first end of the controllable switch;

[0032] The sixth diode is connected in series with the second resistor and is coupled between the gate of the controllable switch and the anode of the fourth diode;

[0033] The second capacitor is coupled between the first end of the controllable switch and the gate of the controllable switch;

[0034] The second terminal of the controllable switch is coupled to the third terminal of the interference suppression circuit.

[0035] In the above-mentioned circuit for preventing a semiconductor switch device from being mistakenly turned on, the fixed potential is smaller than a gate voltage threshold of the semiconductor switch device.

[0036] In the above-mentioned circuit for preventing semiconductor switching devices from being mistakenly turned on, the controllable switch is a PNP-type transistor; the first end of the controllable switch is the emitter of the PNP-type transistor, and the second end of the controllable switch is the collector of the PNP-type transistor.

[0037] In the above-mentioned circuit for preventing a semiconductor switch device from being turned on by mistake, the active clamping circuit comprises:

[0038] a seventh diode, a plurality of voltage regulator tubes, at least one third capacitor and a fourth resistor;

[0039] The multiple Zener diodes, the seventh diode and the fourth resistor are connected in series to form a series connection and then connected between the first end of the semiconductor switching device and the input end of the power amplifier circuit; wherein the multiple Zener diodes are in the same direction and opposite to the direction of the seventh diode, and at least one of the multiple Zener diodes is connected in parallel with at least one of the third capacitors.

[0040] In order to better achieve the purpose of the invention, the present invention also provides a control method for preventing a semiconductor switch from being turned on by mistake, the control method is used in a circuit for preventing a semiconductor switch device from being turned on by mistake; the circuit for preventing a semiconductor switch device from being turned on by mistake comprises an active clamping circuit, a control circuit, a power amplifier circuit and an interference suppression circuit; the control circuit is coupled to the input end of the power amplifier circuit; the output end of the power amplifier circuit is coupled to the gate of the semiconductor switch device; the first end of the active clamping circuit is connected to the first end of the semiconductor switch device, and the second end of the active clamping circuit is connected to the input end of the power amplifier circuit; the interference suppression circuit comprises a controllable switch; the first end of the interference suppression circuit is connected to the control circuit, the second end of the interference suppression circuit is connected to the input end of the power amplifier circuit, and the third end of the interference suppression circuit is connected to a fixed potential point; the control method comprises:

[0041] Step a, determining a preset time period for the active clamping circuit to operate according to a voltage between the first end of the semiconductor switch device and the second end of the semiconductor switch device;

[0042] Step b: after the active clamping circuit completes its operation, turning on the controllable switch so that the potential at the input end of the power amplifier circuit is clamped to a fixed potential.

[0043] In the above control method for preventing a semiconductor switch from being turned on by mistake, the fixed potential is smaller than a gate voltage threshold of the semiconductor switch device.

[0044] In the above control method for preventing a semiconductor switch from being turned on by mistake, when the control circuit output is a high level or the gate voltage of the semiconductor switch device is greater than a preset gate voltage, the controllable switch is turned off.

[0045] In the above control method for preventing the semiconductor switch from being turned on by mistake, when the active clamping circuit is completed and the gate voltage of the semiconductor switch device is a preset gate voltage, the controllable switch is turned on.

[0046] In the above control method for preventing a semiconductor switch from being turned on by mistake, the controllable switch is turned off within the preset time period during which the active clamping circuit is in operation.

[0047] In the above-mentioned control method for preventing the semiconductor switch from being mistakenly turned on, the active clamping circuit starts to act when the voltage at the first end and the second end of the semiconductor switch device is greater than a preset voltage; the active clamping circuit completes its action when the gate voltage of the semiconductor switch device reaches a preset gate voltage.

[0048] By adopting the present invention, an interference suppression circuit is provided so that after the active clamping circuit completes voltage clamping, the potential of the input end of the power amplifier circuit is clamped to a fixed potential, thereby blocking the propagation path of the interference signal and effectively preventing the semiconductor switch device from being mis-conducted.

[0049] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a schematic diagram of a traditional active clamping circuit;

[0051] Figure 2 It is a schematic diagram of a displacement current feedback type active clamping circuit;

[0052] Figure 3 A schematic diagram of a first implementation of a circuit for preventing a semiconductor switch device from being turned on by mistake according to the present invention;

[0053] Figure 4 for Figure 3 Control timing diagram of

[0054] Figure 5 A schematic diagram of a second implementation of a circuit for preventing a semiconductor switch device from being turned on by mistake according to the present invention;

[0055] Figure 6 for Figure 5 Control timing diagram of

[0056] Figure 7 is a schematic diagram of an interference suppression circuit according to an embodiment of the present invention;

[0057] Figure 8 A schematic diagram of a third implementation of a circuit for preventing a semiconductor switch device from being turned on by mistake according to the present invention;

[0058] Fig. 9 is a schematic diagram of an interference suppression circuit according to an embodiment of the present invention;

[0059] Fig.10 The figure is a flowchart of the steps of the method of the present invention. DETAILED DESCRIPTION

[0060] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments to further understand the purpose, solution and effect of the present invention, but it is not intended to limit the scope of protection of the claims attached to the present invention.

[0061] Figure 3 FIG. 1 is a schematic diagram of a first implementation of a circuit for preventing a semiconductor switch device from being turned on by mistake according to the present invention; Figure 3 As shown, an embodiment of the present invention provides a circuit for preventing a semiconductor switch device from being turned on by mistake, comprising: an active clamping circuit 31, a control circuit 32, a power amplifier circuit 33 and an interference suppression circuit 34. The control circuit 32 is coupled to an input end of the power amplifier circuit 33;

[0062] The output end of the power amplifier circuit 33 is coupled to the gate 351 of the semiconductor switch device;

[0063] The first end of the active clamp circuit 31 is connected to the first end 352 of the semiconductor switch device, and the second end of the active clamp circuit 31 is connected to the input end of the power amplifier circuit 33. The active clamp circuit 31 is configured to operate within a preset time period from the moment when the voltage between the first end 352 of the semiconductor switch device and the second end 353 of the semiconductor switch device is greater than a preset voltage;

[0064] The interference suppression circuit 34 includes a controllable switch 341; a first end 342 of the interference suppression circuit 34 is connected to the control circuit 32, a second end 343 of the interference suppression circuit 34 is connected to the input end of the power amplifier circuit 33, and a third end 344 of the interference suppression circuit 34 is connected to a fixed potential point 36; wherein the controllable switch 341 is configured to be turned on after the action of the active clamping circuit 31 is completed, so that the potential of the input end of the power amplifier circuit 33 is clamped to a fixed potential.

[0065] It can be seen that after the action of the active clamping circuit 31 is completed, that is, after the active clamping circuit 31 completes the voltage clamping, the potential of the input end of the power amplifier circuit 33 is clamped to a fixed potential by controlling the controllable switch of the interference suppression circuit 34 to be turned on, thereby limiting the potential of the gate 351 of the semiconductor switching device, so that the active clamping circuit 31 is disabled after the semiconductor switching device is completely turned off, thereby blocking the propagation path of the interference signal, and solving the problem of incorrect opening of the semiconductor switching device without affecting the logical opening of the power amplifier circuit 33 and the normal function of the active clamping circuit 31.

[0066] like Figure 3As shown, the circuit for preventing the semiconductor switching device from being mistakenly turned on of the present invention includes an input resistor 37 and a driving resistor 38; the input resistor 37 is coupled between the control circuit 32 and the input end of the power amplifier circuit 33; the driving resistor 38 is coupled between the output end of the power amplifier circuit 33 and the gate 351 of the semiconductor switching device.

[0067] like Figure 3 As shown, the interference suppression circuit 34 also includes a delay module 345, which is coupled to the first end 342 of the interference suppression circuit 34 and the controllable switch 341 respectively, and is used to receive the control signal output by the control circuit 32, which can be a pulse width modulation signal (Pulse Width Modulation, PWM), and delay a preset delay time to control the controllable switch 341 to be turned on, so that the potential of the input end of the power amplifier circuit 33 is clamped to a fixed potential, thereby blocking the propagation path of the interference signal, and solving the problem of incorrect turning on of the semiconductor switch device without affecting the logical turning on of the semiconductor switch device and the normal function of the active clamping circuit 31.

[0068] Figure 4 for Figure 3 Control timing diagram. Figure 4 In FIG. 1 , the vertical axis represents voltage, the horizontal axis represents time t, PWM represents the control signal of the control circuit 32, and the Vge line represents the gate voltage of the semiconductor switch device. Figure 4As shown, in stage 1: the PWM signal output by the control circuit 32 is at a high level, and the controllable switch 341 of the interference suppression circuit 34 is in an off state according to the high level, at which time the semiconductor switch device is turned on and is in a normal working state. Stage 2: the PWM signal output by the control circuit 32 is at a low level, and the delay module 345 is activated; when the voltage between the first terminal 352 and the second terminal 353 of the semiconductor switch device is greater than the preset voltage, the active clamping circuit 31 is activated, and at this time, the charge flowing out of the first terminal 352 of the semiconductor switch device is injected into the gate 351 of the semiconductor switch device through the active clamping circuit 31, raising the gate voltage of the gate 351 of the semiconductor switch device, so that the gate voltage is greater than the preset gate voltage, and the semiconductor switch device is delayed to turn off, thereby limiting the voltage spike between the first terminal 352 and the second terminal 353 of the semiconductor switch device, so that the semiconductor switch device is not damaged. The preset time period of the action of the active clamping circuit 31 is from the moment when the voltage between the first terminal 352 and the second terminal 353 of the semiconductor switch device is greater than the preset voltage to the moment when the action of the active clamping circuit 31 is completed. Phase 3: The action of the active clamping circuit 31 is completed, the PWM signal output by the control circuit 32 is still at a low level and the action of the delay module 345 is completed. At this time, the gate voltage of the semiconductor switch device is the preset gate voltage, wherein the preset gate voltage can be less than the gate voltage threshold of the semiconductor switch device, the controllable switch 341 is turned on, and the potential of the input terminal of the power amplifier circuit 33 is clamped to a fixed potential to block the interference signal from affecting the shutdown of the semiconductor switch device through the active clamping circuit, and ensure the reliable shutdown of the semiconductor switch device, wherein the fixed potential can be lower than the gate voltage threshold of the semiconductor switch device, for example, when the gate voltage threshold is 6v, the fixed potential is less than 6v, and can be any voltage value between 0v and -20v. It should be noted that the preset delay time of the delay module 345 is the time period of the above-mentioned stage 2, that is, the preset delay time is from the moment when the PWM signal changes from a high level to a low level to the moment when the active clamping circuit completes the action.

[0069] However, in this solution, the preset delay time needs to be designed based on the action time of the active clamp circuit under the worst working conditions. Since the action time of the active clamp circuit under different working conditions can differ by several microseconds, and the component accuracy and temperature drift issues must be considered at the same time, the preset delay time is much longer than the action time of the active clamp circuit, so that the interference suppression circuit cannot be put into operation immediately after the action of the active clamp circuit is completed. This solution is not only complex in design, but also brings about a protection blind spot and reduces reliability. Further improvement is needed.

[0070] Fig. 9 FIG. 1 is a schematic diagram of an embodiment of an interference suppression circuit of the present invention. Fig. 9As shown, the interference suppression circuit 94 includes a fourth diode 901, a fifth diode 902, a sixth diode 903, a second resistor 904, a third resistor 906 and a second capacitor 905. The anode of the fourth diode 901 is coupled to the first end of the interference suppression circuit 94, and the cathode of the fourth diode 901 is coupled to the gate of the controllable switch 941. The anode of the fifth diode 902 is coupled to the second end of the interference suppression circuit 94, and the cathode of the fifth diode 902 is coupled to the first end of the controllable switch 941. The sixth diode 903 is connected in series with the second resistor 904 and coupled between the gate of the controllable switch 941 and the anode of the fourth diode 901. The second capacitor 905 is coupled between the first end of the controllable switch 941 and the gate of the controllable switch 941. The third resistor 906 is connected between the cathode of the fifth diode 902 and the cathode of the fourth diode 901. The second end of the controllable switch 941 is coupled to the third end of the interference suppression circuit 94 , and the third end of the interference suppression circuit 94 is connected to the fixed potential point 96 .

[0071] like Fig. 9 As shown, when the PWM signal is at a high level, the fourth diode 901 is turned on, and the gate potential of the controllable switch 941 is pulled up, so that the controllable switch 941 is turned off, and the PWM signal is amplified by the power amplifier circuit 93 to drive the semiconductor switch device to turn on. When the PWM signal is at a low level, if the voltage between the first end and the second end of the semiconductor switch device is greater than the preset voltage, the active clamping circuit is activated, the fifth diode 902 and the sixth diode 903 are turned on, and the second capacitor 905 is discharged through the second resistor 904. At this time, the controllable switch 941 is in the off state, and the current flows into the gate of the semiconductor switch device, so that the gate voltage of the semiconductor switch device is raised, and the semiconductor switch device is turned on. After the active clamping circuit is completed and the PWM signal is still at a low level, if an interference signal is injected into the second capacitor 905 through the active clamping circuit, the second capacitor 905 is reversely charged, so that the gate voltage of the controllable switch 941 reaches its gate turn-on threshold, and the controllable switch 941 is turned on. At this time, the potential of the input end of the power amplifier circuit 93 is clamped to a fixed potential.

[0072] In the embodiment of the present invention, the second resistor 904 and the second capacitor 905 constitute a delay module. When the PWM signal is at a low level, the delay module generates a preset delay time to ensure that the controllable switch 941 is turned on after the active clamping circuit is completed.

[0073] In the embodiment of the present invention, the fixed potential is less than the gate voltage threshold of the semiconductor switch device, so that the potential of the input end of the power amplifier circuit 93 is clamped to the fixed potential, which can prevent the semiconductor switch device from being mis-turned on.

[0074] like Fig. 9 As shown, in one embodiment of the present invention, the controllable switch 941 is a PNP type transistor; the first end of the controllable switch 941 is the emitter of the PNP type transistor, and the second end of the controllable switch 941 is the collector of the PNP type transistor.

[0075] Figure 5 FIG. 2 is a schematic diagram of a second implementation of a circuit for preventing a semiconductor switch device from being turned on by mistake according to the present invention. Figure 5 As shown, an embodiment of the present invention provides a circuit for preventing a semiconductor switch device from being turned on by mistake, comprising: an active clamping circuit 51, a control circuit 52, a power amplifier circuit 53 and an interference suppression circuit 54. The control circuit 52 is coupled to the input end of the power amplifier circuit 53;

[0076] The output end of the power amplifier circuit 53 is coupled to the gate 551 of the semiconductor switch device;

[0077] The first end of the active clamp circuit 51 is connected to the first end 552 of the semiconductor switch device, and the second end of the active clamp circuit 51 is connected to the input end of the power amplifier circuit 53. The active clamp circuit 51 is configured to operate within a preset time period from the moment when the voltage between the first end 552 of the semiconductor switch device and the second end 553 of the semiconductor switch device is greater than a preset voltage;

[0078] The interference suppression circuit 54 includes a controllable switch 541; a first end 542 of the interference suppression circuit 54 is connected to the control circuit 52, a second end 543 of the interference suppression circuit 54 is connected to the input end of the power amplifier circuit 53, a third end 544 of the interference suppression circuit 54 is connected to the fixed potential point 56, and a fourth end 545 of the interference suppression circuit 54 is connected to the gate 551 of the semiconductor switching device; wherein the controllable switch 541 is configured to be turned on after the action of the active clamping circuit 51 is completed, that is, the gate voltage of the semiconductor switching device is a preset gate voltage, and the controllable switch 541 is turned on, so that the potential of the input end of the power amplifier circuit 53 is clamped to a fixed potential.

[0079] Figure 6 for Figure 5 Control timing diagram. Figure 6 In FIG. 5 , the vertical axis represents voltage, the horizontal axis represents time t, PWM represents the control signal of the control circuit 52, and the Vge line represents the gate voltage of the semiconductor switch device. Figure 6As shown, stage 1: the PWM signal output by the control circuit 52 is at a high level, and the controllable switch 541 is in the off state according to the high level. Stage 2: the PWM signal output by the control circuit 52 is at a low level; when the voltage between the first terminal 552 and the second terminal 553 of the semiconductor switch device is greater than the preset voltage, the active clamping circuit 51 is activated, and the gate voltage of the semiconductor switch device is greater than the preset gate voltage, and the controllable switch 541 is in the off state. Stage 3: the action of the active clamping circuit 51 is completed, and the PWM signal output by the control circuit 52 is still at a low level, and the gate voltage of the semiconductor switch device is the preset gate voltage. The controllable switch 541 is turned on according to the preset gate voltage, and the potential of the input end of the power amplifier circuit 53 is clamped to a fixed potential, wherein the preset gate voltage is less than the gate voltage threshold of the semiconductor switch device. The turn-on time of the controllable switch of this scheme can be automatically adjusted according to the length of the action time of the active clamping circuit, and the delay time is close to zero, which greatly reduces the protection blind area and improves the reliability.

[0080] Figure 7 FIG. 1 is an embodiment of the interference suppression circuit of the present invention. Figure 7 As shown, an embodiment of the present invention provides a circuit for preventing a semiconductor switch device from being turned on by mistake, comprising: an active clamping circuit 71, a control circuit 72, a power amplifier circuit 73 and an interference suppression circuit 74;

[0081] The control circuit 72 is coupled to the input end of the power amplifier circuit 73;

[0082] The output end of the power amplifier circuit 73 is coupled to the gate 753 of the semiconductor switch device;

[0083] The first end of the active clamp circuit 71 is connected to the first end 751 of the semiconductor switch device, and the second end of the active clamp circuit 71 is connected to the input end B of the power amplifier circuit 73. The active clamp circuit 71 is configured to operate within a preset time period from the moment when the voltage between the first end 751 of the semiconductor switch device and the second end 752 of the semiconductor switch device is greater than a preset voltage;

[0084] The interference suppression circuit 74 includes a controllable switch 741; a first end A of the interference suppression circuit 74 is connected to the control circuit 72, a second end of the interference suppression circuit is connected to an input end B of the power amplifier circuit 73, a third end of the interference suppression circuit 74 is connected to a fixed potential point 742, and a fourth end of the interference suppression circuit 74 is connected to a gate 753 of a semiconductor switching device; wherein the controllable switch 741 is configured to be turned on after the action of the active clamping circuit 71 is completed, so that the potential of the input end B of the power amplifier circuit 73 is clamped to a fixed potential.

[0085] It can be seen that in the embodiment of the present invention, by providing an interference suppression circuit 74, the potential of the input terminal B of the power amplifier circuit 73 is clamped to a fixed potential after the active clamping circuit 71 is completed, thereby limiting the potential of the gate 753 of the semiconductor switching device, which can effectively prevent the semiconductor switching device from being mis-turned on.

[0086] refer to Figure 7 As shown, in another embodiment of the present invention, an input resistor 76 and a driving resistor 77 are also included;

[0087] The input resistor 76 is coupled between the control circuit 72 and the input terminal B of the power amplifier circuit 73;

[0088] The driving resistor 77 is coupled between the output terminal of the power amplifier circuit 73 and the gate 753 of the semiconductor switch device.

[0089] Combination Figure 6 and Figure 7 , the controllable switch 741 is configured to be turned off when the output of the control circuit 72 is high (stage 1) or the gate voltage of the semiconductor switch device is greater than the preset gate voltage (stage 2). Therefore, in stages 1 and 2, the controllable switch 741 is disconnected, and the interference suppression circuit is not put into use;

[0090] Combination Figure 6 and Figure 7 In another embodiment of the present invention, the controllable switch 741 is configured to be turned on when the active clamping circuit 71 is completed and the gate voltage of the semiconductor switch device is a preset gate voltage (stage 3), and the preset gate voltage is less than the gate voltage threshold of the semiconductor switch device. It can be seen that stage 3 is the non-working time period of the active clamping circuit 71. At this time, it is necessary to prevent the semiconductor switch device from being turned on by mistake. The controllable switch 741 is turned on, the interference suppression circuit is put into use, and the voltage of the input terminal B is clamped to a fixed potential, which effectively prevents the semiconductor switch device from being turned on by mistake.

[0091] refer to Figure 7 As shown, in another embodiment of the present invention, a circuit for preventing a semiconductor switch device from being turned on by mistake, the fourth terminal of the interference suppression circuit 74 is coupled to the gate of the semiconductor switch device at point C to receive the gate voltage. Figure 6 Determination of stage 2.

[0092] refer to Figure 7 As shown, in another embodiment of the present invention, the interference suppression circuit 74 further includes a first diode 747, a second diode 743, a third diode 744, a first resistor 745 and a first capacitor 746;

[0093] An anode of the first diode 747 is coupled to a first end of the interference suppression circuit 74, and a cathode of the first diode 747 is coupled to a gate of the controllable switch 741;

[0094] An anode of the second diode 743 is coupled to the second end of the interference suppression circuit 74, and a cathode of the second diode 743 is coupled to the first end of the controllable switch 741;

[0095] The first capacitor 746 is coupled between the first end of the controllable switch 741 and the gate of the controllable switch 741;

[0096] The first resistor 745 and the third diode 744 are connected in series and coupled between the gate of the controllable switch and the fourth end of the interference suppression circuit 74;

[0097] The second end of the controllable switch 741 is coupled to the third end of the interference suppression circuit 74 , and the third end of the interference suppression circuit 74 is connected to the fixed potential point 742 .

[0098] In another embodiment of the present invention, the first capacitor 746 is a parasitic capacitor between the first end of the controllable switch 741 and the gate of the controllable switch.

[0099] like Figure 7 As shown, in one embodiment of the present invention, the controllable switch 741 is a PNP type transistor; the first end of the controllable switch 741 is the emitter of the PNP type transistor, and the second end of the controllable switch 741 is the collector of the PNP type transistor.

[0100] refer to Figure 7 As shown, in one embodiment of the present invention, the active clamping circuit 71 includes:

[0101] A seventh diode 711, a plurality of voltage regulator tubes 712, at least one third capacitor 713 and a fourth resistor 714;

[0102] The multiple Zener diodes 712, the seventh diode 711 and the fourth resistor 714 are connected in series to form a series connection and then connected between the first end 751 of the semiconductor switch device and the input end of the power amplifier circuit 73; wherein the multiple Zener diodes 712 are in the same direction and opposite to the direction of the seventh diode 711, and at least one of the multiple Zener diodes 712 is connected in parallel with at least one of the third capacitors 713.

[0103] like Figure 7As shown in FIG. 1 , when the controllable switch 741 is turned on, the potential of the input terminal B of the power amplifier circuit 73 is clamped to a lower fixed potential, and the transmission path of the feedback energy from the active clamp circuit 71 to the gate electrode is blocked. When the controllable switch 741 is turned off, the transmission path of the feedback energy from the active clamp circuit 71 to the gate electrode will be reopened. The control timing of the circuit is shown in FIG. Figure 6 As shown, in stage 1, the PWM signal is at a high level. At this time, the potential at point A is higher than the potential at point B, so that the base-emitter of the controllable switch 741 is reverse biased and turned off; in stage 2, during the operation of the active clamping circuit, the potential at point B is lower than the potential of the gate 753 of the semiconductor switch device, and the base-emitter of the controllable switch 741 is reverse biased and turned off; in stage 3, the active clamping circuit is completed, and the potentials of the base and gate of the controllable switch 741 are at a low level. At this time, interference energy is injected through the active clamping circuit, so that the potential at point B will increase instantly, so that the base-emitter of the controllable switch 741 is forward biased and turned on, thereby injecting interference energy into the fixed potential to avoid the IGBT (semiconductor switch device) from being turned on by mistake.

[0104] Figure 8 It is a schematic diagram of the third implementation method of the circuit for preventing the semiconductor switching device from being turned on by mistake of the present invention. The circuit includes a fully controlled switch Q, the gate of which is connected to the first end of the interference suppression circuit 84, the first end of which is connected to the second end of the interference suppression circuit 84 (at point B in the figure), and the second end of which is coupled to the third end of the interference suppression circuit 84 (at the fixed potential point 86); the control circuit 82 is used to control the conduction or shutdown of the fully controlled switch Q according to the working state of the active clamping circuit and the control signal output by the control circuit 82. During the IGBT turn-on and active clamping circuit action stage, the control circuit 82 turns off the fully controlled switch Q; after the active clamping circuit action is completed, the fully controlled switch Q is turned on to pull the potential of point B at the input end of the power amplifier circuit 83 to a low potential. Its control timing is as follows: Figure 6 As shown in the figure, the specific control process is as follows: when the controller sends a PWM signal of high level, it sends a shutdown signal to the fully controlled switch Q; when the controller determines that the active clamping circuit action phase is over, the controller turns on the fully controlled switch Q and disables the active clamping circuit. The judgment signal for the end of the active clamping phase can be the gate voltage of the IGBT or other signals. If the gate voltage of the semiconductor switch device is used as the turn-on signal of the fully controlled switch Q, the following design can be made: when the gate voltage of the semiconductor switch device is less than the voltage b, the fully controlled switch Q is turned on. The setting of the b value should avoid affecting the function of the active clamping. The lower the b value, the smaller the impact on the voltage clamping.

[0105] Fig.10 is a flowchart of the steps of the method in the present invention, refer to Figure 3 and Fig.10As shown, an embodiment of the present invention further provides a control method for preventing a semiconductor switch from being turned on by mistake, and the control method is used in a circuit for preventing a semiconductor switch device from being turned on by mistake; the circuit for preventing a semiconductor switch device from being turned on by mistake comprises an active clamping circuit 31, a control circuit 32, a power amplifier circuit 33 and an interference suppression circuit 34; the control circuit 32 is coupled to the input end of the power amplifier circuit 33; the output end of the power amplifier circuit 33 is coupled to the gate 351 of the semiconductor switch device; the first end of the active clamping circuit 31 is connected to the first end 352 of the semiconductor switch device, and the second end of the active clamping circuit 31 is connected to the input end of the power amplifier circuit 33; the interference suppression circuit 34 comprises a controllable switch 341; the first end of the interference suppression circuit 34 is connected to the control circuit 32, the second end of the interference suppression circuit 34 is connected to the input end of the power amplifier circuit 33, and the third end of the interference suppression circuit 34 is connected to a fixed potential point 36; the control method comprises:

[0106] Step 210: determining a preset time period for the active clamping circuit to operate according to a voltage between the first terminal of the semiconductor switch device and the second terminal of the semiconductor switch device;

[0107] Step 220: After the active clamping circuit completes its operation, the controllable switch is turned on so that the potential at the input end of the power amplifier circuit is clamped to a fixed potential.

[0108] In a method embodiment of the present invention, when the PWM signal output by the control circuit 32 is at a high level, the semiconductor switch device is driven to turn on and off the controllable switch. When the PWM signal output by the control circuit 32 is converted from a high level to a low level and the voltage between the first end of the semiconductor switch device and the second end of the semiconductor switch device is greater than a preset voltage, the active clamping circuit starts to operate.

[0109] It can be seen that in the embodiment of the method of the present invention, during the time period when the PWM signal output by the control circuit is at a low level and the active clamping circuit is not working, potential clamping is performed by the interference suppression circuit to prevent the gate voltage of the semiconductor switching device from exceeding the gate voltage threshold, thereby preventing mis-conduction.

[0110] In one method embodiment of the present invention, the fixed potential is less than a gate voltage threshold of the semiconductor switch device.

[0111] In a method embodiment of the present invention, when the control circuit output is a high level or the gate voltage of the semiconductor switch device is greater than a preset gate voltage, the controllable switch is turned off.

[0112] In a method embodiment of the present invention, when the active clamping circuit is completed and the gate voltage of the semiconductor switch device is a preset gate voltage, the controllable switch is turned on.

[0113] In a method embodiment of the present invention, the controllable switch is turned off within the preset time period when the active clamping circuit is in operation.

[0114] In a method embodiment of the present invention, the active clamping circuit starts to operate when the voltage at the first and second terminals of the semiconductor switching device is greater than a preset gate voltage; the active clamping circuit completes its operation when the gate voltage of the semiconductor switching device reaches the preset gate voltage.

[0115] As can be seen from the above, the embodiments of the present invention have the following advantages:

[0116] 1. The present invention is not only applicable to semiconductor switch devices, but also to applications with small voltage margin and fast switching speed, and can effectively solve the gate drive interference problem of semiconductor switch devices.

[0117] 2. The present invention has a wide range of applications, and the anti-interference circuit can be used in combination with various active clamping circuits.

[0118] 3. The parameter design of the anti-mis-opening circuit embodiment in the present invention is simple, and there is no need to design delay parameters according to the length of the active clamping circuit action time.

[0119] 4. The present invention has high reliability. The circuit minimizes the delay time and greatly reduces the protection blind area.

[0120] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A circuit for preventing a semiconductor switch device from being turned on by mistake. It is characterized in that include: Active clamping circuit, control circuit, power amplifier circuit and interference suppression circuit; The control circuit is coupled to an input terminal of the power amplifier circuit; The output end of the power amplifier circuit is coupled to the gate of the semiconductor switch device; The first end of the active clamping circuit is connected to the first end of the semiconductor switch device, the second end of the active clamping circuit is connected to the input end of the power amplifier circuit, and the active clamping circuit is configured to perform a voltage clamping action within a preset time period starting from the moment when the voltage between the first end of the semiconductor switch device and the second end of the semiconductor switch device is greater than a preset voltage; The interference suppression circuit includes a controllable switch; a first end of the interference suppression circuit is connected to the control circuit, a second end of the interference suppression circuit is connected to the input end of the power amplifier circuit, and a third end of the interference suppression circuit is connected to a fixed potential point; wherein the controllable switch is configured to be turned on after the action of the active clamping circuit is completed, so that the potential of the input end of the power amplifier circuit is clamped to a fixed potential.

2. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 1, It is characterized in that It also includes input resistance and driving resistance; The input resistor is coupled between the control circuit and the input terminal of the power amplifier circuit; The driving resistor is coupled between the output terminal of the power amplifier circuit and the gate of the semiconductor switch device.

3. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 1, It is characterized in that The controllable switch is configured to be turned off when the control circuit output is at a high level or the gate voltage of the semiconductor switch device is greater than a preset gate voltage.

4. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 1, It is characterized in that The controllable switch is configured to be turned on when the active clamping circuit is completed and the gate voltage of the semiconductor switch device is a preset gate voltage, and the preset gate voltage is less than the gate voltage threshold of the semiconductor switch device.

5. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 1, It is characterized in that The controllable switch is configured to be turned off within the preset time period when the active clamping circuit is in operation.

6. A circuit for preventing a semiconductor switch device from being turned on by mistake according to any one of claims 1 to 5, It is characterized in that The fourth terminal of the interference suppression circuit is coupled to the gate of the semiconductor switch device to receive the gate voltage of the semiconductor switch device.

7. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 6, It is characterized in that The interference suppression circuit also includes a first diode, a second diode, a third diode, a first resistor and a first capacitor; An anode of the first diode is coupled to a first end of the interference suppression circuit, and a cathode of the first diode is coupled to a gate of the controllable switch; An anode of the second diode is coupled to the second end of the interference suppression circuit, and a cathode of the second diode is coupled to the first end of the controllable switch; The first capacitor is coupled between the first end of the controllable switch and the gate of the controllable switch; The first resistor and the third diode are connected in series and coupled between the gate of the controllable switch and the fourth end of the interference suppression circuit; The second terminal of the controllable switch is coupled to a fixed potential point of the third terminal of the interference suppression circuit.

8. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 7, It is characterized in that The first capacitor is a parasitic capacitor between the first end of the controllable switch and the gate of the controllable switch.

9. A circuit for preventing a semiconductor switch device from being turned on by mistake according to any one of claims 1 to 5 It is characterized in that The gate of the controllable switch is connected to the first end of the interference suppression circuit, the first end of the controllable switch is connected to the second end of the interference suppression circuit, and the second end of the controllable switch is coupled to the third end of the interference suppression circuit; The control circuit is used to control the on or off of the controllable switch according to the gate voltage of the semiconductor switch device and the control signal output by the control circuit.

10. The circuit for preventing a semiconductor switch device from being turned on by mistake according to any one of claims 1 to 5, It is characterized in that The interference suppression circuit includes a fourth diode, a fifth diode, a sixth diode, a second resistor and a second capacitor; An anode of the fourth diode is coupled to the first end of the interference suppression circuit, and a cathode of the fourth diode is coupled to the gate of the controllable switch; An anode of the fifth diode is coupled to the second end of the interference suppression circuit, and a cathode of the fifth diode is coupled to the first end of the controllable switch; The sixth diode is connected in series with the second resistor and is coupled between the gate of the controllable switch and the anode of the fourth diode; The second capacitor is coupled between the first end of the controllable switch and the gate of the controllable switch; The second terminal of the controllable switch is coupled to the third terminal of the interference suppression circuit.

11. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 1, It is characterized in that The fixed potential is less than a gate voltage threshold of the semiconductor switch device.

12. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 7, It is characterized in that The controllable switch is a PNP transistor; the first end of the controllable switch is the emitter of the PNP transistor, and the second end of the controllable switch is the collector of the PNP transistor.

13. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 10, It is characterized in that The controllable switch is a PNP transistor; the first end of the controllable switch is the emitter of the PNP transistor, and the second end of the controllable switch is the collector of the PNP transistor.

14. The circuit for preventing a semiconductor switch device from being turned on by mistake according to claim 1, It is characterized in that The active clamping circuit comprises: a seventh diode, a plurality of voltage regulator tubes, at least one third capacitor and a fourth resistor; The multiple Zener diodes, the seventh diode and the fourth resistor are connected in series to form a series connection and then connected between the first end of the semiconductor switching device and the input end of the power amplifier circuit; wherein the multiple Zener diodes are in the same direction and opposite to the direction of the seventh diode, and at least one of the multiple Zener diodes is connected in parallel with at least one of the third capacitors.

15. A control method for preventing a semiconductor switch from being turned on by mistake. It is characterized in that The control method is used in a circuit for preventing a semiconductor switch device from being mis-turned on; the circuit for preventing a semiconductor switch device from being mis-turned on comprises an active clamping circuit, a control circuit, a power amplifier circuit and an interference suppression circuit; the control circuit is coupled to an input end of the power amplifier circuit; the output end of the power amplifier circuit is coupled to a gate of the semiconductor switch device; a first end of the active clamping circuit is connected to a first end of the semiconductor switch device, and a second end of the active clamping circuit is connected to an input end of the power amplifier circuit; the interference suppression circuit comprises a controllable switch; a first end of the interference suppression circuit is connected to the control circuit, a second end of the interference suppression circuit is connected to an input end of the power amplifier circuit, and a third end of the interference suppression circuit is connected to a fixed potential point; the control method comprises: Step a, determining a preset time period for the active clamping circuit to perform a voltage clamping action according to a voltage between the first end of the semiconductor switch device and the second end of the semiconductor switch device; Step b: after the active clamping circuit completes its operation, turning on the controllable switch so that the potential at the input end of the power amplifier circuit is clamped to a fixed potential.

16. The control method for preventing a semiconductor switch from being turned on by mistake according to claim 15, It is characterized in that The fixed potential is less than a gate voltage threshold of the semiconductor switch device.

17. The control method for preventing a semiconductor switch from being turned on by mistake according to claim 15, It is characterized in that When the control circuit output is a high level or the gate voltage of the semiconductor switch device is greater than a preset gate voltage, the controllable switch is turned off.

18. The control method for preventing a semiconductor switch from being turned on by mistake according to claim 15, It is characterized in that When the active clamping circuit is completed and the gate voltage of the semiconductor switch device is a preset gate voltage, the controllable switch is turned on.

19. The control method for preventing a semiconductor switch from being turned on by mistake according to claim 15, It is characterized in that The controllable switch is turned off within the preset time period when the active clamping circuit is in operation.

20. The control method for preventing a semiconductor switch from being turned on by mistake according to claim 15, It is characterized in that The active clamping circuit starts to operate when the voltages at the first and second terminals of the semiconductor switch device are greater than a preset voltage; the active clamping circuit completes its operation when the gate voltage of the semiconductor switch device reaches a preset gate voltage.

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