Integrated circuit and electronic device including a plurality of integrated circuits

Abstract

Embodiments disclose integrated circuits and electronic devices including multiple integrated circuits. An electronic device has multiple integrated circuits that are secured to a support between a transmit antenna and a receive antenna. The integrated circuits generate synchronization signals that are provided to other integrated circuits. Each integrated circuit is formed in a die of an integrated electronic component and is covered by a flip chip ball grid array or embedded wafer level BGA land area. A plurality of solder balls for each integrated circuit are electrically coupled to the electronic component and are bonded between the respective integrated circuit and the support. The solder balls are arranged in an array aligned along a plurality of lines parallel to one direction, where the plurality of lines includes empty lines along which no solder balls are present. A conductive synchronization path is formed on the support and extends between the solder balls of the at least one integrated circuit along the empty lines of the at least one integrated circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an integrated circuit and to an electronic device comprising a plurality of integrated circuits electrically coupled by a synchronization signal. BACKGROUND

[0002] In particular, electronic devices of this type are used in radiofrequency applications, for example in radars for motor vehicles (typically, in the frequency range of 76 GHz to 81 GHz), in which there are multiple transmission and / or reception channels, and / or in imaging applications, for example for medical use.

[0003] In these types of multi-channel applications, currently MMICs (Monolithic Microwave Integrated Circuits) are increasingly used due to their uniform electrical characteristics (typically, they are matched to an impedance of 50 Ω), which makes them easy to use since they can be easily connected in cascade without the need for any external impedance matching network.

[0004] In this way, it is possible to make a device formed by a plurality of MMICs connected in cascade, in which each MMIC is configured to manage a small number of transmission / reception channels. For example, the MMICs can be connected together so that a first MMIC (called master MMIC) generates synchronization signals and provides these signals to all the other MMICs (called slave MMICs). In particular, the master MMIC generates synchronization signals LO at more or less high frequencies (for example, at 20, 40 or 80 GHz) depending on the application. With this arrangement, all the MMICs receive the synchronization signals LO from the master MMIC and are able to use the transmission and reception antennas connections to transmit and receive radiofrequency signals in a synchronized manner.

[0005] For example, in this way, a high-end radar device is able to use three MMICs (one master MMIC and two slave MMICs) to manage 12 reception channels (hereinafter called "RX channels") and 9 transmission channels (hereinafter called "TX channels"), each MMIC being able to manage four RX channels and three TX channels. More generally, a radar device of this type is able to use M MMICs each able to manage X / M RX channels and Y / M TX channels to manage X RX channels and Y TX channels.

[0006] Typically, moreover, MMIC-based devices for transmitting / receiving radiofrequency signals comprise a printed circuit board (PCB) which carries the MMICs and the antennas, and can have Figure 1 a layout of the type shown in Figure 1 and described below.

[0007] For example, Figure 1A device 1 is shown, comprising a printed circuit board (PCB 2) carrying one master MMIC 3 and three slave MMICs 4 to 6 (even if the number of MMICs can be greater or smaller). In Figure 1 top view, the MMICs 3 to 6 are arranged side by side between a receiving antenna structure (RX antenna 10 at the top) and a transmitting antenna structure (TX antenna 11 at the bottom) in Figure 1 . Figure 1

[0008] The high-frequency MMICs 3 to 6 are usually fixed to the PCB 2 and electrically connected together by means of solder balls, as described in more detail below. The PCB 2 has surface electrical connections 13, usually formed as conductive tracks on the surface of the PCB 2, for electrically connecting the MMICs 3 to 6 to the RX antenna 10 and TX antenna 11; buried electrical connections 14, formed by conductive tracks, usually extending in the inner layers of the PCB 2; and connection vias for connecting different levels and surfaces of the PCB 2 for exchanging signals and electrical quantities between the MMICs 3 to 6 in a known manner, and only schematically shown in Figure 1 .

[0009] In radio-frequency applications, due to the high operating frequencies (usually higher than 40 GHz), the solder ball connection is currently implemented by means of FC-BGA (flip-chip ball grid array) technology or eWLB (embedded wafer level BGA) technology.

[0010] As is known, both technologies use a ball grid array 15 fixed on one side (for example, on the back side) of each MMIC 3 to 6 to be coupled to the PCB 2, as exemplified in Figure 2 , where the solder balls are indicated by 15 and a generic MMIC is indicated by 16.

[0011] In the case of FC-BGA technology (see Figure 3 ​which is shown by a cross-section through a portion of the generic MMIC 16), the solder balls 15 are fixed to one side of a connection substrate 7 formed by two plates 8 which house a dielectric material 9. The dielectric material 9 embeds metal connection lines 18 which electrically connect the solder balls 15 with bumps 17 fixed on the connection substrate 7 on the opposite side of the solder balls 15. Furthermore, the bumps 17 are fixed to a die 21 which houses electronic components (indicated as a whole by 22) and enable the passage of signals and possibly other electrical quantities (for example, supply quantities, included in the term "signals" hereinafter) between the electronic components 22 of each MMIC 3 to 6 and the connection substrate 7. A dielectric filling and matching layer (so-called underfill layer 19) extends between the die 21 and the connection substrate 7 and covers the bumps 17. A lid 12 is bonded to the connection substrate 7 by means of an adhesive layer 23 and encloses the die 21, the bumps 17 and the underfill layer 19, so as to form a kind of package with the connection substrate 7.

[0012] In the case of the eWLB technology (see Figure 4 , a cross-section through a portion of the generic MMIC 16 is shown), each solder ball 15 is typically fixed to a respective conductive region 25. The conductive regions 25 (only one of which is shown) are typically made of copper within a dielectric layer 26 and form one or more redistribution layers (in Figure 4 , a single redistribution layer RDL 24). The dielectric layer 26 extends on a passivation layer 27 which covers a die 28, except for an opening at a contact pad 30 formed on the surface of the die 28 and electrically connected to electronic components (indicated as a whole by 31) integrated in the die 28. Here, the die 28 is surrounded by a peripheral region 29. The peripheral region 29 is typically made by compression molding and widens the area of the die 28 so that the dielectric layer 26 (which also extends on the peripheral region 29) can have a larger area than the die 28 so that the solder balls 15 can be arranged on the larger area with a pitch of, for example, 500 pm.

[0013] The eWLB technology allows to obtain minimum length of the interconnections and very good electrical performances up to high frequencies (wavelength in the millimeter range), does not require underfilling of the underfill material, makes it possible to have multiple input / output connections and has low cost.

[0014] Among the signals exchanged between the MMICs 3 to 6, of particular importance is the synchronization signal LO, since it makes it possible to maintain the phase coherence and the amplification balance between the MMICs 3 to 6.

[0015] Currently, the synchronization signal LO (with two different inputs to enable symmetric routing in the PCB 2) is routed using an internal additional layer of the PCB 2 through buried connections 14, as these synchronization connections cannot be made on the top layer of the PCB 2 to avoid crossing surface electrical connections 13 with the RX antenna 10 and TX antenna 11. Figure 1

[0016] However, this results in a complexity of the buried connections 14 and an increase of the high cost of forming the internal additional layer of the PCB 2. Furthermore, a transition between the layers is increased, which results in an unwanted drop of the signal amplitude. SUMMARY

[0017] The present disclosure provides an integrated circuit and an electronic device that overcomes the drawbacks of the prior art using a current connection technology (e.g., a solder ball based current connection technology).

[0018] According to the present disclosure, an integrated circuit and an electronic device are provided.

[0019] In at least one embodiment, an integrated circuit package is provided that includes a die including a semiconductor material and integrated electronic elements. A connection area is overlaid on the die. A plurality of solder balls is secured to the connection area and electrically coupled to the electronic elements, and the solder balls are arranged in an array and aligned along a plurality of lines parallel to one direction. The plurality of lines includes a void line along which no solder balls are present.

[0020] In at least one embodiment, an electronic device is provided that includes a support having a face and a plurality of integrated circuits. Each integrated circuit has integrated electronic elements. Each integrated circuit includes a plurality of solder balls, and the plurality of solder balls is electrically coupled to the electronic elements of the respective integrated circuit, and the solder balls are secured between the face of the support and the respective integrated circuit. An antenna structure is arranged on the face of the support. An electrical connection path is arranged on the face of the support and electrically couples the antenna structure to a first solder ball of the plurality of solder balls of each integrated circuit. The plurality of solder balls of each integrated circuit is arranged in an array and aligned along a plurality of lines parallel to one direction, and the plurality of lines includes a void line along which no solder balls are present. A conductive synchronization path extends on the face of the support and is electrically coupled to at least the first solder ball of each integrated circuit. The conductive synchronization path has at least a first portion that extends along the void line of at least one of the plurality of integrated circuits.

[0021] ​In at least one embodiment, an apparatus is provided that includes a printed circuit board (PCB) having a surface and a semiconductor device package physically connected to the surface of the PCB. The semiconductor device package includes a semiconductor die having integrated electronic elements, a connection area on the semiconductor die, and a plurality of solder balls connected to the connection area and electrically coupled to the electronic elements. The solder balls are arranged in an array and aligned along a plurality of lines parallel to one direction. The plurality of lines includes an empty line along which no solder balls are present. BRIEF DESCRIPTION OF DRAWINGS

[0022] For a better understanding of the present disclosure, some embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings in which:

[0023] Figure 1 A layout of an electronic device having a plurality of integrated circuits for known types of radio frequency applications is shown;

[0024] Figure 2 is a bottom perspective view of an integrated circuit configured to be bonded using ball grid array technology;

[0025] Figure 3 is a cross section of a portion of the integrated circuit of Figure 2 configured to be bonded using FC-BGA technology;

[0026] Figure 4 is a cross section of a portion of the integrated circuit of Figure 2 configured to be bonded using eWLB technology;

[0027] Figure 5 A layout of an electronic device having a plurality of integrated circuits according to an embodiment is shown;

[0028] Figure 6 is a bottom view of the integrated circuit of Figure 5 ;

[0029] Figure 6A shows an enlarged detail of the integrated circuit of Figure 6 ;

[0030] Figure 7 is a cross section of a portion of the integrated circuit of Figure 5 ;

[0031] Figure 8 A layout of an electronic device having a plurality of integrated circuits according to another embodiment is shown;

[0032] Figure 9 is a cross section of a portion of the integrated circuit of the electronic device of Figure 8 along section line IX-IX;

[0033] Figure 10 yes Figure 9 Integrated circuits along with Figure 9 Different embodiments of the same cross-section line;

[0034] Figure 11 The layout of an electronic device having multiple integrated circuits according to different embodiments is shown;

[0035] Figure 12 yes Figure 11 A portion of the integrated circuit of the electronic device is located along the cross-section line XII-XII; and

[0036] Figure 13 yes Figure 12 Integrated circuits along with Figure 12 Cross sections of different embodiments of the same cross-section line. Detailed Implementation

[0037] Figure 5 An electronic device 50 is shown, comprising a printed circuit board 52 (PCB) 52 carrying four microcontrollers (MMICs), such as one master MMIC 53 and three slave MMICs 54 to 56 (although the number of slave MMICs may vary). Figure 5 In the top view, MMICs 53 to 56 are arranged side by side on the receiving antenna structure. Figure 5 The top RX antenna 60 and the transmitting antenna structure ( Figure 5 Between the TX antenna 61 at the bottom center.

[0038] refer to Figure 7 MMICs 53 to 56 include a semiconductor device package 57 (which may be referred to as a die 57 in some embodiments) housing electronic components (schematically represented and generally indicated by 58). A connection region 59 extends on the die 57. In the case of eWLB bonding technology, as referenced above... Figure 4 The connection region is formed by a dielectric layer that accommodates the metal interconnect 61. In the case of FC-BGA bonding technology, the connection region 59 is formed by... Figure 3 A similar bond support is formed as bond support 7. Figure 7 What is not visible is a possible passivation layer, or, in the case of eWLB bonding technology, a possible peripheral region surrounding die 57, or, in the case of FC-BGA bonding technology, an underfill layer and bumps, but they may exist, respectively as follows: Figure 4 and Figure 3 As shown in the image.

[0039] Refer again Figure 5, the MMICs 53 to 56 are connected to the RX antenna 60 and to the TX antenna 61 by surface electrical connections 63 formed as conductive tracks on the surface of the PCB 52 carrying the MMICs 53 to 56 in a known manner. Moreover, as will be described below, the MMICs 53 to 56 are connected to each other by buried connections formed in the PCB 52 and by a synchronization line 64, described in detail below, which routes a synchronization signal LO generated by the master MMIC 53 through an electronic component 74 and is provided to the slave MMICs 54 to 56 for their synchronization and amplitude balancing in a per se known manner.

[0040] In the following, for a better understanding, the slave MMICs 54 to 56 are also referred to as a first slave MMIC 54, a second slave MMIC 55 and a third slave MMIC 56. In the shown embodiment (see in particular Figure 5 ), the master MMIC 53 is arranged between the first slave MMIC 54 (on the left) and the second slave MMIC 55 (on the right). Therefore, the synchronization signal LO passes through the master MMIC 53 and the second slave MMIC 55.

[0041] The MMICs 53 to 56 (see also Figure 6 and Figure 7 ) are fixed and electrically connected to the PCB 52 by means of a ball grid array technique using solder balls 65. The solder balls 65 can be bonded using the FC-BGA technique or using the eWLB technique described above and shown in Figure 3 and Figure 4 . It should be noted that in the following the term "ball" will be used even after bonding, which typically deforms and has a shape different from a sphere.

[0042] As shown in Figure 6 , the solder balls 65 are arranged in rows and columns, which are identified in Figure 6 with the letters A to Y and the numbers 1 to 18, respectively, but there is no solder ball 65 on the J-th row.

[0043] In this way, the J-th row defines a void row or missing row, i.e. the solder balls 65 arranged on the rows K and H Figure 6 are arranged at a distance from each other greater than the distance between other adjacent rows. In particular, with reference to the enlarged detail of Figure 6A , if p denotes the pitch between adjacent rows in the array, i.e. the distance between the center points of the solder balls 65 belonging to mutually adjacent rows, at the void row the distance d is twice the pitch p (d = 2p).

[0044] As shown in Figure 6The synchronization line 64 (on the PCB 52) extends in the empty row between two rows of solder balls 65 arranged at a distance d, as indicated by the dashed lines in the figure.

[0045] With reference to Figure 7 , the PCB 52 comprises in a known manner a body 67 of dielectric material having a first face 67A and a second face 67B, and embedded conductive areas 68 connected together, and embedded to the first face 67A by metal vias 69 for the electrical connection between the MMICs 53 to 56. Possible vias (not shown) can also connect the conductive areas 68 to the second face 67B of the PCB 52. In addition, the first face 67A of the PCB 52 carries the surface electrical connections 63 (not visible here) and the synchronization line 64.

[0046] In particular (see also Figure 5 ), the synchronization line 64 is here formed by a synchronization track 66 comprising a straight portion 66A and branch portions 66B extending from the straight portion 66A to respective solder balls 65 arranged at the terminals of the MMICs 53 to 56 intended to receive / transmit the synchronization signal LO (in Figure 5 , with LOin for the input terminal and LOout for the output terminal). For example, the branch portions 66B of the solder balls 65A connected to the input terminal LOin and to the output terminal LOout of the main MMIC 53 coupled to Figure 5 are indicated in Figure 6 by dashed lines.

[0047] In practice, in the embodiment shown in Figure 5 , the straight portion 66A of the synchronization line 64 extends only under the main MMIC 53 and the second slave MMIC 85, even if all the MMICs 53 to 56 have empty rows, and the branch portions 66B are connected to two solder balls 65 (the solder balls 65A and 65B in Figure 6 ) of the main MMIC 53 and to a single solder ball 65 of the MMICs 54 to 56.

[0048] However, the straight portion 66A is not necessarily formed by a single segment passing through the main MMIC 53 and the second slave MMIC 85, but can be formed by a broken line, only the portions thereof passing through the individual MMICs 53 and 55 being preferably linear.

[0049] The synchronization track 66 can be formed in the same way as the surface electrical connections 63 formed on the first face 67A of the PCB 52, for example as a copper track, and generally has a much lower thickness than the solder balls 65, even if these are slightly deformed after soldering, as shown in Figure 7 .

[0050] Figures 8 to 10 An electronic device 70 is shown implementing different solutions for routing the synchronization signal LO. Here, the MMICs comprise microstrips (with ground regions arranged below) or coplanar waveguides (with ground regions in the same plane as the waveguide). The microstrips or coplanar waveguides are formed above the dies and actually extend over the entire width of each MMIC to connect their opposite sides. The connections with the terminals LOin and LOout are obtained through conductive tracks formed on the PCB and connected to the microstrips or coplanar waveguides through solder balls. Figure 8 and Figure 9 The solution shown in with respect to the bonding of the MMICs through the eWLB technology can also be used in the case of the bonding of the MMICs through the FC-BGA technology, as described below.

[0051] Figure 8 In Figure 9 , the MMICs (here denoted by 83 to 86) have a coupling face 81, formed as shown in Figure 4 , and each MMIC comprises a die 73 of integrated electronic components (denoted as a whole by 74), a peripheral region 76 and a dielectric layer 72. As mentioned above with reference to Figure 4 , the metal connection lines 75, which are schematically represented, extend in the dielectric layer 72 and are connected with the solder balls 95. Also here, for the sake of clarity, the slave MMICs 84 to 86 are referred to as first, second and third slave MMICs. It should be noted that, here too, although not shown, each die 73 originates from a semiconductor wafer subjected to cutting processing and comprises a semiconductor substrate (not shown) covered by one or more insulating layers (not shown) which house the metal connection lines (also not shown), in a manner known per se.

[0052] Moreover, as shown in Figure 5 , in Figure 8 , the MMICs 83 to 86 are arranged side by side between a receiving antenna structure RX antenna 90 and a transmitting antenna structure TX antenna 91 and are coupled to the RX antenna 90 and to the TX antenna 91 through surface electrical connections 93 formed on a PCB (denoted by 92), comprising, in a known manner, a body 97 of dielectric material which embeds conductive regions 98 connected together and to a first face 97A through metal vias 99.

[0053] In particular, with reference to the embodiments of Figure 8 and 9 , each MMIC 83 to 86 has a conductive strip 71 formed in the dielectric layer 72 of the master MMIC 83 and of the slave MMICs 84 to 86.

[0054] The conductive strip 71 is formed here using a redistribution layer RDL.

[0055] Figure 10 Variants are shown in which the MMICs 83 to 86 are bonded using FC-BGA technology. Figure 9

[0056] Here, the electronic device (denoted by 70') has conductive strips 71' formed in a metal layer, which are similar to the conductive strips used to form metal connection lines 88 within a connection substrate 89, which are similar to the metal connection lines 18 of Figure 3 , which are similar to the connection substrate 7 of Figure 3 . In Figure 10 , the plate 8 is not shown, and the underfill layer, bumps and lid are denoted by 77, 79 and 80, respectively.

[0057] In both cases of Figure 9 and Figure 10 , the conductive strips 71, 71' extend over substantially the entire width of the MMICs 83 to 86 (and thus of the dielectric layer 72 or of the connection substrate 89), ending only a short distance from their edges.

[0058] It should be noted that in this case, the term width of the MMICs 53 to 56 indicates the dimension in the direction of abutment of the MMICs 53 to 56.

[0059] As shown in Figure 8 , the electronic device 70, 70' has a synchronization line 96 formed by the conductive strips 71, 71' of some of the MMICs 83 to 86 (crossed by the synchronization line 96) and a trace portion 94 formed on the PCB 92. The conductive strips 71, 71' and the trace portion 94 forming the synchronization line 96 are connected together by solder balls 95.

[0060] In detail, the synchronization line 96 is here formed by the conductive strips 71, 71' of the master MMIC 83 and of the second slave MMIC 85 (arranged to the right of the master MMIC 83 in Figure 9 and Figure 10 ). The conductive strips 71, 71' are not electrically coupled to any element 74 and are connected only to the respective solder balls 95 of the master MMIC 83 and of the second slave MMIC 85. The conductive strips 71, 71' of the first slave MMIC 84 (located at the leftmost side in Figure 8 and partially visible in Figure 9 and 10 ) and of the third slave MMIC 56 (located at the rightmost side in Figure 8 and not visible in Figure 9 and 10 ) are floating (or are connected to an appropriate fixed potential, for example ground).​

[0061] As an alternative to the above, the conductive strips 71, 71'of the first slave MMIC 84 and of the third slave MMIC 56 can be connected to respective solder balls 95, but these solder balls are not connected to any metal wire, or, if envisaged, can be connected only to a common ground wire.

[0062] The trace portions 94 formed on the PCB 92 enable the connection of the synchronization line 96 to the input terminal LOin of the MMICs 83-86 and to the output terminal LOout of the master MMIC 83. In detail, with reference to Figure 9 and Figure 10 , by means of a solder ball (not shown) coupled in an unshown manner to the input terminal LOin of the first slave MMIC 84, identified with 95A (indicated in dashed line in Figure 9 and Figure 10 , as it is not crossed by the section plane); with 95B a solder ball coupled to the first end (left in Figure 9 and Figure 10 ) of the conductive strips 71, 71'of the master MMIC 83; with 95C a solder ball coupled to the second end (right in Figure 9 and 10 ) of the conductive strips 71, 71'of the master MMIC 83; and with 95D a solder ball coupled to the first end (left in Figure 9 and 10 ) of the conductive strips 71, 71'of the second slave MMIC 85, the first trace portion 94A connects the solder ball 95A of the slave MMIC 85 to the solder ball 95B of the master MMIC 83 and to the solder ball (not visible) coupled in an unshown manner to the input terminal LOin of the master MMIC 83; the second trace portion 94B connects the solder ball 95C of the master MMIC 53 to the solder ball 95D of the second slave MMIC 85 and to the solder ball (not visible) coupled in an unshown manner to the output terminal LOout of the master MMIC 83; the third trace portion 94C (shown only in Figure 8 ) connects the second end of the conductive strip 71 of the second slave MMIC 85 to the solder ball (not visible) coupled to the input terminal LOin of the second slave MMIC 85 and to the input terminal LOin solder ball of the third slave MMIC 86.

[0063] It should be noted that this solution can also be applied in the case of a wire bonding / solder ball hybrid technology, as will be evident to the person skilled in the art.

[0064] Figures 11 to 13An electronic device 100 is shown that implements different solutions for routing synchronization signals LO. Here, the MMIC has a microstrip or coplanar waveguide integrated within the die, and the microstrip or coplanar waveguide extends across the entire width of each die to connect its opposite sides. Connections to terminals LOin and LOout occur via metal interconnects or leads within the MMIC and conductive traces formed on the PCB. Figure 11 and Figure 12 The solution shown for bonding MMICs 83 to 86 via eWLB technology can also be used for coupling MMICs 83 to 86 via FC-BGA technology or wire bonding technology, as described in the following references. Figure 13 As stated above.

[0065] In detail, such as Figure 11 and Figure 12 As shown, where Figure 8 and Figure 9 The same parts of the electronic device 70 are indicated by the same reference numerals and are not described again, and the die 73 is indicated as being formed of a semiconductor substrate 104 covered by an insulating layer 105. Each MMIC 83 to 86 has a metal conductive strip 101, which is formed here by a metallization layer extending within the insulating layer 105 of each die 73. Each conductive strip 101 is formed here directly below the surface 73A of the respective die 73. In the case of the master MMIC 83 and the second slave MMIC 85, each conductive strip 101 is connected at its respective end to a corresponding solder ball 95 arranged on the edge of each MMIC 83, 85, and a corresponding metal interconnect 102 formed in the dielectric layer 72 and similar to the metal interconnect 71. In the case of the first subordinate MMIC 84 and the third subordinate MMIC 86, the conductive strip 101 is not electrically connected to the electronic component 74 of the electronic device 100, as described above for conductive strips 71, 71'.

[0066] In practice, in this case, the conductive strip 101 forming the microstrip or coplanar waveguide is manufactured at the wafer level along with the component 74, and is already present when the wafer is cut into individual dies 73.

[0067] This solution can also be applied to bonding using FC-BGA bonding technology (in which case, conductive strip 101 is bonded via, for example...). Figure 10 The bumps and bonding supports shown are electrically coupled to solder balls 95) and applied to electronic devices configured to operate at low frequencies and provided with packages coupled to a PCB via wire bonding (wire bonding package).

[0068] For example, Figure 13An electronic device 110 is shown having a connection scheme of the type described above with reference to Figure 11 but in which the MMICs are connected by wirebonds. Thus, the same elements as in the electronic device 100 of Figure 11 and Figure 12 are denoted by the same reference numerals and are not described again.

[0069] In detail, in the example shown in Figure 13 each MMIC 83-86 comprises a bonding wire 115 connecting the respective contact pad 103 to a pin 116. Also here, the contact pads 103 are arranged at opposite ends of the conductive strips 101; each conductive strip 101 is formed within the insulating layer 105 of each die 73 and extends almost over its entire width. In Figure 13 for simplicity, the insulating layer 105 is shown as a single layer covering the semiconductor substrate 104 of each die 72 and being open only at the contact pads 103. However, the insulating layer 105 can be formed in a known manner from different layers arranged on top of each other.

[0070] The dies 73 and the bonding wires 115 are covered by a packaging layer 117 or a layer containing a dielectric material (e.g. a molding resin) (but the packaging layer can be formed according to any known packaging technique, as it will be apparent to the skilled person). The packaging layer 117 also embeds the pins 116 on all sides except the back side, at which the pins 116 are in direct electrical contact with the trace portions 94 of the synchronization line 96.

[0071] As shown in Figure 12 in Figure 13 the conductive strips 101 of the master MMIC 83 and of the second slave MMIC 85 are connected only by the bonding wires 115. Thus, the conductive strips 101 of the first MMIC 84 and of the third MMIC 86 are floating (or are connected to a suitable fixed potential, e.g. ground). Figure 13 The bonding wire 115 connecting the input terminal LOin of the first slave MMIC 84 to the first trace portion 94A, which is electrically connected to the end of the conductive strip 101 of the master MMIC 83, is thus shown with a dashed line (arranged in a plane parallel to the section plane), as described above with reference to Figure 11 .

[0072] The MMICs and electronic devices described herein have many advantages.

[0073] In particular, the described solution allows to transfer the synchronization signal generated by the master MMIC to the slave MMICs without the need of additional connection layers in the PCB scheme, thus being less costly.

[0074] The packaging structure allows the synchronous signal LO to be carried by the same conductive layer used for the radiofrequency signals exchanged with the antenna structures 60, 61, 90, 91.

[0075] The path of the synchronous signal LO is simplified and can be minimized, thus reducing the loss phenomena or layout complexity.

[0076] Finally, it is clear that modifications and changes can be made to the integrated circuits and electronic devices described and illustrated herein without thereby departing from the scope of the present disclosure. For example, the different embodiments described can be combined to provide further solutions.

[0077] For example, the MMICs can also be arranged not aligned with each other, but just side by side between the RX and TX antenna structures. In this case, the synchronous trace 70 can comprise a zigzag line.

[0078] The electronic device can comprise different types of integrated circuits, even operating at frequencies different from the radiofrequency.

[0079] The various embodiments described above can be combined to provide further embodiments. These and other modifications can be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims and should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. The claims are not limited to the embodiments described above.

Claims

1. An electronic device comprising: a printed circuit board (PCB) having a face; a plurality of integrated circuit packages comprising: a die comprising a semiconductor material and integrated electronic elements, the die having a first side opposite a second side; a connection region overlying the die, the connection region housing a plurality of connection lines and having a first face coupled with the die and a second face opposite the first face; and a plurality of solder balls secured to the second face of the connection region and electrically coupled to the electronic elements by the connection lines, the solder balls being arranged in an array and aligned along a plurality of lines parallel to a direction, wherein the plurality of lines includes a void line extending from the first side to the second side along which no solder balls exist; and a conductive synchronization path extending on the face of the PCB and electrically coupled to at least a first solder ball of each integrated circuit package, the conductive synchronization path having at least a first portion extending along the void line of at least one integrated circuit package of the plurality of integrated circuit packages.

2. The electronic device of claim 1, wherein first lines of the plurality of lines are spaced apart from each other by a first distance, and first adjacent lines of the plurality of lines directly adjacent to the void line are spaced apart from each other by a second distance, the second distance being greater than the first distance.

3. The electronic device of claim 2, wherein the second distance is twice the first distance.

4. The electronic device of claim 1, wherein the integrated circuit packages are monolithic microwave integrated circuit packages.

5. An electronic device comprising: a support having a face; a plurality of integrated circuits, each of the integrated circuits having integrated electronic elements; a plurality of solder balls for each integrated circuit, the plurality of solder balls being electrically coupled to the electronic elements of the respective integrated circuit and secured between the face of the support and the respective integrated circuit; an antenna structure on the face of the support; and an electrical connection path on the face of the support and electrically coupling the antenna structure to a first solder ball of the plurality of solder balls of each integrated circuit; wherein the plurality of solder balls of each integrated circuit are arranged in an array and aligned along a plurality of lines parallel to a direction, the plurality of lines including a void line along which no solder balls exist, and a conductive synchronization path extending on the face of the support and electrically coupled to at least a first solder ball of each integrated circuit, the conductive synchronization path having at least a first portion extending along the void line of at least one integrated circuit of the plurality of integrated circuits.

6. The electronic device of claim 5, wherein the conductive synchronization path is laterally surrounded by the solder balls of the at least one integrated circuit of the plurality of integrated circuits.

7. The electronic device of claim 5, wherein first lines of the plurality of lines are spaced apart from each other by a first distance, and adjacent lines of the plurality of lines directly adjacent to the void line are spaced apart from each other by a second distance, the second distance being greater than the first distance.

8. The electronic device of claim 7, wherein the second distance is twice the length of the first distance.

9. The electronic device of claim 5, wherein: the at least one integrated circuit forms a master integrated circuit and includes an output terminal coupled to a second solder ball and configured to generate a synchronization signal; the plurality of integrated circuits includes a first slave integrated circuit and a second slave integrated circuit arranged on different sides of the master integrated circuit; and the electrically conductive synchronization path has a connection portion extending over the face of the support, the connection portion branching from the first portion and coupled to the first solder ball of the master integrated circuit and the first and second slave integrated circuits. a first connection portion extending between the master integrated circuit and the first slave integrated circuit; 10. The electronic device of claim 9, wherein the connection portion comprises: a second connection portion extending between the master integrated circuit and the second slave integrated circuit; a third connection portion extending between the first portion and a respective first solder ball of the master integrated circuit; and a fourth connection portion extending between the second connection portion and the second solder ball of the master integrated circuit, the third and fourth connection portions extending on opposite sides of the master integrated circuit.

11. The electronic device of claim 5, wherein the solder balls form a flip chip ball grid array coupling or an embedded wafer level BGA coupling.

12. The electronic device of claim 5, wherein the plurality of integrated circuits are monolithic microwave integrated circuits.

13. The electronic device of claim 5, wherein the electronic device is a microwave radar device.

14. A device comprising: a printed circuit board (PCB) having a surface; and a plurality of semiconductor device packages physically coupled to the surface of the PCB, each semiconductor device package including: a semiconductor die having integrated electronic elements, the semiconductor die having a first edge opposite a second edge; a connection region on the semiconductor die, the connection region housing a plurality of connection lines and having a first face coupled to the semiconductor die and a second face opposite the first face; and a plurality of solder balls connected to the second face of the connection region and electrically coupled to the electronic elements by the connection lines, the solder balls arranged in an array and aligned along a plurality of lines parallel to a direction, wherein the plurality of lines includes an empty line extending entirely between the first edge and the second edge, no solder balls present in the empty line; and an electrically conductive synchronization path extending over the surface of the PCB and electrically coupled to at least a first solder ball of each semiconductor device package, the electrically conductive synchronization path having at least a first portion extending along the empty line of at least one semiconductor device package of the plurality of semiconductor device packages. ​ ​ 15. The apparatus of claim 14, wherein first lines of the plurality of lines are spaced apart from each other by a first distance, and first adjacent lines of the plurality of lines that are directly adjacent to the empty lines are spaced apart from each other by a second distance, the second distance being greater than the first distance.

16. The apparatus of claim 15, wherein the second distance is twice the first distance.

17. The apparatus of claim 15, wherein the semiconductor device package is a monolithic microwave integrated circuit package.

18. The apparatus of claim 15, wherein the plurality of solder balls form a flip chip ball grid array coupling or an embedded wafer level BGA coupling.

19. The apparatus of claim 15, wherein the apparatus is a microwave radar apparatus.

20. The apparatus of claim 15, further comprising: an antenna on the surface of the PCB and electrically coupled to the semiconductor device package.

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