Method for electrostatic discharge protection, electrostatic discharge circuit, and integrated circuit

Abstract

Methods, electrostatic discharge circuits, and integrated circuits for electrostatic discharge protection are disclosed. According to embodiments, a method for electrostatic discharge protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating for temperature dependence of the divided voltage to form a temperature-compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamping circuit coupled between the plurality of circuit nodes based on the temperature-compensated divided voltage and based on the transient detection signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to systems and methods for temperature-compensated electrostatic discharge (ESD) protection. BACKGROUND

[0002] Semiconductor integrated circuits are typically sensitive to ESD events due to the small geometry of their device structures. These sensitive device structures can include, for example, metal-oxide-semiconductor (MOS) transistors, which are susceptible to damage when exposed to high current and high voltage. To protect these devices, ESD circuits can be coupled to external interface pins and to an externally connected power supply bus. ESD circuits can also be coupled to sensitive internal nodes and to an internal power supply bus connected to internal power generation circuitry, such as a linear regulator.

[0003] One example of ESD protection circuits commonly used to provide protection to internally connected power supply networks and externally connected power supply networks are active clamps. These active clamps can include transistors having a load path connected between two supply nodes to provide a large current discharge path and a trigger circuit configured to activate the transistors during an ESD event or an electrical overstress (EOS) event. These clamp circuits can include, for example, MOS transistors, bipolar transistors, or thyristors. The trigger circuit can be configured to be sensitive to fast current injection ESD events, such as charged device model (CDM) and system-level ESD events, and to ESD events with moderate transient current injection, such as human body model (HBM) ESD events. In addition to providing protection to fast transient ESD events, ESD protection can also be configured to provide protection to slower transient EOS events with a duration longer than 1 ps. However, during normal operation, the clamp circuit can be configured to be non-conductive.

[0004] During nominal high-temperature operation, in the field or during high-temperature overvoltage reliability testing (e.g., burn-in testing, latch-up testing, high-temperature operating life (HTOL) testing, etc.), the clamp circuit is preferably configured to be in a non-conductive state to avoid malfunction or damage to the device due to an unintended large current flowing through the clamp circuit. However, due to the temperature dependence of the semiconductor device, the ESD protection device is typically prone to triggering and / or prone to high leakage current during operation at high temperatures. SUMMARY

[0005] According to an embodiment, a method for electrostatic discharge (ESD) protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating for temperature dependence of the divided voltage to form a temperature-compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamping circuit coupled between the plurality of circuit nodes based on the temperature-compensated divided voltage and based on the transient detection signal.

[0006] According to another embodiment, an electrostatic discharge (ESD) circuit includes: a voltage divider circuit coupled between a first circuit node and a second circuit node; a temperature compensation circuit coupled to the voltage divider circuit; a transient detection circuit coupled to at least one of the first circuit node or the second circuit node; and a clamping circuit having a load path coupled between the first circuit node and the second circuit node and a control node coupled to an output of the voltage divider circuit and an output of the transient detection circuit.

[0007] According to yet another embodiment, an integrated circuit includes: a plurality of diode-connected transistors and at least one resistor disposed on a semiconductor substrate, the plurality of diode-connected transistors and the at least one resistor coupled in series between a first power connection and a second power connection; a temperature compensation circuit disposed on the semiconductor substrate, the temperature compensation circuit coupled to the plurality of diode-connected transistors and the at least one resistor; a filter resistor and a filter capacitor disposed on the semiconductor substrate, the filter resistor and the filter capacitor coupled in series between the first power connection and the second power connection; a clamping transistor disposed on the semiconductor substrate, the clamping transistor having a load path connected between the first power connection and the second power connection; a first amplifier disposed on the semiconductor substrate, the first amplifier coupled between the plurality of diode-connected transistors and a control node of the clamping transistor; and a second amplifier disposed on the semiconductor substrate, the second amplifier coupled between the filter capacitor and the control node of the clamping transistor. BRIEF DESCRIPTION OF DRAWINGS

[0008] For a more complete understanding of the present application, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which:

[0009] Figure 1A a block diagram of an ESD protection system of an embodiment is shown;

[0010] Figure 1B a schematic diagram of a clamping circuit of an embodiment is shown; and

[0011] Figure 1C a schematic diagram of a transient detection circuit of an embodiment is shown;

[0012] Figure 2Aschematic diagram of a voltage divider, temperature compensation circuit, and amplifier of an embodiment is shown;

[0013] Figure 2B a schematic diagram of a voltage divider circuit of an embodiment is shown;

[0014] Figure 2C a schematic diagram of a temperature compensation circuit of an embodiment is shown; and

[0015] Figure 2D a schematic diagram of an ESD protection system of an embodiment is shown;

[0016] Figure 3A and Figure 3B ESD protection according to an alternative embodiment is shown;

[0017] Figure 4 a plan view of an integrated circuit utilizing an ESD protection system of an embodiment is shown; and

[0018] Figure 5 a block diagram of an ESD protection method of an embodiment is shown.

[0019] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The drawings are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, letters indicating changes of the same structure, material or process step can be indicated after the reference numerals. DETAILED DESCRIPTION

[0020] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present application provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the application, and do not limit the scope of the application.

[0021] The present application will be described with respect to a system and method for temperature compensation of an active ESD clamp circuit coupled between power supply nodes of an integrated circuit in a preferred embodiment in a particular context. However, the present application can be generally applied to ESD protection circuits configured to protect other circuit nodes, board level ESD protection circuits, and temperature compensated trigger circuits.

[0022] In embodiments of the present application, a temperature compensated trigger circuit is used to activate an ESD clamp circuit coupled between two power supply nodes. In some embodiments, the temperature compensated trigger circuit includes a voltage divider circuit and a temperature compensation circuit configured to compensate for temperature dependence of the voltage divider circuit. Additionally, the trigger circuit can also include a transient detection circuit configured to detect a fast transient event on the power supply nodes.

[0023] By temperature compensating the voltage divider circuit, an accurate trigger voltage can be ensured over a wide temperature range. Thus, the trigger voltage can be ensured to be sufficiently greater than the maximum expected supply voltage to reduce the risk of false triggering, while preventing the trigger voltage from exceeding a voltage that increases the risk of ESD-induced device damage. Additionally, by incorporating the transient detection circuit, ESD protection can also be ensured for fast transient ESD events.

[0024] Figure 1A An ESD protection system 100 is shown. In various embodiments, the ESD protection system 100 can be disposed on a semiconductor substrate, such as a silicon substrate, and can be configured to provide protection to various circuits and devices disposed on the semiconductor substrate. As shown, the ESD protection system 100 includes a voltage divider 102, a temperature compensation circuit 104, an amplifier 106, a transient detection circuit 108, and a clamping circuit 110. As shown, the output of the voltage divider 102 is coupled to the input of the amplifier 106 and to a node TIN, and the output of the amplifier 106 is coupled to the clamping circuit 110 at a node TRIG. The output of the transient detection circuit 108 is also coupled to the clamping circuit 110. During operation, the voltage divider 102 provides a divided voltage at the node TIN. The divided voltage can be, for example, a fraction p of the voltage difference between nodes VDD and VSS. Node VDD can also be referred to as a "first power connection," and node VSS can also be referred to as a "second power connection." For example, in some embodiments, VDD can be coupled to a positive supply voltage, and VSS can be coupled to a ground voltage or a negative supply voltage. In other embodiments, VDD can be coupled to a ground node, and VSS can be coupled to a negative supply voltage. In still other embodiments, VDD and VSS can be coupled to internal power supply nodes that are generated from an internal supply voltage generation circuit, such as a voltage regulator or a charge pump. TIN -V VSS = (V VDD -V VSS ) / p, where V TIN is the voltage at node TIN, V VDD is the voltage at node VDD, and V VSS is the voltage at node VSS. In embodiments, nodes VDD and VSS can be power supply nodes, where, during normal operation, node VDD is configured to be coupled to a higher voltage than node VSS. In some embodiments, node VSS can be configured to be coupled to a ground voltage or a negative supply voltage. In other embodiments, node VDD can be configured to be coupled to a ground node, and node VSS can be configured to be coupled to a negative supply voltage. One or both of node VDD or node VSS can be directly coupled to an external pin of an integrated circuit, or can be coupled to an internal power supply node that obtains its supply voltage from an internal supply voltage generation circuit, such as a voltage regulator or a charge pump.

[0025] In embodiments where node VSS is coupled to ground, the relationship between V TIN and V VSS can be simplified to V TIN = V VSSIn various embodiments utilizing temperature-dependent circuit elements, a portion p of the voltage difference between nodes TIN and VSS may be temperature-dependent, such that V TIN =V VSS / p(T), where T is temperature. Thus, in various embodiments, the temperature compensation circuit 104 is configured to compensate for the temperature dependence of the fraction p(T). Thus, if the fraction p(T) increases with temperature (e.g., has a positive temperature coefficient), the temperature compensation circuit 104 is configured to provide a compensation signal that decreases with temperature. On the other hand, if the fraction p(T) decreases with temperature (e.g., has a negative temperature coefficient), the temperature compensation circuit 104 is configured to provide a compensation signal that increases with temperature. In some embodiments, the temperature compensation circuit 104 fully compensates for the temperature dependence of the fraction p(T) in the voltage divider 102, while in other embodiments, the temperature compensation circuit 104 partially compensates for temperature such that the degree of temperature dependence of the fraction p(T) is reduced relative to an uncompensated voltage divider 102.

[0026] In some embodiments, a positive temperature coefficient is associated with avalanche breakdown of a reverse-biased diode or a resistor made of a material such as a metal or heavily doped semiconductor (e.g., a diffused resistor) and an n-well whose resistivity increases with temperature. On the other hand, a negative temperature coefficient is associated with a forward-biased diode or a MOS diode. Polysilicon resistors can be configured to have either a positive or negative temperature coefficient.

[0027] During operation, the voltage divider 102 cooperates with the temperature compensation circuit 104 to provide a temperature-compensated voltage V TIN , the temperature compensated voltage V TIN It is V VDD With V VSS The compensated voltage V TIN is amplified by amplifier 106, which provides a portion of the trigger signal V at node TRIG. TRIG When the trigger signal V TRIG When the threshold voltage of the clamp circuit 110 is exceeded, the clamp circuit 110 turns on and provides a low impedance path between nodes VDD and VSS. In various embodiments, the low impedance path is configured to safely shunt large currents occurring due to ESD events.

[0028] The amplifier 106 may include one or more amplifiers configured to drive the clamp circuit 110. In some embodiments, the amplifier 106 may be configured to drive the voltage V at the node TIN to TIN is compared with a predetermined voltage or voltage within a voltage range to determine when to generate a trigger signal V TRIGIn some implementations, the amplifier 106 can be implemented using one or more inverter circuits.

[0029] In various implementations, the transient detection circuit 108 is configured to provide a portion of the trigger signal V TRIG at the node TRIG in response to a fast transient signal at the node VDD and / or the node VSS. TRIG The portion of the trigger signal V TIN generated by the transient detection circuit 108 can be referred to as a “transient detection signal.” The transient detection circuit 108 can include, for example, a filter with a small time constant, such as an RC filter. In some implementations, the time constant can be between approximately 1 ns and approximately 1 μβ, depending on the particular implementation and its specifications. However, in some cases, time constants outside of this range can be used. In some implementations, the time constant can be set to be in the nanosecond range to detect fast transient events such as the first peak of a CDM or system-level ESD pulse. The maximum value of the time constant can be adjusted to meet various system-specific specifications. For example, the time constant (and other circuit parameters) can be adjusted in a manner that satisfies design goals for power-on time, ESD circuit area, clamping voltage of the ESD protection system 100. The time constant can also be adjusted, for example, to meet predetermined commercial ESD requirements such as the HBM test specification, which defines a current peak at 30 ns. In some implementations, the transient detection circuit 108 can include one or more amplifiers configured to drive the clamping circuit 110.

[0030] Figure 1B Two example circuits that can be used to implement the clamping circuit 110 in Figure 1A are shown. For example, the clamping circuit 110 can be implemented using a circuit 110a that includes a bipolar junction transistor 101 (which can be referred to as a “clamping transistor”) having a base coupled to the trigger node TRIG, an emitter coupled to the node VSS, and a collector coupled to the node VDD. During operation, in response to an ESD event, the trigger signal V TIN is applied to the base of the transistor 101. As the voltage of the trigger signal V TRIG increases, a corresponding current flows from the collector to the emitter of the transistor 101. The current path from the collector to the emitter of the junction transistor 101 can also be referred to as a “load path.” In various implementations, the current handling capability of the transistor 101 is configured to handle at least an expected amount of current associated with an ESD event.

[0031] In another implementation, the clamping circuit 110 can be implemented using a circuit 110b that includes a MOS transistor 103 (also referred to as a “clamping transistor”) having a gate (also referred to as a “control node”) coupled to the trigger node TRIG, a source coupled to the node VSS, and a drain coupled to the node VDD. During operation, in response to an ESD event, the trigger signal V TIN is applied to the gate of the transistor 103. When the voltage of the trigger signal V TRIG exceeds the threshold V T of the transistor 103, a corresponding current flows from the drain to the source of the transistor 103. The current path from the source to the drain of the transistor 103 can also be referred to as a “load path.” In various implementations, the current handling capability of the transistor 103 is configured to handle at least an expected amount of current associated with an ESD event. Although the transistor 103 is depicted in Figure 1B as an NMOS transistor, it should be understood that a PMOS transistor can alternatively be used to implement the transistor 103.

[0032] It should be understood that Figure 1B the circuits 110a and 110b shown are merely two of many possible example circuits that can be used to implement the clamping circuit 110. In alternative implementations of the present disclosure, the clamping circuit 110 can be implemented using other devices including, but not limited to, MOSFETs, IGBTs, JFETs, and thyristors.

[0033] Figure 1C A schematic diagram showing an example implementation of the trigger circuit 108 is shown, which includes a series RC circuit implemented using a resistor 105 and a capacitor 107 connected together at node B, and an amplifier 164 implemented using an inverter 109 that includes a PMOS transistor 162 and an NMOS transistor (the resistor 105 can also be referred to as a “filter resistor,” and the capacitor 107 can also be referred to as a “filter capacitor”). During normal (e.g., non-ESD) operation, the PMOS transistor 162 is off, and the NMOS transistor applies a voltage V VSS at node VSS to the node TRIG. Due to the low pass nature of the series RC circuit, when the voltage between the nodes VDD and VSS rapidly increases, the gate-source voltage of the PMOS transistor 162 increases at a faster rate than the voltage across the capacitor 107. Thus, when the voltage between the nodes VDD and VSS rapidly increases in response to an ESD event, the PMOS transistor 162 turns on for a length of time that is proportional to the RC time constant of the resistor 105 and the capacitor 107.

[0034] It should be understood that Figure 1C The depicted circuit is only one of many example circuits that can be used to implement the trigger circuit 108. In alternative implementations, other trigger circuits known in the art can be used. For example, in one implementation, the positions of the resistor 105 and the capacitor 107 can be reversed, such that the capacitor 107 is coupled between node B and node VDD, and the resistor 105 is coupled between node B and node VSS. In such an implementation, the NMOS 164 is off during normal operation and temporarily on during an ESD event. In such an implementation, an additional inverter circuit 109 can be cascaded with the existing inverter circuit 109 to adjust the polarity of the trigger signal V TRIG of the clamping circuit 110.

[0035] Figure 2A A schematic diagram is shown that illustrates Figure 1A a more detailed view of the voltage divider 102, the temperature compensation circuit 104, and the amplifier 106 depicted in FIG. 1. As shown, the voltage divider 102 includes a plurality of first voltage divider elements 112 coupled between node VDD and node TIN, and a second voltage divider element 114 coupled between node TIN and node VSS. Although only four first voltage divider elements 112 are shown coupled in series between node VDD and node TIN for ease of illustration, it should be understood that any number of first voltage divider elements 112 can be coupled between node VDD and node TIN. Similarly, although only a single second voltage divider element 114 is shown coupled between node TIN and node VSS, it should be understood that two or more second voltage divider elements 114 can be coupled between node TIN and node VSS. In various implementations, the first voltage divider elements 112 and the second voltage divider elements 114 can be implemented using various circuits and devices having a positive temperature coefficient or a negative temperature coefficient, as described below with respect to Figure 2B In some implementations, the first voltage divider elements 112 or the second voltage divider elements 114 can be implemented using circuit elements having temperature stable characteristics.

[0036] The temperature compensation circuit 104 includes a temperature compensation element 116, which can include a circuit element having a positive temperature coefficient or a negative temperature coefficient. The temperature coefficient of the temperature compensation element 116 can be configured to fully or partially compensate for the temperature behavior of the voltage divider circuit 102. The temperature compensation circuit 104 can include a single temperature compensation element 116, or can include a plurality of temperature compensation circuits 116 coupled together in various configurations, as further described below with respect to Figure 2C

[0037] ​The amplifier 106 includes two inverters 109 coupled in series between the node TIN and the node TRIG. The inverters 109 can be implemented, for example, as described above with respect to Figure 1C In some implementations, more than two inverters 109 or fewer than two inverters 109 can be used. In yet another implementation of the application, other amplifier circuits known in the art can be used to implement the amplifier 106.

[0038] Figure 2B Example implementations 102a, 102b, 102c, and 102d that can each be used individually to implement the voltage divider circuit 102 are shown. In the voltage divider circuit 102a, the first voltage divider element 112 is implemented using a junction diode 122 (also can be referred to as a "diode circuit"), and the second voltage divider element 114 is implemented using a resistor 124. The junction diode 122 can be implemented, for example, using a pn junction formed by two adjacent diffusion regions of opposite semiconductor types, or by a semiconductor junction formed by a diffusion region of a first semiconductor type disposed in a well of a second semiconductor type (e.g., a p+ diffusion disposed in an n well). Alternatively, the junction diode 122 can be formed by other diode structures known in the art, such as an NMOS-based diode stack. In implementations, the resistor 124 has a positive temperature coefficient. During operation, the voltage across each forward-biased junction diode 122 decreases with temperature, while the resistance of the resistor 124 increases with temperature. Thus, the divided voltage V TIN (no temperature compensation) generated by the voltage divider 102a increases with temperature. In some implementations, the resistor 124 is implemented using a diffusion resistor, a polysilicon resistor, a metal resistor, or other resistor structures known in the art. The resistor 124 can have a resistance between about 100 Ω and about 100 kΩ, however, values outside this range can be used depending on the particular implementation.

[0039] With respect to the voltage divider circuit 102b that can also be used to implement the voltage divider circuit 102, the first voltage divider element 112 is implemented using diode-connected PMOS devices 126, and the second voltage divider element 114 is implemented using the resistor 124. Alternatively, one or more of the diode-connected PMOS devices 126 can be replaced with corresponding diode-connected NMOS devices. In implementations, the resistor 124 has a positive temperature coefficient. During operation, the voltage across each diode-connected PMOS device 126 decreases with temperature, while the resistance of the resistor 124 increases with temperature. Thus, the divided voltage V TIN (no temperature compensation) generated by the voltage divider 102b increases with temperature, as the resistor dictates the temperature dependence of the entire stack.

[0040] In voltage divider circuit 102c, junction diode 122 is used to implement first voltage divider element 112, and diode 128 is used to implement second voltage divider element 114. Diode 128 can be implemented, for example, using a junction diode or a Zener diode. During an ESD event, the voltage between nodes VDD and VSS increases to the extent that diode 128 experiences avalanche and / or Zener breakdown and the voltage across diode 128 is limited to its breakdown voltage. In embodiments, the voltage across diode 128 used to implement second voltage divider element 114 increases as temperature increases. Thus, in some embodiments, the divided voltage V TIN (no temperature compensation) decreases as temperature increases.

[0041] In some embodiments, the output of an uncompensated voltage divider 102 can decrease as temperature increases. For example, voltage divider circuit 102d includes diode-connected PMOS device 126 used to implement first voltage divider element 112 and diode-connected PMOS device 127 used to implement second voltage divider element 114. Alternatively, one or more of diode-connected PMOS devices 126 can be replaced with corresponding diode-connected NMOS devices. In embodiments, the voltage across diode-connected PMOS device 127 decreases as temperature increases, such that the divided voltage V TIN (no temperature compensation) decreases as temperature increases.

[0042] It will be appreciated that Figure 2B The examples shown represent only four of many possible ways to implement voltage divider circuit 102. In other embodiments of the application, other voltage divider circuits known in the art can be used. For example, other devices besides diodes, PMOS transistors, and resistors can be used to implement voltage divider circuit 102. Bipolar transistors, NMOS transistors, JFET devices, and other circuit devices known in the art can be used to implement first voltage divider element 112 and second voltage divider element 114.

[0043] Figure 2CExample implementations 104a, 104b, 104c, 104d, 104e, 104f, and 104g are shown that can each be used to implement the temperature compensation circuit 104. As shown, the temperature compensation circuit 104a includes an NMOS device 136 having a drain connected to a node TIN and a gate and source connected to a node VSS. During normal operation, the NMOS device 136 is nominally off, but has a leakage current that depends on geometry and temperature. Therefore, as temperature increases, the leakage current increases and tends to pull the voltage at the node TIN to a lower value (e.g., the voltage at TIN does not go as high). Therefore, when the temperature compensation circuit 104a is used in conjunction with an implementation of the voltage divider circuit 102 that has a voltage that increases with increasing temperature (e.g., Figure 2B When the voltage divider circuits 102a and 102b are paired as shown in FIG, the increase in leakage current of the NMOS device 136 at higher temperatures compensates for the increase in resistance of the resistor 124 and the increase in current caused by the decrease in the forward diode voltage of the junction diode 122 (circuit 102a) and the decrease in the voltage across the diode-connected PMOS device (circuit 102b), thereby reducing the voltage V at the node TIN. TIN In some implementations, in addition to being paired with voltage divider circuits 102a and 102b, temperature compensation circuit 104a can also be paired with voltage divider circuit 102c having a positive temperature coefficient.

[0044] The temperature compensation circuit 104b includes an NMOS device 136 having a drain connected to a node TIN and a source connected to a node VSS. The gate of the NMOS device 136 is coupled to the node TIN via a resistor 135 and to the node VSS via a resistor 137. In some embodiments, the resistance of the resistors 135 and 137 are selected and the size of the NMOS device 136 is determined so that the NMOS device 136 is biased in a subthreshold regime. For example, in one embodiment, the resistors 135 and 137 form a resistor divider having a voltage divider ratio between about 50 kΩ and about 5 kΩ. The resistors 135 and 137 can be formed using any type of resistor known in the art. In alternative embodiments, the resistor network formed by the resistors 135 and 137 can have a value different from Figure 2C The topology of two series resistors 135 and 137 is depicted in FIG.

[0045] In various embodiments, for a given gate voltage, the subthreshold current drawn by the NMOS device 136 increases with increasing temperature. Therefore, when the temperature compensation circuit 104b is combined with an implementation of the voltage divider circuit 102 having a voltage that increases with increasing temperature (e.g., Figure 2BThe increase in current drawn by NMOS device 136 compensates for the increase in resistance of resistor 124 and the increase in current due to the decrease in voltage across junction diode 122 (circuit 102a) and diode-connected PMOS device 126 (circuit 102b) when the divider circuits 102a and 102b are paired, thereby reducing the temperature dependence of the voltage V TIN In some implementations, in addition to being paired with divider circuits 102a and 102b, temperature compensation circuit 104b can also be paired with divider circuits 102c that have a positive temperature coefficient.

[0046] Temperature compensation circuit 104c includes diode-connected PMOS device 138 having a source and gate connected to node TIN and a drain connected to node VSS. In various implementations, diode-connected PMOS device 138 is sized such that the voltage across diode-connected PMOS device 138 decreases as temperature increases. Thus, when temperature compensation circuit 104c is paired with implementations of divider circuits 102 that have a voltage that increases as temperature increases (e.g., divider circuits 102a and 102b shown in FIGS. 1A and IB), the increase in current drawn by diode-connected PMOS device 138 (due to its decrease in threshold voltage) at higher temperatures compensates for the increase in resistance of resistor 124 and the increase in current due to the decrease in voltage across junction diode 122 (circuit 102a) and diode-connected PMOS device 126 (circuit 102b), thereby reducing the temperature dependence of the voltage V Figure 2B TIN In some implementations, in addition to being paired with divider circuits 102a and 102b, temperature compensation circuit 104c can also be paired with divider circuits 102c that have a positive temperature coefficient.

[0047] ​In some embodiments, the temperature compensation circuit can include multiple devices coupled in series, as shown with respect to temperature compensation circuits 104d, 104e, and 104f. As shown, temperature compensation circuit 104d includes multiple diode-connected PMOS devices 138 coupled in series between node TIN and VSS, and temperature compensation circuit 104e includes multiple junction diodes coupled in series between node TIN and VSS. While only two diode-connected PMOS devices 138 are described with respect to temperature compensation circuit 104d and only three junction diodes 139 are depicted with respect to temperature compensation circuit 104e, respectively, it should be understood that any number of circuit elements can be coupled in series, depending on the particular embodiment and its specifications. The operation of temperature compensation circuits 104d and 104e is similar to that of temperature compensation circuit 104c described above. That is, the voltage across the multiple circuit elements decreases as temperature increases. Thus, when temperature compensation circuits 104d and 104e are paired with an implementation of voltage divider circuit 102 having a voltage that increases as temperature increases (e.g., voltage divider circuits 102a, 102b, and 102c shown) Figure 2B The increase in current drawn by diode-connected PMOS devices 138 (due to the decrease in their threshold voltage) or junction diodes 139 (due to the decrease in their forward diode voltage) at higher temperatures compensates for the increase in resistance of resistor 124 (circuits 102a and 102b), the increase in breakdown voltage of diode 128 (circuit 102c), and the increase in current due to the decrease in voltage across junction diode 122 (circuits 102a and 102c) and diode-connected PMOS device 126 (circuit 102b). Thus, the temperature dependence of voltage V TIN at node TIN is reduced. In some embodiments, temperature compensation circuits 104d and 104e can be coupled in parallel, as shown with respect to temperature compensation circuit 104f.

[0048] It should be noted that temperature compensation circuits 104d, 104e, and 104f are particularly suitable for pairing with voltage divider circuit 102c having a reverse-biased diode 128 coupled between node TIN and node VSS. In such embodiments, the number of stacked devices in temperature compensation circuits 104d, 104e, or 104f can be selected according to the breakdown voltage of diode 128. For example, when diode 128 has a higher breakdown voltage, more devices (e.g., diode-connected PMOS devices 128 or junction diodes 139) can be coupled in series, and when diode 128 has a lower breakdown voltage, fewer devices can be coupled in series.

[0049] A resistor can also be used to implement an embodiment of a temperature compensation circuit, as shown with respect to temperature compensation circuit 104g including resistor 142. In an embodiment, resistor 142 has a positive temperature coefficient such that the resistance of the resistor increases as temperature increases. When temperature compensation circuit 104g is paired with an embodiment of voltage divider circuit 102 having a voltage divider circuit 102 that decreases in voltage as temperature increases, such as voltage divider circuit 102d shown in Figure 2B FIG. 6B, the increase in resistance of resistor 142 at higher temperatures compensates for the decrease in threshold voltage of diode-connected PMOS device 127 at higher temperatures.

[0050] It should be understood that temperature compensation circuits 104a, 104b, 104c, 104d, 104e, 104f, and 104g are merely seven non-limiting examples of embodiments of temperature compensation circuits that can be used to compensate voltage divider 102. In alternative embodiments of the present application, other combinations of circuit elements can be used to temperature compensate voltage divider 102.

[0051] Figure 2D An embodiment of ESD protection system 180 is shown in which voltage divider circuit 102 is implemented using voltage divider circuit 102b described above with respect to Figure 2B temperature compensation circuit 104 is implemented using temperature compensation circuit 104b described above with respect to Figure 2C transient detection circuit 108 is implemented using transient detection circuit 108 described above with respect to Figure 1C amplifier 106 is implemented using two inverters 109, and clamp circuit 110 is implemented using clamp circuit 110b described above with respect to Figure 1B FIG. 6B. It should be understood that the embodiment of ESD protection system 180 shown in Figure 2D FIG. 6B is merely one non-limiting example of how various embodiments of voltage divider circuits, temperature compensation circuits, amplifiers, transient detection circuits, and clamp circuits can be combined to form an ESD protection circuit.

[0052] Figure 3A An ESD protection system 200 according to an alternative embodiment of the present application is shown in Figure 3A FIG. 7. ESD protection system 200 shown in Figure 1A, except that the output of the transient detection circuit 108 is connected to the voltage divider circuit 102 at node TIN. Optionally, an additional instance of the temperature compensation circuit 104 can be coupled in parallel with one of the first voltage divider elements 112. During an ESD event, when the transient detection circuit 108 detects a fast transient at nodes VDD and VSS, the voltage at node TIN rises rapidly, and the additional compensation circuit 104 provides additional temperature compensation for the voltage divider 102. In some embodiments, the additional compensation circuit 104 can be omitted.

[0053] Figure 3B The ESD protection system 220 shown in FIG. 1 is similar to Figure 3A , except that transient detection circuit 108 is implemented using capacitor 224 coupled between node VDD and voltage divider 102. During an ESD event associated with a fast transient voltage increase at node VDD, the increased voltage at node VDD is coupled to node TIN, thereby increasing the voltage at node TIN.

[0054] Figure 4 A plan view of an integrated circuit 300 incorporating an embodiment of the ESD protection system described herein is shown. As shown, the integrated circuit 300 includes a plurality of signal pads 312, a first power pad 308 connected to a node VDD and a power rail 302a, and a second power pad 310 connected to a node VSS and a power rail 304a. The first power pad 308 and the second power pad 310 provide power to a circuit 314a. An ESD protection circuit 306a coupled between nodes VDD and VSS, which can be implemented using any of the ESD protection systems described above, provides ESD protection to a circuit 314a coupled to power rails 302a and 304a.

[0055] The integrated circuit also includes internal power rails 302b and 304a coupled to power rails 302a and 304b via an ESD coupling network 320, which can be implemented using diodes as shown. In some embodiments, the internal power rails 302b and 304b and the circuit 314b powered by the internal power rails 302b and 304b form a power domain separate from the circuit 314a and the power rails 302a and 304a. In various embodiments, the ESD protection circuit 306b coupled to the internal power rails 302b and 304b can be implemented using any of the ESD protection systems described above to provide ESD protection to the circuit 314b coupled to the internal power rails 302b and 304b. It should be understood that Figure 4The illustrated integrated circuit 300 is merely one specific example of how an implementation of an ESD protection system can be incorporated into an integrated circuit. In alternative implementations, any number of implementations of ESD protection circuits can be used to provide protection for any number of power domains.

[0056] Figure 5 A flowchart of an implementation method 400 of ESD protection that can be applied to the above-described implementations of ESD protection systems is shown. In step 402, a voltage between a plurality of circuit nodes is divided using a voltage divider circuit to form a divided voltage. In some implementations, the voltage divider circuit 102 described herein in implementations can be used to provide the divided voltage. In one implementation, the nodes VDD and VSS described with respect to the above implementations form the plurality of circuit nodes. In step 404, the temperature dependence of the divided voltage is compensated. In various implementations, the temperature compensation circuit 104 described in the above various implementations can be used to temperature compensate the divided voltage.

[0057] In step 406, the voltage between the plurality of circuit nodes is compensated using a transient detection circuit, such as the transient detection circuit 108 described in the above implementations, to form a transient detection signal. In step 408, a clamping circuit coupled between the plurality of circuit nodes is activated based on the compensated divided voltage and based on the transient detection circuit. In some implementations, the clamping circuit can be implemented using the clamping circuit 110 described herein with respect to implementations. For example, the clamping circuit can be activated based on an output (node TRIG) from the amplifier 106 and / or the transient detection circuit 108 described herein with respect to implementations. It should be appreciated that some or all of the method steps 402, 404, 406, and 408 are performed simultaneously in some implementations.

[0058] Implementations of the present application are summarized here. Other implementations can be appreciated from the entire specification and claims submitted herewith.

[0059] Example 1. A method for electrostatic discharge (ESD) protection, the method comprising: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating for a temperature dependence of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamping circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.

[0060] Example 2. The method of example 1, further comprising: amplifying the temperature compensated divided voltage, and providing the amplified temperature compensated divided voltage to an input node of the clamping circuit.

[0061] Example 3. The method of example 1 or 2, further comprising amplifying the transient detection signal and providing the amplified transient detection signal to the clamp circuit.

[0062] Example 4. The method of one of examples 1-3, further comprising providing the transient detection signal to the voltage divider circuit.

[0063] Example 5. The method of one of examples 1-4, further comprising amplifying the transient detection signal and providing the amplified transient detection signal to the voltage divider circuit.

[0064] Example 6. The method of one of examples 1-5, wherein temperature compensating the voltage divider circuit comprises providing a temperature dependent current to a node of the voltage divider circuit.

[0065] Example 7. The method of one of examples 1-6, wherein the voltage divider circuit comprises a plurality of diode circuits coupled in series with a resistor.

[0066] Example 8. The method of example 7, wherein: each diode circuit of the plurality of diode circuits comprises a diode-connected transistor; and temperature compensating the voltage divider circuit comprises using a temperature compensation circuit comprising a transistor having a load path coupled between a node of the voltage divider circuit and one of the plurality of circuit nodes, and a resistor network coupled between the node of the voltage divider circuit and a control node of the transistor.

[0067] Example 9. The method of one of examples 1-8, wherein the transient detection circuit comprises an RC circuit.

[0068] Example 10. An electrostatic discharge (ESD) circuit comprising: a voltage divider circuit coupled between a first circuit node and a second circuit node; a temperature compensation circuit coupled to the voltage divider circuit; a transient detection circuit coupled to at least one of the first circuit node or the second circuit node; and a clamp circuit having a load path coupled between the first circuit node and the second circuit node and a control node coupled to an output of the voltage divider circuit and to an output of the transient detection circuit.

[0069] Example 11. The ESD circuit of example 10, further comprising a first amplifier coupled between an output of the voltage divider circuit and the control node of the clamp circuit.

[0070] Example 12. The ESD circuit of example 11, further comprising a second amplifier coupled between an output of the transient detection circuit and the control node of the clamping circuit.

[0071] Example 13. The ESD circuit of example 11, further comprising a second amplifier coupled between an output of the transient detection circuit and the voltage divider circuit.

[0072] Example 14. The ESD circuit of one of examples 11-13, wherein the first amplifier comprises an inverter.

[0073] Example 15. The ESD circuit of one of examples 10-14, wherein: the voltage divider circuit comprises a plurality of diode circuits coupled in series with a resistor; and the temperature compensation circuit is configured to provide a temperature dependent current.

[0074] Example 16. The ESD circuit of example 15, wherein: each diode circuit of the plurality of diode circuits comprises a diode-connected transistor; and the temperature compensation circuit comprises a transistor having a load path coupled between a node of the voltage divider circuit and one of a first circuit node or a second circuit node, and a resistor network coupled between the node of the voltage divider circuit and a control node of the transistor.

[0075] Example 17. The ESD circuit of one of examples 10-16, wherein the temperature compensation circuit comprises a plurality of temperature compensation circuits.

[0076] Example 18. The ESD circuit of one of examples 10-17, wherein the first circuit node is a power supply node and the second circuit node is a ground node.

[0077] Example 19. The ESD circuit of one of examples 10-18, wherein the transient detection circuit comprises an RC circuit coupled to at least one of the first circuit node or the second circuit node.

[0078] Example 20. An integrated circuit comprising: a plurality of diode-connected transistors and at least one resistor disposed on a semiconductor substrate, the plurality of diode-connected transistors and the at least one resistor coupled in series between a first power connection and a second power connection; a temperature compensation circuit disposed on the semiconductor substrate, the temperature compensation circuit coupled to the plurality of diode-connected transistors and the at least one resistor; a filter resistor and a filter capacitor disposed on the semiconductor substrate, the filter resistor and the filter capacitor coupled in series between the first power connection and the second power connection; a clamp transistor disposed on the semiconductor substrate, the clamp transistor having a load path connected between the first power connection and the second power connection; a first amplifier disposed on the semiconductor substrate, the first amplifier coupled between the plurality of diode-connected transistors and a control node of the clamp transistor; and a second amplifier disposed on the semiconductor substrate, the second amplifier coupled between the filter capacitor and the control node of the clamp transistor.

[0079] Example 21. The integrated circuit of example 20, wherein: each of the plurality of diode-connected transistors comprises a diode-connected MOS transistor; and the clamp transistor comprises a MOS transistor.

[0080] Example 22. The integrated circuit of example 20 or 21, wherein: the temperature compensation circuit comprises: a first MOS transistor having a first source / drain coupled to the plurality of diode-connected transistors and a second source / drain coupled to the second power connection; a first resistor coupled between a gate of the first MOS transistor and the first source / drain; and a second resistor coupled between the gate and the second source / drain.

[0081] While the application has been described with reference to illustrative implementations, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative implementations, as well as additional implementations of the application, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims shall cover any such modifications or implementations.

Claims

1. A method for electrostatic discharge (ESD) protection, the method comprising: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; providing a temperature dependent current to a node of the voltage divider circuit with a temperature compensation circuit for compensating a temperature dependence of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal, wherein the temperature compensation circuit comprises a transistor having a load path coupled between a node of the voltage divider circuit and one of the plurality of circuit nodes and a resistor network coupled between the node of the voltage divider circuit and a control node of the transistor. amplifying the temperature compensated divided voltage and providing the amplified temperature compensated divided voltage to an input node of the clamp circuit.

2. The method of claim 1, further comprising: amplifying the transient detection signal and providing the amplified transient detection signal to the clamp circuit.

3. The method of claim 2, further comprising:

4. The method of claim 2, further comprising providing the transient detection signal to the voltage divider circuit. amplifying the transient detection signal and providing the amplified transient detection signal to the voltage divider circuit.

5. The method of claim 2, further comprising: the voltage divider circuit comprises a plurality of diode circuits coupled in series with resistors.

6. The method of claim 1, wherein, 7. The method of claim 6, wherein: each diode circuit of the plurality of diode circuits comprises a diode-connected transistor. the transient detection circuit comprises an RC circuit.

8. The method of claim 1, wherein, 9. An electrostatic discharge (ESD) circuit comprising: a voltage divider circuit coupled between a first circuit node and a second circuit node; a temperature compensation circuit coupled to the voltage divider circuit, wherein the temperature compensation circuit is configured to provide a temperature dependent current; a transient detection circuit coupled to at least one of the first circuit node or the second circuit node; and a clamp circuit having a load path coupled between the first circuit node and the second circuit node and a control node coupled to an output of the voltage divider circuit and to an output of the transient detection circuit, wherein the temperature compensation circuit comprises a transistor having a load path coupled between a node of the voltage divider circuit and one of the plurality of circuit nodes and a resistor network coupled between the node of the voltage divider circuit and a control node of the transistor.

10. The ESD circuit of claim 9, further comprising a first amplifier coupled between an output of the voltage divider circuit and the control node of the clamp circuit.

11. The ESD circuit of claim 10, further comprising a second amplifier coupled between an output of the transient detection circuit and the control node of the clamp circuit.

12. The ESD circuit of claim 10, further comprising a second amplifier coupled between an output of the transient detection circuit and the voltage divider circuit. ​ ​ 13. The ESD circuit of claim 10, wherein, The first amplifier includes an inverter.

14. The ESD circuit of claim 9, wherein: The voltage divider circuit includes a plurality of diode circuits coupled in series with a resistor.

15. The ESD circuit of claim 14, wherein: Each diode circuit of the plurality of diode circuits includes a diode-connected transistor.

16. The ESD circuit of claim 14, wherein, The temperature compensation circuit includes a plurality of temperature compensation circuits.

17. The ESD circuit of claim 9, wherein, The first circuit node is a power supply node and the second circuit node is a ground node.

18. The ESD circuit of claim 9, wherein, The transient detection circuit includes an RC circuit coupled to at least one of the first circuit node or the second circuit node.

19. An integrated circuit, comprising: a plurality of diode-connected transistors and at least one resistor disposed on a semiconductor substrate, the plurality of diode-connected transistors and the at least one resistor coupled in series between a first power supply connection and a second power supply connection; a temperature compensation circuit disposed on the semiconductor substrate, the temperature compensation circuit coupled to the plurality of diode-connected transistors and the at least one resistor; a filter resistor and a filter capacitor disposed on the semiconductor substrate, the filter resistor and the filter capacitor coupled in series between the first power supply connection and the second power supply connection; a clamp transistor disposed on the semiconductor substrate, the clamp transistor having a load path connected between the first power supply connection and the second power supply connection; a first amplifier disposed on the semiconductor substrate, the first amplifier coupled between the plurality of diode-connected transistors and a control node of the clamp transistor; and a second amplifier disposed on the semiconductor substrate, the second amplifier coupled between the filter capacitor and the control node of the clamp transistor.

20. The integrated circuit of claim 19, wherein: each of the plurality of diode-connected transistors includes a diode-connected MOS transistor; and the clamp transistor includes a MOS transistor.

21. The integrated circuit of claim 20, wherein the temperature compensation circuit includes: a first MOS transistor having a first source / drain coupled to the plurality of diode-connected transistors and a second source / drain coupled to the second power supply connection; a first resistor coupled between a gate of the first MOS transistor and the first source / drain; and a second resistor coupled between the gate and the second source / drain. ​ ​

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