Multi-gate transistor and memory device using the same

Abstract

The present invention discloses a multi-gate transistor and a memory device using the same, wherein the multi-gate transistor comprises: a doped drain region; a doped source region; a gate group, comprising a first gate and a second gate; a channel, wherein the doped drain region and the doped source region are located on both sides of the channel; and an intermediate layer formed between the channel and the gate group. After a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group respectively, at least one P sub-channel and at least one N sub-channel are induced in the channel, and the multi-gate transistor is equivalent to having a positive-negative-positive-negative (PNPN) structure.

Description

Technical Field

[0001] The invention relates to a multi-gate transistor and a memory device using the same. Background Art

[0002] With the rapid development of artificial intelligence (AI) and big data analysis, hardware accelerators have attracted more and more attention. As for hardware accelerators, neuromorphic computing has become the mainstream architecture due to its high computing capacity and low power consumption.

[0003] The Integrate-and-Fire (IF) circuit plays an important role in neuromorphic computing. The main function of the IF circuit is to generate precise pulses to represent data using the number of pulses. Currently, the IF circuit requires a large number of capacitors and differential amplifiers, and the IF circuit needs to add additional circuits to improve the error tolerance rate and adjust the pulse frequency. Therefore, the circuit area of ​​the IF circuit is not easy to reduce. Summary of the invention

[0004] According to an embodiment of the present invention, a multi-gate transistor is provided, comprising: a doped drain region; a doped source region; a gate group, comprising a first gate and a second gate; a channel, wherein the doped drain region and the doped source region are located on both sides of the channel; and an intermediate layer formed between the channel and the gate group. After a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, at least one P sub-channel and at least one N sub-channel are induced in the channel, and the multi-gate transistor is equivalent to having a positive-negative-positive-negative (PNPN) structure.

[0005] According to another embodiment of the present invention, a memory device is proposed, including: a memory array, including multiple memory cells, multiple word lines and multiple bit lines; a data transmission circuit coupled to the memory array; an integrated release circuit coupled to the data transmission circuit, the data transmission circuit sends multiple operation results of these cells of the memory array to the integrated release circuit, the integrated release circuit generates multiple pulses according to the operation results of these cells of the memory array, wherein a number of these pulses represents the operation results of these cells; and a control circuit coupled to the integrated release circuit and the memory array, the control circuit sends a control signal to the integrated release circuit and the memory array according to the pulses generated by the integrated release circuit, wherein the integrated release circuit includes a multi-gate transistor as described above.

[0006] According to another embodiment of the present invention, a multi-gate transistor is proposed, comprising: a doped drain region; a doped source region; a gate group, comprising a first gate and a second gate; a doped channel, the doped drain region and the doped source region being located on both sides of the doped channel; and an intermediate layer formed between the doped channel and the gate group, wherein a first gate voltage and a second gate voltage are respectively applied to the first gate and the second gate of the gate group to enhance the channel induction capability of the doped channel, and the multi-gate transistor is equivalent to having a positive-negative-positive-negative (PNPN) structure.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A functional block diagram of a memory device according to an embodiment of the present invention is shown.

[0009] FIG. 2A to FIG. 2F A schematic diagram showing a multi-gate transistor according to an embodiment of the present invention.

[0010] FIG. 3A to FIG. 3C A schematic diagram showing a multi-gate transistor according to another embodiment of the present invention.

[0011]

Explanation of symbols

[0012] 100: memory device

[0013] 110: Memory array

[0014] 120: Data transmission circuit

[0015] 130: Integrated distribution circuit

[0016] 140: Control circuit

[0017] C: Capacitor

[0018] T1: Multi-gate transistor

[0019] T2: Suppression transistor

[0020] INV: Inverter

[0021] T3: Bias transistor

[0022] G1~G3: Gate

[0023] D: Drain region

[0024] S: Source region

[0025] 210: Middle layer

[0026] 220: Undoped channel

[0027] 220_1~220_3: Subchannel

[0028] 310: Middle layer

[0029] 320: Undoped channel

[0030] 320_1~320_2: Subchannel DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0032] The technical terms in this specification refer to the customary technical terms in this field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present invention has one or more technical features. Under the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0033] Please refer to Figure 1 , which illustrates a functional module diagram of a memory device according to an embodiment of the present invention. Figure 1 The memory device 100 can be used as a neural network hardware accelerator, but the present invention is not limited thereto. The memory device 100 includes a memory array 110 , a data transporting circuit 120 , an integrated issuing circuit 130 , and a control circuit 140 .

[0034] The memory array 110 includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The architecture of the memory array 110 is not particularly limited herein. The memory cells of the memory array 110 may be used to perform operations, such as but not limited to, multiplication and accumulation (MAC) operations.

[0035] The data transmission circuit 120 is coupled to the memory array 110 , and is used to send the operation results of the cells in the memory array 110 to the integrated issuing circuit 130 .

[0036] The integrated issuing circuit 130 is coupled to the data transmitting circuit 120 , and is used to generate pulses according to the operation results of the cells of the memory array 110 , wherein the number of the pulses can represent the operation results of the cells.

[0037] The control circuit 140 is coupled to the integrated issuing circuit 130 and the memory array 110. The control circuit 140 can send a control signal to the integrated issuing circuit 130 and the memory array 110 according to the pulse generated by the integrated issuing circuit 130 to adjust the pulse frequency, thereby improving the error tolerance rate.

[0038] The integrated release circuit 130 includes a capacitor C, a multi-gate transistor T1 , an inhibitory transistor T2 , an inverter INV and a bias transistor T3 .

[0039] The capacitor C is coupled to the data transmitting circuit 120 for temporarily storing data transmitted from the data transmitting circuit 120 .

[0040] The multi-gate transistor T1 is a transistor having at least two or more gates. The details of the multi-gate transistor T1 will be described below. The multi-gate transistor T1 is coupled to the data transmission circuit 120, the inverter INV and the bias transistor T3. In particular, one of the gates of the multi-gate transistor T1 is coupled to the capacitor C, the source thereof is grounded, and the drain thereof is coupled to the inverter INV.

[0041] The suppression transistor T2 is coupled to the control circuit 140 and is controlled by a control signal transmitted by the control circuit 140. When the control signal controls the suppression transistor T2 to be turned on, the suppression transistor T2 can form a discharge path to discharge the capacitor C.

[0042] An input terminal of the inverter INV is coupled to the multi-gate transistor T1 and the bias transistor T3 , and an output terminal thereof is coupled to the control circuit 140 . The inverter INV can output a pulse to the control circuit 140 .

[0043] The gate of the bias transistor T3 receives the bias voltage VA, the source thereof is coupled to the operation voltage VDD, and the drain thereof is coupled to the inverter INV.

[0044] Please refer to FIG. 2A to FIG. 2F , which shows a schematic diagram of a multi-gate transistor T1 according to an embodiment of the present invention. FIG. 2A to FIG. 2F As shown, the multi-gate transistor T1 includes: gates G1, G2 and G3, a drain region (D), a source region (S), an interlayer 210 and an undoped channel 220. The drain region (D) is doped into a P+ region, and the source region (S) is doped into an N+ region. The drain voltage VD and the source voltage VS applied to the drain region (D) and the source region (S) are, for example but not limited to, +3V and 0V respectively. FIG. 2A to FIG. 2F, the gate G1 of the multi-gate transistor T1 is coupled to the capacitor C. The gates G1, G2 and G3 may also be referred to as a gate group. The drain region (D) and the source region (S) are located on both sides of the undoped channel 220. In the following description, the channel is taken as an example of an undoped channel, but it should be understood that the present invention is not limited thereto. In other possible embodiments of the present invention, the channel may also be a doped channel, which is also within the scope of protection of the present invention.

[0045] The intermediate layer 210 may be, for example but not limited to, a gate oxide layer or a charge storage layer. The charge storage layer may be, for example but not limited to, a floating gate or a charge trapping structure. The charge trapping structure may be, for example but not limited to, a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) layer or a Bandgap Engineered Silicon Oxide Nitride Oxide Silicon (BESONOS) layer.

[0046] According to the gate voltages VG1, VG2 and VG3 applied to the gates G1, G2 and G3, three sub-channels 220_1, 220_2 and 220_3 are induced in the undoped channel 220. Specifically, the gate voltage VG1 applied to the gate G1 may induce the sub-channel 220_1 below the gate G1; the gate voltage VG2 applied to the gate G2 may induce the sub-channel 220_2 below the gate G2; and the gate voltage VG3 applied to the gate G3 may induce the sub-channel 220_3 below the gate G3.

[0047] In particular, if the gate voltage is less than a threshold voltage (Vth), a P sub-channel will be induced under the gate; and if the gate voltage is greater than the threshold voltage (Vth), an N sub-channel will be induced under the gate.

[0048] like Figure 2C , VG1<Vth,VG2> Vth, VG3>Vth, so the three sub-channels 220_1, 220_2 and 220_3 sensed are P sub-channel, N sub-channel and N sub-channel respectively. Figure 2C From the perspective of FIG. 1 , the behavior of the multi-gate transistor T1 is like a PNPN structure, that is, from the right to the left of the figure, the drain region, the three sub-channels and the source region are respectively the P+ region, the N sub-channel, the P sub-channel, the N sub-channel and the N+ region. Therefore, it can be equivalently regarded as a PNPN (positive-negative-positive-negative) structure.

[0049] Furthermore, in the embodiments of the present invention, taking Figure 2C as an example, first apply VG1 < Vth, VG2 > Vth, VG3 > Vth to induce three sub-channels 220_1, 220_2, and 220_3 which are P sub-channel, N sub-channel, and N sub-channel respectively. After inducing these three sub-channels, the applied voltage VG1 can be removed (but the voltages VG2 and VG3 still need to be maintained to keep the channel induction). Then, when the memory device 100 is applied to AI operations, the gate voltage of the gate G1 of the multi-gate transistor T1 is determined by the capacitor C and the suppression transistor T2. That is, when the suppression transistor T2 is turned off, the cross-voltage of the capacitor C is the gate voltage of the gate G1 of the multi-gate transistor T1; and when the suppression transistor T2 is turned on, the capacitor C is discharged and the gate voltage of the gate G1 of the multi-gate transistor T1 is 0V. Therefore, when the gate voltage of the gate G1 of the multi-gate transistor T1 (i.e., the cross-voltage of the capacitor C) exceeds the threshold voltage, the multi-gate transistor T1 is turned on to output a pulse from the drain to the inverter INV; and when the gate voltage of the gate G1 of the multi-gate transistor T1 (i.e., the cross-voltage of the capacitor C) does not exceed the threshold voltage, the multi-gate transistor T1 is turned off and does not output a pulse from the drain to the inverter INV.

[0050] As Figure 2D , VG1 < Vth, VG2 < Vth, VG3 > Vth, so the three induced sub-channels 220_1, 220_2, and 220_3 are P sub-channel, P sub-channel, and N sub-channel respectively. Therefore, taking Figure 2D into consideration, the behavior of the multi-gate transistor T1 is like a PNPN structure. That is, from the right side to the left side of the drawing, the drain region, the three sub-channels, and the source region are P+ region, N sub-channel, P sub-channel, P sub-channel, and N+ region respectively. Therefore, it can be regarded as a PNPN structure.

[0051] As Figure 2E , VG1 > Vth, VG2 < Vth, VG3 > Vth, so the three induced sub-channels 220_1, 220_2, and 220_3 are N sub-channel, P sub-channel, and N sub-channel respectively. Therefore, taking Figure 2E into consideration, the behavior of the multi-gate transistor T1 is like a PNPN structure. That is, from the right side to the left side of the drawing, the drain region, the three sub-channels, and the source region are P+ region, N sub-channel, N sub-channel, P sub-channel, and N+ region respectively. Therefore, it can be regarded as a PNPN structure.

[0052] As Figure 2F , VG1 > Vth, VG2 < Vth, VG3 < Vth, so the three induced sub-channels 220_1, 220_2, and 220_3 are N sub-channel, P sub-channel, and P sub-channel respectively. Therefore, taking Figure 2F As shown, the multi-gate transistor T1 behaves as if it has a PNPN structure. That is to say, from the right side to the left side of the drawing, the drain region, the three sub-channels, and the source region are respectively a P+ region, an N sub-channel, a P sub-channel, a P sub-channel, and an N+ region. Therefore, it can be regarded as a PNPN structure.

[0053] Now, please refer to FIG. 3A to FIG. 3C , which shows a schematic diagram of the multi-gate transistor T1 according to another embodiment of the present invention. As FIG. 3A to FIG. 3C shown, the multi-gate transistor T1 includes: gates G1 to G2, a drain region (D), a source region (S), an intermediate layer 310, and an undoped channel 320. In FIG. 3A to FIG. 3C , the gate G1 of the multi-gate transistor T1 is coupled to the capacitor C.

[0054] According to the gate voltages VG1 and VG2 applied to the gates G1 and G2, two sub-channels 320_1 and 320_2 are induced in the undoped channel 320. Specifically, the gate voltage VG1 applied to the gate G1 can induce the sub-channel 320_1 under the gate G1; and the gate voltage VG2 applied to the gate G2 can induce the sub-channel 320_2 under the gate G2.

[0055] In particular, if the gate voltage is less than the threshold voltage (Vth), a P sub-channel will be induced under the gate; and if the gate voltage is greater than the threshold voltage (Vth), an N sub-channel will be induced under the gate.

[0056] As Figure 3C shown, VG1 > Vth and VG2 < Vth. Therefore, the two induced sub-channels 320_1 and 320_2 are an N sub-channel and a P sub-channel respectively. Thus, as Figure 3C shown, the multi-gate transistor T1 behaves as if it has a PNPN structure. That is to say, from the right side to the left side of the drawing, the drain region, the two sub-channels, and the source region are respectively a P+ region, an N sub-channel, a P sub-channel, and an N+ region. Therefore, it can be regarded as a PNPN structure.

[0057] Of course, the present invention is not limited to the above examples. Those skilled in the art can infer from the above description how to control the gate voltage so that the multi-gate transistor T1 behaves as if it has a PNPN structure.

[0058] In other possible embodiments of the present invention, the channel may also be a doped channel, which is also within the scope of protection of the present invention. When the channel is a doped channel, the channel sensing capability can also be enhanced by controlling the gate voltages applied to the multi-gate transistor, and the multi-gate transistor (including the doped channel) behaves like a PNPN structure. In addition, in other possible embodiments of the present invention, regardless of the doping state of the doped channel of the multi-gate transistor, the multi-gate transistor (including the doped channel) can behave like a PNPN structure by controlling the gate voltage.

[0059] In addition, in other possible embodiments of the present invention, the multi-gate transistor T1 may include four gates or more gates, and the principle thereof is as described above and will not be repeated.

[0060] In the embodiment of the present invention, the multi-gate transistor T1 has at least two gates, and its channel is not doped, but a voltage is used to control the gate to form an N sub-channel and a P sub-channel in the undoped channel.

[0061] In the embodiment of the present invention, the multi-gate transistor T1 can generate a VI (voltage-current) relationship diagram with a super-steep slope. When the multi-gate transistor T1 is turned on, the multi-gate transistor T1 can generate a pulse (the potential of the pulse is the cross voltage of the capacitor C) to the back-end inverter INV. The control circuit 140 can output a control signal to the next stage or return it to the current stage for subsequent processing.

[0062] In the embodiment of the present invention, the multi-gate transistor T1 has a very small subthreshold swing (SS), so its energy consumption is also small.

[0063] The memory device of the embodiment of the present invention can be applied to AI recognition and homeostasis operations, and has the advantages of high recognition rate and low power consumption.

[0064] In the embodiment of the present invention, the integrated transmitting circuit has a super-steep subthreshold swing multi-gate transistor, so it can completely replace the differential amplifier with a large circuit area, and can also generate precise timing pulses. In addition, by adjusting the threshold voltage of the multi-gate transistor, the multi-gate transistor itself can achieve frequency normalization, so no additional circuit is required. Therefore, the memory device of the embodiment of the present invention (which can be used to implement a hardware accelerator) has the advantage of a small circuit area.

[0065] In addition, the ultra-steep subthreshold swing multi-gate transistor has a high tolerance to process variation and circuit noise.

[0066] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, comprising: A memory array includes a plurality of memory cells, a plurality of word lines and a plurality of bit lines; a data transmission circuit coupled to the memory array; an integrated issuing circuit coupled to the data transmission circuit, the data transmission circuit sending a plurality of operation results of the cells of the memory array to the integrated issuing circuit, the integrated issuing circuit generating a plurality of pulses according to the operation results of the cells of the memory array, wherein a number of the pulses represents the operation results of the cells; and a control circuit coupled to the integrated issuing circuit and the memory array, the control circuit sending a control signal to the integrated issuing circuit and the memory array according to the pulses generated by the integrated issuing circuit, The integrated emission circuit includes a multi-gate transistor, and the multi-gate transistor includes: a doped drain region; a doped source region; A gate group, including a first gate, a second gate and a third gate; a channel, the doped drain region and the doped source region being located on two sides of the channel; and an intermediate layer formed between the channel and the gate group, Among them, after a gate voltage is applied to the first gate, the second gate and the third gate of the gate group respectively, three sub-channels are induced in the channel. If the gate voltage is less than the threshold voltage, a P sub-channel will be induced in the channel below the gate. If the gate voltage is greater than the threshold voltage, an N sub-channel will be induced in the channel below the gate, and the multi-gate transistor is equivalent to having a positive-negative positive-negative structure.

2. The memory device according to claim 1, wherein: When the first gate voltage is less than a threshold voltage, a P sub-channel is induced in the channel by a first sub-channel corresponding to the first gate; When the second gate voltage is greater than the threshold voltage, in the channel, a second sub-channel corresponding to the second gate induces an N sub-channel; as well as When a third gate voltage applied to the third gate is greater than the threshold voltage, an N sub-channel is induced in the channel in a third sub-channel corresponding to the third gate.

3. The memory device according to claim 1, wherein: When the first gate voltage is less than a threshold voltage, a P sub-channel is induced in the channel by a first sub-channel corresponding to the first gate; When the second gate voltage is less than the threshold voltage, a second sub-channel corresponding to the second gate induces a P sub-channel in the channel; as well as When a third gate voltage applied to the third gate is greater than the threshold voltage, an N sub-channel is induced in the channel in a third sub-channel corresponding to the third gate.

4. The memory device according to claim 1, wherein: When the first gate voltage is greater than a threshold voltage, in the channel, a first sub-channel corresponding to the first gate induces an N sub-channel; When the second gate voltage is less than the threshold voltage, a second sub-channel corresponding to the second gate induces a P sub-channel in the channel; as well as When a third gate voltage applied to the third gate is greater than the threshold voltage, an N sub-channel is induced in the channel in a third sub-channel corresponding to the third gate.

5. The memory device according to claim 1, wherein: When the first gate voltage is greater than a threshold voltage, in the channel, a first sub-channel corresponding to the first gate induces an N sub-channel; When the second gate voltage is less than the threshold voltage, a second sub-channel corresponding to the second gate induces a P sub-channel in the channel; as well as When a third gate voltage applied to the third gate is less than the threshold voltage, a third sub-channel corresponding to the third gate induces a P sub-channel in the channel.

6. The memory device according to claim 1, wherein: The middle layer is a gate oxide layer or a charge storage layer, and the charge storage layer is a floating gate or a charge trapping structure.

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