Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate, wherein a cell device structure for realizing a device function is arranged in the substrate; a dielectric layer above the substrate, wherein a first type of contact hole and a second type of contact hole are arranged in the dielectric layer, and the first type of contact hole and the second type of contact hole penetrate through the dielectric layer; a cell region metal electrode and a terminal region metal electrode above the dielectric layer, wherein the cell region metal electrode fills the first type of contact hole, and the terminal region metal electrode fills the second type of contact hole; and a passivation layer above the cell region metal electrode and the terminal region metal electrode, wherein part of the cell region metal electrode and part of the dielectric layer are exposed. The semiconductor device of the embodiment improves the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Semiconductor devices typically consist of a dielectric layer, a metal layer, and a passivation layer stacked sequentially on a substrate. During semiconductor device manufacturing, the metal layer and passivation layer need to be etched. Due to process requirements, both the metal layer and passivation layer must be over-etched. During the over-etching of the metal layer, the dielectric layer beneath the etched area is also etched. During the over-etching of the passivation layer, the dielectric layer in the scribe line area is etched. The reduced thickness of the etched dielectric layer allows impurities such as metal ions, moisture, and chemicals from the external atmosphere to easily penetrate into the dielectric layer and affect the electric field distribution of the cellular device structure in the substrate, thus reducing the reliability of the semiconductor device. Summary of the Invention

[0003] In view of the above problems, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which improves the stability of the electric field distribution in the cellular device structure in the substrate and improves the reliability of the semiconductor device.

[0004] According to a first aspect of the present invention, a semiconductor device is provided, comprising:

[0005] A substrate, wherein a cellular device structure for realizing device functions is disposed in the substrate;

[0006] A dielectric layer located above the substrate, wherein a first type of contact hole and a second type of contact hole are provided in the dielectric layer, and the first type of contact hole and the second type of contact hole penetrate the dielectric layer;

[0007] The cell region metal electrode and the terminal region metal electrode are located above the dielectric layer, wherein the cell region metal electrode fills the first type of contact hole and the terminal region metal electrode fills the second type of contact hole;

[0008] A passivation layer is located above the cell region metal electrode and the terminal region metal electrode, the passivation layer exposing part of the cell region metal electrode and part of the dielectric layer.

[0009] Optionally, the semiconductor device further includes: a barrier layer located between the dielectric layer and the passivation layer, the barrier layer covering the dielectric layer, the first type of contact hole and the second type of contact hole penetrating the barrier layer, and the passivation layer exposing a portion of the barrier layer.

[0010] Optionally, the passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer is located below the second passivation layer, and the sidewalls of the first passivation layer and the second passivation layer are flush.

[0011] Optionally, the passivation layer includes a first passivation layer and a second passivation layer, wherein the first passivation layer is located below the second passivation layer, and the second passivation layer covers the sidewall of the first passivation layer.

[0012] Optionally, the material of the first passivation layer includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride.

[0013] Optionally, the thickness of the first passivation layer includes to

[0014] Optionally, the material of the second passivation layer includes polyimide.

[0015] Optionally, the thickness of the second passivation layer includes 2 to 15 μm.

[0016] Optionally, the material of the barrier layer includes one or a combination of silicon nitride and silicon oxynitride.

[0017] Optionally, the material of the barrier layer includes one or a combination of materials selected from Ti, TiN, W, Al, Cu, Pt and Co.

[0018] Optionally, the thickness of the barrier layer includes to

[0019] Optionally, the etching selectivity ratio between the metal layer and the barrier layer is higher than that between the metal layer and the dielectric layer, and the etching selectivity ratio between the passivation layer and the barrier layer is higher than that between the passivation layer and the dielectric layer.

[0020] Optionally, the semiconductor device includes a scribe line region, the distance between the sidewall of the terminal metal electrode and the sidewall of the scribe line region is greater than or equal to 30 μm; and the distance between the sidewall of the terminal metal electrode and the sidewall of the first passivation layer is greater than or equal to 5 μm.

[0021] Optionally, the distance between the sidewall of the second passivation layer and the sidewall of the first passivation layer is greater than or equal to 5 μm.

[0022] Optionally, the cellular device structure includes P-type or N-type doped components, capacitors, resistors, metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, integrated circuits, flash memory, complementary metal-oxide-semiconductor, bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor, microelectromechanical systems (MEMS), and Schottky devices.

[0023] According to a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising:

[0024] Forming a cellular device structure in a substrate to realize the device function;

[0025] A dielectric layer is formed above the substrate, and a first type of contact hole and a second type of contact hole are formed in the dielectric layer, the first type of contact hole and the second type of contact hole penetrating the dielectric layer;

[0026] A cellular metal electrode and a terminal metal electrode are formed above the dielectric layer. The cellular metal electrode fills the first type of contact hole, and the terminal metal electrode fills the second type of contact hole.

[0027] A passivation layer is formed over the cell region metal electrode and the terminal region metal electrode, the passivation layer exposing a portion of the cell region metal electrode and a portion of the dielectric layer.

[0028] Optionally, after forming a dielectric layer over the substrate, the manufacturing method further includes:

[0029] A barrier layer is formed above the dielectric layer, the barrier layer covers the dielectric layer, the first type of contact hole and the second type of contact hole penetrate the barrier layer, and the passivation layer exposes a portion of the barrier layer.

[0030] Optionally, forming a passivation layer over the cell region metal electrode and the terminal region metal electrode includes:

[0031] A first passivation layer material and a second passivation layer material are sequentially deposited on top of the cell region metal electrode and the terminal region metal electrode;

[0032] Pattern the second passivation layer material to form a second passivation layer;

[0033] Using the second passivation layer as a mask, the first passivation layer material is patterned to form a first passivation layer, with the sidewalls of the first passivation layer and the second passivation layer flush.

[0034] Optionally, forming a passivation layer over the cell region metal electrode and the terminal region metal electrode includes:

[0035] A first passivation layer material is deposited over the cell region metal electrode and the terminal region metal electrode, and the first passivation layer material is patterned to form a first passivation layer;

[0036] A second passivation layer material is deposited over the first passivation layer, and the second passivation layer material is patterned to form a second passivation layer, the second passivation layer covering the sidewall of the first passivation layer.

[0037] Optionally, the material of the first passivation layer includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride.

[0038] Optionally, the thickness of the first passivation layer includes to

[0039] Optionally, the material of the second passivation layer includes polyimide.

[0040] Optionally, the thickness of the second passivation layer includes 2 to 15 μm.

[0041] Optionally, the material of the barrier layer includes one or a combination of silicon nitride and silicon oxynitride.

[0042] Optionally, the material of the barrier layer includes one or a combination of materials selected from Ti, TiN, W, Al, Cu, Pt and Co.

[0043] Optionally, the thickness of the barrier layer includes: to

[0044] Optionally, the etching selectivity ratio between the metal layer and the barrier layer is higher than that between the metal layer and the dielectric layer, and the etching selectivity ratio between the passivation layer and the barrier layer is higher than that between the passivation layer and the dielectric layer.

[0045] Optionally, the semiconductor device includes a scribe line region, the distance between the sidewall of the terminal metal electrode and the sidewall of the scribe line region is greater than or equal to 30 μm; and the distance between the sidewall of the terminal metal electrode and the sidewall of the first passivation layer is greater than or equal to 5 μm.

[0046] Optionally, the distance between the sidewall of the second passivation layer and the sidewall of the first passivation layer is greater than or equal to 5 μm.

[0047] Optionally, the cellular device structure includes P-type or N-type doped components, capacitors, resistors, metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, integrated circuits, flash memory, complementary metal-oxide-semiconductor, bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor, microelectromechanical systems (MEMS), and Schottky devices.

[0048] According to the semiconductor device and its manufacturing method provided in the embodiments of the present invention, the etching selectivity ratio of the metal layer to the barrier layer is higher than that of the metal layer to the dielectric layer (first dielectric layer and second dielectric layer). Similarly, the etching selectivity ratio of the passivation layer (first passivation layer and second passivation layer) to the barrier layer formed in subsequent processes is higher than that of the passivation layer to the dielectric layer. In the metal etching process and the passivation layer material etching process, the barrier layer effectively prevents over-etching, ensuring the integrity of the first and second dielectric layers. Impurities such as metal ions, water vapor, and chemical substances in the external atmosphere cannot penetrate the second and first dielectric layers and affect the electric field distribution of the cellular device structure in the substrate below the first dielectric layer. This improves the stability of the electric field distribution of the cellular device structure in the substrate and enhances the reliability of the semiconductor device.

[0049] Furthermore, the thickness of the first passivation layer is thinner than that of the traditional structure, resulting in less over-etching of the first passivation layer. By controlling the over-etching, the etching of the second dielectric layer and the first dielectric layer in the scribe line area is reduced, allowing the first dielectric layer and the second dielectric layer to remain intact. Impurities such as metal ions, water vapor, and chemicals in the external atmosphere cannot penetrate the second dielectric layer and the first dielectric layer and affect the electric field distribution of the cellular device structure in the substrate below the first dielectric layer. This improves the stability of the electric field distribution of the cellular device structure in the substrate and enhances the reliability of the semiconductor device.

[0050] Furthermore, the second passivation layer is made of polyimide, which has good step-filling ability, high temperature resistance, corrosion resistance, and radiation resistance. It also has excellent flexibility, which can increase the chip's impact resistance and high humidity resistance. It can effectively solve problems such as cracks and fractures caused by the mismatch between passivation layer stress and packaging process, improve the stability of device performance, and reduce reliability risks. Attached Figure Description

[0051] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0052] Figure 1 A cross-sectional schematic diagram of a semiconductor device in the related art is shown;

[0053] Figure 2 A cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention is shown;

[0054] Figures 3 to 8 A cross-sectional schematic diagram of different stages of the manufacturing method of the semiconductor device according to the first embodiment of the present invention is shown;

[0055] Figure 9 A cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention is shown;

[0056] Figures 10 to 15 The diagram shows cross-sectional schematics of different stages in the manufacturing method of a semiconductor device according to a second embodiment of the present invention. Detailed Implementation

[0057] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0058] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0059] Figure 1 A schematic cross-sectional view of a semiconductor device in the related art is shown. For example... Figure 1As shown, the semiconductor device 100 includes: a substrate 110, in which a cellular device structure (not shown) for realizing device functions is disposed; the cellular device structure includes structures such as P-type or N-type doped capacitors, resistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), and sensors. The substrate 110 includes a semiconductor substrate 111 and an epitaxial layer 112 located above the semiconductor substrate 111. A first dielectric layer 121 is located above the substrate 110; the material of the first dielectric layer 121 includes silicon dioxide. A second dielectric layer 122 is located above the first dielectric layer 121, and a first type of contact hole 131 and a second type of contact hole 132 are disposed in the first dielectric layer 121 and the second dielectric layer 122, the first type of contact hole 131 and the second type of contact hole 132 penetrating the first dielectric layer 121 and the second dielectric layer 122 and extending into the substrate 110; the material of the second dielectric layer 122 includes silicon dioxide doped with impurity ions, such as silicon dioxide doped with boron and silicon dioxide doped with phosphorus. The cell region metal electrode 141 and the terminal region metal electrode 142 are located above the second dielectric layer 122. The cell region metal electrode 141 fills the first type of contact hole 131, and the terminal region metal electrode 142 fills the second type of contact hole 132. The cell region metal electrode 141 and the terminal region metal electrode 142 are isolated from each other. It should be noted that the semiconductor device 100 includes a die 101 and a scribe line region 102. The die 101 includes a cell region and a terminal region. The terminal region includes a gate electrode region, a voltage divider ring region, and a cutoff ring region. The voltage divider ring region is located outside the cell region, and the cutoff ring region is located outside the voltage divider ring region. The cell device structure and the cell region metal electrode 141 are located in the cell region, and the terminal region metal electrode 142 is located in the terminal region. A first passivation layer 151 is located above the cell region metal electrode 141 and the terminal region metal electrode 142; a second passivation layer 152 is located above the first passivation layer 151. The sidewalls of the first passivation layer 151 are flush with each other. The first passivation layer 151 and the second passivation layer 152 expose a portion of the cell region metal electrode 141 (as an electrode lead-out window) and a portion of the first dielectric layer 121 of the scribe line region 102 (as a scribe line opening window). The material of the first passivation layer 151 includes silicon dioxide, and the thickness of the first passivation layer 151 includes [missing information]. to The material of the second passivation layer 152 includes one or more materials selected from silicon nitride and silicon oxynitride, and the thickness of the second passivation layer 152 includes... to

[0060] During the fabrication of semiconductor device 100, a metal layer 140 is deposited above the second dielectric layer 122, the metal layer 140 is patterned, and after selectively removing a portion of the metal layer 140, cell region metal electrodes 141 and terminal region metal electrodes 142 are formed. According to device performance requirements, the cell region metal electrodes 141 and terminal region metal electrodes 142 are isolated from each other. To reduce abnormalities such as gate electrode short circuits and current leakage between the gate and source electrodes caused by metal residue between the cell region metal electrodes 141 and terminal region metal electrodes 142, the metal layer 140 typically needs to be over-etched. Due to the gas characteristics of metal etching, the selectivity of silicon dioxide etching is poorly controlled, and metal over-etching can easily reach the second dielectric layer 122 or even the first dielectric layer 121. After metal etching, the remaining total thickness of the first dielectric layer 121 and the second dielectric layer 122 is T1.

[0061] A first passivation layer material and a second passivation layer material are deposited above the cell region metal electrode 141 and the terminal region metal electrode 142. The first and second passivation layer materials are then patterned. After selectively removing portions of the first and second passivation layer materials, a first passivation layer 151 and a second passivation layer 152 are formed above the cell region metal electrode 141 and the terminal region metal electrode 142. During the subsequent packaging process of the semiconductor device 100, if the passivation layer material on the portion of the cell region metal electrode 141 that serves as the electrode lead-out window is not completely removed, it can easily cause poor contact between the package and the cell region metal electrode 141, reducing the reliability of the semiconductor device 100. In the manufacturing process of the semiconductor device 100, multiple dies are fabricated on the same substrate, separated by dicing lines. After dicing, the semiconductor device 100 is formed. The passivation layer material in related technologies has high mechanical stress. If the passivation layer material in the dicing channel is not completely removed, the first passivation layer 151 and the second passivation layer 152 are prone to edge chipping and debris during die dicing, increasing the risk of die fragmentation and contamination, and reducing the reliability of the semiconductor device 100. Therefore, the first and second passivation layer materials usually need to be over-etched. Over-etching of the first and second passivation layer materials can easily etch the second dielectric layer 122 or even the first dielectric layer 121. After the first and second passivation layer materials are etched, the remaining total thickness of the first dielectric layer 121 and the second dielectric layer 122 is T2. In extreme cases, the remaining total thickness T2 of the first dielectric layer 121 and the second dielectric layer 122 is zero.

[0062] In semiconductor device 100, there is usually a stepped structure (e.g., cell region metal electrode 141 and terminal region metal electrode 142). In related technologies, the mechanical stress of the passivation layer material is difficult to adjust, the step coverage is relatively poor, and the passivation layer material on the surface of the stepped structure is prone to abnormalities such as passivation layer cracks and fractures at the step corners, which reduces the reliability of semiconductor device 100.

[0063] Figure 1 The film retention of the first dielectric layer 121, second dielectric layer 122, first passivation layer 151, and second passivation layer 152 in the semiconductor device 100 shown represents the typical film retention in the die region 101 and dicing region 102 of a power semiconductor device after metal etching and passivation layer material etching. These front-end manufacturing processes create chip-level stress. If the passivation layer material performance is poor, or the stress matching between the package and the passivation layer material is inadequate, the package of the semiconductor device 100 is prone to problems such as voids and hermeticity. During the accelerated aging test of the semiconductor device 100, the semiconductor device 100 undergoes extreme condition tests such as high temperature, high humidity, power-on, and multiple cycles, which can easily lead to abnormalities such as passivation layer fracture, ion contamination, and moisture ingress, resulting in performance failure of the semiconductor device 100. Figure 1 As shown, after the semiconductor device 100 undergoes packaging and accelerated aging testing, cracks 103, 104, 105, 106, 107, and 108 appear in the first passivation layer 151 and the second passivation layer 152. Impurities such as metal ions, water vapor, and chemicals in the external atmosphere penetrate the die etching cell region metal electrode 141 and the terminal region metal electrode 142 through cracks 103, 106, and 107, and penetrate the second dielectric layer 122 and the first dielectric layer 121 through cracks 104, 105, and 108. The thinner the remaining total thickness T1 of the first dielectric layer 121 and the second dielectric layer 122 after metal etching, the easier it is for impurities such as metal ions, water vapor, and chemicals in the external atmosphere to penetrate the remaining second dielectric layer 122 and the first dielectric layer 121, affecting the electric field distribution of the cell device structure in the substrate 110 below the first dielectric layer 121. Furthermore, the thinner the remaining total thickness T2 of the first dielectric layer 121 and the second dielectric layer 122 after etching the first passivation layer material and the second passivation layer material, the easier it is for impurities such as metal ions, water vapor, and chemical substances in the external atmosphere to penetrate from the 109 region through the remaining second dielectric layer 122 and the first dielectric layer 121 and affect the electric field distribution of the cellular device structure in the substrate 110 below the first dielectric layer 121.

[0064] Based on this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which will be described in detail below with reference to the accompanying drawings.

[0065] Figure 2 A schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention is shown. Figure 2As shown, the semiconductor device 200 includes: a substrate 210, in which a cellular device structure (not shown) for implementing device functions is disposed; the cellular device structure includes P-type or N-type doped structures, capacitors, resistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), integrated circuits (ICs), flash memory, complementary metal-oxide-semiconductor (CMOS), bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor (BCD, BIPOLAR-CMOS-DMOS), microelectromechanical systems (MEMS), and Schottky devices, etc. The substrate 210 includes a semiconductor substrate 211 and an epitaxial layer 212 located above the semiconductor substrate 211. In some embodiments, depending on product requirements, the substrate 210 may not include the epitaxial layer 212, and may only include a semiconductor substrate 211 of a specific doping type (e.g., N-type or P-type). A dielectric layer is located above the substrate 210. First contact holes 231 and second contact holes 232 are provided in the dielectric layer, extending through the dielectric layer and into the substrate 210. In some embodiments, depending on product requirements, the first contact holes 231 and second contact holes 232 may not extend into the substrate 210. The dielectric layer includes a first dielectric layer 221 and a second dielectric layer 222. The first dielectric layer 221 is located below the second dielectric layer 222. The material of the first dielectric layer 221 includes silicon dioxide, and the thickness of the first dielectric layer 221 includes... to The first dielectric layer 221 serves as the basic isolation layer for the cellular device structure in the substrate 210. The material of the second dielectric layer 222 includes silicon dioxide doped with impurity ions, such as boron-doped silicon dioxide or phosphorus-doped silicon dioxide. The thickness of the second dielectric layer 222 includes... to The second dielectric layer 222 is mainly used to planarize the surface of the semiconductor device 200 and absorb impurities such as metal ions, water vapor, and chemical substances in the external atmosphere.

[0066] The semiconductor device 200 also includes a cell region metal electrode 241 and a termination region metal electrode 242 located above the second dielectric layer 222. The cell region metal electrode 241 fills a first type of contact hole 231, and the termination region metal electrode 242 fills a second type of contact hole 232. Depending on product requirements, the cell region metal electrode 241 and the termination region metal electrode 242 can be isolated from each other or connected to each other. The cell region metal electrode 241 includes a source electrode that connects the source holes of the cell, and the termination region metal electrode 242 includes a gate electrode that connects the gate holes of the cell. It should be noted that the semiconductor device 200 includes a die 201 and a scribe line region 202. The die 201 includes a cell region and a termination region. The termination region includes a gate electrode region, a voltage divider ring region, and a cutoff ring region. The voltage divider ring region is located outside the cell region, and the cutoff ring region is located outside the voltage divider ring region. The cellular device structure and the cellular region metal electrode 241 are located in the cellular region, while the terminal region metal electrode 242 is located in the terminal region. The materials of the cellular region metal electrode 241 and the terminal region metal electrode 242 include one or a combination of materials selected from Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, and Ni.

[0067] The semiconductor device 200 also includes a passivation layer located above the cell region metal electrode 241 and the terminal region metal electrode 242. The passivation layer exposes a portion of the cell region metal electrode 241 (as an electrode lead-out window) and a portion of the second dielectric layer 222 of the scribe line region 202 (as a scribe line opening window). There is no metal residue between the cell region metal electrode 241 and the terminal region metal electrode 242, reducing anomalies such as gate electrode short circuits and current leakage between the gate and source electrodes, thus improving the reliability of the semiconductor device 200. The passivation layer material in the scribe line region 202 is thoroughly removed, making it less prone to edge chipping, debris, or other residues during die dicing, reducing the risk of die contamination by debris and further improving the reliability of the semiconductor device 200.

[0068] The passivation layer includes a first passivation layer 251 and a second passivation layer 252. The first passivation layer 251 is located below the second passivation layer 252, and the sidewalls of the first passivation layer 251 and the second passivation layer 252 are flush. The material of the first passivation layer 251 includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride. The thickness of the first passivation layer 251 includes... to Since the morphological angles of the cell region metal electrode 241 and the terminal region metal electrode 242 (which form a stepped structure on the dielectric layer) are relatively straight, and the thicker the first passivation layer 251 is, the greater the stress on the first passivation layer 251, in order to reduce the situation where the first passivation layer 251 does not cover the steps well at the corner positions of the cell region metal electrode 241 and the terminal region metal electrode 242, and to reduce the problem of cracks and fractures in the first passivation layer 251, the thickness of the first passivation layer 251 in this embodiment is thinner than that of the traditional structure, which improves the reliability of the semiconductor device 200.

[0069] During the etching process of the first passivation layer material to form the first passivation layer 251, the over-etching amount of the first passivation layer 251 is relatively small. By controlling the over-etching amount of the first passivation layer 251, the etching of the second dielectric layer 222 and the first dielectric layer 221 in the scribe line region 202 can be reduced, so that the first dielectric layer 221 and the second dielectric layer 222 remain intact. Impurities such as metal ions, water vapor, and chemical substances in the external atmosphere are not easily transmitted through the second dielectric layer 222 and the first dielectric layer 221 to affect the electric field distribution of the cell device structure in the substrate 210 below the first dielectric layer 221. This improves the stability of the electric field distribution of the cell device structure in the substrate 210 and improves the reliability of the semiconductor device 200.

[0070] The second passivation layer 252 is made of polyimide, and its thickness ranges from 2 to 15 μm. Polyimide possesses excellent high-temperature resistance, corrosion resistance, and radiation resistance, as well as superior mechanical ductility and tensile strength, which can increase the impact resistance and high-humidity resistance of the semiconductor device 200. As a protective layer for the semiconductor device 200, polyimide can effectively solve problems such as passivation layer cracks and fractures caused by stress mismatch between the passivation layer and the packaging process, thereby improving the stability and reliability of the semiconductor device 200. Polyimide is generally divided into photosensitive polyimide and non-photosensitive polyimide, and the appropriate type and thickness of polyimide can be selected according to specific process requirements.

[0071] The semiconductor device 200 also includes a barrier layer 223. The barrier layer 223 is located between a dielectric layer (first dielectric layer 221 and second dielectric layer 222) and a passivation layer (first passivation layer 251 and second passivation layer 252). The barrier layer 223 covers the dielectric layer. First type contact holes 231 and second type contact holes 232 penetrate the barrier layer 223 and the dielectric layer. The passivation layer exposes a portion of the barrier layer 223 in the scribe line region 202 (as a scribe line opening window). The material of the barrier layer 223 includes one or more of silicon nitride and silicon oxynitride. In some embodiments, the material of the barrier layer 223 includes one or more of Ti, TiN, W, Al, Cu, Pt, and Co. Choosing a metallic material for the barrier layer 223 enhances its etching resistance, but often requires additional metal etching of the barrier layer during contact hole etching and metal etching processes. The thickness of the barrier layer 223 includes... to

[0072] The etching selectivity ratio of the metal layer (the cell region metal electrode 241 and the terminal region metal electrode 242 are formed by patterned metal layers) to the barrier layer 223 is higher than that of the metal layer to the dielectric layer (the first dielectric layer 221 and the second dielectric layer 222). Similarly, the etching selectivity ratio of the passivation layer (the first passivation layer 251 and the second passivation layer 252) to the barrier layer 223 is higher than that of the passivation layer to the dielectric layer. The barrier layer 223 can effectively block over-etching during metal etching and passivation layer etching, ensuring the dielectric layer remains intact and its thickness meets design requirements. Impurities such as metal ions, water vapor, and chemicals in the external atmosphere are less likely to penetrate the second dielectric layer 222 and the first dielectric layer 221 and affect the electric field distribution of the cell device structure in the substrate 210 below the first dielectric layer 221. This improves the stability of the electric field distribution of the cell device structure in the substrate 210 and enhances the reliability of the semiconductor device 200.

[0073] The distance d1 between the sidewall of the terminal metal electrode 242 and the sidewall of the scribe line region 202 is greater than or equal to 30 μm. The distance d2 between the sidewall of the terminal metal electrode 242 and the sidewall of the first passivation layer 252 is greater than or equal to 5 μm. The larger the distance d1 between the sidewall of the terminal metal electrode 242 and the sidewall of the scribe line region 202 and the distance d2 between the sidewall of the terminal metal electrode 242 and the sidewall of the first passivation layer 251, the smaller the reliability risk introduced from the scribe line region 202 after the semiconductor device 200 is packaged.

[0074] Figures 3 to 8 A cross-sectional schematic diagram of different stages of a method for manufacturing a semiconductor device according to a first embodiment of the present invention is shown. (Reference) Figures 3 to 8 The method for manufacturing semiconductor device 200 includes the following steps.

[0075] like Figure 3 As shown, a substrate 210 is provided, in which a cellular device structure (not shown) for implementing device functions is disposed. The cellular device structure includes P-type or N-type doped structures, capacitors, resistors, MOSFETs, IGBTs, integrated circuits (ICs), flash memory, complementary metal-oxide-semiconductor (CMOS), bipolar-complementary-metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor (BCD), microelectromechanical systems (MEMS), and Schottky devices, etc. The substrate 210 includes a semiconductor substrate 211 and an epitaxial layer 212 located above the semiconductor substrate 211. In some embodiments, depending on product requirements, the substrate 210 may not include the epitaxial layer 212, and may only include a semiconductor substrate 211 with a specific doping type (e.g., N-type or P-type). The material of the substrate 210 includes, for example, group III-V semiconductors such as GaAs, InP, GaN, and SiC, and group IV semiconductors such as Si and Ge. Those skilled in the art can define various cellular device structures included in the substrate, as well as various compositional structures on the substrate surface, based on the characteristics of the product.

[0076] A dielectric layer and a barrier layer 223 are sequentially formed above a substrate 210 using one or more chemical vapor deposition processes, such as low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), HTO, and SRO. The dielectric layer includes a first dielectric layer 221 and a second dielectric layer 222. The first dielectric layer 221 is located below the second dielectric layer 222. The material of the first dielectric layer 221 includes silicon dioxide, and the thickness of the first dielectric layer 221 includes... to The first dielectric layer 221 serves as the basic isolation layer for the cellular device structure in the substrate 210. The material of the second dielectric layer 222 includes silicon dioxide doped with impurity ions, such as boron-doped silicon dioxide or phosphorus-doped silicon dioxide. The thickness of the second dielectric layer 222 includes... to The second dielectric layer 222 is mainly used to planarize the surface of the semiconductor device 200 and absorb impurities such as metal ions, water vapor, and chemicals in the external atmosphere. The barrier layer 223 is made of one or a combination of silicon nitride and silicon oxynitride. The thickness of the barrier layer 223 includes... to In some embodiments, a metal material is deposited on the second dielectric layer 222 using conventional semiconductor process techniques such as sputtering or evaporation to form a barrier layer 223. The material of the barrier layer 223 includes one or a combination of materials selected from Ti, TiN, W, Al, Cu, Pt, and Co.

[0077] The material of the barrier layer 223 has a higher etching selectivity than the materials of the first dielectric layer 221 and the second dielectric layer 222.

[0078] like Figure 4 As shown, the first dielectric layer 221, the second dielectric layer 222, and the barrier layer 223 are etched using processes such as photolithography and etching. The etched portions of the first dielectric layer 221, the second dielectric layer 222, and the barrier layer 223 form first-type contact holes 231 and second-type contact holes 232. In this embodiment, the first-type contact holes 231 and second-type contact holes 232 penetrate the first dielectric layer 221, the second dielectric layer 222, and the barrier layer 223, and extend into the substrate 210. In some embodiments, depending on product requirements, the first-type contact holes 231 and second-type contact holes 232 may not extend into the substrate 210.

[0079] like Figure 5 As shown, a metal material is deposited on top of the barrier layer 223 using conventional semiconductor process techniques such as sputtering or evaporation. The metal material fills the first type of contact hole 231 and the second type of contact hole 232 to form a metal layer 240.

[0080] It should be noted that the etching selectivity ratio between the metal layer 240 and the barrier layer 223 is higher than that between the metal layer 240 and the dielectric layers (first dielectric layer 221 and second dielectric layer 222). Similarly, the etching selectivity ratio between the passivation layers (first passivation layer 251 and second passivation layer 252) and the barrier layer 223 formed in subsequent processes is higher than that between the passivation layer and the dielectric layer. The barrier layer 223 can effectively prevent over-etching during metal etching and passivation layer etching, ensuring the dielectric layer remains intact and its thickness meets design requirements. This reduces the impact on device reliability caused by subsequent etching, which allows metal ions, moisture, and chemicals to permeate through the dielectric layer, altering the electric field distribution within the substrate 210.

[0081] like Figure 6As shown, the metal layer 240 is patterned using processes such as photolithography and etching (including wet etching and dry etching), and the remaining metal layer 240 forms the cell region metal electrode 241 and the terminal region metal electrode 242. The cell region metal electrode 241 fills the first type of contact hole 231, and the terminal region metal electrode 242 fills the second type of contact hole 232. In some embodiments, depending on product requirements, the cell region metal electrode 241 and the terminal region metal electrode 242 can be isolated from each other or connected to each other. The cell region metal electrode 241 includes a source electrode that connects the source holes of the cell, and the terminal region metal electrode 242 includes a gate electrode that connects the gate holes of the cell. It should be noted that the semiconductor device 200 includes a die 201 and a scribe line region 202. The die 201 includes a cell region and a terminal region. The terminal region includes a gate electrode region, a voltage divider ring region, and a cutoff ring region. The voltage divider ring region is located outside the cell region, and the cutoff ring region is located outside the voltage divider ring region. The cellular device structure and the cellular region metal electrode 241 are located in the cellular region, while the terminal region metal electrode 242 is located in the terminal region. The materials of the cellular region metal electrode 241 and the terminal region metal electrode 242 include one or a combination of materials selected from Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, and Ni.

[0082] In some embodiments, to reduce metal residue between the cell region metal electrode 241 and the terminal region metal electrode 242, and to reduce abnormalities such as gate electrode short circuits and current leakage between the gate electrode and the source electrode, over-etching of the metal layer 240 is typically required during the metal etching process. The barrier layer 223 effectively blocks over-etching, ensuring the integrity of the first dielectric layer 221 and the second dielectric layer 222. Impurities such as metal ions, water vapor, and chemicals in the external atmosphere are less likely to penetrate the second dielectric layer 222 and the first dielectric layer 221 and affect the electric field distribution of the cell device structure in the substrate 210 below the first dielectric layer 221. This improves the stability of the electric field distribution of the cell device structure in the substrate 210 and enhances the reliability of the semiconductor device 200.

[0083] Since dry etching can effectively reduce chip area, it is preferred in this embodiment. The morphology angles of the cell region metal electrode 241 and the terminal region metal electrode 242 obtained by dry etching are relatively straight.

[0084] like Figure 7As shown, a first passivation layer material is formed above the cell region metal electrode 241 and the terminal region metal electrode 242, and a second passivation layer material is formed above the first passivation layer material. The first passivation layer material includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride. In this embodiment, the first passivation layer material is preferably silicon nitride or silicon oxynitride. Because the morphological angles of the cell region metal electrode 241 and the terminal region metal electrode 242 (which form a stepped structure on the dielectric layer) are relatively straight, and because the thicker the first passivation layer, the greater the stress in the first passivation layer, the thickness of the first passivation layer is thinner than that of a conventional structure in order to reduce the problem of poor step coverage by the first passivation layer at the corner positions of the cell region metal electrode 241 and the terminal region metal electrode 242, as well as the problems of cracks and fractures in the first passivation layer. The thickness of the first passivation layer includes... to The second passivation layer material includes polyimide, and the thickness of the second passivation layer ranges from 2 to 15 μm. Polyimide possesses excellent high-temperature resistance, corrosion resistance, and radiation resistance, as well as excellent mechanical ductility and tensile strength, which can increase the impact resistance and high humidity resistance of the semiconductor device 200. As a protective layer for the semiconductor device 200, polyimide can effectively solve problems such as passivation layer cracks and fractures caused by mismatch between passivation layer stress and packaging processes, thereby improving the reliability of the semiconductor device 200. Polyimide is generally divided into photosensitive polyimide and non-photosensitive polyimide, and the appropriate type and thickness of polyimide can be selected according to specific process requirements.

[0085] like Figure 8 As shown, the second passivation layer material is patterned using processes such as exposure and development. The second passivation layer material above a portion of the cell region metal electrode 241 (serving as electrode line lead-out windows) and a portion of the barrier layer 243 (serving as scribe line opening windows) in the scribe line region is selectively removed, forming the second passivation layer 252. Using the remaining second passivation layer 252 as a mask, the first passivation layer material is patterned using processes such as photolithography and etching. The first passivation layer material above a portion of the cell region metal electrode 241 (serving as electrode line lead-out windows) and a portion of the barrier layer 243 (serving as scribe line opening windows) in the scribe line region is selectively removed, forming the first passivation layer 251. The sidewalls of the first passivation layer 251 and the second passivation layer 252 are flush. The first passivation layer 251 and the second passivation layer 252 expose a portion of the cell region metal electrode 241 (serving as electrode line lead-out windows) and a portion of the barrier layer 243 (serving as scribe line opening windows) in the scribe line region. The distance d1 between the sidewall of the terminal metal electrode 242 and the sidewall of the scribe line region 202 is greater than or equal to 30 μm. The distance d2 between the sidewall of the terminal metal electrode 242 and the sidewall of the first passivation layer 252 is greater than or equal to 5 μm.

[0086] In some embodiments, to ensure the complete removal of the first and second passivation layer materials in the dicing region 202 and reduce the occurrence of chipping, debris, or other residues in the first and second passivation layers 251 and 252 during die dicing, the first passivation layer material is over-etched using processes such as photolithography and etching. The barrier layer 223 effectively prevents over-etching, ensuring the integrity of the first dielectric layer 221 and the second dielectric layer 222. The thickness of the first passivation layer 251 is thinner than that of conventional structures, resulting in less over-etching of the first passivation layer 251. By controlling the over-etching amount, the etching of the second dielectric layer 222 and the first dielectric layer 221 in the dicing region 202 can be reduced, further ensuring the integrity of the first dielectric layer 221 and the second dielectric layer 222. Impurities such as metal ions, water vapor, and chemical substances in the external atmosphere are less likely to pass through the second dielectric layer 222 and the first dielectric layer 221 and affect the electric field distribution of the cell device structure in the substrate 210 below the first dielectric layer 221, thereby improving the stability of the electric field distribution of the cell device structure in the substrate 210 and improving the reliability of the semiconductor device 200.

[0087] Figure 9 A schematic diagram of the structure of a semiconductor device according to a second embodiment of the present invention is shown. Figure 9 As shown, the structure of semiconductor device 300 is similar to... Figure 2 The structure of the semiconductor device 200 shown is basically the same, except that the second passivation layer 352 covers the sidewall of the first passivation layer 351. The distance d3 between the sidewall of the second passivation layer 352 and the sidewall of the first passivation layer 351 is greater than or equal to 5 μm. Utilizing the mechanical extensibility and isolation properties of the second passivation layer 352, impurities such as metal ions, water vapor, and chemicals in the external atmosphere are prevented from passing through the second dielectric layer 322 and the first dielectric layer 321 and affecting the electric field distribution of the cell device structure in the substrate 310 below the first dielectric layer 321. This improves the stability of the electric field distribution of the cell device structure in the substrate 310 and enhances the reliability of the semiconductor device 300.

[0088] Figures 10 to 15 A cross-sectional schematic diagram of different stages of a method for manufacturing a semiconductor device according to a second embodiment of the present invention is shown. (Reference) Figures 10 to 15 The manufacturing method of semiconductor device 300 includes the following steps.

[0089] Figures 10 to 13 The manufacturing method of the semiconductor device 300 shown is similar to Figures 3 to 6 The manufacturing method of the semiconductor device 200 shown is the same, so it will not be described again here.

[0090] like Figure 14As shown, a first passivation layer material is formed over the cell region metal electrode 341 and the terminal region metal electrode 342 using conventional semiconductor process technologies such as low-pressure chemical vapor deposition (LPCVD) or ion-enhanced chemical vapor deposition (PECVD). The material of the first passivation layer includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride, and the thickness of the first passivation layer includes... to The first passivation layer material is patterned by photolithography, etching and other processes, and the first passivation layer material above part of the cell region metal electrode 341 (as electrode line lead-out window) and part of the dicing channel region barrier layer 343 (as dicing channel opening window) is selectively removed to form the first passivation layer 351.

[0091] like Figure 15 As shown, a second passivation layer material is formed above the first passivation layer 351. The second passivation layer material includes polyimide, and the thickness of the second passivation layer includes 2 to 15 μm. The second passivation layer material is patterned using processes such as photolithography, exposure, and development. The second passivation layer material above part of the cell region metal electrode 241 (as an electrode line lead-out window) and part of the blocking layer 243 (as a scribe line opening window) in the scribe line region is selectively removed, forming a second passivation layer 252. The second passivation layer 352 covers the sidewalls of the first passivation layer 351. The distance d3 between the sidewalls of the second passivation layer 352 and the sidewalls of the first passivation layer 351 is greater than or equal to 5 μm.

[0092] According to the semiconductor device and its manufacturing method provided in the embodiments of the present invention, the etching selectivity ratio of the metal layer to the barrier layer is higher than that of the metal layer to the dielectric layer (first dielectric layer and second dielectric layer). Similarly, the etching selectivity ratio of the passivation layer (first passivation layer and second passivation layer) to the barrier layer formed in subsequent processes is higher than that of the passivation layer to the dielectric layer. In the metal etching process and the passivation layer material etching process, the barrier layer effectively prevents over-etching, ensuring the integrity of the first and second dielectric layers. Impurities such as metal ions, water vapor, and chemical substances in the external atmosphere cannot penetrate the second and first dielectric layers and affect the electric field distribution of the cellular device structure in the substrate below the first dielectric layer. This improves the stability of the electric field distribution of the cellular device structure in the substrate and enhances the reliability of the semiconductor device.

[0093] The thickness of the first passivation layer is thinner than that of the traditional structure, resulting in less over-etching of the first passivation layer. By controlling the over-etching, the etching of the second dielectric layer and the first dielectric layer in the scribe line area is reduced, allowing the first dielectric layer and the second dielectric layer to remain intact. Impurities such as metal ions, water vapor, and chemicals in the external atmosphere cannot penetrate the second dielectric layer and the first dielectric layer and affect the electric field distribution of the cellular device structure in the substrate below the first dielectric layer. This improves the stability of the electric field distribution of the cellular device structure in the substrate and enhances the reliability of the semiconductor device.

[0094] The second passivation layer is made of polyimide, which has good step-filling ability, high temperature resistance, corrosion resistance, and radiation resistance. It also has excellent flexibility, which can increase the chip's impact resistance and high humidity resistance. It can effectively solve problems such as cracks and fractures caused by the mismatch between passivation layer stress and packaging process, improve the stability of device performance, and reduce reliability risks.

[0095] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: A substrate, wherein a cellular device structure for realizing device functions is disposed in the substrate; A dielectric layer located above the substrate, wherein a first type of contact hole and a second type of contact hole are provided in the dielectric layer, and the first type of contact hole and the second type of contact hole penetrate the dielectric layer; The cell region metal electrode and the terminal region metal electrode are located above the dielectric layer, wherein the cell region metal electrode fills the first type of contact hole and the terminal region metal electrode fills the second type of contact hole; A passivation layer located above the cell region metal electrode and the terminal region metal electrode, the passivation layer exposing a portion of the cell region metal electrode and a portion of the dielectric layer; A barrier layer is located between the dielectric layer and the passivation layer, the barrier layer covers the dielectric layer, a first type of contact hole and a second type of contact hole penetrate the barrier layer, the semiconductor device includes a scribe line region, the passivation layer exposes a portion of the barrier layer in the scribe line region, and the portion of the barrier layer exposed by the passivation layer in the scribe line region serves as a scribe line opening window; The passivation layer includes a first passivation layer and a second passivation layer, with the first passivation layer located below the second passivation layer. The thickness of the first passivation layer ranges from 50 Å to 5000 Å. The material of the second passivation layer includes polyimide, and the thickness of the second passivation layer ranges from 2 to 15 μm. The thickness of the barrier layer ranges from 50 Å to 2000 Å. The etching selectivity ratio between the metal electrode and the barrier layer is higher than that between the metal electrode and the dielectric layer, and the etching selectivity ratio between the passivation layer and the barrier layer is higher than that between the passivation layer and the dielectric layer. The distance between the sidewall of the terminal metal electrode and the sidewall of the dicing area is greater than or equal to 30 μm; the distance between the sidewall of the terminal metal electrode and the sidewall of the first passivation layer is greater than or equal to 5 μm.

2. The semiconductor device according to claim 1, wherein, The sidewalls of the first passivation layer and the second passivation layer are flush.

3. The semiconductor device according to claim 1, wherein, The second passivation layer covers the sidewall of the first passivation layer.

4. The semiconductor device according to claim 2 or 3, wherein, The material of the first passivation layer includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride.

5. The semiconductor device according to claim 1, wherein, The barrier layer is made of one or a combination of silicon nitride and silicon oxynitride.

6. The semiconductor device according to claim 1, wherein, The material of the barrier layer includes one or a combination of materials selected from Ti, TiN, W, Al, Cu, Pt and Co.

7. The semiconductor device according to claim 3, wherein, The distance between the sidewall of the second passivation layer and the sidewall of the first passivation layer is greater than or equal to 5 μm.

8. The semiconductor device according to claim 1, wherein, The cellular device structures include P-type or N-type doped capacitors, resistors, metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, flash memory, bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor systems, microelectromechanical systems (MEMS), and Schottky devices.

9. A method for manufacturing a semiconductor device, comprising: Forming a cellular device structure in a substrate to realize the device function; A dielectric layer is formed above the substrate, and a first type of contact hole and a second type of contact hole are formed in the dielectric layer, the first type of contact hole and the second type of contact hole penetrating the dielectric layer; A cellular metal electrode and a terminal metal electrode are formed above the dielectric layer. The cellular metal electrode fills the first type of contact hole, and the terminal metal electrode fills the second type of contact hole. A passivation layer is formed above the cell region metal electrode and the terminal region metal electrode, the passivation layer exposing a portion of the cell region metal electrode and a portion of the dielectric layer; After forming a dielectric layer over the substrate, a barrier layer is formed over the dielectric layer, the barrier layer covers the dielectric layer, a first type of contact hole and a second type of contact hole penetrate the barrier layer, the semiconductor device includes a scribe line region, the passivation layer exposes a portion of the barrier layer in the scribe line region, and the portion of the barrier layer exposed by the passivation layer in the scribe line region serves as a scribe line opening window; The passivation layer includes a first passivation layer and a second passivation layer, with the first passivation layer located below the second passivation layer. The thickness of the first passivation layer ranges from 50 Å to 5000 Å. The material of the second passivation layer includes polyimide, and the thickness of the second passivation layer ranges from 2 to 15 μm. The thickness of the barrier layer ranges from 50 Å to 2000 Å. The etching selectivity ratio between the metal electrode and the barrier layer is higher than that between the metal electrode and the dielectric layer, and the etching selectivity ratio between the passivation layer and the barrier layer is higher than that between the passivation layer and the dielectric layer. The distance between the sidewall of the terminal metal electrode and the sidewall of the dicing area is greater than or equal to 30 μm; the distance between the sidewall of the terminal metal electrode and the sidewall of the first passivation layer is greater than or equal to 5 μm.

10. The manufacturing method according to claim 9, wherein, Forming a passivation layer over the cell region metal electrode and the terminal region metal electrode includes: A first passivation layer material and a second passivation layer material are sequentially deposited on top of the cell region metal electrode and the terminal region metal electrode; Pattern the second passivation layer material to form the second passivation layer; Using the second passivation layer as a mask, the first passivation layer material is patterned to form the first passivation layer, with the sidewalls of the first passivation layer and the second passivation layer flush.

11. The manufacturing method according to claim 9, wherein, Forming a passivation layer over the cell region metal electrode and the terminal region metal electrode includes: A first passivation layer material is deposited over the cell region metal electrode and the terminal region metal electrode, and the first passivation layer material is patterned to form the first passivation layer; A second passivation layer material is deposited over the first passivation layer, and the second passivation layer material is patterned to form the second passivation layer, which covers the sidewalls of the first passivation layer.

12. The manufacturing method according to claim 10 or 11, wherein, The material of the first passivation layer includes one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride.

13. The manufacturing method according to claim 9, wherein, The barrier layer is made of one or a combination of silicon nitride and silicon oxynitride.

14. The manufacturing method according to claim 9, wherein, The material of the barrier layer includes one or a combination of materials selected from Ti, TiN, W, Al, Cu, Pt, and Co.

15. The manufacturing method according to claim 11, wherein, The distance between the sidewall of the second passivation layer and the sidewall of the first passivation layer is greater than or equal to 5 μm.

16. The manufacturing method according to claim 9, wherein, The cellular device structures include P-type or N-type doped capacitors, resistors, metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, flash memory, bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor systems, microelectromechanical systems (MEMS), and Schottky devices.

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