Shallow trench isolation (STI) structure for suppressing dark current and forming method

Abstract

A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench having a greater depth and width than the target STI structure and epitaxially growing a substrate material in the trench for a length of time necessary to provide a target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a greater depth and width than a depth and width of the STI structure and a semiconductor material epitaxially grown in the trench to provide a critical dimension and a target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region, and an STI structure between the photodiode region and the pixel transistor region.

Description

TECHNICAL FIELD

[0001] A shallow trench isolation (STI) structure for suppressing dark current and a method of forming are disclosed. BACKGROUND

[0002] Wafer-level manufacturing using complementary metal-oxide-semiconductor (CMOS) technology has enabled the incorporation of camera modules in many applications including automotive, security, and mobile devices. For example, Figure 1 A camera 190 is depicted imaging a scene. The camera 190 includes an image sensor 100 that includes a pixel array 154. In an implementation, the pixel array 154 is an array of individual pixels formed in a semiconductor wafer substrate such as silicon. Similar cameras used in automotive applications include, for example, rear-facing cameras, as well as front- and side-facing cameras.

[0003] There is a continuing demand for higher resolution in image sensors, preferably achieved by increasing the number of pixels on a wafer while keeping the overall image sensor at the same size or smaller. The more pixels in an image sensor, the greater the resolution of the image captured by the image sensor. This can be achieved by reducing the size of the pixels so that more pixels can be placed on the wafer, or by reducing the space between the pixels.

[0004] Each pixel in an image sensor includes several devices, including, for example, a photodiode and multiple transistors. For efficient operation, the devices in an image sensor must be electrically isolated from one another. However, as the size of the pixels becomes smaller, device isolation becomes more difficult, particularly in terms of current leakage between the devices. Shallow trench isolation (STI) is a semiconductor processing technique that etches trenches in the wafer substrate to isolate the pixels and individual devices within the pixels, however, this technique often results in trap-assisted tunneling and increased dark current, especially when used in high temperature environments such as those often found in automotive applications.

[0005] Figure 2A and Figure 2B is a cross-sectional view of the STI structure during manufacturing. Referring to Figure 2AThe substrate 202 is formed of silicon, although other semiconductor materials can be used, such as bulk substrate silicon doped with n-type or p-type dopants, silicon-on-insulator (SOI) substrates, silicon germanium, or gallium arsenide. A pad oxide layer 204 is grown on the substrate 202, and then a mask layer of pad nitride layer 206 is formed on the pad oxide layer 204. After a photolithography process to pattern the pad nitride layer 206, a trench 208 is etched through the pad oxide layer 204 and the pad nitride layer 206 and into the substrate 202 by a process of isotropic dry etching, such as plasma etching. The trench 208 has a target width, which refers to a critical dimension CD and a target depth TD based on requirements of subsequent device fabrication on the substrate 202.

[0006] Figure 2B The completed STI structure is shown after additional processing steps, including, for example, pad oxidation, oxide fill, chemical mechanical polishing (CMP), and nitride removal. The trench 208 is filled with oxide 210 that forms an oxide cap 214. A thin oxide layer 212 remains on the active portion of the substrate 202 in preparation for further processing. The width of the oxide cap 214 is slightly less than the STI boundary, as shown by gap G. This is a result of the nitride removal etch process, which also typically removes a portion of the oxide.

[0007] Silicon dangling bonds on the walls and bottom of the trench 208 created by the etching can contribute to increased dark current. Dangling or broken bonds formed along the trench sidewalls or between the silicon dioxide and silicon interfaces form trap sites. These trap sites can capture electrons or holes during operation, generating current within or near the photodiode region of the respective pixel, and contribute to the generation of dark current or current in the photodiode region in the absence of incident light. One method to address this issue is a surface treatment process of thermal anneal and pad oxidation, which grows a thin oxide layer on the STI structure sidewalls, however, this method still leaves enough Si dangling bonds that contribute to dark current. Another method is boron implantation to passivate the STI-Si interface, however, boron diffuses into the silicon around the trench and thus impacts the full well capacity of the photodiode by reducing the photodiode area. Thus, these processes do not completely address the silicon dangling bonds. SUMMARY

[0008] In a first aspect, a method of forming a target shallow trench isolation (STI) structure in a semiconductor substrate includes etching a trench having a bottom and sidewalls in the semiconductor substrate, the trench having a depth (D) that is deeper than a target depth (TD) of the target STI structure and a width (W) that is wider than a critical dimension (CD) of the target STI structure; and reducing the depth and the width of the trench by epitaxially growing semiconductor material in the trench until the depth reaches the target depth and the width equals the critical dimension.

[0009] In a second aspect, a shallow trench isolation (STI) structure having a target depth TD and a critical dimension CD includes: a semiconductor substrate having a planar region of a substrate top surface forming a trench extending into the semiconductor substrate and having a trench depth D relative to the planar region of the substrate top surface surrounding the trench such that D is greater than TD, and a trench width W at the substrate top surface such that W is greater than CD; and a semiconductor material epitaxially grown in the trench to provide the STI structure having a depth equal to TD and a critical dimension equal to CD. W， In a second aspect, a shallow trench isolation (STI) structure having a target depth TD and a critical dimension CD includes: a semiconductor substrate having a planar region of a substrate top surface forming a trench extending into the semiconductor substrate and having a trench depth D relative to the planar region of the substrate top surface surrounding the trench such that D is greater than TD, and a trench width W at the substrate top surface such that W is greater than CD; and a semiconductor material epitaxially grown in the trench to provide the STI structure having a depth equal to TD and a critical dimension equal to CD.

[0010] In a third aspect, an image sensor includes: a semiconductor substrate; a photodiode region including one or more photodiodes formed in a planar region of a substrate top surface of the semiconductor substrate; a pixel transistor region including one or more pixel transistors formed in the planar region of the substrate top surface; a shallow trench isolation (STI) structure formed between the photodiode region and the pixel transistor region, the STI structure having a target depth TD and a critical dimension CD, the STI structure including a trench extending into the semiconductor substrate and having a trench depth D relative to the planar region of the substrate top surface surrounding the trench such that D is greater than TD, and a trench width W at the substrate top surface such that W is greater than CD; and a semiconductor material epitaxially grown in the trench to provide the STI structure having a depth equal to TD and a critical dimension equal to CD. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 A camera including an image sensor in an embodiment is depicted.

[0012] Figure 2A and Figure 2B is a cross-sectional view of a shallow trench isolation (STI) structure.

[0013] Figure 3A is a cross-sectional view of a trench etched in a semiconductor substrate according to an embodiment.

[0014] Figure 3B is a cross-sectional view of the STI in a subsequent manufacturing step in an embodiment. Figure 3A is a cross-sectional view of the STI in a subsequent manufacturing step in an embodiment.

[0015] Figure 3C is a cross-sectional view of the STI in a subsequent manufacturing step in an embodiment. Figure 3B is a cross-sectional view of the STI in a subsequent manufacturing step in an embodiment.

[0016] Figure 3D is a cross-sectional view of the STI in a subsequent manufacturing step in an embodiment. Figure 3C is a cross-sectional view of the STI in a subsequent manufacturing step in an embodiment.

[0017] Figure 3Eis a cross-sectional view of an STI structure according to an embodiment.

[0018] Figure 4 is a flowchart showing a method for fabricating an STI structure in an embodiment.

[0019] Figure 5A is a pixel layout of an image sensor including an STI isolation structure in an embodiment.

[0020] Figure 5B is a cross-sectional view of a cut line B- Figure 5A of an STI structure in an embodiment. of an STI structure in an embodiment. DETAILED DESCRIPTION

[0021] In an embodiment, a target shallow trench isolation (STI) structure having a width (often referred to as a critical dimension (CD)) and a target depth (TD) can be formed in a wafer substrate. The STI formation in the wafer substrate is performed prior to fabricating photodiodes, transistors, and other devices in the substrate. The CD of the STI structure significantly affects the density of the pixels, and thus the performance of the image sensor. Figures 3A to 3E Several stages in the formation of an STI structure according to an embodiment are depicted. Figures 3A to 3E The following description is best understood together with the figures in the following order:

[0022] Figure 3A is a cross-sectional view of a substrate 302, a pad oxide layer 304, and a pad nitride layer 306. In an embodiment, the substrate 302 is formed of silicon, although other semiconductor materials can be used, such as bulk substrate silicon doped with n-type or p-type dopants, silicon on insulator (SOI) substrates, silicon germanium, etc. The pad oxide layer 304 can be formed by a thermal oxidation process to form a thin oxide layer on a planar surface 305 (e.g., a front side surface) of the substrate 302. In one example, a pad nitride layer 306 can be formed on the pad oxide layer 304, such as by depositing a silicon nitride material on the pad oxide layer 304 using a deposition process, such as a chemical vapor deposition or physical vapor deposition process. The pad nitride layer 306 is used in a photolithography process to pattern the surface of the substrate 302 for etching a trench 308.

[0023] The trench 308 is patterned and etched through the pad oxide layer 304 and the pad nitride layer 306 and into the substrate 302 by a process of isotropic dry etching (e.g., plasma etching). In an embodiment, the isotropic dry etching parameters depend on the material of the substrate 302 and include pressure, gas composition (e.g., oxygen O2, fluorine gas, SF6, CF4, CHF3, C4F8), gas generation or injection method, and generator power. As material is removed from the trench 308, the etching process leaves silicon (Si) dangling bonds 310 on the sidewalls and bottom of the trench. For clarity of illustration, the Figure 3ANot all Si dangling bonds are labeled with reference numbers.

[0024] In embodiments, the trench 308 is etched into the substrate 302 to a depth D that is deeper than a target depth (TD) of the target STI structure, and to a width W that is wider than a critical dimension (CD) of the target STI structure. In embodiments, the depth D and the target depth (TD) refer to a depth or distance from a planar surface 305 of the substrate 302 (e.g., a front side surface of the substrate 302 or a substrate top surface of the substrate 302) into the substrate 302. After etching, the trench 308 can be subjected to a surface treatment process to remove some Si defects and reduce the moisture at the trench surface, e.g., SiConi TM and a hydrogen bake. For example, SiConi TM is a soft dry chemical etch process (e.g., plasma) that can selectively remove oxidized silicon surface defects by exposing the area to be etched to an etchant such as H2, HF3, and NH3. A hydrogen bake is a subsequent surface cleaning process to remove the presence of oxide on the silicon interface. However, these processes cannot remove all Si dangling bonds created by the etching.

[0025] Figure 3B is a cross-sectional view of the substrate 302 after an epitaxial growth process. The depth D and width W of the trench 308 have been reduced by the epitaxial growth region 312. A semiconductor material corresponding to the material of the substrate 302 is grown on the sidewalls and bottom of the trench 308 within the epitaxial growth region 312, as indicated by the arrows 314. In general, epitaxy is a process of forming a new layer on a substrate with a crystal structure that is aligned with the crystal structure of the substrate, as opposed to other techniques that result in random crystal orientation. In embodiments, the epitaxial growth process is performed at a temperature of about 700 °C to 750 °C using, for example, BH3 (borane) and SiH4 (silane) vapor phase epitaxy. Although a representative example is given, any suitable epitaxial growth process can be used.

[0026] The parameters of the epitaxial growth process, such as length of time, growth rate, and temperature, are selected to grow the substrate material on the bottom and sides of the trench 308 such that the trench is reduced to the CD and TD of the target STI structure. In embodiments, the depth of the trench 308 is reduced by an amount x of about 50 to 500 Angstroms by the epitaxial growth process. Due to the geometry of the trench 308, the sidewall growth rate is about 25-35% of the trench bottom growth rate. In embodiments, each sidewall experiences epitaxial growth where the coefficient a is between about 0.25 to 0.35. This results in a range of about 15 to 150 Angstroms on each sidewall.

[0027] Because the substrate material is epitaxially grown on the surfaces of the trenches 308, the Si dangling bonds 310 on the sidewalls and the bottom of the trenches 308 are solidified as shown. Incorporating the epitaxial growth step in the STI structure fabrication means that the material grown in the trenches 308 has a crystal structure that is aligned with the crystal structure of the substrate 302. Subsequent STI processing steps are shown in Figure 3C and Figure 3D . Figure 3C is a cross-sectional view of the substrate 302 after a liner oxidation step, in which a thin oxide layer is grown in the trenches 308 and an oxide gap fill is performed, in which a dielectric material 316 (e.g., silicon oxide) is deposited, filling the trenches 308 and covering the liner nitride layer 306. A subsequent chemical mechanical polishing (CMP) process is performed to planarize the dielectric material layer 309 for subsequent processing steps.

[0028] Figure 3D is a cross-sectional view of the substrate 302 after a processing step in which excess dielectric material 316 is removed from the planar surface of the liner nitride layer 306. This step also removes a portion of the dielectric material 316 that has filled the trenches 308 within the liner nitride layer 306, as shown at 317. Subsequently, the nitride mask or liner nitride layer 306 is removed by an anisotropic etching process (e.g., a wet etching process) similar to the process used to pattern the substrate 302 prior to etching the trenches 308, as shown in Figure 3A .

[0029] Figure 3E is a cross-sectional view of an embodiment of the STI structure 318 with the CD and TD of the target STI structure. The STI structure 318 includes an oxide cap 322 that protrudes from the planar surface 305 of the substrate 302 and spans between the opposite sides of the trench 308 on the planar surface 305. The anisotropic etching process described above with reference to Figure 3D also removes a portion of the liner oxide layer 304 and the oxide cap 322. In embodiments, the height h of the oxide cap 322 (e.g., the distance between the planar top surface of the oxide cap 322 and the planar top surface of the liner oxide layer 304) is related to the initial thickness of the liner nitride layer 306 and the liner oxide layer 304 and the etching process used to remove the liner nitride layer 306.

[0030] In embodiments, the width W of the oxide cap 322 Figure 3A is related to the width W of the trench 308 of W and is greater than the CD of the STI structure 318. For example, this width Figure 3B of the oxide cap 322 is related to the thickness of the epitaxial sidewall growth (e.g., as shown in W .The thickness of the epitaxial growth region 312 shown is related to this, and provides a better profile for the STI structure 318. This is because the pad nitride layer 306 is etched to have a width... W The opening of the groove 308 ( Figure 3A Therefore, the subsequent deposition of dielectric material 316 ( Figure 3C This results in a wider area of ​​dielectric material within the pad nitride layer 306, for example, with Figure 2A Compared to the pad nitriding layer 206, the pad nitriding layer 306 has the same openings for the trench 208 as the CD of the trench 208. Figure 3E In the process, the oxide cap 322 is wider than the CD of the STI structure 318, extending across the boundary of the STI structure 318 (or the interface between the substrate and the dielectric material 316) to at least a lateral distance from the flat surface 305 of the substrate 302 (e.g., the front surface or the top surface of the substrate). d .

[0031] The oxide cap 322 prevents the corner 320 of the STI structure 318 from being exposed. Despite... Figure 3E Only one corner is shown, but the following discussion applies to both sides of the oxide cap 322 in the illustrated cross-sectional view. When corner 320 is exposed, as... Figure 2B As shown in the gap G, when the gate electrode is formed in the substrate 302, this can lead to TDDB (Time-Dependent Dielectric Breakdown) failure due to gate leakage. This, in turn, can lower the threshold voltage of nearby transistor devices (e.g., source follower, reset transistor, row select transistor). The overlapping region 324 (represented by the circled region) of the oxide cap 322 and the pad oxide layer 304 (used as the gate oxide of the transistor device) minimizes TDDB failures and improves the reliability of devices (e.g., image sensor devices) incorporated into the STI structure 318.

[0032] Figure 4 This is a flowchart illustrating a method 400 for manufacturing an STI structure according to an embodiment. Method 400 includes steps 412 and 414. In an embodiment, method 400 further includes at least one of steps 402, 404, 406, 408, 410, and 416. In an embodiment, method 400 further includes step 414.

[0033] Step 402 includes preparing, for example Figure 3A The semiconductor substrate shown has a pad oxide layer and a pad nitride layer. In the example of step 402, a pad oxide layer 304 and a pad nitride layer 306 are formed on the substrate 302, but other semiconductor materials may also be used. In embodiments, various methods may be used to form the pad oxide layer 304 and the pad nitride layer 306, as referenced above. Figure 3AThe pad nitride layer 306 is used in the photolithography process to pattern the surface of the substrate 302 in preparation for etching trenches 308.

[0034] Step 404 includes defining the critical dimension (CD) and target depth (TD) of the target STI structure. In an example of step 404, the CD and TD of the target STI structure are selected based on the preferred pixel density and preferred performance of the image sensor formed in the substrate. Step 406 includes selecting parameters for the epitaxial growth process. In an example of step 406, the selected parameters will provide... x growth and coefficient of bottom thickness α Between 0.25 and 0.35 The growth of sidewall thickness. This produces approximately 15 to 150 angstroms on each sidewall. The range.

[0035] Step 408 includes determining Figures 3A to 3E The etching width of trench 308. In the example of step 408, the width is determined. W The width W Basically equal to CD plus sidewall thickness twice as much, of which It is positive and less than or equal to 1. In the implementation, the coefficient... Between 0.25 and 0.35. Step 410 includes determining a depth D, which is substantially equal to TD plus the bottom thickness x. In an implementation, steps 406 to 410 can be performed in any order and / or iteratively.

[0036] Step 412 includes patterning and etching trench 308. In one embodiment, step 412 includes patterning trench 308 prior to the etching process. In an example of step 412, at least one parameter of the etching process is selected to produce trench 308 having a width W and depth D as determined in steps 408 and 410. Step 414 includes performing an epitaxial growth process according to the parameters selected in step 406.

[0037] Step 416 may include the remaining semiconductor manufacturing steps, including those described above and Figures 3C to 3D The pads shown are oxidized, dielectric filled (e.g., oxide filled), chemically mechanically polished (CMP), and nitride removed.

[0038] In implementations, the above-described method 400 and STI structure 318 provide additional benefits in forming trenches on a substrate using nitride as a mask. Photolithography processes have a lower effective limit on the size of a region that can be effectively masked. This also limits the critical dimension (e.g., target trench width) that can be achieved for a target STI structure. In implementations, a target STI structure can be formed that is even smaller than the lower photolithography patterning limit by etching a trench at the patterning limit and then epitaxially growing additional substrate material in the trench. This further reduces the space of the STI (spacer between photodiode region and pixel transistor region) and increases the area on the substrate for photodiodes, thus a larger size pixel array can be formed, enabling higher imaging resolution.

[0039] The method 400 provides a shallow trench isolation structure that has no Si dangling bonds on the bottom and sidewalls of the trench created by the plasma etch, as silicon is epitaxially grown on these surfaces, thus fixing the Si dangling bonds. In implementations, any type of substrate can be used, including doped silicon, as doped silicon can also be epitaxially grown to match the substrate. This provides a doped substrate that has no silicon surface damage caused by boron implantation doping.

[0040] Figure 5A A partial pixel layout of an image sensor is depicted. Figure 5B A cross-sectional view along the cut line B-B of Figure 5A of FIG. 4A is depicted. A cross-sectional view along the cut line B-B of Figure 5A and Figure 5B The following description is best understood when read in conjunction with the accompanying drawings. Figure 5A is a plan view showing two adjacent pixels separated by an STI isolation structure according to an implementation. Each pixel includes a substrate having an active region (or light sensing region) 500 and a pixel transistor region 514. A photodiode 502, a transfer transistor 504, and a floating diffusion node 506 are formed in the active region of the substrate. Each of the transfer transistors 504 selectively transfers photo-generated charge from the corresponding photodiode 502 to the corresponding floating diffusion node 506 in response to a transfer signal received at a transfer gate 503 of the corresponding transfer transistor 504. The photodiode 502 and the floating diffusion node 506 are formed of a doped region having a first conductivity type (e.g., N-type opposite to a substrate having a second conductivity type (e.g., P-type)). The polarity of the conductivity types can be reversed depending on the circuit design. Pixel transistors such as a reset transistor 508, a source follower transistor 510, and a row select transistor 512 are formed in the pixel transistor region 514 of the substrate adjacent to the active region. The photodiode 502 in the active region 500 is isolated from the pixel transistors in the pixel transistor region 514 by STI structures 516 and 518, which correspond toFigure 3E The STI structure 318. In some embodiments, relative to the front side 540a of the substrate ( Figure 5B The junction depth of the source and drain regions associated with each corresponding pixel transistor in pixel transistor region 514 is less than or shallower than the target depth (TD) of the individual STI structures 516 and 518.

[0041] In one example, the reset transistor 508, the source follower transistor 510, and the row select transistor 512 are N-channel transistors. In such an example, the source and drain regions of each of the reset transistor 508, the source follower transistor 510, and the row select transistor 512 are N-type doped regions, that is, doped regions of a second conductivity type opposite to the first conductivity type of the substrate.

[0042] In the example shown, refer to Figure 5B The photodiode 502 is separated by the pixel transistor region 514, such as Figure 5A As shown in the plan view. In an embodiment, the pixel transistor region 514 includes STI structures 516 and 518 formed in a well region of a first conductivity type (hereinafter referred to as P-type well 520) and deep trench isolation structures 522, 524. The P-type well 520 is used to provide further passivation to the sidewalls of the STI structures 516 and 518 around the STI structures 516 and 518. The deep trench isolation structures 522 and 524 are located below the STI structures 516 and 518, respectively. In one embodiment, deep trench isolation structures 522 and 524 with a dielectric-filled material are formed on the back side 540b of the substrate. The deep trench isolation structures 522 and 524 are configured to extend from the back side 540b of the substrate into the substrate and land on the bottom of the respective STI structures 516 and 518. A pinning layer 534 is provided to passivate the silicon oxide / silicon interface between the oxide layer 536 and the silicon surface of the photodiode 502 to reduce dark current noise associated with the silicon oxide / silicon interface. Pinning layer 534 is a doped region of the same first conductivity type as the P-well 520 and the substrate. In one example, pinning layer 534 is configured to have a higher doping concentration than the P-well 520. Pinning layer 534 and P-well 520 are grounded. In the embodiment, STI structures 516 and 518, along with deep trench isolation structures 522 and 524, collectively isolate pixel transistors (e.g., reset transistors, source follower transistors, and row select transistors) from photodiodes 502 disposed in the active region 500.

[0043] In some embodiments, deep trench isolation structures 522, 524 may also be disposed between adjacent photodiodes 502, providing electrical isolation between adjacent photodiodes 502.

[0044] The source follower gate 510g of the source follower transistor 510 is located between the oxide caps 526 and 528 of the STI structures 516 and 518, respectively, as shown in cross-sectional view A-A'. (Refer to the above text) Figure 3E The overlap region 532 of the oxide cap 528 discussed protects the corner 530 of the STI structure 518. This is to minimize TDDB failures and improve the reliability of devices (e.g., image sensor devices) incorporated into the STI structure 518. Although in Figure 5B Only one corner is marked, but both corners of oxide caps 528 and 526 are similarly protected. Similar benefits also apply to reset transistor 508 and row select transistor 512.

[0045] For the sake of simplicity, in Figure 5A The diagram shows two photodiodes per pixel, but in other embodiments, a pixel may include more or fewer photodiodes. Similarly, the pixel layout shown illustrates a "four-transistor configuration," where the pixel transistors for each corresponding pixel include a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor. In some embodiments, a pixel may be configured as a "three-transistor configuration," including only a transfer transistor, a reset transistor, and a source follower transistor. In some embodiments, a pixel may be configured as a "five-transistor configuration," including a transfer transistor, a row select transistor, a source follower transistor, a reset transistor (and an overflow transistor or a double floating diffuse (DFD) transistor). Therefore, the number of photodiodes in a pixel and the number of pixel transistors used to control pixel operation can depend on the configuration of the relevant pixels.

[0046] By using STI structures 516 and 518 in the isolation between the photodiode and pixel transistor regions of the image sensor, dark current and white pixel noise can be reduced, and the imaging performance of the image sensor can be improved.

[0047] Combination of features

[0048] Without departing from the scope of this disclosure, the features described above and those claimed below can be combined in various ways. The following examples illustrate some possible non-limiting combinations:

[0049] (A1) A method for forming a target shallow trench isolation (STI) structure in a semiconductor substrate, comprising etching a trench having a bottom and sidewalls in the semiconductor substrate, the trench having a depth (D) greater than a target depth (TD) of the target STI structure and a width (W) greater than a critical dimension (CD) of the target STI structure; reducing the depth and width of the trench by epitaxially growing semiconductor material in the trench until the depth reaches the target depth and the width is equal to the critical dimension.

[0050] (A2) In method (A1), the semiconductor material can be epitaxially grown at a temperature between about 700 °C and 750 °C.

[0051] (A3) In method (A1), the epitaxially grown semiconductor material may be the same as the semiconductor substrate.

[0052] (A4) In any of the methods (A1) to (A3), the semiconductor substrate and the epitaxially grown semiconductor material may be formed from silicon.

[0053] (A5) In method (A4), the semiconductor material grown epitaxially is doped silicon.

[0054] (A6) Any of the methods (A1) to (A5) may further include oxidizing the semiconductor substrate to form an oxide layer on the surface of the semiconductor substrate.

[0055] (A7) Method (A6) may also include filling the trench with oxide.

[0056] (A8) Method (A7) may also include forming an oxide cap having a width and height h greater than CD above the top surface of the substrate.

[0057] (A9) In any of the methods (A1) to (A8), the T-TD can be between about 50 and 500 angstroms.

[0058] (A10) In any of methods (A1) through (A9), It can be between approximately 15 and 150 angstroms.

[0059] (A11) In any of the methods (A1) to (A10), when the substrate may have a top surface, the method may further include forming a target STI structure in the top surface and forming a photodiode and at least one pixel transistor in the top surface on the opposite side of the target STI structure.

[0060] (B1) A shallow trench isolation (STI) structure having a target depth TD and a critical size CD, comprising a semiconductor substrate having a top surface of the substrate, the top surface of the substrate forming a trench extending into the semiconductor substrate, the trench having a trench depth D relative to a flat region of the top surface of the substrate surrounding the trench such that D is greater than TD, and having a trench width W at the top surface of the substrate such that W is greater than CD; and a semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth equal to TD and a critical size equal to CD.

[0061] (B2) In structure (B1), the epitaxially grown semiconductor material is the same as the semiconductor substrate.

[0062] (B3) In structure (B2), the semiconductor substrate and the epitaxially grown semiconductor material can be formed from silicon.

[0063] (B4) In structure (B3), the epitaxially grown semiconductor material is doped silicon.

[0064] (B5) Any of structures (B1) to (B4) may further include an oxide filling the trench.

[0065] (B6) Any of structures (B1) to (B5) may further include a width and height greater than CD above the top surface of the substrate. h Oxide cap.

[0066] (B7) In any of the structures (B1) to (B6), the T-TD can be between approximately 50 and 500 angstroms.

[0067] (B8) In any of the structures (B1) to (B7), It can be between approximately 15 and 150 angstroms.

[0068] (B9) In any of the structures (B1) to (B8), the STI structure may be disposed on the wafer between at least one photodiode and at least one pixel transistor formed on the wafer.

[0069] (C1) An image sensor, comprising: a semiconductor substrate; a photodiode region having one or more photodiodes formed in a flat region on a top surface of the semiconductor substrate; a pixel transistor region including one or more pixel transistors formed in a flat region on a top surface of the substrate; and an STI structure according to any one of embodiments (B1) to (B9), which is formed between the photodiode region and the pixel transistor region according to any one of the method embodiments (A1) to (A11).

[0070] Modifications may be made to the methods and systems described above without departing from the scope of this disclosure. Therefore, it should be noted that the content included in the above description or shown in the accompanying drawings should be interpreted illustratively, not restrictively. In this document, unless otherwise stated: (a) the adjective “exemplary” means used as an example, instance, or illustration, and (b) the phrase “in an embodiment” is equivalent to the phrase “in some embodiments” and does not refer to all embodiments. The appended claims are intended to cover all the general and specific features described herein, as well as all statements within the scope of the methods and systems, which, linguistically, may be said to fall within the scope of the claims.

Claims

1. A method for forming a target shallow trench isolation structure in a semiconductor substrate, comprising: A trench having a bottom and sidewalls is etched in the semiconductor substrate, the trench having a depth greater than the target depth of the target shallow trench isolation structure and a width greater than the critical dimension of the target shallow trench isolation structure; The depth and width of the trench are reduced by epitaxially growing a semiconductor material in the trench until the depth reaches the target depth and the width is equal to the critical dimension, wherein the semiconductor substrate and the semiconductor material layer are formed of the same material; Dielectric material is deposited on the semiconductor material layer in the trench and on the semiconductor substrate; A portion of the dielectric material is removed to form an oxide cap having a width and height greater than a critical dimension above the substrate surface of the semiconductor substrate; and A gate electrode of a transistor is formed on at least a portion of the oxide cap and on the semiconductor substrate.

2. The method according to claim 1, wherein, The semiconductor material is epitaxially grown at a temperature between 700 °C and 750 °C.

3. The method according to claim 1, wherein, The semiconductor substrate and the epitaxially grown semiconductor material also include doped silicon.

4. The method of claim 1, further comprising oxidizing the semiconductor substrate to form an oxide layer on the surface of the semiconductor substrate before depositing the dielectric material in the trench.

5. The method according to claim 1, wherein, The semiconductor substrate further includes a top surface, and the method further includes: The target shallow trench isolation structure is formed in the top surface; and A photodiode and at least one pixel transistor are formed in the top surface on the opposite side of the target shallow trench isolation structure.

6. A shallow trench isolation structure having a target depth and critical dimensions, comprising: A semiconductor substrate has a top surface of the substrate forming a trench that extends into the semiconductor substrate and has a trench depth relative to a flat region surrounding the top surface of the substrate such that the trench depth is greater than a target depth, and has a trench width at the top surface of the substrate such that the trench width is greater than a critical dimension. Semiconductor material is epitaxially grown in the trench to provide the shallow trench isolation structure with a depth equal to the target depth and a width equal to the critical dimension; as well as A dielectric material disposed in the trench and on the semiconductor material, the dielectric material including a cap layer having a width and height greater than a critical dimension above the surface of the substrate, wherein the gate electrode of the transistor is formed on the cap layer and the top surface of the substrate.

7. The shallow trench isolation structure according to claim 6, wherein, The epitaxially grown semiconductor material is the same as the semiconductor substrate.

8. The shallow trench isolation structure according to claim 7, wherein, The semiconductor substrate and the epitaxially grown semiconductor material include silicon, and the dielectric material includes oxide.

9. The shallow trench isolation structure according to claim 8, wherein, The epitaxially grown semiconductor material includes doped silicon.

10. The shallow trench isolation structure according to claim 6, wherein, The trench depth minus the target depth is between 50 angstroms and 500 angstroms.

11. The shallow trench isolation structure according to claim 6, wherein, (Groove width - critical size) / 2 is between 15 angstroms and 150 angstroms.

12. The shallow trench isolation structure according to claim 6, wherein, The shallow trench isolation structure is disposed on the wafer and located between at least one photodiode and at least one pixel transistor formed on the wafer.

13. An image sensor, comprising: Semiconductor substrate; The photodiode region includes one or more photodiodes formed in a flat region on the top surface of the semiconductor substrate; A pixel transistor region, including a pixel transistor formed in the flat region on the top surface of the substrate, wherein the pixel transistor includes a gate electrode; A shallow trench isolation structure is formed between the photodiode region and the pixel transistor region having a transistor, the shallow trench isolation structure electrically isolating the photodiode region from the transistor, and the shallow trench isolation structure has a target depth and a critical dimension, the shallow trench isolation structure comprising: A trench extends into the semiconductor substrate and has a trench depth relative to the flat region of the top surface of the substrate surrounding the trench, such that the trench depth is greater than a target depth, and has a trench width at the top surface of the substrate, such that the trench width is greater than a critical dimension. Semiconductor material is epitaxially grown in the trench to provide the shallow trench isolation structure having a depth equal to a target depth and a width equal to a critical dimension; and An oxide material is filled in the trench, and the oxide material includes an oxide cap having a width and height greater than a critical dimension above the substrate surface, wherein the gate electrode of the pixel transistor is formed on the oxide cap.

14. The image sensor according to claim 13, wherein, The trench depth minus the target depth is between 50 angstroms and 500 angstroms, and (trench width - critical dimension) / 2 is between 15 angstroms and 150 angstroms.

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