Dry development of the resist

Abstract

Dry development of a resist can be used, for example, to form a patterned mask in high-resolution patterning. Dry development can advantageously be achieved by a method of processing a semiconductor substrate, the method comprising: providing a photopatterned resist onto a substrate layer on the semiconductor substrate in a processing chamber; and dry-developing the photopatterned resist by removing either the exposed or unexposed portions of the resist by a dry development process that includes exposure to a chemical compound to form a resist mask. The resist can be an EUV-sensitive thin-film EUV resist containing an organometallic oxide or an organometallic.

Description

[0001] Incorporation by reference

[0002] The PCT application form is filed simultaneously with this specification as part of this application. Each application for which this application claims the benefit or priority as identified in the PCT application form filed simultaneously is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] In semiconductor manufacturing, thin film patterning in semiconductor processing is typically an important step. Patterning involves lithography. In conventional lithography techniques (e.g., 193 nm lithography), a pattern is printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby causing a chemical reaction in the photoresist that removes certain portions of the photoresist after development to form the pattern.

[0004] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22 nm, 16 nm, and other nodes. In the 16 nm node, for example, the width of a typical via or line in a damascene structure is generally no greater than about 30 nm. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography techniques to improve resolution. Summary of the Invention

[0005] Dry development of a resist can be used, for example, to form a patterned mask in high-resolution patterning. According to some aspects of the present disclosure, dry development can be advantageously achieved by a method of processing a semiconductor substrate, the method comprising: providing a photopatterned resist onto a substrate layer on the semiconductor substrate in a processing chamber; and dry-developing the photopatterned resist by removing either the exposed or unexposed portions of the resist by a dry development process that includes exposure to a chemical compound to form a resist mask. In some embodiments, the resist can be an EUV-sensitive thin film EUV resist containing an organometallic oxide or organometallic.

[0006] In some embodiments of the present disclosure, a suitable resist can be an EUV resist that is vapor-deposited onto the substrate layer. In other embodiments, a suitable resist can be an EUV resist that is spin-coated onto the substrate layer. In some embodiments, the EUV resist can be an organotin oxide. In some embodiments, the dry development process can include a plasma. In other embodiments, the dry development process can be a plasma-free heat treatment.

[0007] In some embodiments, the dry development process may include exposure to a compound for an appropriate time at an appropriate flow rate, pressure, and temperature, the compound comprising R x Z y , where R = B, Al, Si, C, S, SO and x>0, and Z = Cl, H, Br, F and y>0.

[0008] In some embodiments, the photo-patterned EUV resist is a 10-20 nm thick film containing organotin oxide, which is deposited based on the gas-phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to EUV exposure dose, and post-exposure bake. The dry development process includes non-plasma thermal exposure of the photo-patterned EUV resist at 120 °C, 10 mT, 500 sccm BCl3 for 30 seconds.

[0009] In some embodiments, the method further includes: after dry development to form the resist mask, using the resist mask to etch the substrate layer.

[0010] In some embodiments, the resist is sensitive to a radiation source selected from the group consisting of DUV, EUV, X-ray, and electron beam radiation.

[0011] In another aspect, there is provided an apparatus for performing dry development of a patterned resist. Such an apparatus may include: a vacuum processing chamber having a substrate (e.g., wafer) support; a vacuum line; a dry development chemical gas line; one or more heaters for substrate temperature control; and a controller programmed with instructions for processing a semiconductor substrate. The instructions may include code for: providing a patterned resist on a substrate layer on the semiconductor substrate to the vacuum processing chamber; and removing an exposed or unexposed portion of the patterned resist by a dry development process including exposure to a chemical compound to form a resist mask.

[0012] In some embodiments, the interior of the processing chamber of the apparatus may be coated with a corrosion inhibitor.

[0013] In some embodiments, the controller may be programmed with instructions for the dry development process, where the dry development process includes plasma. In other embodiments, the controller may be programmed with instructions for the dry development process, where the dry development process is a non-plasma heat treatment.

[0014] In some embodiments, the controller may be programmed with instructions for the dry development process, where the dry development process includes exposure to a compound for an appropriate time at an appropriate flow rate, pressure, and temperature, the compound comprising R x Z y , where R = B, Al, Si, C, S, SO and x>0, and Z = Cl, H, Br, F and y>0.

[0015] In some embodiments, the controller may be programmed with instructions for the dry development process, where the photopatterned EUV resist is a 10 - 20 nm thick film containing organotin oxide, deposited based on the gas-phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to EUV exposure dose, and post-exposure bake, and the dry development process includes non-plasma thermal exposure of the photopatterned EUV resist at 120 °C, 10 mT, 500 sccm BCl3 for 30 seconds.

[0016] In some embodiments, the controller may be programmed, where the process further involves etching the substrate layer using the resist mask after the resist mask is formed in dry development. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] According to specific embodiments of the present disclosure, Figure 1A-1B and 2 show the processing stages and results of negative dry development.

[0018] Figure 3 FIG. depicts a schematic diagram of an embodiment of a processing station apparatus suitable for implementing the dry development embodiments described herein.

[0019] Figure 4 FIG. depicts an embodiment of a multi-station processing tool suitable for implementing the dry development embodiments described herein.

[0020] Figure 5 FIG. schematically shows a cross-sectional view of an inductively coupled plasma apparatus suitable for implementing certain embodiments or aspects of embodiments.

[0021] Figure 6 FIG. depicts a semiconductor processing cluster tool architecture having a vacuum integrated deposition and patterning module docked to a vacuum transfer module, suitable for implementing the processing described herein. DETAILED DESCRIPTION

[0022] The present disclosure generally relates to the field of semiconductor processing. In particular aspects, the present disclosure relates to processes and apparatus for dry development of photoresists (e.g., EUV, DUV, X-ray, or electron beam sensitive metal and / or metal oxide containing photoresists), e.g., to form a patterned mask in EUV patterning.

[0023] Specific embodiments of the present disclosure will be described in detail. Examples of specific embodiments are depicted in the accompanying drawings. While the present disclosure will be described in conjunction with these specific embodiments, it should be understood that the present disclosure should not be limited to these specific embodiments. On the contrary, it should include substitutions, alterations, and equivalents that fall within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the present disclosure.

[0024] Extreme ultraviolet light (EUV) lithography can extend lithography technology by moving to a smaller imaging source wavelength than can be achieved with conventional lithography methods. An EUV light source of about 10 - 20 nm, or 11 - 14 nm wavelength (e.g., 13.5 nm wavelength) can be used in state-of-the-art lithography tools (also referred to as scanners). EUV radiation is strongly absorbed in many solid and fluid materials, including quartz and water vapor, and thus operates in a vacuum. Similar good performance can be obtained using other forms of radiation, including DUV, X-ray, or electron beam radiation. While the description herein primarily refers to EUV as the photoresist irradiation source, it should be understood that these other forms of radiation may also be considered in alternative embodiments.

[0025] EUV lithography uses EUV resists, which are patterned to form masks for etching underlying layers. EUV resists can be polymer-based chemically amplified resists (CARs), which are produced by liquid-based spin coating techniques. An alternative to CARs is a directly photopatternable metal oxide-containing film, such as those available from Inpria Corporation (Corvallis, OR) and described, for example, in U.S. Patent Publications US 2017 / 0102612, US 2016 / 021660, and US 2016 / 0116839, which are incorporated herein by reference, at least in part because they disclose photopatternable metal oxide-containing films. Such films can be produced by spin coating techniques or dry vapor deposition. The metal oxide-containing film can be patterned directly by EUV exposure in a vacuum environment (i.e., without using a separate photoresist), providing sub-30nm patterning resolution, for example, as described in U.S. Patent 9,996,004, entitled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARD MASKS, issued June 12, 2018, and / or PCT / US19 / 31618, filed May 9, 2019, entitled METHODS FOR MAKING EUV-PATTERNABLE HARD MASKS, and / or PCT / US2019 / 060742, filed November 11, 2019, entitled METHODS FOR MAKING HARD MASKS USEFUL IN NEXT-GENERATION LITHOGRAPHY, the disclosures of which relate at least to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks and are incorporated herein by reference. Generally, patterning involves exposing the EUV resist to EUV radiation to form a photopattern in the photoresist, and then developing to remove a portion of the photoresist according to the photopattern to form a mask.

[0026] Directly photo-patternable EUV resists can be composed of, or contain, metals and / or metal oxides incorporated within an organic component. The metals / metal oxides are very promising because they enhance EUV photon absorption and generate secondary electrons and / or exhibit increased etch selectivity to the underlying film stack and device layers. To date, these photoresists have been developed using wet (solvent) schemes, which require moving the wafer to a track where the wafer is exposed to developer, dried, and baked. The wet development step not only limits throughput but can also result in line collapse and / or delamination due to surface tension effects.

[0027] In one implementation of the present disclosure, a metal oxide-containing film (e.g., organotin oxide) sensitive to EUV is vapor deposited on a semiconductor substrate. Subsequently, the metal oxide-containing film is directly patterned by EUV exposure in a vacuum environment, and the pattern is developed to form a metal oxide-containing mask. As described herein, the development of EUV resist films containing organometallic oxides, EUV resist films containing organometals, or other directly photo-patternable EUV resist films is performed by a dry process.

[0028] The methods and apparatuses presently disclosed present general methods that can be applied to various specific implementations. Embodiments of the present disclosure present processes and apparatuses for dry development of metal- and / or metal oxide-containing resists for EUV photolithography, using chemical compounds as part of the EUV resist mask formation process. Other embodiments include combining all dry steps of film formation by vapor deposition, (EUV) lithographic photo-patterning, and dry development. Dry development can improve performance (e.g., prevent line collapse and delamination due to surface tension in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include eliminating the use of organic solvent developers, reducing sensitivity to adhesion issues, and having no solubility-based limitations.

[0029] According to a particular embodiment, a dry process is provided for developing EUV-sensitive metal- and / or metal oxide-containing photoresists. One embodiment is applicable to the dry development of Sn- and SnOx (tin oxide)-based resists that contain some amount of C, H, and O (and possibly additional components such as F). In various embodiments, the metal oxide-containing film can be a photosensitive organometallic oxide film, such as organotin oxide, e.g., alkyltin oxide (oxide / hydroxide) RSnO x OH (3-x)。Effective compositions include those in which the alkyl substituent is a tert-butyl or isopropyl substituent, where the carbon atom bonded to the tin atom is bonded to three or two other carbon atoms (correspondingly). When exposed to EUV light, such substituents appear to undergo more efficient cleavage, resulting in a change that allows for pattern development. In various embodiments, EUV exposure results in the loss of the alkyl substituent, forming new Sn-O-Sn crosslinks, which may occur after the EUV exposure step, such as during a post-exposure bake step in which the film may be exposed to ambient oxygen and / or moisture.

[0030] Development can be performed by using a mild plasma (high pressure, low power) or heat treatment while flowing in dry development chemicals (e.g., BCl3 or other Lewis acids). According to a particular embodiment, BCl3 is capable of rapidly removing the unexposed material, leaving a pattern of the exposed film, which can be transferred into the underlying layer by a plasma-based etching process (e.g., a conventional etching process).

[0031] According to the present disclosure, in a dry development process using a mild plasma or heat treatment (e.g., >5 mT (e.g., >15 mT), <1000 W (e.g., <500 W) transformer-coupled plasma (TCP) (in other embodiments, CCP, ICP, or downstream plasma can be used), 0 to 300 °C (e.g., 30 to 120 °C), 100 to 1000 sccm (e.g., about 500 sccm) of dry development chemicals, for 1 to 3000 seconds (e.g., 10 - 600 seconds)), after optical patterning in an EUV scanner, the wafer can directly enter a dry development / etch chamber and skip the material and production costs associated with wet development on a track. Alternatively, post-exposure bake can be performed in a development chamber or another chamber, during which the exposed areas undergo further crosslinking to form a denser SnO2-like network structure. The dry process can provide more tunability and provide further critical dimension (CD) control and residue removal.

[0032] By adopting a non-plasma thermal scheme, productivity can be significantly increased because multiple wafers can be batch-developed simultaneously in a low-cost thermal vacuum chamber / furnace. A suitable chamber can include a vacuum line, a dry development chemical (e.g., BCl3) line, and a heater for temperature control. In addition, since the process is thermal, the interior of the chamber can be coated with a corrosion-resistant film, such as an organic polymer (e.g., polytetrafluoroethylene (PTFE), e.g., Teflon TM ) or an inorganic coating, without the risk of removal by plasma exposure.

[0033] In various embodiments, dry development of a photoresist containing a certain amount of metal, metal oxide, and organic components can be achieved by plasma or thermal, plasma (including possibly photo-activated (i.e., lamp-heated, such as UV lamp-heated) or a combination of methods, and simultaneously flowing into a dry development gas including a compound having the formula R x Z y , where R = B, Al, Si, C, S, SO and x > 0, and Z = Cl, H, Br, F and y > 0. Dry development can produce positive or negative types, where the R x Z y substance selectively removes unexposed or exposed material, leaving the exposed or unexposed complement as a mask.

[0034] This process has been demonstrated for EUV resist compositions based on organotin oxides, which can be applied to commercially available spin-on formulations (e.g., formulations available from Inpria Corporation), as well as formulations applied using dry vacuum deposition techniques (e.g., formulations described in the applicant's previous applications above). Negative dry development has been achieved by exposing the non-EUV exposed areas to a selective dry development (removal) with BCl3 flow without igniting the plasma. A specific example of the dry development process involves an EUV-sensitive resist film containing organotin oxide (e.g., 10 - 20 nm thick), which is deposited based on the gas-phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to EUV exposure and post-exposure bake, and then dry developed for 30 seconds at 120 °C, 10 mT, 500 sccm BCl3 using a non-plasma heat treatment.

[0035] Reference Figure 1A-1B and 2 show negative dry development according to a specific embodiment of the present disclosure. As Figure 1A shown, after photopatterning and optional baking in the EUV scanner described above, the wafer 100 can be provided to an etching chamber. The wafer 100 includes a substrate 102 (e.g., Si) layer, a layer to be etched 104 disposed on the substrate (e.g., an ashing-hardened mask (e.g., silicon oxycarbide (SOC)), or other materials (e.g., silicon, silicon oxide, silicon nitride, etc.); in other embodiments, it can be a layer stack), and a photopatterned EUV resist film 106 (e.g., a 10 - 20 nm thick organotin oxide-containing layer disposed on the layer to be etched). As Figure 1BAs shown, by exposing to a flow of dry development chemicals (e.g., BCl3) without igniting a plasma, the non-EUV exposed regions 106A (the darker portions in the figure) of the photoresist 106 can be removed during a dry development process. Thereafter, the developed photoresist 106 can be used as a mask to etch the layer 104 to be etched to provide Figure 2 the structure shown in

[0036] Alternative Embodiments

[0037] Due to enhanced adsorption of EUV photons, EUV-sensitive resists such as those containing metals and metal oxides described above are used for EUV patterning. However, challenges include high linewidth and line edge roughness, as well as residue issues. These two challenges may be mostly attributed to the randomness of light and non-optimal Gaussian distribution, resulting in partial or complete exposure of materials in areas where the resist should remain unexposed and vice versa.

[0038] Wet development has very high selectivity and has shown clear on / off behavior, resulting in the inability of the wet development process to remove partially or completely mis-exposed regions. Then, remaining residues are left after the wet development process, resulting in residues and high line edge and linewidth roughness. Interestingly, since the dry development process can adjust the etch rate and selectivity based on multiple control knobs (e.g., time, temperature, pressure, gas flow), it can be further applied to residue removal and smoothing of metal-containing resist lines by removing these partially exposed residues.

[0039] Equipment

[0040] As described above, a suitable processing chamber for implementing the non-plasma thermal embodiments of the present disclosure can be composed of a vacuum processing chamber with a substrate (e.g., wafer) support, a vacuum pipeline, a BCl3 pipeline, and one or more heaters for temperature control. The interior of the non-plasma heat treatment chamber can be covered with a corrosion-resistant organic polymer (e.g., polytetrafluoroethylene (PTFE), e.g., Teflon TM ) without the risk of being removed by plasma exposure.

[0041] Figure 3 A schematic diagram of an embodiment of a processing station 300 is depicted. The processing station 300 has a processing chamber body 302 for maintaining a low-pressure environment suitable for performing the dry development embodiments described above. Multiple processing stations 300 can be included in a common low-pressure processing tool environment. For example, Figure 4 An embodiment of a multi-station processing tool 400 is depicted, such as one that can be purchased from Lam Research Corporation (Fremont, CA) Processing tool. In some embodiments, one or more hardware parameters of the processing station 300 (including those discussed in detail below) can be programmatically adjusted by one or more computer controllers 350.

[0042] The processing station can be configured as a module in a cluster tool. Figure 6 Depicts a semiconductor processing cluster tool architecture with vacuum integrated deposition and patterning modules, suitable for implementing the embodiments described herein. Such a cluster processing tool architecture can include a resist deposition, a resist exposure (EUV scanner), a resist dry development, and an etch module, as described above and further described below with reference to Figure 5 and 6 described further.

[0043] In some embodiments, some processing functions can be continuously performed in the same module, such as dry development and etching. Embodiments of the present disclosure relate to methods and apparatuses for receiving a wafer (including a photopatterned EUV resist thin film layer disposed on an etch layer or layer stack) into a dry development / etch chamber after photopatterning in an EUV scanner; dry developing the photopatterned EUV resist thin film layer; and then etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0044] Returning to Figure 3 , the processing station 300 is in fluid communication with a reactant delivery system 301a for delivering a processing gas to a distribution showerhead 306. The reactant delivery system 301a optionally includes a mixing vessel 304 for mixing and / or conditioning the processing gas for delivery to the showerhead 306. One or more mixing vessel inlet valves 320 can control the introduction of the processing gas into the mixing vessel 304. When plasma exposure is used, plasma can also be delivered to the showerhead 306 or plasma can be generated in the processing station 300. As described above, in at least some embodiments, non-plasma thermal exposure is advantageous.

[0045] Figure 3 Includes an optional vaporization point 303 for vaporizing a liquid reactant to be supplied to the mixing vessel 304. In some embodiments, a liquid flow controller (LFC) can be disposed upstream of the vaporization point 303 to control the mass flow rate of the liquid for vaporization and delivery to the processing station 300. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. Then, the plunger valve of the LFC can be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller electrically connected to the MFM.

[0046] The showerhead 306 distributes the processing gas toward the substrate 312. In Figure 3In the illustrated embodiment, the substrate 312 is located below the showerhead 306 and is shown resting on the pedestal 308. The showerhead 306 can have any suitable shape and can have any suitable number and configuration of openings for dispensing a processing gas to the substrate 312.

[0047] In some embodiments, the pedestal 308 can be raised or lowered to expose the substrate 312 to the volume between the substrate 312 and the showerhead 306. It should be understood that in some embodiments, the pedestal height can be adjusted programmatically via a suitable computer controller 350.

[0048] In certain embodiments, the pedestal 308 can be temperature controlled by a heater 310. In some embodiments, as described in the disclosed embodiments, during non-plasma thermal exposure of a photopatterned resist to a dry developing chemical (e.g., BCl3), the pedestal 308 can be heated to a temperature greater than 0 °C and up to 300 °C or higher, such as 50 to 120 °C, such as about 65 to 80 °C.

[0049] In addition, in some embodiments, pressure control for the processing station 300 can be provided by a butterfly valve 318. As shown in the embodiment of Figure 3 the butterfly valve 318 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control for the processing station 300 can also be adjusted by changing the flow rate of one or more gases introduced to the processing station 300.

[0050] In some embodiments, the position of the showerhead 306 can be adjusted relative to the pedestal 308 to change the volume between the substrate 312 and the showerhead 306. Additionally, it should be understood that the vertical position of the pedestal 308 and / or the showerhead 306 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 308 can include a rotational axis for rotating the orientation of the substrate 312. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more suitable computer controllers 350.

[0051] When plasma can be used, such as in mild plasma-based dry development embodiments and / or in etching operations implemented in the same chamber, the showerhead 306 and the pedestal 308 are electrically connected to an RF (radio frequency) power source 314 and a matching network 316 to provide power to the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure of the processing station, the concentration of the gas, the RF source power, the RF source frequency, and the plasma power pulse timing. For example, the RF power source 314 and the matching network 316 can operate at any suitable power to form a plasma having a desired composition of radical species. An example of a suitable power is up to about 500 W.

[0052] In some embodiments, instructions for the controller 350 can be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting the conditions of a process stage can be included in the corresponding recipe stage of a process recipe. In certain cases, the process recipe stages can be arranged in sequence such that all instructions for a process stage are executed simultaneously with that process stage. In some embodiments, instructions for setting one or more reactor parameters can be included in a recipe stage. For example, instructions for setting the flow rate of a dry development chemical reactant gas (such as BCl3), and time delay instructions for a recipe stage. In some embodiments, the controller 350 can include any of the features of the Figure 4 system controller 450 described below.

[0053] As described above, one or more processing stations can be included in a multi-station processing tool. Figure 4 A schematic view of an embodiment of a multi-station processing tool 400 is shown, which has an in-bound load lock 402 and an out-bound load lock 404, one or both of which can include a remote plasma source. A robot 406 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 408 through an atmospheric port 410 into the in-bound load lock 402. The wafer is placed by the robot 406 on a pedestal 412 in the in-bound load lock 402, the atmospheric port 410 is closed, and the load lock is evacuated. When the in-bound load lock 402 includes a remote plasma source, the wafer can be exposed to remote plasma processing in the load lock to treat the silicon nitride surface before being introduced into the processing chamber 414. Additionally, the wafer can also be heated in the in-bound load lock 402, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 416 leading to the processing chamber 414 is opened, and another robot (not shown) places the wafer on a pedestal in the first station shown in the reactor for processing. Although the Figure 4 embodiment depicted in includes a load lock, it should be understood that in some embodiments, the substrate can be directly introduced into the processing station.

[0054] The depicted processing chamber 414 includes four processing stations, Figure 4 numbered 1 to 4 in the illustrated embodiment. Each station has a heated pedestal (shown as 418 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station may have different or multiple uses. For example, in some embodiments, the processing station may be switchable between a dry development and an etching processing mode. Additionally or alternatively, in some embodiments, the processing chamber 414 may include a matching pair of one or more dry development and etching processing stations. Although the depicted processing chamber 414 includes four stations, it should be understood that the processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0055] Figure 4 Some embodiments of a wafer handling system for transporting wafers within the processing chamber 414 are depicted. In some embodiments, the wafer handling system may transport wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system may be employed. Non-limiting examples include a wafer turntable and a robotic arm for handling wafers. Figure 4 An embodiment of a system controller 450 for controlling the processing conditions and the hardware state of the processing tool 400 is also depicted. The system controller 450 may include one or more memory devices 456, one or more mass storage devices 454, and one or more processors 452. The processor 452 may include a computer or CPU, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0056] In some embodiments, system controller 450 controls all activities of processing tool 400. System controller 450 executes system control software 458 stored in mass storage device 454, loaded into memory device 456, and executed by processor 452. Alternatively, control logic may be hard-coded in controller 450. Application specific integrated circuits, programmable logic devices (such as field programmable gate arrays, or FPGAs), etc. may be used for these purposes. In the following discussion, whether using "software" or "code", functionally equivalent hard-coded logic may be used in place thereof. System control software 458 may include instructions for controlling timing, gas mixing, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck, and / or pedestal position, and other parameters for specific processes performed by processing tool 400. System control software 458 may be configured in any suitable manner. For example, various processing tool component subroutines or control objects may be written to control the operation of processing tool components for performing various processing tool processes. System control software 458 may be encoded in any suitable computer-readable programming language.

[0057] In some embodiments, system control software 458 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored in mass storage device 454 and / or memory device 456 and associated with system controller 450 may be employed in some embodiments. Examples of programs or program segments for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0058] The substrate positioning program may include program code for a processing tool component that loads a substrate onto pedestal 418 and controls the spacing between the substrate and other parts of processing tool 400.

[0059] The process gas control program may include code for controlling gas composition (e.g., BCl3 gas as described herein) and flow rate and optionally code for flowing the gas into one or more processing stations prior to deposition to stabilize the pressure in the processing stations. The pressure control program may include code for controlling the pressure within a processing station by adjusting, for example, a throttle valve in the exhaust system of the processing station, the gas flow into the processing station, and the like.

[0060] The heater control program may include code for controlling the current flowing to a heating unit for heating the substrate. Alternatively, the heater control program may control the conveyance of a heat transfer gas (such as helium) toward the substrate.

[0061] The plasma control program may include code for setting the RF power level applied to the processing electrodes in one or more processing stations according to the embodiments herein.

[0062] The pressure control program may include code for maintaining the pressure in the reaction chamber according to the embodiments herein.

[0063] In some embodiments, a user interface may be associated with the system controller 450. The user interface may include a display screen, a graphical software display of the equipment and / or process conditions, and user input devices such as a pointing device, a keyboard, a touch screen, a microphone, etc.

[0064] In some embodiments, the parameters adjusted by the system controller 450 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe, which may be input using the user interface.

[0065] Signals for monitoring the process may be provided by the analog and / or digital input connectors of the system controller 450 from various process tool sensors. Signals for controlling the process may be output through the analog and digital output connectors of the process tool 400. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain the process conditions.

[0066] The system controller 450 may provide program instructions for performing the deposition process described above. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control these parameters to operate the dry development and / or etching process according to the various embodiments described in the present invention.

[0067] The system controller 450 will generally include one or more memory devices and one or more processors configured to execute the instructions to cause the device to perform the methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling the process operations according to the disclosed embodiments may be coupled to the system controller 450.

[0068] In some implementations, system controller 450 is part of a system that can be part of the above-described embodiments. Such systems can include semiconductor processing apparatuses that include one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer chucks, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronics can be referred to as a "controller" that can control various elements or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, system controller 450 can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of tools and other transfer tools, and / or load locks coupled to or interfaced with a particular system.

[0069] Broadly speaking, system controller 450 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions that are transmitted to system controller 450 in various individual settings (or program files) that define operating parameters for performing a specific process on or with a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer for performing one or more processing steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0070] In some implementations, system controller 450 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to the system, or a combination thereof. For example, system controller 450 can be in the "cloud" or be all or part of a wafer fab host system, allowing for remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some embodiments, a remote computer (e.g., a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows for the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some embodiments, system controller 450 receives instructions in the form of data that specify the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be for the type of process to be performed and the type of tool that system controller 450 is configured to connect to or control. Thus, as described above, system controller 450 can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work towards a common goal (e.g., the processes and controls described herein). An example of a distributed controller for these purposes can be one or more integrated circuits on a chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control in-chamber processes.

[0071] Under non-limiting conditions, an example system can include a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, an orbit chamber or module, an EUV lithography chamber (scanner) or module, a dry develop chamber or module, and any other semiconductor processing system that can be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0072] As described above, depending on the one or more process steps to be performed by the tool, system controller 450 can communicate with one or more other tool circuits or modules, other tool components, combined tools, other tool interfaces, adjacent tools, adjoining tools, tools located throughout the factory, a host, another controller, or tools used in a material handling that transports a container of wafers between tool locations and / or load ports in a semiconductor manufacturing facility.

[0073] An inductively coupled plasma (ICP) reactor is now described. In certain embodiments, it may be suitable for etching operations, and the etching process is applicable to the implementation of certain embodiments. Although an ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may also be used.

[0074] Figure 5 A cross-sectional view of an inductively coupled plasma device 500 is schematically shown, which is suitable for implementing certain embodiments or aspects of embodiments (e.g., dry development and / or etching). An example of such a device is manufactured by Lam Research Corp., Fremont, CA The reactor. The inductively coupled plasma device 500 includes an integral processing chamber, which is structurally defined by a chamber wall 501 and a window 511. The chamber wall 501 can be made of stainless steel or aluminum. The window 511 can be made of quartz or other dielectric materials. An optional internal plasma grid 550 divides the total processing chamber into an upper sub-chamber 502 and a lower sub-chamber 503. In most embodiments, the plasma grid 550 can be removed to utilize the chamber space formed by both the sub-chambers 502 and 503. A chuck 517 is positioned in the lower sub-chamber 503 near the bottom inner surface. The chuck 517 is configured to receive and hold a semiconductor wafer 519 on which etching and deposition processes are performed. The chuck 517 can be an electrostatic chuck for supporting the wafer 519 when the wafer 519 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 517 and has an upper surface substantially in the same plane as the top surface of the wafer 519 (when the wafer is present above the chuck 517). The chuck 517 also includes an electrostatic electrode for clamping and releasing the wafer. A filter and a DC clamp power source (not shown) can be provided for this purpose. Other control systems can also be provided for lifting the wafer 519 away from the chuck 517. The chuck 517 can be charged with an RF power source 523. The RF power source 523 is connected to a matching circuit 521 through a connection member 527. The matching circuit 521 is connected to the chuck 517 through a connection member 525. In this way, the RF power source 523 is connected to the chuck 517. In various embodiments, the bias power source of the electrostatic chuck can be set to about 50V, or to a different bias power source depending on the process performed according to the disclosed embodiments. For example, the bias power source can be between about 20Vb and about 100V, or between about 30V and about 150V.

[0075] The element for plasma generation includes a coil 533 located above the window 511. In some embodiments, the coil is not used in the disclosed embodiments. The coil 533 is made of a conductive material and includes at least one full turn. In Figure 5An example of the coil 533 shown in [Figure] includes three turns. The cross-section of the coil 533 is shown by symbols, where a coil with an "X" symbol indicates that the coil extends rotationally into the page, and conversely, a coil with a "●" symbol indicates that the coil extends rotationally out of the page. The element for plasma generation further includes an RF power source 541 configured to provide RF power to the coil 533. Generally, the RF power source 541 is connected to the matching circuit 539 through a connector 545. The matching circuit 539 is connected to the coil 533 through a connector 543. In this way, the RF power source 541 is connected to the coil 533. An optional Faraday shield 549 is positioned between the coil 533 and the window 511. The Faraday shield 549 can be held in a spaced-apart relationship relative to the coil 533. In some embodiments, the Faraday shield 549 is disposed directly above the window 511. In some embodiments, the Faraday shield 549 is between the window portion 511 and the chuck 517. In some embodiments, the Faraday shield 549 does not maintain a spaced-apart relationship with the coil 533. For example, the Faraday shield 549 can be directly below the window 511 without a gap. Each of the coil 533, the Faraday shield 549, and the window 511 is configured to be substantially parallel to each other. The Faraday shield 549 can prevent metal or other substances from depositing on the window 511 of the processing chamber 524.

[0076] The process gas can flow into the processing chamber through one or more main gas inlets 560 located in the upper sub-chamber 502 and / or through one or more side gas inlets 570. Similarly, although not explicitly shown, similar gas inlets can be used to supply the process gas to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a single-stage or two-stage dry mechanical pump and / or a turbomolecular pump 540, can be used to pump the process gas out of the processing chamber 524 and maintain the pressure inside the processing chamber 524. For example, this vacuum pump can be used to evacuate the lower sub-chamber 503 during the ALD purge operation. A valve-controlled conduit can be used to fluidly connect the vacuum pump to the processing chamber 524 to selectively control the application of the vacuum environment provided by the vacuum pump. During the operation of the plasma processing, this can be performed using a closed-loop controlled flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown). Similarly, a vacuum pump and a valve fluidly connected to the capacitively coupled plasma processing chamber in a controlled manner can also be used.

[0077] During operation of the apparatus 500, one or more processing gases may be supplied through gas flow inlets 560 and / or 570. In certain embodiments, the processing gas may be supplied only through the main gas flow inlet 560, or only through the side gas flow inlet 570. In some cases, the gas flow inlets shown in the figures may be replaced by more complex gas flow inlets, such as by one or more showerheads. The Faraday shield 549 and / or optional grid 550 may include internal channels and holes through which the processing gas can be delivered to the interior of the chamber. One or both of the Faraday shield 549 and optional grid 550 may serve as a showerhead for delivering the processing gas. In some embodiments, a liquid evaporation and delivery system may be located upstream of the processing chamber 524 such that once the liquid reactant or precursor is evaporated, the evaporated reactant or precursor is introduced into the chamber through gas flow inlets 560 and / or 570.

[0078] RF power is supplied from the RF power source 541 to the coil 533 to cause an RF current to flow through the coil 533. The RF current flowing through the coil 533 generates an electromagnetic field around the coil 533. This electromagnetic field generates an induced current within the upper sub-chamber 502. The resulting ions and radicals physically and chemically interact with the wafer 519 to etch features of the wafer and selectively deposit a layer on the wafer 519.

[0079] If a plasma grid 550 is used such that both an upper sub-chamber 502 and a lower sub-chamber 503 exist, the induced current acts on the gas present in the upper sub-chamber 502 to generate an electron-ion plasma in the upper sub-chamber 502. The optional internal plasma grid 550 limits the amount of hot electrons in the lower sub-chamber 503. In some embodiments, the apparatus 500 is designed and operated such that the plasma present in the lower sub-chamber 503 is an "ion-ion" plasma.

[0080] Both the upper electron-ion plasma and the lower ion-ion plasma may contain cations and anions, but the ion-ion plasma will have a greater ratio of anions to cations. Volatile etch and / or deposition by-products may be removed from the lower sub-chamber 503 through port 522. The chuck 517 disclosed herein may be operated in an elevated temperature range between about 10°C and about 250°C. This temperature will depend on the process operation and the specific recipe.

[0081] The apparatus 500 may be coupled to a facility (not shown) when installed in a cleanroom or a manufacturing plant. Such a facility includes ducts that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to the apparatus 500 when installed in the target manufacturing plant. Additionally, the apparatus 500 may be coupled to a transfer chamber, allowing for the transfer of semiconductor wafers in and out of the apparatus 500 by a robotic arm, for example, using typical automation.

[0082] In some embodiments, system controller 530, which may include one or more physical or logical controllers, controls some or all of the operations in processing chamber 524. System controller 530 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 500 includes a switching system for controlling flow rate and duration when executing the disclosed embodiments. In some embodiments, the apparatus 500 may have a switching time of up to about 500 ms or up to about 750 ms. The switching time may depend on the flowing chemical composition, recipe selection, reactor architecture, and other factors.

[0083] In some implementations, system controller or controller 530 is part of a system, which may be part of the above examples. Such systems may include semiconductor processing apparatus that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or particular processing components (wafer pedestal, gas flow system, etc.). These systems may be integrated with electronics for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronics may be integrated into controller 530, which may control various components or sub-components of one or more systems. Depending on the processing parameters and / or system type, the system controller may be programmed to control any of the processes disclosed herein, including controlling the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer delivery in and out of the tool and other transfer tools and / or load locks connected to or interfacing with a particular system.

[0084] Broadly speaking, controller 530 may be defined as electronics having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. The integrated circuits may include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions delivered to the controller in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or with respect to a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or die of a wafer.

[0085] In some implementations, system controller 530 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the system. For example, the controller can be in the "cloud" or in all or part of a wafer fab host system, which can allow for remote access to wafer processing. The computer can implement remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, study trends or performance criteria from multiple manufacturing operations, to change parameters of the current process, set process steps to follow the current process, or initiate a new process. In some examples, a remote computer (such as a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then conveyed from the remote computer to the system. In some examples, system controller 530 receives instructions in the form of data that specify parameters for each process step to be executed during one or more operations. It should be understood that the parameters can be specific to the type of process to be executed and the type of tool that the controller is configured to interface with or control. Thus, as described above, system controller 530 can be distributed, for example, by including one or more discrete controllers that are networked together and work towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which are combined to control the process on the chamber.

[0086] Exemplary systems can include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, extreme ultraviolet (EUV) lithography chambers (scanners) or modules, dry lithography chambers or modules, and any other semiconductor processing system that can be associated with or used for the manufacture and / or preparation of semiconductor wafers.

[0087] As described above, depending on one or more process steps to be executed by a tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a host computer, another controller, or tools used in the material transport that shuttles a wafer container between tool locations and / or load ports in a semiconductor manufacturing facility.

[0088] The implementation of EUVL patterning can utilize any suitable tool, which is commonly referred to as a scanner, such as the TWINSCAN NXE provided by ASML (Veldhoven, NL): platform. The EUVL patterning tool can be a stand-alone device into which the substrate is moved or out of which the substrate is moved for deposition and etching as described herein. Alternatively, as described below, the EUVL patterning tool can be a module on a larger multi-component tool. Figure 6 Depicted is a semiconductor processing cluster tool architecture having a vacuum integrated deposition, EUV patterning, and dry development etching module docked to a vacuum transfer module, suitable for performing the processes described herein. Although these processes can be implemented in the absence of such vacuum integration equipment, such equipment may be advantageous in certain implementations.

[0089] Figure 6 Depicted is a semiconductor processing cluster tool architecture having a vacuum integrated deposition and patterning module docked to a vacuum transfer module, suitable for performing the processes described herein. The configuration of the transfer module for "transferring" wafers between multiple storage devices and processing modules can be referred to as a "cluster tool architecture" system. Depending on the requirements of a particular process, the deposition and patterning modules are vacuum integrated. Other modules (such as for etching) can also be included on the cluster.

[0090] A vacuum transfer module (VTM) 638 is docked to four processing modules 620a - 620d, which can each be optimized to perform various manufacturing processes. As an example, the processing modules 620a - 620d can be used to perform deposition, evaporation, ELD, dry development, etching, stripping, and / or other semiconductor processes. For example, module 620a can be an ALD reactor that can be operated to perform non-plasma thermal atomic layer deposition as described herein, such as the Vector tool available from Lam Research Corporation (Fremont, CA). Module 620b can be a PEALD tool (such as Lam ). It should be understood that the figures are not necessarily drawn to scale.

[0091] Airlocks 642 and 646 (also referred to as load locks or transfer modules) are docked to the VTM 638 and the patterning module 640. For example, as described above, a suitable patterning module can be the TWINSCAN platform (provided by ASML (Veldhoven, NL)). This tool architecture allows for the transfer of workpieces (such as semiconductor substrates or wafers) under vacuum so as not to react prior to exposure. The integration of the deposition module with the lithography tool is facilitated by the fact that EUVL also requires a substantially reduced pressure due to the strong optical absorption of ambient gases (such as H2O, O2, etc.) for incident photons.

[0092] As described above, the integration architecture is only one possible implementation of the tools for performing the processing. The performance of these processes can also use more conventional stand-alone EUVL scanners and deposition reactors (such as Lam Vector tools) as modules, which are either stand-alone or integrated into a cluster architecture together with other tools (such as etching, stripping, etc. (such as Lam Kiyo or Gamma tools)), for example, refer to Figure 6 the ones described (but without the integrated patterning module).

[0093] The air lock 642 can be an "output" load lock, representing the transfer of the substrate from the VTM 638 for use by the deposition module 620a to the patterning module 640, and the air lock 646 can be an "input" load lock, indicating the transfer of the substrate from the patterning module 640 back to the VTM 638. The input load lock 646 can also serve as an interface to the outside of the tool for the entry and exit of the substrate. Each processing module has a facet for docking the module to the VTM 638. For example, the deposition processing module 620a has a facet 636. Within each facet, sensors (such as sensors 1-18 shown in the figure) are used to detect the passage of the wafer when the wafer 626 moves between the corresponding stations. The patterning module 640 and the air locks 642, 646 can be similarly equipped with additional facets and sensors (not shown).

[0094] The main VTM robot 622 transfers the wafer 626 between the modules (including the air locks 642 and 646). In one implementation, the robot 622 has one arm, and in another implementation, the robot 622 has two arms, where each arm has an end effector 624 to pick up the wafer (such as the wafer 626) for conveyance. The front-end robot 644 is used to transfer the wafer 626 from the output air lock 642 into the patterning module 640 and from the patterning module 640 into the input air lock 646. The front-end robot 644 can also convey the wafer 626 between the input load lock 646 and the outside of the tool for the entry and exit of the substrate. Since the input air lock 646 can match the environment between the atmosphere and the vacuum, the wafer 626 can move between these two pressure environments without being damaged.

[0095] It should be noted that EUVL tools typically operate at a higher vacuum compared to deposition tools. If this is the case, it is desirable to increase the vacuum environment of the substrate during transfer from deposition to the EUVL tool to allow the substrate to outgas before entering the patterning tool. The output gas lock 642 can provide this function by maintaining the transferred wafer at a lower pressure (not higher than the pressure in the patterning module 640) for a period of time and evacuating any off-gassing, so that the optical components of the patterning tool are not contaminated by off-gassing from the substrate. A suitable pressure for the output off-gas lock is not more than 1E-8 Torr.

[0096] In some embodiments, the system controller 650 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. It should be noted that the controller can be local to the cluster architecture, or can be located outside the cluster architecture on the manufacturing floor, or can be located at a remote location and connected to the cluster architecture via a network. The system controller 650 can include one or more memory devices and one or more processors. The processor can include a central processing unit (CPU) or a computer, analog and / or digital input / output connections, a stepper motor control board, and other similar components. A plurality of instructions for implementing appropriate control operations are executed on the processor. These instructions can be stored on a memory device connected to the controller or can be provided via a network. In certain embodiments, the system controller executes system control software.

[0097] The system control software can include instructions for controlling the timing of the applications and scales of aspects of any tool or module operation. The system control software can be configured in any suitable manner. For example, various processing tool component subroutines or control objects can be written to control the operation of the processing tool components required to implement various processing tool programs. The system control software can be encoded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions to control the various parameters described above. For example, each stage of semiconductor manufacturing processing can include one or more instructions executed by the system controller. For example, instructions for setting the processing conditions for the condensation, deposition, evaporation, patterning, and / or etching stages can be included in the corresponding recipe stages.

[0098] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include a processing chamber for patterning, depositing, and etching, and a controller including instructions for forming a negative pattern mask. The instructions may include program code for, in the processing chamber, performing the following processes: exposing a substrate surface by EUV exposure to pattern features in a chemically amplified resist (CAR) on a semiconductor substrate; dry-developing the photo-patterned resist; and using the patterned photoresist as a mask to etch an underlying layer or layer stack.

[0099] It should be noted that the computer controlling the wafer movement may be local to the cluster architecture, or may be external to the cluster architecture on the manufacturing floor, or may be located at a remote location and connected to the cluster architecture via a network. Regarding Figure 3 、 4 or any one of 5, the controller described above may be implemented with the Figure 6 tools in.

[0100] Conclusion

[0101] Processes and apparatus in the context of EUV patterning are disclosed for dry-developing metal and / or metal oxide photoresists to form, for example, a patterned mask.

[0102] It should be understood that the examples and embodiments described herein are for illustrative purposes only and various modifications or variations are hereby suggested to those skilled in the art. Although various details have been omitted for clarity purposes, various design alternatives may be implemented. Therefore, these examples should be considered illustrative rather than restrictive, and the present disclosure is not limited to the details presented herein but may be modified within the scope of the disclosure.

Claims

1. A method for processing a semiconductor substrate, comprising: Providing an EUV-patterned resist on a substrate layer on the semiconductor substrate in a processing chamber, wherein the EUV-patterned resist comprises an unexposed organometallic oxide portion and an exposed metal oxide portion, and wherein organic substituents are cleaved by EUV exposure; Performing dry development on the EUV-patterned resist to remove the exposed portion or the unexposed portion of the EUV-patterned resist to form a resist mask, the dry development comprising exposing the resist to a chemical compound that is selective between the organometallic oxide portion and the metal oxide portion.

2. The method according to claim 1, wherein the EUV-patterned resist is vapor deposited on the substrate layer.

3. The method according to claim 1, wherein the EUV-patterned resist is spin-coated on the substrate layer.

4. The method according to claim 1, wherein the EUV-patterned resist comprises organotin oxide.

5. The method according to claim 1, wherein the dry development comprises plasma.

6. The method according to claim 1, wherein the dry development comprises a plasma-free heat treatment.

7. The method according to claim 1, wherein the dry development process comprises exposing to a compound for a suitable period of time at a suitable flow rate, pressure and temperature, the compound comprising R x Z y , where R = B, Al, Si, C, S, SO and x>0, and Z = Cl, H, Br, F and y>0.

8. The method according to claim 1, wherein the EUV-patterned EUV resist is a 10 - 20 nm thick film containing organotin oxide, which is deposited based on the gas-phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to an EUV exposure dose, and post-exposure bake, and the dry development comprises a non-plasma thermal exposure of the EUV-patterned resist at 120 °C, 10 mT, 500 sccm BCl3 for 30 seconds.

9. The method according to claim 1, further comprising: After performing dry development to form the resist mask, the resist mask is used to etch the substrate layer.

10. The method according to claim 1, wherein the chemical compound comprises BCl3.

11. An apparatus for performing dry development of an EUV resist, the apparatus comprising: A vacuum processing chamber having a substrate support; A vacuum line; A dry development chemical gas line; One or more heaters for substrate temperature control; And A controller programmed with instructions for processing a semiconductor substrate, the instructions including code for: Providing an EUV-patterned resist on a substrate layer on the semiconductor substrate to the vacuum processing chamber; And Removing the exposed portion or the unexposed portion of the EUV-patterned resist by a dry development process including exposure to a chemical compound to form a resist mask, Wherein the EUV-patterned resist comprises a portion containing an organometallic oxide and a portion containing a metal oxide, and Wherein the chemical compound in the dry development process is selective between the portion containing an organometallic oxide and the portion containing a metal oxide.

12. The apparatus according to claim 11, wherein the controller is programmed to have instructions for the dry development process, including: Wherein the unexposed portion of the EUV-patterned resist is removed.

13. The apparatus according to claim 11, wherein the interior of the processing chamber is coated with a corrosion inhibitor.

14. The apparatus according to claim 11, wherein the controller is programmed to have instructions for the dry development process, including wherein the dry development process includes plasma.

15. The apparatus according to claim 11, wherein the controller is programmed to have instructions for the dry development process, including wherein the dry development process includes heat treatment without plasma.

16. The apparatus according to claim 11 or 12, wherein the controller is programmed to have instructions for the dry development process, including wherein the dry development process includes exposure to a compound for an appropriate time at an appropriate flow rate, pressure, and temperature, the compound comprising R x Z y , where R = B, Al, Si, C, S, SO and x > 0, and Z = Cl, H, Br, F and y > 0.

17. The apparatus according to claim 11 or 12, wherein the controller is programmed to have instructions for the dry development process, including wherein the EUV patterning resist is a 10 - 20 nm thick film containing organotin oxide, which is deposited based on the gas phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to an EUV exposure dose, and post-exposure bake, and the dry development process includes non-plasma thermal exposure of the EUV patterning resist at 120 °C, 10 mT, 500 sccm BCl3 for 30 seconds.

18. The apparatus according to claim 11, wherein the controller is programmed to have instructions for the following operation: after performing dry development to form the resist mask, using the resist mask to etch the substrate layer.

19. The apparatus according to claim 11 or 18, wherein the substrate is a wafer.

20. The apparatus according to claim 11, wherein the chemical compound includes BCl3.

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