Display device and repair method thereof

Abstract

A display device according to an embodiment of the present invention includes: a base layer including a display area and a non-display area; and a plurality of pixels, each having a plurality of sub-pixels including a light-emitting area arranged in the display area and emitting light and a peripheral area arranged around the light-emitting area, wherein the sub-pixels include: at least one first electrode and at least one second electrode, extending in one direction and separated from each other; and a plurality of light-emitting elements, arranged between the first electrode and the second electrode to emit light, wherein at least one of the first electrode and the second electrode includes at least two first electrode patterns separated from each other, and the first electrode patterns are connected by at least one first connection pattern arranged in the light-emitting area.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device, and more particularly, to a display device including an ultra-small light emitting element and a method of repairing the display device. Background Art

[0002] A light emitting diode can have relatively satisfactory durability even under severe environmental conditions and has excellent performance in terms of life span and brightness. Recently, research on a technology for applying such a light emitting diode to various display devices has become quite active.

[0003] As part of such research, technology for manufacturing an LED having a small size corresponding to a micrometer order or a nanometer order using an inorganic crystal structure (for example, a structure obtained by growing a nitride-based semiconductor) is being developed. Summary of the invention

[0004] Technical issues

[0005] Various embodiments of the present disclosure relate to a display device capable of operating a defective pixel as a normal pixel and a method of repairing the display device.

[0006] Technical Solution

[0007] A display device according to an embodiment of the present disclosure may include: a base layer including a display area and a non-display area; and a plurality of pixels arranged in the display area, each including a plurality of sub-pixels each including an emission area configured to emit light and a peripheral area arranged around the emission area. The sub-pixels may include: at least one first electrode and at least one second electrode extending in one direction and spaced apart from each other; and a plurality of light-emitting elements arranged between the first electrode and the second electrode and configured to emit light. At least one of the first electrode and the second electrode may include at least two first electrode patterns spaced apart from each other, and the first electrode patterns may be combined by at least one first connection pattern arranged in the emission area.

[0008] In an embodiment, the first electrode may be disposed between two second electrodes adjacent to each other. The first electrode may include a first electrode pattern.

[0009] In an embodiment, the second electrode may be disposed between two first electrodes adjacent to each other. The second electrode may include a first electrode pattern.

[0010] In an embodiment, the first connection pattern may be integrally formed with the first electrode pattern.

[0011] In an embodiment, the display device may further include: a first contact electrode extending along the first electrode and configured to couple the first electrode to one of the opposite ends of the light emitting element; and a second contact electrode extending along the second electrode and configured to couple the second electrode to the remaining end of the opposite end of the light emitting element. At least one of the first contact electrode and the second contact electrode may include at least two second electrode patterns spaced apart from each other, and the second electrode patterns may be coupled by at least one second connection pattern.

[0012] In an embodiment, the second connection pattern may be integrally formed with one of the first contact electrode and the second contact electrode.

[0013] In an embodiment, the second connection pattern may be formed integrally with the first contact electrode.The first electrode may be disposed between the second connection pattern and the light emitting element.

[0014] In an embodiment, the second connection pattern may be formed integrally with the second contact electrode.The second electrode may be disposed between the second connection pattern and the light emitting element.

[0015] In an embodiment, at least portions of the first connection pattern and the second connection pattern may overlap each other.

[0016] In embodiments, the first connection patterns and the second electrode patterns may be spaced apart from each other.

[0017] In an embodiment, the number of the first connection patterns and the number of the second connection patterns may be different from each other.

[0018] A display device according to an embodiment of the present disclosure may include: a base layer including a display area and a non-display area; and a plurality of pixels arranged in the display area, each including a plurality of sub-pixels including an emission area configured to emit light and a peripheral area arranged around the emission area. The sub-pixels may include: at least one first electrode and at least one second electrode extending in one direction and spaced apart from each other; a plurality of light-emitting elements arranged between the first electrode and the second electrode and configured to emit light; a first contact electrode extending along the first electrode and configured to combine the first electrode with one of the opposite ends of the light-emitting element; and a second contact electrode extending along the second electrode and configured to combine the second electrode with the remaining end of the opposite end of the light-emitting element. At least one of the first electrode and the second electrode may include at least two first electrode patterns spaced apart from each other. At least one of the first contact electrode and the second contact electrode may include at least two second electrode patterns spaced apart from each other, and the second electrode patterns may be combined by at least one connection pattern arranged in the emission area.

[0019] In an embodiment, the connection pattern may be formed integrally with the first contact electrode.The first electrode may be disposed between the connection pattern and the light emitting element.

[0020] In an embodiment, the connection pattern may be formed integrally with the second contact electrode.The second electrode may be disposed between the connection pattern and the light emitting element.

[0021] Embodiments of the present disclosure may provide a method for repairing a display device. The display device may include: a base layer including a display area and a non-display area; and a plurality of pixels arranged in the display area, and each including a plurality of sub-pixels each including an emission area configured to emit light and a peripheral area arranged around the emission area. The pixel may include: a first electrode and a second electrode extending in one direction and separated from each other; and a plurality of light-emitting elements arranged between the first electrode and the second electrode and configured to emit light. At least one of the first electrode and the second electrode may include two electrode patterns separated from each other, and the electrode patterns are combined by at least one connection pattern arranged in the emission area. The method may include separating an electrode pattern combined with a normal light-emitting element among the plurality of light-emitting elements and an electrode pattern combined with a defective light-emitting element among the plurality of light-emitting elements.

[0022] In an embodiment, separating the electrode pattern may include separating a contact electrode coupled to a normal light emitting element from a contact electrode coupled to a defective light emitting element when the contact electrode couples the electrode pattern to one of opposite ends of the light emitting element.

[0023] In an embodiment, the method may further include: when the first electrode includes an electrode pattern, forming a first cutting line on a first contact electrode configured to combine the first electrode with one of opposite ends of the light emitting element; and forming a second cutting line spaced apart from the first cutting line on the first contact electrode. A junction point between the defective light emitting element and the first contact electrode may be disposed between the first cutting line and the second cutting line.

[0024] In an embodiment, a first cutting line and a second cutting line may be formed on the first electrode.

[0025] In an embodiment, the method may further include: when the second electrode includes an electrode pattern, forming a first cutting line on a second contact electrode configured to combine the second electrode with one of opposite ends of the light emitting element; and forming a second cutting line separated from the first cutting line on the second contact electrode. A junction point between the defective light emitting element and the second contact electrode may be disposed between the first cutting line and the second cutting line.

[0026] In an embodiment, a first cutting line and a second cutting line may be formed on the second electrode.

[0027] Beneficial Effects

[0028] In the display device and the method of repairing the display device according to the present disclosure, even when a defective light emitting element exists in a sub-pixel, the defective light emitting element can be easily repaired, and the sub-pixel can be normally operated using other light emitting elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a perspective view showing a light emitting diode according to an embodiment of the present disclosure.

[0030] Figure 2 The display device according to the embodiment of the present disclosure is shown, and the use Figure 1 Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0031] Figures 3a to 3d is a diagram showing various embodiments of the present invention. Figure 2 A circuit diagram of an example of a unit light emitting area of ​​a display device.

[0032] Figure 4 The embodiment of the present disclosure includes Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0033] Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0034] Figures 6a to 6c is a diagram showing various shapes of the first connection pattern Figure 4 A plan view of a sub-pixel.

[0035] Figure 7 is a schematic diagram showing another embodiment of the present disclosure including Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0036] Figure 8 It is along Figure 7 A cross-sectional view taken along line II-II'.

[0037] Figures 9a to 9d is a diagram showing various shapes of the second connection pattern Figure 7 A plan view of a sub-pixel.

[0038] Fig.10a is a schematic diagram showing another embodiment of the present disclosure including Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0039] Fig.10b and Fig.10c wherein the first connection pattern and the second connection pattern are separated from each other Fig.10a A plan view of a sub-pixel.

[0040] Fig.11 The invention schematically shows a modified embodiment of the present invention. Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0041] Fig.12a and Figure 12b is a diagram showing various shapes of connection patterns Fig.11 A plan view of a sub-pixel.

[0042] Fig.13a FIG. 1 is a diagram showing defects caused by a defective light emitting element according to an embodiment of the present disclosure, and only Figure 2 Sub-pixels of the pixel shown in .

[0043] Fig.13b It shows Fig.13a Figure 1 shows the repair method.

[0044] Fig.13c is a diagram showing the emission area after the repair operation Fig.13b . DETAILED DESCRIPTION

[0045] The same components will be represented by the same reference numerals. In addition, it should be noted that the drawings may be exaggerated in thickness, proportion and size of components only for the convenience and clarity of description. The term "and / or" may include any and all combinations of one or more of the related listed items.

[0046] It will be understood that although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be named as the second element. Similarly, the second element can also be named as the first element. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0047] Furthermore, the terms "below", "beneath", "above", "on", etc. are used herein to explain the relationship between one or more components shown in the drawings. These terms may be relative terms describing the positions of components in the drawings.

[0048] It will also be understood that the terms “comprises,” “including,” “having,” and / or variations thereof, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0049] Figure 1 is a perspective view showing a light emitting diode according to an embodiment of the present disclosure.

[0050] like Figure 1 As shown in , the light emitting element LD according to an embodiment of the present disclosure may include a first conductive semiconductor layer 11 , a second conductive semiconductor layer 13 , and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 .

[0051] For example, the light emitting element LD may have a structure formed by continuously stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13. The light emitting element LD may be provided in a rod shape extending in one direction. Here, the term "rod shape" may include a rod-like shape or a strip-like shape extending in a longitudinal direction (ie, having an aspect ratio greater than 1).

[0052] The light emitting element LD may have a rod shape formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13 in a longitudinal direction of the light emitting element LD, and has one end and the other end based on the active layer 12. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on one end of the light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the other end.

[0053] The light emitting element LD may be manufactured in a small size having a diameter and / or length corresponding to, for example, a micrometer-level or nanometer-level size. However, the size of the light emitting element LD according to an embodiment of the present disclosure is not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements of the display device to which the light emitting element LD is applied.

[0054] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant such as Si, Ge, or Sn. The material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0055] The active layer 12 may be formed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. According to an embodiment of the present disclosure, a capping layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the capping layer may be formed of an AlGaN layer or an InAlGaN layer. In addition, a material such as AlGaN or AlInGaN may be used to form the active layer 12.

[0056] If an electric field having a predetermined voltage or higher is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by the combination of electron-hole pairs in the active layer 12 .

[0057] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant such as Mg. The material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0058] According to an embodiment of the present disclosure, the light emitting element LD may include not only the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13, but also a fluorescent layer, another active layer, another semiconductor layer, and / or an electrode layer disposed on and / or below each layer. For example, the light emitting element LD may include an electrode layer disposed on the second conductive semiconductor layer 13.

[0059] The light emitting element LD may further include an insulating film 14. In the embodiment of the present disclosure, the insulating film 14 may be omitted, or may be provided to cover only some of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0060] For example, the insulating film 14 may be provided on a portion of the light emitting element LD except for the opposite ends thereof so that the opposite ends of the light emitting element LD may be exposed. Figure 1 , the insulating film 14 from which a part has been removed is shown for the purpose of explanation, but the light emitting element LD may be formed such that the entire side surface of the cylinder of the light emitting element LD is surrounded by the insulating film 14 .

[0061] The insulating film 14 may be provided to surround at least a portion of the outer peripheral surface of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13. For example, the insulating film 14 may be provided to surround at least the outer peripheral surface of the active layer 12.

[0062] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material in the group consisting of, but the present disclosure is not limited thereto. In other words, various materials having insulating properties may be used.

[0063] If the insulating film 14 is provided on the light emitting element LD, the active layer 12 can be prevented from being short-circuited with the first electrode and / or the second electrode (not shown).

[0064] Due to the insulating film 14, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In the case where a plurality of light emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesired short circuit from occurring between adjacent light emitting elements LD.

[0065] The light emitting element LD can be used as a light source for various display devices. For example, the light emitting element LD can be used in a lighting device or a self-emitting display device.

[0066] Hereinafter, a display device including a light emitting element LD according to an embodiment of the present disclosure will be described in detail.

[0067] Figure 2 The display device according to the embodiment of the present disclosure is shown, and the use Figure 1 Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0068] For illustration purposes, Figure 2 The structure of the display device is schematically shown, focusing on the display area DA on which an image is displayed. In some embodiments, although not shown, at least one driving circuit (eg, a scan driver and a data driver) and / or a plurality of signal lines may also be provided in the display device.

[0069] Reference Figure 1 and Figure 2 According to an embodiment of the present disclosure, a display device may include a base layer BSL, a plurality of pixels PXL disposed on the base layer BSL and each including at least one light emitting element LD, a driver (not shown) disposed on the base layer BSL and configured to drive the pixels PXL, and a line component (not shown) configured to combine the pixels PXL with the driver.

[0070] The display device may be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD. In the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0071] Recently, considering resolution, contrast and operating speed, an active matrix display device capable of selectively turning on each pixel PXL has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix display device in which the pixels PXL can be turned on in groups may also employ components (e.g., a first electrode and a second electrode) for driving the light emitting element LD.

[0072] The base layer BSL may be a substrate of a display device and include a display area DA and a non-display area NDA. The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver for driving the pixels PXL and some of the line components for coupling the pixels PXL to the driver are disposed.

[0073] Although an example in which the display area DA is disposed in the central area of ​​the display device and the non-display area NDA is disposed in the peripheral area of ​​the display device to surround the display area DA is shown in the drawings, the present disclosure is not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0074] The display area DA may have various shapes. For example, the display area DA may be provided in various forms such as a closed polygon including sides formed by straight lines, a circle including sides formed by curved lines, an ellipse, etc., and a semicircle including sides formed by straight lines and curved lines, a semi-ellipse, etc. The non-display area NDA may be provided on at least one side of the display area DA. Although a structure in which the non-display area NDA surrounds the display area DA is shown in the drawings, the present disclosure is not limited thereto.

[0075] The base layer BSL may be a rigid substrate or a flexible substrate, but the present disclosure is not limited thereto. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer BSL may be a transparent substrate, but is not limited thereto. In addition, the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0076] The pixels PXL may be disposed in the display area DA on the base layer BSL. Each of the pixels PXL refers to a minimum unit for displaying an image, and a plurality of pixels PXL may be provided.

[0077] Each of the pixels PXL may include a light emitting element LD configured to be driven in response to a scan signal and a data signal. The light emitting element LD may have a small size corresponding to a nanometer or micrometer level and be coupled in parallel to a light emitting element LD disposed adjacent thereto. The light emitting element LD may form a light source of the corresponding pixel PXL.

[0078] In addition, each of the pixels PXL may include a plurality of sub-pixels SP1, SP2, and SP3. For example, each pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 configured to emit light of different colors. For example, the first sub-pixel SP1 may be a red sub-pixel configured to emit red light, the second sub-pixel SP2 may be a green sub-pixel configured to emit green light, and the third sub-pixel SP3 may be a blue sub-pixel configured to emit blue light. However, the colors, types, and / or numbers of the sub-pixels forming each pixel PXL are not limited to the aforementioned examples.

[0079] Although Figure 2 The pixels PXL are shown to be arranged in the display area DA in a matrix form in a first direction DR1 and a second direction DR2 different from the first direction DR1, but the arrangement of the pixels PXL can be changed in various ways without being limited to the foregoing example. In addition, the arrangement of the plurality of sub-pixels of each pixel PXL can also be changed in various ways.

[0080] The driver may provide a driving signal to each pixel PXL through the line assembly and thus control the operation of the pixel PXL. Figure 2 In the figure, the wire components are omitted for the purpose of convenience of illustration.

[0081] The driver may include a scan driver configured to provide a scan signal to the pixel PXL through a scan line, an emission driver configured to provide an emission control signal to the pixel PXL through an emission control line, a data driver configured to provide a data signal to the pixel PXL through a data line, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0082] Figures 3a to 3d is a diagram showing various embodiments of the present invention. Figure 2 A circuit diagram of an example of a unit light emitting region of a display device.

[0083] Reference Figures 3a to 3d , each of the first to third sub-pixels may be composed of an active pixel. However, the type, configuration and / or driving method of each of the first to third sub-pixels are not particularly limited. For example, each of the first to third sub-pixels may be composed of a pixel of a passive or active display device that may have various known structures.

[0084] In addition, refer to Figures 3a to 3d , the first to third sub-pixels may have substantially the same structure or similar structures. Hereinafter, for the purpose of convenience, the first sub-pixel among the first to third sub-pixels will be described as a representative example.

[0085] Reference Figure 1 , Figure 2 and Figure 3a , the first sub-pixel SP1 may include an emission area EMA configured to generate light having a brightness corresponding to the data signal and a peripheral area disposed around the emission area EMA. Here, a pixel driving circuit 144 for driving the emission area EMA may be disposed in the peripheral area. Although the pixel driving circuit 144 and the emission area EMA are shown as being separated from each other in the drawings, a portion of the pixel driving circuit 144 may be disposed in the emission area EMA.

[0086] The emission area EMA may include a plurality of light emitting elements LD connected in parallel to each other between a first driving power source VDD and a second driving power source VSS. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. Here, during the emission period of the first sub-pixel SP1, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light emitting element LD or more.

[0087] A first electrode (e.g., an anode electrode) of each of the light emitting elements LD may be coupled to a first driving power source VDD via the pixel driving circuit 144. A second electrode (e.g., a cathode electrode) of each of the light emitting elements LD may be coupled to a second driving power source VSS. Each of the light emitting elements LD may emit light at a brightness corresponding to a driving current controlled by the pixel driving circuit 144.

[0088] Although Figures 3a to 3d The light emitting elements LD are shown to be connected in parallel with each other in the same direction (e.g., forward direction) between the first driving power supply VDD and the second driving power supply VSS, but the present disclosure is not limited thereto. For example, some of the light emitting elements LD may be connected to each other in the forward direction between the first driving power supply VDD and the second driving power supply VSS, and other light emitting elements LD may be connected to each other in the reverse direction.

[0089] One of the first driving power source VDD and the second driving power source VSS may be supplied in the form of an AC voltage. In this case, the light emitting elements LD may emit light alternately through the same connection direction group. In addition, the first sub-pixel SP1 may include only a single light emitting element LD.

[0090] The pixel driving circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. The structure of the pixel driving circuit 144 is not limited to Figure 3a The structure of the embodiment shown in .

[0091] A first electrode of the first transistor (T1, a switching transistor) is coupled to the data line Dj, and a second electrode of the first transistor (T1, a switching transistor) is coupled to the first node N1. Here, the first electrode and the second electrode of the first transistor T1 may be different electrodes. If the first electrode is a source electrode, the second electrode is a drain electrode. The gate electrode of the first transistor T1 is coupled to the scan line Si.

[0092] When a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor T1 is supplied from the scan line Si, the first transistor T1 is turned on to electrically couple the data line Dj with the first node N1. Here, a data signal of a corresponding frame is supplied to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged to the storage capacitor Cst.

[0093] A first electrode of the second transistor (T2, driving transistor) is coupled to the first driving power source VDD, and a second electrode of the second transistor (T2, driving transistor) is electrically coupled to a first electrode of each of the light emitting elements LD. A gate electrode of the second transistor T2 is coupled to the first node N1. In this way, the second transistor T2 can control the amount of driving current to be supplied to the light emitting element LD in response to the voltage of the first node N1.

[0094] One electrode of the storage capacitor Cst is coupled to the first driving power source VDD, and the other electrode of the storage capacitor Cst is coupled to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1, and maintains the charged voltage until a data signal of a subsequent frame is supplied.

[0095] For illustration purposes, Figure 3a A pixel driving circuit 144 having a relatively simple structure is shown, which includes a first transistor T1 configured to transmit a data signal to a first subpixel SP1, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to supply a driving current corresponding to the data signal to the light emitting element LD.

[0096] However, the present disclosure is not limited thereto, and the structure of the pixel driving circuit 144 may be changed in various ways. For example, the pixel driving circuit 144 may further include at least one transistor element (such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD) or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1).

[0097] In addition, although Figure 3a The transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel driving circuit 144 are shown to be formed of P-type transistors, but the type of transistor is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 included in the pixel driving circuit 144 may be an N-type transistor.

[0098] like Figure 3b As shown in , in addition to the first transistor T1 and the second transistor T2, the pixel driving circuit 144 may further include a third transistor T3. The third transistor T3 may be coupled between the j-th data line Dj and the anode electrode of each of the light emitting elements LD. The gate electrode of the third transistor T3 may be coupled to the control line CLi, so that the third transistor T3 may be turned on when a control signal is supplied to the control line CLi, and turned off in other cases.

[0099] For convenience purposes, Figure 3b It is shown that all of the first transistor T1 to the third transistor T3 are formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 included in the pixel driving circuit 144 may be formed of an N-type transistor, or all of the first transistor T1 to the third transistor T3 may be N-type transistors.

[0100] Next, refer to Figure 1 , Figure 2 and Figure 3c , the first transistor T1 and the second transistor T2 may be N-type transistors. In addition to the change in the connection position of some components caused by the change in the type of transistor, Figure 3c The configuration and operation of the pixel driving circuit 144 shown in FIG. Figure 3a The configuration and operation of the pixel driving circuit 144 are similar. Therefore, detailed descriptions thereon will be omitted.

[0101] Reference Figure 1 , Figure 2 and Figure 3d, the pixel driving circuit 144 may be coupled to the scan line Si and the data line Dj of the first sub-pixel SP1. For example, if the first sub-pixel SP1 is disposed on the i-th row and the j-th column of the display area DA, the pixel driving circuit 144 of the first sub-pixel SP1 may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0102] In addition, the pixel driving circuit 144 may also be coupled to at least one other scan line. For example, the first subpixel SP1 disposed on the i-th row of the display area DA may also be coupled to the i-1th scan line Si-1 and / or the i+1th scan line Si+1.

[0103] The pixel driving circuit 144 may be coupled not only to the first driving power source VDD and the second driving power source VSS, but also to a third power source. For example, the pixel driving circuit 144 may also be coupled to an initialization power source Vint.

[0104] The pixel driving circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0105] One electrode (e.g., source electrode) of the first transistor (T1, driving transistor) may be coupled to the first driving power source VDD via the fifth transistor T5, and the other electrode (e.g., drain electrode) of the first transistor (T1, driving transistor) may be coupled to one end of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1.

[0106] The second transistor (T2, a switching transistor) may be coupled between the j-th data line Dj coupled to the first sub-pixel SP1 and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 is coupled to the i-th scan line Si coupled to the first sub-pixel SP1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 is turned on to electrically couple the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1.

[0107] The third transistor T3 is coupled between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is coupled to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 is turned on to electrically couple the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0108] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is coupled to a previous scan line, for example, the i-1th scan line Si-1. When a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 is turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than a minimum voltage of the data signal.

[0109] The fifth transistor T5 is coupled between the first driving power source VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is coupled to the corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 can be turned off when the emission control signal having the gate-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0110] The sixth transistor T6 is coupled between the first transistor T1 and one end of the light emitting element LD. The gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0111] The seventh transistor T7 is coupled between one end of the light emitting element LD and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is coupled to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 can be turned on so that the voltage of the initialization power supply Vint can be supplied to the first end of the light emitting element LD.

[0112] The storage capacitor Cst is coupled between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0113] For convenience purposes, Figure 3dIt is shown that all of the first transistor T1 to the seventh transistor T7 are formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 included in the pixel driving circuit 144 may be formed of an N-type transistor, or all of the first transistor T1 to the seventh transistor T7 may be N-type transistors.

[0114] Hereinafter, the following will be described in detail with reference to the accompanying drawings. Figure 2 pixels of a display device.

[0115] Figure 4 The embodiment of the present disclosure includes Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG. Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0116] Although for illustrative purposes, Figure 4 It is shown that a plurality of light emitting elements LD disposed in each sub-pixel are aligned horizontally, but the arrangement of the light emitting elements LD is not limited thereto. For example, at least some of the light emitting elements LD may be aligned in a direction intersecting the horizontal direction. Figure 4 and Figure 5 The transistor coupled to the light emitting element LD and the signal line coupled to the transistor are omitted in FIG. Figure 4 and Figure 5 A simplified structure of one pixel PXL is shown, for example, each electrode is shown to have only a single electrode layer, but the present disclosure is not limited thereto.

[0117] Reference Figures 1 to 5 , the display device according to an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are disposed.

[0118] Each of the pixels PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 disposed on the base layer BSL. In an embodiment of the present disclosure, the first sub-pixel SP1 may be a red sub-pixel configured to emit red light, the second sub-pixel SP2 may be a green sub-pixel configured to emit green light, and the third sub-pixel SP3 may be a blue sub-pixel configured to emit blue light. However, the color, type, and / or number of sub-pixels forming each pixel PXL are not limited to the aforementioned examples.

[0119] Each of the first to third sub-pixels SP1 to SP3 may include an emission area EMA configured to emit light and a peripheral area PPA disposed around a perimeter of the emission area EMA.

[0120] Each of the first to third sub-pixels SP1 to SP3 may include a base layer BSL, a pixel circuit layer PCL, and a display element layer DPL.

[0121] The pixel circuit layer PCL may include a buffer layer BFL disposed on the base layer BSL, a first transistor T1 and a second transistor T2 disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3 may also include a passivation layer PSV disposed on the first transistor T1 and the second transistor T2 and the driving voltage line DVL.

[0122] The base layer BSL may be a rigid or flexible substrate, and the material or properties of the base layer BSL are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or tempered glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer BSL may be a transparent substrate, but the present disclosure is not limited thereto, and the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate. In addition, although the base layer BSL is shown in the drawings as having a single-layer structure, the base layer BSL may have a multi-layer structure.

[0123] The buffer layer BFL may prevent impurities from diffusing into the first transistor T1 and the second transistor T2. The buffer layer BFL may be omitted depending on the material or processing conditions of the substrate.

[0124] The first transistor T1 may be electrically coupled to some of the light emitting elements LD disposed on the display element layer DPL of the corresponding sub-pixel. In this case, the first transistor T1 may be a driving transistor configured to drive the light emitting element LD. The second transistor T2 may be a switching transistor configured to switch the first transistor T1.

[0125] Each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0126] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a source region contacting the source electrode SE and a drain region contacting the drain electrode DE. A region between the source region and the drain region may be a channel region.

[0127] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor of an undoped semiconductor pattern. Each of the source region and the drain region may be a semiconductor pattern doped with impurities.

[0128] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. The source electrode SE and the drain electrode DE may contact the source region and the drain region of the semiconductor layer SCL respectively through corresponding contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0129] In the drawings, although the first transistor T1 and the second transistor T2 are LTPS thin film transistors, the first transistor T1 and the second transistor T2 are not limited thereto.

[0130] In addition, although the driving voltage line DVL is shown as being disposed on the interlayer insulating layer ILD in the drawings, the location of the driving voltage line DVL is not limited thereto. For example, the driving voltage line DVL may be disposed on any insulating layer included in the pixel circuit layer PCL. Figure 3a VSS) can be applied to the driving voltage line DVL.

[0131] The passivation layer PSV may include a first contact hole CH1 exposing a portion of the drain electrode DE of the first transistor T1 and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0132] The display element layer DPL may be disposed on the pixel circuit layer PCL and may include a wall PW, a bank BNK, first and second electrodes REL1 and REL2, first and second connection lines CNL1 and CNL2, a plurality of light emitting elements LD, first and second contact electrodes CNE1 and CNE2, and the like.

[0133] A wall PW may be disposed on the passivation layer PSV in the emission area EMA of each of the first to third subpixels SP1 to SP3. A bank BNK formed of the same material as the wall PW may be formed and / or disposed between adjacent subpixels to define the emission area EMA of each subpixel.

[0134] Adjacent walls PW may be disposed on the passivation layer PSV and spaced apart from each other by a length L of one light emitting element LD or more. The light emitting element LD may be disposed between adjacent walls PW in the emission area EMA.

[0135] The wall PW may include a curved surface having a cross-sectional shape such as a semicircular or semi-elliptical shape, the width of which decreases upward from one surface of the passivation layer PSV. In the drawings, the wall PW is shown as having a trapezoidal cross-section. In the cross-sectional view, the shape of each of the walls PW is not limited to the aforementioned example, and may be changed in various ways within the range that the efficiency of light emitted from each of the light emitting elements LD can be enhanced.

[0136] The bank BNK may be further disposed on the passivation layer PSV. The bank BNK may be disposed in the peripheral area PPA between adjacent sub-pixels SP1 to SP3 and define an emission area EMA of each of the sub-pixels SP1 to SP3. The bank BNK may prevent light emitted from the sub-pixels SP1 to SP3 from traveling to adjacent sub-pixels SP1 to SP3.

[0137] The wall PW and the bank BNK may be formed of the same material on the same layer. For example, although the wall PW and the bank BNK may be formed of an organic insulating material including an organic material, the present disclosure is not limited thereto.

[0138] The first connection line CNL1 may be electrically coupled to the pixel circuit layer PCL through a first contact hole CH1 formed in the passivation layer PSV. In detail, the first connection line CNL1 may be connected to a portion of the drain electrode DE of the first transistor T1 of the pixel circuit layer PCL. Figure 4 The first contact hole CH1 is shown to be formed in the peripheral area PPA, but the first contact hole CH1 may be formed in the emission area EMA.

[0139] The first connection line CNL1 may extend from each of the first to third sub-pixels SP1 to SP3 in the first direction DR1. In order to independently drive each of the first to third sub-pixels SP1 to SP3, one first connection line CNL1 may be disposed in each sub-pixel.

[0140] The second connection line CNL2 may also be electrically coupled to the pixel circuit layer PCL through a second contact hole CH2 formed in the passivation layer PSV. In detail, the second connection line CNL2 may be connected to a portion of the driving voltage line DVL of the pixel circuit layer PCL.

[0141] The second connection line CNL2 may extend in a direction parallel to the direction in which the first connection line CNL1 extends. The second connection line CNL2 may be provided in common to the first to third subpixels SP1 to SP3. Therefore, the first to third subpixels SP1 to SP3 may be commonly coupled to the second connection line CNL2.

[0142] Each of the first and second electrodes REL1 and REL2 may be disposed in the emission area EMA of each of the first to third subpixels SP1 to SP3 and extend in a second direction DR2 intersecting the first direction DR1. The first and second electrodes REL1 and REL2 may be disposed on the same plane and spaced apart from each other by a predetermined distance.

[0143] Although the drawings show a case where two first electrodes REL1 and second electrodes REL2 are provided in each of the sub-pixels SP1 to SP3, one or more first electrodes REL1 and second electrodes REL2 may be provided in each of the sub-pixels SP1 to SP3. In the case where a plurality of first electrodes REL1 and second electrodes REL2 are provided, the first electrodes REL1 and second electrodes REL2 may be alternately provided.

[0144] The first electrode REL1 may be coupled to the first connection line CNL1. For example, the first electrode REL1 may be integrally coupled to the first connection line CNL1. In the drawings, a case where the first electrode REL1 diverges from the first connection line CNL1 in the second direction DR2 is shown. Although the first electrode REL1 is shown to have two first electrode patterns in the drawings, the number of the first electrode REL1 and the number of the first electrode patterns are not limited thereto.

[0145] In the case where the first electrode REL1 and the first connection line CNL1 are formed and / or disposed integrally with each other, the first connection line CNL1 can be considered as a region of the first electrode REL1. However, the present disclosure is not limited thereto. For example, in some embodiments, the first electrode REL1 and the first connection line CNL1 can be formed separately and electrically coupled to each other through a contact hole, a through hole, etc. not shown.

[0146] The first electrode REL1 may be disposed adjacent to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. In the drawings, a case is shown where the first electrode REL1 is disposed adjacent to the first end EP1 of the light emitting element LD and the first electrode REL1 is electrically coupled to the first end EP1 of the light emitting element LD through the first contact electrode CNE1. Therefore, a signal of the first transistor T1 applied to the first electrode REL1 may be transmitted to each of the light emitting elements LD through the first contact electrode CNE1.

[0147] The second electrode REL2 may be coupled to the second connection line CNL2. For example, the second electrode REL2 may be integrally coupled to the second connection line CNL2. Although the drawings show that the second connection line CNL2 extends in the first direction DR1 and the second electrode REL2 has two first electrode patterns, the number of the second electrodes REL2 and the number of the first electrode patterns are not limited thereto.

[0148] In the case where the second electrode REL2 and the second connection line CNL2 are formed and / or arranged integrally with each other, the second connection line CNL2 can be considered as a region of the second electrode REL2. However, the present disclosure is not limited thereto. For example, in some embodiments, the second electrode REL2 and the second connection line CNL2 can be formed separately and electrically connected to each other through a contact hole, a through hole, etc. not shown.

[0149] The second electrode REL2 may be disposed adjacent to the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD. In the drawings, a case is shown where the second electrode REL2 is electrically coupled to the second end EP2 of the light emitting element LD through the second contact electrode CNE2. Therefore, the voltage of the second driving power source VSS applied to the second electrode REL2 may be transmitted to each of the light emitting elements LD.

[0150] Each of the first electrode REL1 and the second electrode REL2 may function as an alignment electrode for aligning the light emitting element LD in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 .

[0151] In detail, before the light emitting element LD is aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, a first alignment voltage may be applied to the first electrode REL1 through the first connection line CNL1, and a second alignment voltage may be applied to the second electrode REL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. When predetermined alignment voltages having different voltage levels are respectively applied to the first electrode REL1 and the second electrode REL2, an electric field may be formed between the first electrode REL1 and the second electrode REL2. Therefore, the light emitting element LD may be aligned between the first electrode REL1 and the second electrode REL2.

[0152] In a plan view, in each sub-pixel, the second electrode REL2 and the first electrode REL1 may be alternately disposed. In the drawing, a case where the second electrode REL2 is disposed between the first electrodes REL1 is shown.

[0153] After the light emitting element LD is aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 , each of the first and second electrodes REL1 and REL2 may function as a driving electrode for driving the light emitting element LD.

[0154] The first electrode REL1 and the second electrode REL2 disposed on the wall PW may be made of a material having a predetermined reflectivity to allow light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD to travel in a direction along which an image of the display device is displayed (e.g., in a forward direction). In this case, the first electrode REL1 and the second electrode REL2 may function as a reflector for enhancing the efficiency of light emitted from the light emitting element LD.

[0155] In detail, the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 may be formed of a conductive material having a predetermined reflectivity. Metals (e.g., Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof) may be used as the conductive material. However, the materials of the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 are not limited to the aforementioned materials.

[0156] Although the drawings show a case where each of the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 has a single-layer structure, it may have a multi-layer structure formed by stacking two or more materials among metals, alloys, conductive oxides, and conductive polymers.

[0157] Any one of the first electrode REL1 and the second electrode REL2 may be an anode electrode, and the other may be a cathode electrode. In an embodiment of the present disclosure, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode.

[0158] In an embodiment of the present disclosure, at least one first connection pattern CNP1 may be provided in the emission area EMA. At least one first connection pattern CNP1 may combine two first electrode patterns separated from each other. For example, at least one first connection pattern CNP1 may combine the first electrode pattern of the first electrode REL1 or the first electrode pattern of the second electrode REL2. In the accompanying drawings, a case where at least one first connection pattern CNP1 combines the first electrode pattern of the second electrode REL2 is shown.

[0159] The first connection pattern CNP1 may be spaced apart from the second connection line CNL2 and disposed in the emission area EMA of each of the sub-pixels SP1 to SP3. Here, the first connection pattern CNP1 may be integrally formed with the second electrode REL2.

[0160] When defects are caused by some of the plurality of light emitting elements LD provided in each of the sub-pixels and the sub-pixels are repaired, the first connection pattern CNP1 may serve to minimize the non-emission area of ​​the sub-pixels.

[0161] For example, in the case where a defective light emitting element is detected, a portion of the second electrode REL2 coupled to the defective light emitting element may be separated (disconnected). In this case, even when a portion of the second electrode REL2 is separated (disconnected), other light emitting elements LD are coupled to the second electrode REL2 through the first connection pattern CNP1 and thus may operate normally.

[0162] Each of the light emitting elements LD may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size corresponding to, for example, a nanometer order or a micrometer order.

[0163] Although at least two or tens of light emitting elements LD are disposed in the emission area EMA of each of the first to third subpixels SP1 to SP3, the present disclosure is not limited thereto. In embodiments, the number of light emitting elements LD disposed in each subpixel may be changed in various ways.

[0164] Each of the light emitting elements LD may include a stacked emission pattern formed by continuously stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13 in a longitudinal direction of each light emitting element LD. In addition, each of the light emitting elements LD may further include an insulating film 14 surrounding the outer peripheral surface of the stacked emission pattern. In the embodiment of the present disclosure, each of the light emitting elements LD may have a cylindrical shape. In this case, each light emitting element LD may have a first end EP1 corresponding to any one of the lower part of the cylinder and the upper part of the cylinder and a second end EP2 corresponding to the other of the lower part of the cylinder and the upper part of the cylinder. Any one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the first end EP1 of each light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the second end EP2 of each light emitting element LD.

[0165] In an embodiment of the present disclosure, the light emitting element LD may be aligned between the first electrode REL1 and the second electrode REL2. The second insulating layer INS2 may be disposed on the light emitting element LD to cover a portion of the upper surface of each of the light emitting elements LD. The first insulating layer INS1 may be disposed between each of the light emitting elements LD and the passivation layer PSV.

[0166] The first insulating layer INS1 may be filled into the space between the passivation layer PSV and each of the light emitting elements LD to stably support the light emitting element LD and prevent the light emitting element LD from being removed from the passivation layer PSV. The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer having the advantage of protecting the light emitting element LD from the pixel circuit layer PCL, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer having the advantage of planarizing the supporting surface of the light emitting element LD.

[0167] The second insulating layer INS2 may be disposed on the light emitting element LD. The second insulating layer INS2 may be an organic insulating layer including an organic material. In an embodiment of the present disclosure, the second insulating layer INS2 may be disposed on a portion of the upper surface of each of the light emitting elements LD so that the opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside. The first contact electrode CNE1 and the second contact electrode CNE2 may be coupled to the exposed opposite ends EP1 and EP2 of the light emitting element LD.

[0168] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same plane and may be separated from each other by a predetermined distance on the second insulating layer INS2 and thus electrically and / or physically separated from each other. In other words, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer and formed by the same manufacturing process. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers.

[0169] The first contact electrode CNE1 and the second contact electrode CNE2 may be respectively combined with the first electrode REL1 and the second electrode REL2 exposed from the first insulating layer INS1. The first contact electrode CNE1 and the second contact electrode CNE2 and the first electrode REL1 and the second electrode REL2 may be disposed on the wall PW. In other words, as described above, the first contact electrode CNE1 and the second contact electrode CNE2 may respectively extend in the directions along which the first electrode REL1 and the second electrode REL2 extend, and may respectively overlap with the first electrode REL1 and the second electrode REL2 on the corresponding wall PW.

[0170] In other words, the first contact electrode CNE1 may include second electrode patterns respectively coupled to the first electrode patterns of the first electrodes REL1. The second contact electrode CNE2 may also include second electrode patterns respectively coupled to the first electrode patterns of the second electrodes REL2.

[0171] The first and second contact electrodes CNE1 and CNE2 may be formed of a transparent conductive material to allow light emitted from the light emitting element LD to travel in a forward direction of the display device through the first and second electrodes REL1 and REL2 .

[0172] A third insulating layer INS3 for covering the first and second contact electrodes CNE1 and CNE2 may be disposed on the first and second contact electrodes CNE1 and CNE2. The third insulating layer INS3 may prevent the first and second contact electrodes CNE1 and CNE2 from being exposed to the outside, thereby preventing the first and second contact electrodes CNE1 and CNE2 from being corroded.

[0173] The third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although the third insulating layer INS3 may have a single-layer structure as shown in the drawings, the present disclosure is not limited thereto. For example, the third insulating layer INS3 may have a multi-layer structure. In the case where the third insulating layer INS3 has a multi-layer structure, the third insulating layer INS3 may have a structure formed by alternately stacking a plurality of inorganic insulating layers and a plurality of organic insulating layers. For example, the third insulating layer INS3 may have a structure formed by sequentially stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer.

[0174] As described above, the opposite ends EP1 and EP2 of the light emitting element LD can be respectively coupled to the first electrode REL1 and the second electrode REL2 through the first contact electrode CNE1 and the second contact electrode CNE2, so that a predetermined voltage can be applied to the opposite ends EP1 and EP2, respectively, and each of the light emitting elements LD can emit light by combining electron-hole pairs in the active layer 12 of the light emitting element LD. Here, the active layer 12 can emit light having a wavelength range of 400nm to 900nm. However, the wavelength range of the light emitted from the active layer 12 is not limited thereto and can be changed in various ways.

[0175] As described above, in the display device according to the present disclosure, the first electrode patterns of the second electrode REL2 may be coupled to each other through at least one first connection pattern CNP1 so that the number of light emitting elements LD that do not emit light may be minimized even when some light emitting elements LD are defective.

[0176] Here, the first connection pattern CNP1 may be formed in various shapes and couple the first electrode patterns of the second electrode REL2 to each other.

[0177] Figures 6a to 6c is a diagram showing various shapes of the first connection pattern Figure 4 A plan view of a sub-pixel.

[0178] like Figures 6a to 6c As shown in FIG. 1 , the first electrode patterns of the second electrode REL2 may be connected to each other through a plurality of first connection patterns CNP1. The plurality of first connection patterns CNP1 may be as shown in FIG. Figure 6a and Figure 6b In the direction perpendicular to the direction along which the second electrode REL2 extends, as shown in FIG. Figure 6c The settings shown in are in the diagonal direction.

[0179] The second electrode pattern of one of the first contact electrode CNE1 and the second contact electrode CNE2 may be coupled by at least one second connection pattern.

[0180] Figure 7 is a schematic diagram showing another embodiment of the present disclosure including Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG. Figure 8 It is along Figure 7 A cross-sectional view taken along line II-II'. Figures 9a to 9d is a diagram showing various shapes of the second connection pattern Figure 7 A plan view of a sub-pixel.

[0181] like Figure 7 and Figure 8 As shown in , the second electrode pattern of the second contact electrode CNE2 may be combined by the second connection pattern CNP2. The second electrode pattern of the second contact electrode CNE2 and the second connection pattern CNP2 may be formed integrally with each other. Figures 9a to 9d As shown in FIG. 8 , a plurality of second connection patterns CNP2 may be provided.

[0182] In an embodiment of the present disclosure, the first electrode pattern of one of the first and second electrodes REL1 and REL2 may be coupled by at least one first connection pattern CNP1. The second electrode pattern of one of the first and second contact electrodes CNE1 and CNE2 may be coupled by at least one second connection pattern CNP2.

[0183] Fig.10a is a schematic diagram showing another embodiment of the present disclosure including Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG. Fig.10b and Fig.10c wherein the first connection pattern and the second connection pattern are separated from each other Fig.10a A plan view of a sub-pixel.

[0184] like Fig.10a and Fig.10b As shown in , the first electrode patterns of the second electrode REL2 may be coupled via the first connection pattern CNP1 , and the second electrode patterns of the second contact electrode CNE2 may be coupled via the second connection pattern CNP2 .

[0185] like Fig.10a As shown in , the first connection pattern CNP1 and the second connection pattern CNP2 may completely overlap each other, or at least partially overlap each other. Fig.10b As shown in , the first connection pattern CNP1 and the second connection pattern CNP2 may be spaced apart from each other instead of overlapping each other. Fig.10c As shown in FIG. 1 , the number of the first connection patterns CNP1 and the number of the second connection patterns CNP2 may be different from each other.

[0186] At least one first connection pattern CNP1 may be coupled to the first electrode pattern of the second electrode REL2. In this case, the sub-pixel may be repaired by cutting off a portion of the second electrode REL2.

[0187] Fig.11 The invention schematically shows a modified embodiment of the present invention. Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG. Fig.12a and Figure 12b is a diagram showing various shapes of connection patterns Fig.11 A plan view of a sub-pixel.

[0188] like Fig.11 As shown in , the first connection pattern CNP1 disposed in the emission area EMA may be combined with the first electrode pattern of the first electrode REL1. Here, the first connection pattern CNP1 may be integrally formed with the first electrode pattern of the first electrode REL1.

[0189] In this case, the first electrode REL1 may be disposed between the second electrodes REL2. In the case where a defective light emitting element is detected, a portion of the first electrode REL1 coupled to the defective light emitting element may be separated (disconnected). In this case, even when a portion of the first electrode REL1 is separated (disconnected), another portion of the first electrode REL1 may be coupled through the first connection pattern CNP1, so that the number of light emitting elements LD that do not emit may be minimized.

[0190] like Fig.12a As shown in , the first contact electrode CNE1 may include a second electrode pattern so that the second electrode pattern of the first contact electrode CNE1 may be integrated with the second connection pattern CNP2. Figure 12b As shown in , the first electrode patterns of the first contact electrodes REL1 may be coupled via the first connection pattern CNP1 , and the second electrode patterns of the first contact electrodes CNE1 may be coupled via the second connection pattern CNP2 .

[0191] Here, the first connection patterns CNP1 and the second connection patterns CNP2 may be spaced apart from each other without overlapping each other. The number of the first connection patterns CNP1 and the number of the second connection patterns CNP2 may be different from each other.

[0192] In the display device according to the present disclosure, when repairing the sub-pixels SP1 to SP3 in which defective light-emitting elements are arranged, some of the first electrode REL1 and the first contact electrode CNE1 or the second electrode REL2 and the second contact electrode CNE2 connected by at least one of the first connection pattern CNP1 and the second connection pattern CNP2 can be disconnected, so that the number of light-emitting elements LD that do not emit light can be minimized.

[0193] For example, in the case where the first connection pattern CNP1 is directly coupled to the first electrode pattern of the first electrode REL1 or the second connection pattern CNP2 is integrally formed with the second electrode pattern of the first contact electrode CNE1 so that the first electrode pattern of the first electrode REL1 is indirectly coupled via the second connection pattern CNP2, the periphery of the first electrode REL1 coupled to the defective light emitting element may be disconnected. Conversely, in the case where the first connection pattern CNP1 is directly coupled to the first electrode pattern of the second electrode REL2 or the second connection pattern CNP2 is integrally formed with the second electrode pattern of the second contact electrode CNE2 so that the first electrode pattern of the second electrode REL2 is indirectly coupled, the periphery of the second electrode REL2 coupled to the defective light emitting element may be disconnected.

[0194] Hereinafter, a method of repairing a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0195] Fig.13a FIG. 1 is a diagram showing defects caused by a defective light emitting element according to an embodiment of the present disclosure, and only Figure 2 Sub-pixels of the pixel shown in . Fig.13b It shows Fig.13a Figure 1 shows the repair method. Fig.13c is a diagram showing the emission area after the repair operation Fig.13b .

[0196] like Fig.13a As shown in FIG. 1 , in the case where some of the plurality of light emitting elements LD disposed in the sub-pixel are defective light emitting elements DLD, the first electrode REL1 and the second electrode REL2 may be short-circuited by the defective light emitting elements DLD. In this case, the signal cannot pass through the first contact hole ( Figure 4 CH1) is transmitted to some light emitting elements LD arranged in parallel with the defective light emitting element DLD.

[0197] In detail, as shown, the signal does not pass through the first contact hole ( Figure 4 The signal CH1 is transmitted to the light emitting element LD disposed at the far end closer to the first electrode REL1 than the defective light emitting element DLD. Therefore, the signal cannot pass through the first contact hole ( Figure 4 The area of ​​the light emitting element LD to which CH1 is transmitted may be the non-emitting area NEMA.

[0198] In the embodiments of the present disclosure, Fig.13bAs shown in FIG. 1 , a portion of the first electrode pattern coupled to the first connection pattern CNP1 among one end of the defective light emitting element DLD may be separated (disconnected) so that a defect of a sub-pixel attributable to the defective light emitting element DLD may be repaired.

[0199] For example, as shown in the drawing, in the case where the first electrode patterns of the second electrode REL2 are coupled through the first connection pattern CNP1 , the position of the defective light emitting element DLD is checked, and then a portion of the second electrode REL2 is cut off by a process such as a laser cutting process.

[0200] In detail, a first cutting line CL1 is formed on the second contact electrode CNE2 that combines the second electrode REL2 with one of the opposite ends of each defective light emitting element DLD. A second cutting line CL2 is formed on the second contact electrode CNE2 at a position separated from the first cutting line CL1. Here, a junction point between the defective light emitting element DLD and the second contact electrode CNE2 is disposed between the first cutting line CL1 and the second cutting line CL2. When the first cutting line CL1 and the second cutting line CL2 are formed on the second contact electrode CNE2 as described above, the second electrode REL2 below the second contact electrode CNE2 may also be cut.

[0201] Although not shown, in the case where the first electrode REL1 corresponds to the first electrode pattern coupled through the first connection pattern CNP1 , the position of the defective light emitting element DLD is checked and then a portion of the first electrode REL1 may be cut off by a process such as a laser cutting process.

[0202] In detail, a first cutting line CL1 is formed on the first contact electrode CNE1 that combines the first electrode REL1 with one of the opposite ends of each defective light emitting element DLD. A second cutting line CL2 is formed on the first contact electrode CNE1 at a position separated from the first cutting line CL1. Here, a junction point between the defective light emitting element DLD and the first contact electrode CNE1 is disposed between the first cutting line CL1 and the second cutting line CL2. When the first cutting line CL1 and the second cutting line CL2 are formed on the first contact electrode CNE1 as described above, the first electrode REL1 below the first contact electrode CNE1 may also be cut.

[0203] Therefore, in the repair method of the display device according to the embodiment of the present disclosure, the first electrode REL1 and the first contact electrode CNE1 or the second electrode REL2 and the second contact electrode CNE2 in the area combined with the defective light emitting element DLD can be floated. Therefore, the signal of the pixel circuit layer is not transmitted only to the defective light emitting element DLD, so that the area where only the defective light emitting element DLD is provided is the non-emission area NEMA, and other light emitting elements LD can receive the signal of the pixel circuit layer through the connection pattern CNP and emit light normally. Therefore, the size of the non-emission area formed by the repair can be minimized.

[0204] Although the embodiments of the present disclosure have been disclosed, it will be appreciated by those skilled in the art that the present disclosure may be implemented in other specific forms without departing from the scope and spirit of the disclosure as disclosed in the appended claims. Therefore, it should be understood that the embodiments are only for illustrative purposes and do not limit the boundaries of the present invention.

Claims

1. A display device, comprising: A substrate layer including a display area and a non-display area; as well as a plurality of pixels disposed in the display area and each including a plurality of sub-pixels each including an emission area configured to emit light and a peripheral area disposed around the emission area, The subpixel includes: a first connection line and a second connection line extending in a first direction; at least one first electrode and at least one second electrode branching from the first connection line and the second connection line to extend in a second direction perpendicular to the first direction, and spaced apart from each other in the first direction; and a plurality of light emitting elements arranged between the first electrode and the second electrode and configured to emit light. At least one of the first electrode and the second electrode includes at least two first electrode patterns separated from each other, and the first electrode patterns are combined by at least one first connection pattern arranged in the emission area, and the at least one first connection pattern is arranged between the first connection line and the second connection line.

2. The display device according to claim 1, in, The first electrode is disposed between two second electrodes adjacent to each other, and Wherein, the first electrode includes a first electrode pattern.

3. The display device according to claim 1, in, The second electrode is disposed between two first electrodes adjacent to each other, and Wherein, the second electrode includes a first electrode pattern.

4. The display device according to claim 1, wherein: The first connection pattern is integrally formed with the first electrode pattern.

5. The display device according to claim 1, further comprising: a first contact electrode extending along the first electrode and configured to couple the first electrode to one of the opposite ends of the light emitting element; as well as a second contact electrode extending along the second electrode and configured to couple the second electrode to the remaining end of the opposite end of the light emitting element, At least one of the first contact electrode and the second contact electrode includes at least two second electrode patterns separated from each other, and the second electrode patterns are connected by at least one second connection pattern.

6. The display device according to claim 5, wherein: A second connection pattern is integrally formed with one of the first contact electrode and the second contact electrode.

7. The display device according to claim 6, in, A second connection pattern is formed integrally with the first contact electrode, and Wherein, the first electrode is arranged between the second connection pattern and the light emitting element.

8. The display device according to claim 6, in, A second connection pattern is formed integrally with the second contact electrode, and The second electrode is arranged between the second connection pattern and the light emitting element.

9. The display device according to claim 5, wherein: At least a portion of the first connection pattern and the second connection pattern overlap each other.

10. The display device according to claim 5, wherein: The first connection patterns and the second electrode patterns are spaced apart from each other.

11. The display device according to claim 5, wherein: The number of the first connection patterns and the number of the second connection patterns are different from each other.

12. A display device, comprising: A substrate layer including a display area and a non-display area; as well as a plurality of pixels disposed in the display area and each including a plurality of sub-pixels each including an emission area configured to emit light and a peripheral area disposed around the emission area, The subpixel includes: at least one first electrode and at least one second electrode, extending in one direction and spaced apart from each other; a plurality of light emitting elements, disposed between the first electrode and the second electrode and configured to emit light; a first contact electrode, extending along the first electrode and configured to combine the first electrode with one of the opposite ends of the light emitting element; and a second contact electrode, extending along the second electrode and configured to combine the second electrode with the remaining end of the opposite end of the light emitting element. wherein at least one of the first electrode and the second electrode comprises at least two first electrode patterns separated from each other, and At least one of the first contact electrode and the second contact electrode includes at least two second electrode patterns separated from each other, and the second electrode patterns are connected by at least one connection pattern provided in the emission region.

13. The display device according to claim 12, in, A connection pattern is formed integrally with the first contact electrode, and Wherein, the first electrode is arranged between the connection pattern and the light emitting element.

14. The display device according to claim 12, in, A connection pattern is formed integrally with the second contact electrode, and The second electrode is arranged between the connection pattern and the light emitting element.

15. A method for repairing a display device, in, The display device includes: a base layer including a display area and a non-display area; and a plurality of pixels disposed in the display area and each including a plurality of sub-pixels each including an emission area configured to emit light and a peripheral area disposed around the emission area, The subpixel includes: a first connection line and a second connection line extending in a first direction; a first electrode and a second electrode branching from the first connection line and the second connection line to extend in a second direction perpendicular to the first direction, and spaced apart from each other in the first direction; and a plurality of light emitting elements arranged between the first electrode and the second electrode and configured to emit light. wherein at least one of the first electrode and the second electrode includes two electrode patterns separated from each other, and the electrode patterns are combined by at least one connection pattern provided in the emission region, and the at least one connection pattern is provided between the first connection line and the second connection line, The method includes separating an electrode pattern combined with a normal light emitting element among the plurality of light emitting elements and an electrode pattern combined with a defective light emitting element among the plurality of light emitting elements.

16. The method according to claim 15, wherein: Separating the electrode pattern includes: when the contact electrode combines the electrode pattern with one of the opposite ends of the light emitting element, The contact electrode bonded to the normal light emitting element among the plurality of light emitting elements is separated from the contact electrode bonded to the defective light emitting element.

17. The method according to claim 16, further comprising: When the first electrode includes an electrode pattern, forming a first cutting line on a first contact electrode configured to couple the first electrode to one of opposite ends of the light emitting element; as well as forming a second cutting line separated from the first cutting line on the first contact electrode, Wherein, a junction between the defective light emitting element and the first contact electrode is arranged between the first cutting line and the second cutting line.

18. The method according to claim 17, wherein: The first cutting line and the second cutting line are formed on the first electrode.

19. The method according to claim 16, further comprising: When the second electrode includes an electrode pattern, forming a first cutting line on a second contact electrode configured to couple the second electrode to one of opposite ends of the light emitting element; as well as forming a second cutting line separated from the first cutting line on the second contact electrode, Wherein, a junction between the defective light emitting element and the second contact electrode is arranged between the first cutting line and the second cutting line.

20. The method according to claim 19, wherein: The first cutting line and the second cutting line are formed on the second electrode.

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