Intelligent load identification circuit, method and photovoltaic power generation system

Abstract

The present application relates to the field of photovoltaic energy storage devices, and in particular to an intelligent load identification circuit, method, and photovoltaic power generation system, wherein the intelligent load identification circuit includes a control circuit, a power supply circuit, and a load interface. The power supply circuit includes a power input terminal for receiving electrical energy and a first power output terminal, the first power output terminal being connected to the control circuit, a sampling circuit being connected between the control circuit and the load interface, the sampling circuit being used to detect the voltage and / or current output by an external load received by the load interface; the power supply circuit also includes a second power output terminal, a switching circuit being connected between the second power output terminal and the load interface, the switching circuit being connected to the control circuit, and the switching circuit being used to control the conduction or disconnection of the circuit between the power supply circuit and the load interface. The present application has the effect of improving the safety of external load charging.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic off-grid energy storage equipment, and in particular to an intelligent load identification circuit, method and photovoltaic power generation system. Background Art

[0002] At present, solar photovoltaic power generation systems have been widely used due to their clean, safe, convenient and efficient characteristics.

[0003] In related technologies, photovoltaic power generation systems generate electricity through solar panels and store the electrical energy in batteries. The solar panels and batteries together constitute a photovoltaic power generation module and serve as a charging power source for external loads. By connecting the charging interface of the external load to the load interface of the photovoltaic power generation system, the external load can be charged.

[0004] Regarding the related technologies mentioned above, the inventors believe that if the external load is not equipped with a charging protection circuit, the charging interface of the external load can output voltage and current to the outside and the charging limit voltage of the external load is lower than the output voltage of the load interface. In the process of using the load interface to charge the external load, the external load will be overcharged and there is a possibility of explosion, posing a safety hazard. Summary of the Invention

[0005] In order to improve the safety of external load charging, the present application provides an intelligent load identification circuit, method and photovoltaic power generation system.

[0006] In a first aspect, the present application provides an intelligent load identification circuit, which adopts the following technical solution:

[0007] An intelligent load identification circuit includes a control circuit, a power supply circuit, and a load interface. The power supply circuit includes a power input terminal for receiving electric energy and a first power output terminal, the first power output terminal being connected to the control circuit. A sampling circuit is connected between the control circuit and the load interface, and the sampling circuit is used to detect the voltage and / or current output by an external load received by the load interface.

[0008] The power supply circuit also includes a second power supply output end, a switching circuit is connected between the second power supply output end and the load interface, the switching circuit is connected to the control circuit, and the switching circuit is used to control the circuit between the power supply circuit and the load interface to be turned on or off.

[0009] By adopting the above technical solution, when charging an external load, the control circuit controls the switch circuit to disconnect. If the external load is not equipped with a charging protection circuit, and the charging interface of the external load outputs voltage and current, the sampling circuit can detect the presence of voltage and / or current at the load interface, and the control circuit continues to control the switch circuit to disconnect, resulting in the circuit between the power supply circuit and the load interface being disconnected, making the power supply circuit unable to charge the external load. If the external load is equipped with a charging protection circuit, and the charging interface of the external load does not output voltage and current, the control circuit controls the switch circuit to connect, connecting the circuit between the power supply circuit and the load interface, allowing the power supply circuit to charge the external load. Therefore, by adding a switching circuit and a sampling circuit, the possibility of overcharging the external load can be reduced, thereby improving the safety of external load charging.

[0010] Optionally, the switching circuit includes a MOS transistor T11, the gate of the MOS transistor T11 is connected to the signal output end of the control circuit, the drain of the MOS transistor T11 is connected to the load interface, and the source of the MOS transistor T11 is connected to the second power output end of the power supply circuit.

[0011] By adopting the above technical solution, the control circuit outputs a high-level signal, which increases the gate voltage of MOS transistor T11, connects the drain and source of MOS transistor T11, and connects the power supply circuit to the load interface. When the control circuit outputs a low-level signal, the gate voltage of MOS transistor T11 decreases, disconnects the drain and source of MOS transistor T11, and disconnects the power supply circuit from the load interface. The high and low level signals output by the control circuit control the conduction and disconnection of MOS transistor T11, thereby controlling the conduction or disconnection of the circuit between the power supply circuit and the load interface. This results in a simple circuit design and high reliability.

[0012] Optionally, the sampling circuit includes:

[0013] A voltage sampling circuit, used to detect whether the load interface receives the voltage output by the external load;

[0014] The current sampling circuit is used to detect whether the load interface receives the current output by the external load.

[0015] By adopting the above technical solution, a voltage sampling circuit can be set to sample the voltage of the load interface, or a current sampling circuit can be set to sample the current of the load interface. A voltage sampling circuit and a current sampling circuit can also be set at the same time to sample the voltage and current of the load interface.

[0016] Optionally, the power supply circuit further includes a step-down circuit, a voltage input end of the step-down circuit is connected to the power input end of the power supply circuit, and a voltage output end of the step-down circuit is connected to the second power output end of the power supply circuit.

[0017] By adopting the above technical solution, the power supply voltage is stepped down by the step-down circuit, so that the voltage at the load interface meets the user's usage requirements.

[0018] Optionally, the step-down circuit includes a step-down chip U3 and a feedback circuit, the voltage input end of the step-down chip U3 is connected to the power input end of the power supply circuit, and the voltage output end of the step-down chip U3 is connected to the second power output end of the power supply circuit;

[0019] The step-down chip U3 includes a current feedback terminal, a voltage feedback terminal, and a voltage output terminal. The feedback circuit is connected to the current feedback terminal, the voltage feedback terminal, and the voltage output terminal, respectively.

[0020] By adopting the above technical solution and providing a feedback circuit for the step-down chip, not only the supply voltage can be stepped down, but also a constant current and constant voltage voltage output can be ensured.

[0021] Optionally, a first diode D1 is connected in series between the power input end of the power supply circuit and the voltage input end of the step-down circuit, the anode end of the first diode D1 is connected to the power input end of the power supply circuit, and the cathode end of the first diode D1 is connected to the voltage input end of the step-down circuit.

[0022] By adopting the above technical solution, a first diode D1 is provided between the power supply circuit and the step-down circuit, which can reduce the possibility of current backflow, thereby reducing the possibility of damage to electronic components on the power input side of the power supply circuit, thereby playing a protective role.

[0023] Optionally, a filter circuit is connected between the cathode end of the first diode D1 and the analog ground GND.

[0024] By adopting the above technical solution, the setting of the filter circuit can filter out the noise in the DC power supply, making the DC voltage input at the voltage input end of the step-down circuit more stable.

[0025] Optionally, the power supply circuit further includes a voltage stabilizing circuit, wherein the voltage input end of the voltage stabilizing circuit is connected to the power input end of the power supply circuit, and the voltage output end of the voltage stabilizing circuit is connected to the first power output end of the power supply circuit.

[0026] By adopting the above technical solution, the mutual interference between the power supply circuit of the control circuit and the step-down circuit can be effectively reduced, and a stable operating voltage input can be provided for the control circuit.

[0027] In a second aspect, the present application provides a photovoltaic power generation system, which adopts the following technical solution:

[0028] A photovoltaic power generation system comprises the intelligent load identification circuit described in the first aspect and a photovoltaic power generation module, wherein the power input end of the power supply circuit is connected to the photovoltaic power generation module.

[0029] By adopting the above technical solution, when the photovoltaic power generation system is charging the load, the control circuit controls the switch circuit to disconnect; if the charging interface of the external load outputs voltage or current, the sampling circuit can detect the presence of voltage and / or current at the load interface, and the control circuit continues to control the switch circuit to disconnect, resulting in the circuit between the power supply circuit and the load interface being disconnected, making the power supply circuit unable to charge the load; if the charging interface of the external load does not output voltage or current, the control circuit controls the switch circuit to connect, connecting the circuit between the power supply circuit and the load interface, allowing the power supply circuit to charge the external load. Therefore, by adding a switch circuit and a sampling circuit to the photovoltaic power generation system, overcharging of the external load can be prevented, thereby improving the safety of charging the external load.

[0030] In a third aspect, the present application provides an intelligent load identification method using the intelligent load identification circuit described in the first aspect, which adopts the following technical solutions:

[0031] An intelligent load identification method, comprising:

[0032] The control circuit controls the switch circuit to be disconnected;

[0033] After the switch circuit is disconnected, the control circuit detects, through a sampling circuit, whether the load interface receives the voltage and / or current output by the external load;

[0034] If not, the control circuit controls the switch circuit to be turned on, and at the same time the control circuit starts timing and records the current timing value;

[0035] Determine whether the current timing value is equal to a preset value. If so, return to the step of controlling the switch circuit to be disconnected.

[0036] By adopting the above technical solution, when charging an external load, the control circuit controls the switch circuit to disconnect; if the external load is not equipped with a charging protection circuit, the charging interface of the external load outputs voltage and current to the outside, then the sampling circuit can detect the presence of voltage and / or current at the load interface, and the control circuit continues to control the switch circuit to disconnect, resulting in the circuit between the power supply circuit and the load interface being disconnected, making it impossible for the power supply circuit to charge the external load; if the external load is equipped with a charging protection circuit, the charging interface of the external load does not output voltage and current to the outside, and the control circuit controls the switch circuit to conduct, connecting the circuit between the power supply circuit and the load interface, so that the power supply circuit can charge the external load; at the same time, the control circuit starts timing and records the current timing value. After the current timing value is equal to the preset value, the control circuit controls the switch circuit to disconnect and detects whether there is voltage and / or current at the load interface. By adding a switch circuit and a sampling circuit and performing a cyclic timing judgment, charging of an external load without a protection circuit can be prevented, thereby improving the safety of external load charging.

[0037] In summary, this application includes at least one of the following beneficial technical effects:

[0038] 1. If the external load is not equipped with a charging protection circuit, and the charging interface of the load outputs voltage and current, the sampling circuit can detect the presence of voltage and / or current at the load interface, and the control circuit will continue to control the switch circuit to disconnect, causing the circuit between the power supply circuit and the load interface to be disconnected, making it impossible for the power supply circuit to charge the external load; if the external load is equipped with a charging protection circuit, and the charging interface of the external load does not output voltage and current, the control circuit will control the switch circuit to conduct, connecting the circuit between the power supply circuit and the load interface, allowing the power supply circuit to charge the load. Therefore, by adding a switching circuit and a sampling circuit, overcharging of the external load can be prevented, thereby improving the safety of charging the external load;

[0039] 2. The high and low level signals output by the control circuit control the conduction and disconnection of the MOS tube T11, thereby controlling the conduction or disconnection of the circuit between the power supply circuit and the load interface. The circuit design is simple and has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a structural block diagram of the intelligent load identification circuit of an embodiment of the present application.

[0041] Figure 2 1 is a schematic diagram of a sampling circuit, a switching circuit, and a control circuit according to an embodiment of the present application.

[0042] Figure 3 1 is a circuit schematic diagram of the power supply circuit of an embodiment of the present application.

[0043] Figure 4It is a structural block diagram of the photovoltaic power generation system of an embodiment of the present application.

[0044] Figure 5 It is a flow chart of the intelligent load identification method according to an embodiment of the present application.

[0045] Explanation of the accompanying reference numerals: 101, control circuit; 102, power supply circuit; 1021, step-down circuit; 10211, feedback circuit; 1022, filter circuit; 1023, voltage stabilizing circuit; 10231, transistor voltage stabilizing circuit; 103, load interface; 104, sampling circuit; 1041, voltage sampling circuit; 1042, current sampling circuit; 105, switching circuit; 201, photovoltaic power generation module. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1-5 It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0047] The embodiment of the present application discloses an intelligent load identification circuit. Figure 1 The intelligent load identification circuit includes a control circuit 101 , a power supply circuit 102 , a load interface 103 , a sampling circuit 104 and a switch circuit 105 .

[0048] In this embodiment, the power supply circuit 102 includes a power input terminal VCC, a first power output terminal, and a second power output terminal S. The first output terminal of the power supply circuit 102 is connected to the power input terminal of the control circuit 101, and the second power output terminal S of the power supply circuit 102 is connected to the load interface 103 via the switch circuit 105; the load interface 103 is also connected to the control circuit 101 via the sampling circuit 104.

[0049] Reference Figure 2 The control circuit 101 includes a control chip U1, and the control chip U1 can be a chip of model N76E003AT20.

[0050] As an optional implementation of this embodiment, refer to Figure 3 The power supply circuit 102 includes a voltage stabilizing circuit 1023 . A voltage input terminal of the voltage stabilizing circuit 1023 is connected to a power input terminal VCC of the power supply circuit 102 , and a voltage output terminal of the voltage stabilizing circuit 1023 is connected to a first power output terminal of the power supply circuit 102 .

[0051] In this optional embodiment, the voltage stabilizing circuit 1023 includes a voltage stabilizing transistor circuit 10231 and a three-terminal voltage stabilizing diode U2. The supply voltage received by the power input terminal VCC is first stabilized at 10V by the voltage stabilizing transistor circuit 10231, and then converted by the three-terminal voltage stabilizing diode U2 to output a 5V voltage. The 5V voltage is then transmitted from the first power output terminal to the control circuit 101, providing the operating voltage for the control chip U1.

[0052] Further, refer to Figure 2 and Figure 3 The voltage-stabilizing transistor circuit 10231 includes a transistor T1 and a voltage-stabilizing diode D2. A second diode D3 and a first resistor R1 are connected in series to the collector of the transistor T1. The anode of the second diode D3 is connected to the voltage input terminal of the voltage-stabilizing circuit 1023, and the cathode of the second diode D3 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the collector of the transistor T1. The base of the transistor T1 is connected to the cathode of the voltage-stabilizing diode D2, and the anode of the voltage-stabilizing diode D2 is connected to the analog ground GND. A second resistor R2 is connected between the base and collector of the transistor T1.

[0053] In the voltage-stabilizing transistor circuit 10231, the second resistor R2 and the voltage-stabilizing diode D3 form a basic circuit for voltage stabilization. A stable voltage is obtained on the voltage-stabilizing diode D3. The base of the transistor T1 is connected to the cathode terminal of the voltage-stabilizing diode D3, forming an emitter follower. The emitter voltage of the transistor T1 follows the base voltage. Therefore, a stable voltage can be output at the emitter of the transistor T1.

[0054] The emitter of the transistor T1 is connected to the input terminal (pin 3) of the three-terminal voltage regulator U2; the common terminal (pin 1) of the three-terminal voltage regulator U2 is connected to the analog ground GND, and the output terminal (pin 1) of the three-terminal voltage regulator U2 is connected to the first power output terminal, and the first power output terminal is connected to the 4th pin of the control chip U1. The control chip U1 is powered by a 5V voltage.

[0055] The three-terminal voltage regulator U2 can be a 7805 three-terminal voltage regulator. The three-terminal voltage regulator U2 has the characteristics of low power consumption, low voltage drop and high precision, which can reduce losses while providing a stable 5V voltage.

[0056] Furthermore, a first capacitor C1 is connected between the connection point between the first resistor R1 and the collector of transistor T1 and analog ground GND. A second capacitor C2 and a third capacitor C3 are connected in parallel between the emitter of transistor T1 and the anode of Zener diode D2. These capacitors C1, C2, and C3 all function as filters. A fourth capacitor C4 and a fifth capacitor C5 are connected in parallel between the common terminal of the three-terminal Zener diode U2 and the output terminal of the three-terminal Zener diode U2. Similarly, these capacitors C4 and C5 also function as filters.

[0057] As an optional implementation of this embodiment, refer to Figure 3 The power supply circuit 102 includes a step-down circuit 1021 , a voltage input terminal of the step-down circuit 1021 is connected to the power input terminal VCC of the power supply circuit 102 , and a voltage output terminal of the step-down circuit 1021 is connected to the second power output terminal S of the power supply circuit 102 .

[0058] In this optional embodiment, the buck circuit 1021 includes a buck chip U3, which can be a CX8812 synchronous buck DC-DC controller. The voltage input terminal of the buck circuit 1021 is connected to pin 3 of the buck chip U3 via a third resistor R3 and an eighth capacitor C8. Pin 4 of the buck chip U3 is connected to the voltage input terminal of the buck circuit 1021. Pins 5 and 6 of the buck chip U3 are both 5V voltage output pins; in this embodiment, only pin 5 is used. Pins 7 and 8 of the buck chip U3 are connected to analog ground GND.

[0059] Buck circuit 1021 also includes a third diode D4. Pin 5 of buck chip U3 is connected to the cathode of third diode D4, and the anode of third diode D4 is connected to analog ground GND. The cathode of third diode D4 is connected sequentially to fourth resistor R4, then to ninth capacitor C9, and finally to analog ground GND. Third diode D4 provides a freewheeling circuit for the output pin of buck chip U3, providing a freewheeling function. The provision of ninth capacitor C9 prevents excessive peak current from damaging third diode D4.

[0060] Further, refer to Figure 3The buck circuit 1021 further includes a feedback circuit 10211, which includes a first inductor L1, a fifth resistor R5, and a sixth resistor R6. One end of the first inductor L1 is connected to pin 5 of the buck chip U3. The other end of the first inductor L1 is connected to the voltage output terminal of the buck circuit 1021 through the sixth resistor R6. The voltage output terminal of the buck circuit 1021 is the second power output terminal S of the power supply circuit 102. The fifth resistor R5 and the sixth resistor R6 are connected in parallel. One end of the sixth resistor R6 connected to the first inductor L1 is also connected to pin 2 of the buck chip U3. The connection point between the sixth resistor R6 and the fifth resistor R5 is connected to pin 1 of the buck chip U3.

[0061] The step-down chip U3 utilizes the feedback circuit 10211 and relies on the internal constant voltage control loop to stabilize the output voltage at 5V, detects the output current through the voltage difference between the 1st pin and the 2nd pin, and relies on the internal constant current control loop to adjust the current output so that the output current value is a preset value, thereby enabling the voltage output end of the step-down circuit 1021 to output constant voltage and constant current.

[0062] A twelfth capacitor C12 and a thirteenth capacitor C13 are connected in parallel between the voltage output terminal of the step-down circuit 1021 and the analog ground GND. The twelfth capacitor C12 and the thirteenth capacitor C13 are used to filter out noise to make the DC output of the voltage output terminal of the step-down circuit 1021 more stable.

[0063] Further, refer to Figure 3 One end of the third resistor R3 away from the eighth capacitor C8 is connected to the first diode D1, the cathode end of the first diode D1 is connected to the third resistor R3, and the anode end of the first diode D1 is connected to the power input end VCC.

[0064] When current flows from the power supply circuit 102 to the step-down circuit 1021, the first diode D1 is in the on state. When current flows from the step-down circuit 1021 to the power supply circuit 102, the first diode D1 is in the off state. Therefore, the first diode D1 can prevent current backflow, reducing the possibility of damage to the electrical components connected to the power input terminal VCC, thereby providing protection. The first diode D1 can be an SS34 diode.

[0065] Furthermore, the power supply circuit 102 further includes a filtering circuit 1022. The filtering circuit 1022 includes a sixth capacitor C6 and a seventh capacitor C7 connected in parallel; one end of the sixth capacitor C6 is connected to the cathode end of the first diode D1, and the other end of the sixth capacitor C6 is connected to the analog ground GND. The sixth capacitor C6 and the seventh capacitor C7 are used to filter out noise to make the DC input of the step-down circuit 1021 more stable.

[0066] As an optional implementation of this embodiment, refer to Figure 2 and Figure 3 The switch circuit 105 includes a MOS transistor T11. The source of the MOS transistor T11 is connected to the second power output terminal S, the drain of the MOS transistor T11 is connected to the positive electrode A+ of the load interface 103, and a seventh resistor R7 is connected in series between the gate of the MOS transistor T11 and the 12th pin of the control chip U1. The gate of the MOS transistor T11 is also electrically connected to a pull-up resistor R22. The other end of the pull-up resistor R22 is electrically connected to the first power output terminal of the power supply circuit 102, that is, the output end of the three-terminal voltage regulator U2.

[0067] The high-level signal output by the control chip U1 at pin 12 is not sufficient to turn on the drain and source terminals of the MOS transistor T11. After a pull-up resistor R22 is set at the gate of the MOS transistor T11, the control chip U1 outputs a high-level signal at pin 12 to turn on the drain and source terminals of the MOS transistor T11. The control chip U1 outputs a low-level signal at pin 12 to turn off the drain and source terminals of the MOS transistor T11.

[0068] The MOS transistor T11 is driven by voltage and has a small gate current. However, due to the presence of parasitic capacitance inside the gate of the MOS transistor T11, a large instantaneous current is generated when the control chip U1 controls the MOS transistor T11 to be turned on or off. The seventh resistor R7 can form an RC charging and discharging circuit with the parasitic capacitance to reduce the current value of the instantaneous current, thereby reducing the possibility of the instantaneous current damaging the control chip U1.

[0069] As an optional implementation of this embodiment, refer to Figure 2 and Figure 3 The sampling circuit 104 includes a voltage sampling circuit 1041 and a current sampling circuit 1042. The voltage sampling circuit 1041 includes an eighth resistor R8 and a ninth resistor R9. One end of the eighth resistor R8 is connected to the positive electrode A+ of the load interface 103, the other end of the eighth resistor R8 is connected to the ninth resistor R9, and the other end of the ninth resistor R9 is connected to the negative electrode A- of the load interface 103. The connection point between the eighth resistor R8 and the ninth resistor R9 is connected to the 5th pin of the control chip U1. The connection point between the eighth resistor R8 and the ninth resistor R9 is also connected to a tenth capacitor C10. The other end of the tenth capacitor C10 is connected to the negative electrode A- of the load interface 103.

[0070] The current sampling circuit 1042 includes a tenth resistor R10 and a thirteenth resistor R13. One end of the tenth resistor R10 is connected to the negative electrode A- of the load interface 103, and the other end is connected to the analog ground GND. The two ends of the tenth resistor R10 are connected in parallel to an eleventh resistor R11 and a twelfth resistor R12. One end of the thirteenth resistor R13 is connected to the negative electrode A- of the load interface 103, and the other end is connected to the 14th pin of the control chip U1. The connection point between the thirteenth resistor R13 and the 14th pin of the control chip U1 is connected to an eleventh capacitor C11, and the other end of the eleventh capacitor C11 is connected to the analog ground GND.

[0071] The resistors in the voltage sampling circuit 1041 and the current sampling circuit 1042 are both high-precision resistors with an error of no more than 1%. This allows the voltage sampling circuit 1041 and the current sampling circuit 1042 to accurately sample the voltage and current of the load interface 103, while reducing the possibility of erroneous sampling by the sampling circuit 104. In addition, the tenth capacitor C10 and the eleventh capacitor C11 act as filters to make the sampled values ​​more accurate.

[0072] In this embodiment, refer to Figure 2 The load interface 103 can be set as a USB interface J1. An auxiliary load R14 can be connected between the positive pole A+ and the negative pole A- of the USB interface J1. The auxiliary load R14 makes the 5V voltage output by the USB interface J1 more stable, reducing the possibility of damage to the external load due to the unstable output voltage of the USB interface J1.

[0073] Further, refer to Figure 2 A PTC thermistor is connected in series between the positive electrode A+ of the USB interface J1 and the drain of the MOS tube T11. The PTC thermistor is a protection element. When the current is abnormal, the temperature value rises and exceeds the limit value of the PTC thermistor. The PTC thermistor can automatically disconnect and automatically reset when the current returns to normal. The PTC thermistor can play the role of overload protection and circuit protection.

[0074] For example, if a short circuit occurs in the circuit at USB interface J1, the current will increase, which will increase the heat generated by the PTC thermistor. The temperature will rise and exceed the limit value of the PTC thermistor. At this time, the resistance of the PTC thermistor will rapidly increase infinitely, thereby blocking the current and playing a protective role. When the current value returns to normal, the temperature drops, the resistance of the PTC thermistor will return to normal, and it will automatically reset.

[0075] Without sampling circuit 104 and switch circuit 105, external loads cannot be identified. Using power supply circuit 102 to charge an external load capable of outputting voltage and current could result in the external load being overcharged, posing a safety hazard and potentially exploding. However, this issue can be resolved by using sampling circuit 104 to detect and control chip U1 to automatically switch switch circuit 105 on and off, intelligently identifying external loads and automatically controlling whether the external load is charged.

[0076] For example, an external load like a miner's lamp lacks a charging protection circuit and can directly output voltage and current through its charging port. Furthermore, the built-in power supply voltage of the miner's lamp is low. In this case, control chip U1 can detect the presence of voltage and current at load port 103 through sampling circuit 104. Control chip U1 then controls switch circuit 105 to remain off, preventing charging of external loads that can output voltage and current, thereby reducing the possibility of explosion. When charging external loads like mobile phones, since these loads have built-in charging protection circuits, no voltage or current is output at the charging port. Control circuit 101 is unable to detect voltage and current, and controls switch circuit 105 to conduct, enabling power supply circuit 102 to charge external loads whose charging port does not output voltage or current.

[0077] The implementation principle of the intelligent load identification circuit of the embodiment of the present application is as follows: when the user connects the charging interface of the external load to the load interface 103, the control chip U1 sends a low-level signal to the MOS tube T11 to control the MOS tube T11 to be disconnected, thereby controlling the power supply circuit 102 to be unable to connect with the load interface 103. At the same time, the control chip U1 detects the load interface 103 through the sampling circuit 104. When there is voltage and / or current at the load interface 103, the control chip U1 receives the voltage and / or current signal, and the control chip U1 continues to control the MOS tube T11 to be disconnected, and the power supply circuit 102 is not connected to the load interface 103. 3 is connected, the user cannot charge the external load through the load interface 103; when there is no voltage and / or current at the load interface 103, the control chip U1 cannot detect the voltage and / or current, and the control chip U1 outputs a high-level signal to the MOS tube T11 to control the MOS tube T11 to be turned on, thereby controlling the power supply circuit 102 to be connected to the load interface 103, and the user can use the load interface 103 to charge the external load. By automatically controlling whether the load interface 103 is powered on, the power supply circuit 102 is prevented from charging the external load whose charging interface can output voltage and current, thereby reducing the possibility of overcharging.

[0078] The present application also discloses a photovoltaic power generation system. Figure 4The photovoltaic power generation system includes the intelligent load identification circuit and the photovoltaic power generation module 201 described in the above embodiment.

[0079] The photovoltaic power generation module 201 includes a solar panel and a battery. The solar panel is connected to the battery, and the battery is connected to the power input terminal of the power supply circuit 102 in the intelligent load identification circuit.

[0080] The solar panel receives sunlight to generate electricity and charge the battery. The battery provides power to the intelligent load identification circuit so that the intelligent load identification circuit can work and charges the external load through the intelligent load identification circuit.

[0081] The present application also discloses an intelligent load identification method using the intelligent load identification circuit described in the above embodiment. Figure 5 ,The intelligent load identification method mainly includes the following steps:

[0082] In step S301 , the control circuit 101 is used to control the switch circuit 105 to be turned off.

[0083] Specifically, the control circuit 101 controls the MOS transistor T11 in the switch circuit 105 to be disconnected, and the step-down circuit 1021 is disconnected from the load interface 103 .

[0084] In step S302, the control circuit 101 detects whether the load interface 103 receives the voltage and / or current output by the external load through the sampling circuit 104. If yes, the control circuit 101 returns to step S301; if not, the control circuit 101 proceeds to step S303.

[0085] Specifically, the control circuit 101 detects whether the load interface 103 receives the voltage and / or current output by the external load through the sampling circuit 104. When there is voltage and current at the load interface 103, the control circuit 101 can detect the voltage and current and returns to step S301; when there is no voltage and current at the load interface 103, the control circuit 101 cannot detect the voltage and current and proceeds to step S303.

[0086] In step S303 , the control circuit 101 controls the switch circuit 105 to be turned on, and at the same time, the control circuit 101 starts timing and records the current timing value.

[0087] Specifically, the control circuit 101 controls the MOS transistor T11 in the switch circuit 105 to be turned on, so that the buck circuit 1021 can supply power to the outside through the load interface 103 . At the same time, the control circuit 101 starts timing from zero and records the current timing value.

[0088] Step S304: determine whether the current timing value is equal to the preset value. If so, return to step S301.

[0089] Specifically, the preset value may be set to 5 minutes. When the current timing value is equal to 5 minutes, the process returns to step S301. If not, the process continues timing.

[0090] The above are all preferred embodiments of the present application and are not intended to limit the scope of protection of this application. Unless otherwise specified, any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features. In other words, unless otherwise specified, each feature is merely an example of a series of equivalent or similar features.

Claims

1. An intelligent load identification circuit, comprising a control circuit (101), a power supply circuit (102) and a load interface (103), wherein the power supply circuit (102) comprises a power input terminal for receiving electric energy and a first power output terminal, wherein the first power output terminal is connected to the control circuit (101), and is characterized in that: A sampling circuit (104) is connected between the control circuit (101) and the load interface (103), and the sampling circuit (104) is used to detect the voltage and / or current output by the external load received by the load interface (103); The power supply circuit (102) further comprises a second power supply output terminal, a switch circuit (105) is connected between the second power supply output terminal and the load interface (103), the switch circuit (105) is connected to the control circuit, and the switch circuit (105) is used to control the circuit between the power supply circuit (102) and the load interface (103) to be turned on or off; The power supply circuit (102) further comprises a step-down circuit (1021), wherein a voltage input end of the step-down circuit (1021) is connected to a power input end of the power supply circuit (102), and a voltage output end of the step-down circuit (1021) is connected to a second power output end of the power supply circuit (102); The step-down circuit (1021) comprises a step-down chip U3 and a feedback circuit (10211); the voltage input end of the step-down chip U3 is connected to the power input end of the power supply circuit (102); and the voltage output end of the step-down chip U3 is connected to the second power output end of the power supply circuit (102); The step-down chip U3 comprises a current feedback terminal, a voltage feedback terminal and a voltage output terminal, and the feedback circuit (10211) is connected to the current feedback terminal, the voltage feedback terminal and the voltage output terminal respectively; The power supply circuit (102) further comprises a voltage stabilizing circuit (1023), wherein a voltage input end of the voltage stabilizing circuit (1023) is connected to a power input end of the power supply circuit (102), and a voltage output end of the voltage stabilizing circuit (1023) is connected to a first power output end of the power supply circuit (102); The voltage stabilizing circuit (1023) comprises a voltage stabilizing transistor circuit (10231) and a three-terminal voltage stabilizing diode U2; the voltage stabilizing transistor circuit (10231) comprises a transistor T1 and a voltage stabilizing diode D2; the collector of the transistor T1 is connected in series with a second diode D3 and a first resistor R1; the anode end of the second diode D3 is connected to the voltage input end of the voltage stabilizing circuit 1023; the cathode end of the second diode D3 is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the collector of the transistor T1; the base of the transistor T1 is connected to the cathode end of the voltage stabilizing diode D2; the anode end of the voltage stabilizing diode D2 is connected to the analog ground GND; the second resistor R2 is connected between the base and the collector of the transistor T1; The emitter of the transistor T1 is connected to the input end of the three-terminal voltage regulator U2; the common end of the three-terminal voltage regulator U2 is connected to the analog ground GND, and the output end of the three-terminal voltage regulator U2 is connected to the first power supply output end, and the first power supply output end is connected to the 4th pin of the control chip U1.

2. The intelligent load identification circuit according to claim 1, characterized in that: The switch circuit (105) comprises a MOS transistor T11, the gate of the MOS transistor T11 being connected to the signal output end of the control circuit (101), the drain of the MOS transistor T11 being connected to the load interface (103), and the source of the MOS transistor T11 being connected to the second power output end of the power supply circuit (102).

3. The intelligent load identification circuit according to claim 1 or 2, characterized in that: The sampling circuit (104) comprises: A voltage sampling circuit (1041) is used to detect whether the load interface (103) receives the voltage output by the external load; The current sampling circuit (1042) is used to detect whether the load interface (103) receives the current output by the external load.

4. The intelligent load identification circuit according to claim 1, characterized in that: A first diode D1 is connected in series between the power input terminal of the power supply circuit (102) and the voltage input terminal of the step-down circuit (1021), the anode terminal of the first diode D1 is connected to the power input terminal of the power supply circuit (102), and the cathode terminal of the first diode D1 is connected to the voltage input terminal of the step-down circuit (1021).

5. The intelligent load identification circuit according to claim 4, characterized in that: A filter circuit (1022) is connected between the cathode end of the first diode D1 and the analog ground GND.

6. A photovoltaic power generation system, characterized in that: It comprises the intelligent load identification circuit according to any one of claims 1 to 5 and a photovoltaic power generation module (201), wherein the power input end of the power supply circuit (102) is connected to the photovoltaic power generation module (201).

7. An intelligent load identification method using the intelligent load identification circuit according to any one of claims 1 to 5, characterized in that: include: The control circuit (101) controls the switch circuit (105) to be disconnected; After the switch circuit (105) is disconnected, the control circuit (101) detects, via a sampling circuit (104), whether the load interface (103) receives the voltage and / or current output by the external load; If not, the control circuit (101) controls the switch circuit (105) to be turned on, and at the same time the control circuit (101) starts timing and records the current timing value; It is determined whether the current timing value is equal to a preset value. If so, the process returns to the step where the control circuit (101) controls the switch circuit (105) to be disconnected.

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