IGBT module temperature sampling detection system and error optimization method

Abstract

The present invention provides an IGBT module temperature sampling detection system and an error optimization method, wherein the detection system comprises an NTC sampling circuit, an optical coupler isolation and an FPGA. The NTC sampling circuit comprises an NTC resistor R1, a resistor R2 and a capacitor C1 connected in series from top to bottom, and also comprises a 555 chip, wherein the NTC resistor R1 is a temperature sampling resistor inside the IGBT module, the middle point of the NTC resistor R1 and the resistor R2 connected in series is connected to the analog signal input end of the 555 chip, the middle point of the resistor R2 and the capacitor C1 connected in series is connected to the trigger end of the charge and discharge circuit of the 555 chip, the output end of the 555 chip is the output end of the NTC sampling circuit, connected to the input end of the optical coupler isolation, and the output end of the optical coupler isolation is connected to the input of the FPGA chip. By using the high-speed operation characteristics of the FPGA, the error comparison algorithm of the capacitance value during discharge is used, and the new cycle operation time can be used to obtain a very accurate IGBT temperature, thereby controlling the heat dissipation system of the SVG device, ensuring the reliable operation of the SVG device, and improving the accuracy of the temperature detection of the IGBT module.

Description

Technical Field

[0001] The present invention relates to the technical field of high and low voltage SVG, and in particular to an IGBT module temperature sampling and detection system and an error optimization method. Background Art

[0002] With the rapid development of power electronics technology, reactive power compensation SVG, photovoltaic grid connection, wind power conversion and other power electronic equipment are increasingly used in power grids. Among them, IGBT is a key component for realizing power electronic power conversion and a key factor affecting system performance and reliable operation. Temperature, as a sensitive parameter of the IGBT module, will directly affect the internal carriers of the IGBT, and then affect a series of key parameters such as the breakdown voltage, switching time, and switching loss of the IGBT. Therefore, the temperature sampling of the IGBT module is extremely important. At present, mainstream IGBT module manufacturers will preset negative temperature coefficient resistors NTC in the module to facilitate the detection of the temperature of the IGBT module.

[0003] At present, there are several ways to test the temperature of IGBT:

[0004] The resistor voltage divider method is then used to measure the temperature through the single-chip microcomputer sampling. However, since the NTC resistance value can vary by more than a thousand times, the AD sampling of common single-chip microcomputers cannot meet the requirements of high-precision temperature measurement in the full temperature range.

[0005] Comparator comparison method: This circuit is relatively simple and can be used as a temperature protection switch. When the temperature reaches the specified temperature, the temperature switch will be activated for protection, but it cannot linearly measure the module junction temperature.

[0006] The external thermistor measurement method uses a thermistor to detect the temperature of the substrate or heat sink of the IGBT module. However, due to the temperature difference between the heat sink and the IGBT at different positions, the junction temperature of the module cannot be accurately and effectively measured.

[0007] In addition, the IGBT and the test system in the above methods are not completely isolated. Since the switching frequency of the IGBT is at the KHz level, the sampling system is easily interfered by the IGBT device. Therefore, a new type of IGBT temperature sampling circuit is needed to solve the above problems.

[0008] In addition, in the circuit application using chip 555 for sampling, since the pulse frequency f is inversely proportional to the oscillation capacitor C1, and the oscillation capacitor C1 is affected by the ambient temperature, the detection error is a factor that cannot be ignored. Summary of the invention

[0009] In order to solve the technical problems raised by the background technology, the present invention provides an IGBT module temperature sampling detection system and an error optimization method. By taking advantage of the high-speed operation characteristics of FPGA and utilizing the error comparison algorithm of the capacitance value during discharge, a very accurate IGBT temperature can be obtained by applying a new cycle operation time, thereby controlling the heat dissipation system of the SVG device and ensuring the reliable operation of the SVG device.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] An IGBT module temperature sampling and detection system comprises an NTC sampling circuit, an optical coupler isolation and an FPGA.

[0012] The NTC sampling circuit includes an NTC resistor R1, a resistor R2, and a capacitor C1 connected in series from top to bottom, and also includes a 555 chip. The NTC resistor R1 is a temperature sampling resistor inside the IGBT module. The upper end of the NTC resistor R1 is connected to the power supply VCC, and the lower end of the capacitor C1 is grounded. The middle point of the series connection of the NTC resistor R1 and the resistor R2 is connected to the analog signal input end of the 555 chip, and the middle point of the series connection of the resistor R2 and the capacitor C1 is connected to the trigger end of the charge and discharge circuit of the 555 chip. The output end of the 555 chip is the output end of the NTC sampling circuit, which is connected to the input end of the optocoupler isolation, and the output end of the optocoupler isolation is connected to the input of the FPGA chip.

[0013] The detection error optimization method of the IGBT module temperature sampling detection system includes the following:

[0014] Step 1: Initial calculation:

[0015] In the charging and discharging circuit of the multivibrator composed of NTC resistor R1, resistor R2, and capacitor C1, the charging and discharging time of capacitor C1 is T H and T L , the full response equation of the RC circuit to step excitation is:

[0016] u c (t) = V0e t / τ +E(1-e t / τ ) (1)

[0017] in: E=V CC , τ=(R1+R2)C1, and the above formula can be rearranged to obtain:

[0018]

[0019] Taking the natural logarithm with base e on both sides of the equation, we get the charging time:

[0020] T H=(R1+R2)C1*Ln2 (3)

[0021] Similarly, the discharge time is:

[0022] T L =R2C1Ln2 (4)

[0023] Combining the charging and discharging time, we get the oscillation period T and frequency f as follows:

[0024] T=T H +T L =(R1+2R2)C1*Ln2 (5)

[0025] f=1 / ((R1+2R2)C1*Ln2) (6)

[0026] In formula (3), R1 is used as the sampling resistor of NTC, and R2 and C1 are used as constants. Therefore, the value of NTC resistor R1 is obtained through the relationship between different NTC resistors R1 and the charging and discharging time in cycle T, thereby obtaining the temperature value of IGBT.

[0027] Step 2: Optimize detection error

[0028] 1) In FPGA, detect the pulse length of the sampling input port of FPGA to obtain the real-time new discharge time and period T Lnew and T new ;

[0029] 2) The new discharge time T Lnew The new capacitance value C is calculated by formula (4): 1new ;

[0030] 3) The optimized oscillation period T is obtained through the FPGA algorithm formula (7) new1 (abs is the absolute value of the brackets);

[0031]

[0032] 4) The oscillation period T calculated by formula (7) new1 The corresponding optimized IGBT resistance R is further calculated by formula (5): 1new , and then the optimized IGBT temperature is obtained.

[0033] Furthermore, the optimization selection method of the resistor R2 and the capacitor C1 is also included, as follows:

[0034] The optimization selection principle is that the smaller the resistance of resistor R2, the better, and the larger the capacitance of capacitor C1, the better. However, if the capacitance C1 is too large, it will cause excessive charging and discharging currents and damage the 555 chip. The increase of resistor R2 and capacitor C1 will also affect the system response time. Therefore, in the actual system, it is necessary to comprehensively consider various aspects to select appropriate resistors and capacitors.

[0035] 1) Sampling frequency selection: Since there is a phase-locked loop inside the FPGA, the sampling frequency range is set to 1M-200M;

[0036] 2) According to the variation range of NTC resistor R1, NTC resistor R1 is selected to have the maximum value, and resistor R2 is selected to have 500Ω, 5000Ω, and 50000Ω respectively. The values ​​of capacitor C1 can be obtained by formula (8):

[0037]

[0038] 3) According to the value of capacitor C1, use Matlab to draw the curves of NTC resistor R1, charge and discharge resistor R2 and sampling frequency when the resistor R2 is 500Ω, 5000Ω and 50000Ω respectively;

[0039] 4) According to the NTC resistor R1, the charge and discharge resistor R2 and the sampling frequency change curve when the resistor R2 is 500Ω, 5000Ω and 50000Ω respectively, the value of the resistor R2 with the best linearity is selected as the final selection of the resistor R2;

[0040] 5) After the final selection of the resistor R2 is determined, the final selection value of the capacitor C1 is the value of the capacitor C1 corresponding to the formula (8).

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] 1) 555 converts the analog signal changes of the NTC resistor into digital signal changes, which can save the circuit overhead of analog sampling, and the digital signal changes are more conducive to FPGA chip filtering and signal processing.

[0043] 2) By utilizing the high-speed operation characteristics of FPGA, using the error comparison algorithm of the capacitance value during discharge, and applying the new cycle operation time, a very accurate IGBT temperature can be obtained. When the capacitance value of capacitor C1 changes with external interference, the original oscillation period can be corrected to a correct period value through the method of the present invention, thereby obtaining the correct NTC temperature value of the IGBT, thereby controlling the heat dissipation system of the SVG device, ensuring the reliable operation of the SVG device, and improving the accuracy of temperature detection of the IGBT module. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a circuit diagram of the IGBT module temperature sampling and detection system of the present invention;

[0045] Figure 2 It is a curve diagram of the change of the NTC resistor R1, the charge and discharge resistor R2 and the sampling frequency of the present invention;

[0046] Figure 3 It is a curve diagram of the change of the charge and discharge capacitor C1 and the charge and discharge cycle of the present invention;

[0047] Figure 4 The NTC sampling resistor of the present invention is 5K, the C1 charging capacitor is 0.57uf, the charging and discharging time and the waveform of the optocoupler end;

[0048] Figure 5 The NTC sampling resistor of the present invention is 2K, the C1 charging capacitor is 0.57uf, the charging and discharging time and the waveform of the optocoupler end;

[0049] Figure 6 The NTC sampling resistor of the present invention is 5K, the C1 charging capacitor is 0.92uf, the charging and discharging time and the waveform of the optocoupler end;

[0050] Figure 7 The NTC sampling resistor of the present invention is 2K, the C1 charging capacitor is 0.92uf, the charging and discharging time and the waveform of the optocoupler end;

[0051] Figure 8 The NTC sampling resistor of the present invention is 5K, the C1 charging capacitor is 1.12uf, the charging and discharging time and the waveform of the optocoupler end;

[0052] Fig. 9 The NTC sampling resistor of the present invention is 2K, the C1 charging capacitor is 1.12uf, the charging and discharging time and the optocoupler end waveform. DETAILED DESCRIPTION

[0053] The specific implementation modes provided by the present invention are described in detail below with reference to the accompanying drawings.

[0054] 1. Circuit structure

[0055] like Figure 1 As shown, the NTC sampling circuit includes an NTC resistor R1, a resistor R2, and a capacitor C1 connected in series from top to bottom, and also includes a 555 chip. The NTC resistor R1 is a temperature sampling resistor inside the IGBT module. The upper end of the NTC resistor R1 is connected to the power supply VCC, and the lower end of the capacitor C1 is grounded. The middle point of the series connection of the NTC resistor R1 and the resistor R2 is connected to the analog signal input end of the 555 chip, and the middle point of the series connection of the resistor R2 and the capacitor C1 is connected to the trigger end of the charge and discharge circuit of the 555 chip. The output end of the 555 chip is the output end of the NTC sampling circuit, which is connected to the input end of the optocoupler isolation, and the output end of the optocoupler isolation is connected to the input of the FPGA chip.

[0056] 2. NTC resistance detection principle of IGBT based on 555

[0057] In the field of IGBT technology, the common sense formula It can be seen that:

[0058]

[0059] You can check the corresponding IGBT manual through the IGBT official website (such as Infineon's official website) to get the B value, R0, T0, and the corresponding temperature can be obtained through the NTC resistor of the IGBT.

[0060] IGBT temperature sampling circuit based on 555 Figure 1 As shown in the figure, capacitor C1, resistor R2 and IGBT internal NTC resistor R1 constitute the charging and discharging components of the chip oscillator. The temperature change of the IGBT causes the temperature change of the internal NTC thermistor, which changes the time when the oscillation circuit composed of 555 outputs a high level, and finally causes the frequency of the rectangular wave output by 555 to change with the temperature change.

[0061] The current / pulse width conversion function is realized by the 555 chip. The pin definition of the 555 chip is as follows: PIN1 is the ground terminal, PIN2 and PIN6 are the trigger terminals of the RC charge and discharge circuit, PIN3 is the digital signal output terminal, PIN4 and PIN7 are the analog signal input terminals of the NTC resistor of the IGBT. PIN5 is the standby terminal, and PIN8 is the chip power supply VCC terminal.

[0062] 3. The optimal selection of resistor R2 and capacitor C1 is as follows:

[0063] The optimization selection principle is that the smaller the resistance of resistor R2, the better, and the larger the capacitance of capacitor C1, the better. However, if the capacitance C1 is too large, it will cause excessive charging and discharging currents and damage the 555 chip. The increase of resistor R2 and capacitor C1 will also affect the system response time. Therefore, in the actual system, it is necessary to comprehensively consider various aspects to select appropriate resistors and capacitors.

[0064] 1) Sampling frequency selection: Since there is a phase-locked loop inside the FPGA, the sampling frequency range is set to 1M-200M;

[0065] 2) According to the variation range of NTC resistor R1, NTC resistor R1 is selected to have the maximum value, and resistor R2 is selected to have 500Ω, 5000Ω, and 50000Ω respectively. The values ​​of capacitor C1 can be obtained by formula (8):

[0066]

[0067] 3) According to the value of capacitor C1, use Matlab to draw the curves of NTC resistor R1, charge and discharge resistor R2 and sampling frequency when the resistor R2 is 500Ω, 5000Ω and 50000Ω respectively;

[0068] 4) According to the change curve of NTC resistance R1, charge and discharge resistance R2 and sampling frequency when resistance R2 is 500Ω, 5000Ω and 50000Ω respectively, as shown in the figure Figure 2 As shown, the value of the resistor R2 with the best linearity is selected as the final selection of the resistor R2;

[0069] 5) After the final selection of the resistor R2 is determined, the final selection value of the capacitor C1 is the value of the capacitor C1 corresponding to the formula (8). Specific embodiment:

[0071] This design uses FPGA sampling frequency of 100M to calculate:

[0072] The selected temperature is updated every 100ms. Taking Infineon's IGBT as an example, its NTC resistance range is 100Ω-100KΩ. Through matlab, the curves of f and R1 are drawn when R2 is 500Ω, 5000Ω, and 50000Ω respectively. See Figure 2 , R = 5000Ω The test system has very good linearity, the resistor R2 is selected as 5KΩ, and the NTC resistor is selected as the maximum value of 100KΩ. The formula can be obtained:

[0073]

[0074] Finally, the capacitor C1 is selected as a 0.92uF capacitor and the resistor R2 is selected as a 5KΩ precision resistor.

[0075] 4. Detection Error Optimization

[0076] In the circuit application using chip 555 for sampling, since the pulse frequency f is inversely proportional to the oscillation capacitor C1, and the oscillation capacitor C1 is affected by the ambient temperature, the detection error is a factor that cannot be ignored. Figure 3 As shown in the figure, when the capacitance value changes from 0.47uF to 1.39uF, the relationship curve between the charging capacitance value of C1 and the cycle, the cycle error can reach about 10ms. The present invention uses the high-speed operation characteristics of FPGA, the error comparison algorithm of the capacitance value during discharge, and the new cycle operation time to obtain a very accurate IGBT temperature, thereby controlling the heat dissipation system of the SVG device and ensuring the reliable operation of the SVG device.

[0077] A detection error optimization method of an IGBT module temperature sampling detection system of the present invention includes the following steps:

[0078] Step 1: Initial calculation:

[0079] In the charging and discharging circuit of the multivibrator composed of NTC resistor R1, resistor R2, and capacitor C1, the charging and discharging time of capacitor C1 is T H and T L , the full response equation of the RC circuit to step excitation is:

[0080] u c (t) = V0e t / τ +E(1-e t / τ ) (1)

[0081] in: E=V CC , τ=(R1+R2)C1, and the above formula can be rearranged to obtain:

[0082]

[0083] Taking the natural logarithm with base e on both sides of the equation, we get the charging time:

[0084] T H =(R1+R2)C1*Ln2 (3)

[0085] Similarly, the discharge time is:

[0086] T L =R2C1Ln2 (4)

[0087] Combining the charging and discharging time, we get the oscillation period T and frequency f as follows:

[0088] T=T H +T L =(R1+2R2)C1*Ln2 (5)

[0089] f=1 / ((R1+2R2)C1*Ln2) (6)

[0090] In formula (3), R1 is used as the sampling resistor of NTC, and R2 and C1 are used as constants. Therefore, the value of NTC resistor R1 is obtained through the relationship between different NTC resistors R1 and the charging and discharging time in cycle T, thereby obtaining the temperature value of IGBT.

[0091] Step 2: Optimize detection error

[0092] 1) In FPGA, detect the pulse length of the sampling input port of FPGA to obtain the real-time new discharge time and period T Lnew and T new ;

[0093] 2) The new discharge time T LnewThe new capacitance value C is calculated by formula (4): 1new ;

[0094] 3) The optimized oscillation period T is obtained through the FPGA algorithm formula (7) new1 (abs is the absolute value of the brackets);

[0095]

[0096] 4) The oscillation period T calculated by formula (7) new1 The corresponding optimized IGBT resistance R is further calculated by formula (5): 1new , and then the optimized IGBT temperature is obtained.

[0097] In the actual test below, the NTC temperature measuring resistor R1 is selected as 2K (corresponding to 46 degrees) and 5K (corresponding to 25 degrees), and the capacitance of the charging and discharging capacitor C1 is changed from (0.47uf+0.1uf) to (0.92uf+0.1uf). The result graph is observed through an oscilloscope. Channel 4 is the digital signal output end of the 555 chip, channel 3 is the charge and discharge time of the C1 charging capacitor, and channel 1 is the digital signal sent to the FPGA signal end by the optical coupler isolation output. At the same time, the temperature value collected by the FPGA is observed.

[0098] like Figure 4 As shown, the NTC sampling resistor is 5K, the C1 charging capacitor is 0.57uf, and the captured oscilloscope screenshot shows that the calculated temperature on the FPGA side is 25 degrees, the charging time is 6.406ms, and the discharging time is 2.040ms.

[0099] like Figure 5 As shown, the NTC sampling resistor is 2K, the C1 charging capacitor is 0.57uf, and the captured oscilloscope screenshot shows that the calculated temperature on the FPGA side is 46 degrees, the charging time is 5.014ms, and the discharging time is 2.042ms.

[0100] like Figure 6 As shown, the NTC sampling resistor is 5K, the C1 charging capacitor is 0.92uf, and the captured oscilloscope screenshot shows that the calculated temperature on the FPGA side is 25 degrees, the charging time is 10.41ms, and the discharging time is 3.34ms.

[0101] like Figure 7 As shown, the NTC sampling resistor is 2K, the C1 charging capacitor is 0.92uf, and the captured oscilloscope screenshot shows that the calculated temperature on the FPGA side is 46 degrees, the charging time is 8.30ms, and the discharging time is 3.34ms.

[0102] like Figure 8As shown, the NTC sampling resistor is 5K, the C1 charging capacitor is 0.92uf, and the captured oscilloscope screenshot shows that the calculated temperature on the FPGA side is 25 degrees, the charging time is 11.30ms, and the discharging time is 3.70ms.

[0103] like Fig. 9 As shown, the NTC sampling resistor is 2K, the C1 charging capacitor is 0.92uf, and the captured oscilloscope screenshot shows that the calculated temperature on the FPGA side is 46 degrees, the charging time is 11.30ms, and the discharging time is 3.70ms.

[0104] Experiments show that by taking advantage of the high-speed operation of FPGA, using the error comparison algorithm of the capacitance value during discharge and applying the new cycle operation time, it is possible to obtain a very accurate IGBT temperature, thereby controlling the cooling system of the SVG device and ensuring the reliable operation of the SVG device.

[0105] The above embodiments are implemented based on the technical solution of the present invention, and detailed implementation methods and specific operation processes are given, but the protection scope of the present invention is not limited to the above embodiments. The methods used in the above embodiments are conventional methods unless otherwise specified.

Claims

1. A detection error optimization method for an IGBT module temperature sampling detection system, characterized in that: The system includes an NTC sampling circuit, an optical coupler isolation and an FPGA; The NTC sampling circuit includes an NTC resistor R1, a resistor R2, and a capacitor C1 connected in series from top to bottom, and also includes a 555 chip. The NTC resistor R1 is a temperature sampling resistor inside the IGBT module. The upper end of the NTC resistor R1 is connected to the power supply VCC, and the lower end of the capacitor C1 is grounded. The middle point of the series connection of the NTC resistor R1 and the resistor R2 is connected to the analog signal input end of the 555 chip. The middle point of the series connection of the resistor R2 and the capacitor C1 is connected to the trigger end of the charge and discharge circuit of the 555 chip. The output end of the 555 chip is the output end of the NTC sampling circuit, which is connected to the input end of the optocoupler isolation, and the output end of the optocoupler isolation is connected to the input of the FPGA chip; The detection error optimization method includes the following steps: Step 1: Initial calculation: In the charging and discharging circuit of the multivibrator composed of NTC resistor R1, resistor R2, and capacitor C1, the charging and discharging time of capacitor C1 is T H and T L , the full response equation of the RC circuit to step excitation is: u c (t)=V0e t / τ +E(1-e t / τ ) (1) in: E=VCC,τ=(R1+R2)C1,arranging the above formula gives: Taking the natural logarithm with base e on both sides of the equation, we get the charging time: T H =(R1+R2)C1*Ln2 (3) Similarly, the discharge time is: T L =R2C1Ln2 (4) Combining the charging and discharging times, we get the oscillation period T and frequency f as follows: T=T H +T L =(R1+2R2)C1*Ln2 (5) f=1 / ((R1+2R2)C1*Ln2) (6) In formula (3), R1 is used as the sampling resistor of NTC, and R2 and C1 are used as constants. Therefore, the value of NTC resistor R1 is obtained through the relationship between different NTC resistors R1 and the charging and discharging time in cycle T, thereby obtaining the temperature value of IGBT; Step 2: Optimize detection error 1) In FPGA, detect the pulse length of the sampling input port of FPGA to obtain the real-time new discharge time and period T Lnew and T new ; 2) The new discharge time T Lnew The new capacitance value C is calculated by formula (4) 1new ; 3) The optimized oscillation period T is obtained through the FPGA algorithm formula (7) new1 , abs is the absolute value function; 4) The oscillation period T calculated by formula (7) new1 The corresponding optimized NTC resistance R is further calculated by formula (5) 1new , and then the optimized IGBT temperature is obtained.

2. The detection error optimization method of the IGBT module temperature sampling detection system according to claim 1, characterized in that: It also includes the optimization selection method of resistor R2 and capacitor C1, as follows: The optimization selection principle is that the smaller the resistance of resistor R2, the better, and the larger the capacitance of capacitor C1, the better. However, if the capacitance C1 is too large, it will cause excessive charging and discharging currents and damage the 555 chip. The increase of resistor R2 and capacitor C1 will also affect the system response time. Therefore, in the actual system, it is necessary to comprehensively consider various aspects to select appropriate resistors and capacitors. 1) Sampling frequency selection: Since there is a phase-locked loop inside the FPGA, the sampling frequency range is set to 1M-200M; 2) According to the variation range of NTC resistor R1, NTC resistor R1 is selected to have the maximum value, and resistor R2 is selected to have 500Ω, 5000Ω, and 50000Ω respectively. The values ​​of capacitor C1 can be obtained by formula (8): 3) According to the value of capacitor C1, use Matlab to draw the curve of NTC resistance R1 and sampling frequency change when resistance R2 takes 500Ω, 5000Ω, and 50000Ω respectively; 4) According to the NTC resistance R1 and sampling frequency change curves when the resistance R2 is 500Ω, 5000Ω, and 50000Ω respectively, the value of the resistance R2 with the best linearity is selected as the final selection of the resistance R2; 5) After the final selection of the resistor R2 is determined, the final selection value of the capacitor C1 is the value of the capacitor C1 corresponding to the formula (8).

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