EUV photomask and method for manufacturing the same

Abstract

The present disclosure relates to an EUV photomask and a method for manufacturing the same. A reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an intermediate layer disposed on the cap layer, an absorber layer disposed on the intermediate layer, and a cover layer disposed on the absorber layer. The intermediate layer includes a material having a lower hydrogen diffusion rate than a material of the cap layer.

Description

Technical Field

[0001] The present disclosure generally relates to EUV photomasks and methods of making the same. Background Art

[0002] Photolithography is one of the key operations in the semiconductor manufacturing process. Photolithography technology includes ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). Photomask is an important component in photolithography. It is crucial to manufacture EUV photomasks with high contrast, including high reflectivity parts and high absorption parts. Summary of the invention

[0003] According to one embodiment of the present disclosure, a reflective mask is provided, comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; an intermediate layer disposed on the cap layer; an absorber layer disposed on the intermediate layer; and a covering layer disposed on the absorber layer, wherein the intermediate layer comprises a material having a lower hydrogen diffusion rate than that of the cap layer.

[0004] According to another embodiment of the present disclosure, a method for manufacturing a reflective mask is provided, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a covering layer on the absorber layer, and a hard mask layer on the covering layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer; patterning the covering layer and the absorber layer by using the patterned hard mask layer to form an opening; and removing the hard mask layer, wherein, after removing the hard mask layer, a portion of the intermediate layer is exposed in the opening.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a reflective mask is provided, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer arranged on the substrate, a cap layer arranged on the reflective multilayer, an intermediate layer arranged on the cap layer, an absorber layer arranged on the intermediate layer, a covering layer arranged on the absorber layer, and a hard mask layer arranged on the covering layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer as a mask; patterning the covering layer and the absorber layer by using the patterned hard mask layer as a mask to form an opening; and removing the hard mask layer, wherein: the reflective multilayer comprises alternately stacked Si layers and Mo layers, and the uppermost Si layer of the reflective multilayer is separated from the cap layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B , Figure 1C and Figure 1D An EUV photomask blank according to an embodiment of the present disclosure is shown.

[0008] Figure 2A A cross-sectional view of a photomask blank according to an embodiment of the present disclosure is shown, and Figure 2B A cross-sectional view of a photomask according to an embodiment of the present disclosure is shown.

[0009] Figure 3A A cross-sectional view of a photomask blank according to an embodiment of the present disclosure is shown, and Figure 3B A cross-sectional view of a photomask according to an embodiment of the present disclosure is shown.

[0010] Figure 4A A cross-sectional view of a photomask blank according to an embodiment of the present disclosure is shown, and Figure 4B A cross-sectional view of a photomask according to an embodiment of the present disclosure is shown.

[0011] Figure 5A A cross-sectional view of a photomask blank according to an embodiment of the present disclosure is shown, and Figure 5B A cross-sectional view of a photomask according to an embodiment of the present disclosure is shown.

[0012] Fig. 6A A cross-sectional view of a photomask blank according to an embodiment of the present disclosure is shown, and Figure 6B A cross-sectional view of a photomask according to an embodiment of the present disclosure is shown.

[0013] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically illustrated.

[0014] Fig. 8A , Figure 8B , Figure 8C and Fig.8D A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically illustrated.

[0015] Fig.9A , Fig. 9B and Fig. 9C A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically illustrated.

[0016] Fig. 10A A flowchart showing a method of manufacturing a semiconductor device, and Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E Sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0017] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or desired characteristics of the device. In addition, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an additional feature that may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For simplicity and clarity, various features may be arbitrarily drawn in different proportions.

[0018] In addition, for ease of description, spatially related terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to describe the relationship of an element or feature shown in the figure to another (one or more) element or (one or more) feature. These spatially related terms are intended to cover different orientations of the device in use or operation except for the orientation shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may also be interpreted accordingly. In addition, the term "made of..." may mean "including" or "consisting of..." In the present disclosure, the phrase "one of A, B and C" refers to "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and unless otherwise specified, it does not mean that one element is from A, one element is from B and one element is from C. The materials, configurations, processes and / or dimensions explained with respect to one embodiment may be used in other embodiments, and their detailed description may be omitted.

[0019] Embodiments of the present disclosure provide a method for manufacturing an EUV photomask. More specifically, the present disclosure provides a technique for preventing or suppressing damage to a back conductive layer of an EUV photomask.

[0020] EUV lithography (EUVL) uses scanners that use light in the extreme ultraviolet (EUV) region with a wavelength of about 1 nm to about 100 nm, for example, 13.5 nm. The mask is a key component of the EUVL system. Since optical materials are not transparent to EUV radiation, the EUV photomask is a reflective mask. The circuit pattern is formed in an absorber layer disposed above the reflective structure. The absorber layer has a low EUV reflectivity, for example, less than 3-5%.

[0021] The present disclosure provides an EUV reflective photomask having a low reflective (high absorption) absorber structure.

[0022] Figure 1A and Figure 1B An EUV reflective photomask blank according to an embodiment of the present disclosure is shown. Figure 1D A patterned EUV reflective photomask is shown ready for EUV lithography. Figure 1A is a plan view (seen from the top), and Figure 1B It is a cross-sectional view along the X direction.

[0023] In some embodiments, an EUV photomask having a circuit pattern is formed from an EUV photomask blank 5. The EUV photomask blank 5 includes a substrate 10, a multilayer Mo / Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a cap layer 20, an absorber layer 25, a capping (or anti-reflection) layer 27, and a hard mask layer 30. Figure 1B As shown, a back conductive layer 45 is formed on the back side of the substrate 10 .

[0024] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, for example, fused silica glass or fused quartz. In some embodiments, the low thermal expansion glass substrate transmits light of a visible wavelength, a portion of infrared wavelengths (near infrared) near the visible spectrum, and a portion of ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths close to extreme ultraviolet wavelengths. In some embodiments, the size of the substrate 10 is 152 mm×152 mm and the thickness is approximately 20 mm. In other embodiments, the size of the substrate 10 is less than 152 mm×152 mm and is equal to or greater than 148 mm×148 mm. In some embodiments, the shape of the substrate 10 is square or rectangular.

[0025] In some embodiments, the width of the functional layers (multilayer Mo / Si stack 15, cap layer 20, absorber layer 25, cap layer 27, and hard mask layer 30) above the substrate is less than the width of the substrate 10. In some embodiments, the size of the functional layer is in the range of from about 138 mm×138 mm to 142 mm×142 mm. In some embodiments, the shape of the functional layer is square or rectangular.

[0026] In other embodiments, the absorber layer 25, the cap layer 27, and the hard mask layer 30 have smaller dimensions than the substrate 10, the multilayer Mo / Si stack 15, and the cap layer 20, ranging from about 138 mm×138 mm to 142 mm×142 mm, as shown in FIG. Figure 1C When each functional layer is formed by, for example, sputtering, a smaller size of one or more functional layers can be formed by using a frame-shaped cover having an opening ranging from about 138 mm×138 mm to 142 mm×142 mm. In other embodiments, all layers above the substrate 10 have the same size as the substrate 10.

[0027] In some embodiments, the Mo / Si multilayer stack 15 includes about 30 layers of silicon and molybdenum alternating layers to about 60 layers of silicon and molybdenum alternating layers. In certain embodiments, about 40 to about 50 layers of silicon and molybdenum alternating layers are formed. In some embodiments, for a wavelength of interest, such as 13.5nm, the reflectivity is higher than about 70%. In some embodiments, the silicon layer and the molybdenum layer are formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable method of forming a film. Each layer of silicon and molybdenum is about 2 nm to about 10 nm thick. In some embodiments, the silicon layer and the molybdenum layer have approximately the same thickness. In other embodiments, the silicon layer and the molybdenum layer have different thicknesses. In some embodiments, the thickness of each silicon layer is about 4nm, and the thickness of each molybdenum layer is about 3nm. In some embodiments, the bottom layer of the multilayer stack 15 is a Si layer or a Mo layer.

[0028] In other embodiments, the multilayer stack 15 includes alternating layers of molybdenum and beryllium. In some embodiments, the number of layers in the multilayer stack 15 ranges from about 20 to about 100, but any number of layers is allowed as long as sufficient reflectivity is maintained for imaging the target substrate. In some embodiments, the reflectivity is higher than about 70% for wavelengths of interest, such as 13.5 nm. In some embodiments, the multilayer stack 15 includes about 30 to about 60 layers of alternating layers of Mo and Be. In other embodiments of the present disclosure, the multilayer stack 15 includes about 40 to about 50 layers of alternating layers of Mo and Be.

[0029] In some embodiments, the capping layer 20 is disposed on the Mo / Si multilayer stack 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the capping layer 20 is formed of elemental ruthenium (non-Ru compound), ruthenium alloy (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV or RuVN), or ruthenium-based oxide (e.g., RuO2, RuNbO, RiVO or RuON) with a thickness of about 2nm to about 10nm. In certain embodiments, the thickness of the capping layer 20 is from about 2nm to about 5nm. In some embodiments, the thickness of the capping layer 20 is 3.5nm±10%. In some embodiments, the capping layer 20 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable method of forming a film. In other embodiments, a Si layer is used as the capping layer 20. As described below in some embodiments, one or more layers are disposed between the capping layer and the multilayer 15.

[0030] The absorber layer 25 is disposed on the cap layer 20. In some embodiments, the absorber layer 25 is a Ta-based material. In some embodiments, the absorber layer 25 is made of TaN, TaO, TaB, TaBO or TaBN, and has a thickness of about 25 nm to about 100 nm. In certain embodiments, the thickness of the absorber layer 25 is in the range of about 50 nm to about 75 nm. In other embodiments, the absorber layer 25 includes a Cr-based material, for example, CrN, CrO, and / or CrON. In some embodiments, the absorber layer 25 has a multilayer structure of Cr, CrO or CrON. In some embodiments, the absorber layer 25 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film. As described below in some embodiments, one or more layers are disposed between the cap layer 20 and the absorber layer 25.

[0031] In some embodiments, a capping layer or anti-reflection layer 27 is disposed on the absorber layer 25. In some embodiments, the capping layer 27 includes a Ta-based material, such as TaB, TaO, TaBO, or TaBN, silicon, a silicon-based compound (e.g., silicon oxide, SiN, SiON, or MoSi), ruthenium, or a ruthenium-based compound (Ru or RuB). In certain embodiments, the capping layer 27 is made of tantalum oxide (Ta2O5 or non-stoichiometric (e.g., oxygen-deficient) tantalum oxide) and has a thickness of about 2 nm to about 20 nm. In other embodiments, a TaBO layer having a thickness ranging from about 2 nm to about 20 nm is used as the capping layer. In some embodiments, the thickness of the capping layer 27 is about 3 nm to 10 nm. In some embodiments, the capping layer 27 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film.

[0032] In some embodiments, the hard mask layer 30 is disposed on the cap layer 27. In some embodiments, the hard mask layer 30 is made of a Cr-based material, for example, CrO, CrON, or CrCON. In other embodiments, the hard mask layer 30 is made of a Ta-based material, for example, TaB, TaO, TaBO, or TaBN. In other embodiments, the hard mask layer 30 is made of silicon, a silicon-based compound (for example, SiN or SiON), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the thickness of the hard mask layer 30 is about 4 nm to about 20 nm. In some embodiments, the hard mask layer 30 includes two or more different material layers. In some embodiments, the hard mask layer 30 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film.

[0033] In some embodiments, the back conductive layer 45 is disposed on a second main surface of the substrate 10, which is opposite to the first main surface of the substrate 10 on which the Mo / Si multilayer stack 15 is formed. In some embodiments, the back conductive layer 45 is made of TaB (tantalum boride) or other Ta-based conductive materials. In some embodiments, tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4 and TaB2. In other embodiments, tantalum boride is polycrystalline or amorphous. In other embodiments, the back conductive layer 45 is made of a Cr-based conductive material (CrN or CrON). In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or less than 20Ω / □. In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or greater than 0.1Ω / □. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or less than 0.25nm. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or greater than 0.05nm. In addition, in some embodiments, the flatness of the back conductive layer 45 (within the EUV photomask) is equal to or less than 50 nm. In some embodiments, the flatness of the back conductive layer 45 is greater than 1 nm. In some embodiments, the thickness of the back conductive layer 45 is in the range from about 50 nm to about 400 nm. In other embodiments, the back conductive layer 45 has a thickness of about 50 nm to about 100 nm. In certain embodiments, the thickness is in the range from about 65 nm to about 75 nm. In some embodiments, the back conductive layer 45 is formed by atmospheric chemical vapor deposition (CVD), low pressure CVD, plasma enhanced CVD, laser enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition (including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation and sputtering), or any other suitable method of forming a film. In some embodiments, in the case of CVD, the source gas includes TaCl5 and BCl3.

[0034] Figure 2A and FIG. 2B to FIG. 6A and Figure 6B Various structures of a mask blank ("A" panel) and a patterned photomask ("B" panel) are shown.

[0035] In some embodiments, Figure 2A and Figure 2BAs shown, an intermediate layer 22 is formed between the cap layer 20 and the absorber layer 25. In some embodiments, the intermediate layer 22 is used to protect the cap layer 20. In some embodiments, the intermediate layer 22 includes a Ta-based compound (e.g., TaB, TaO, TaBO, or TaBN), silicon, a silicon-based compound (e.g., silicon oxide, SiN, SiON, or MoSi), molybdenum, niobium, niobium oxide, ruthenium, or a ruthenium-based compound (RuO2 or RuB). In other embodiments, the intermediate layer 22 includes a metal oxide, such as niobium oxide, tantalum oxide, ruthenium oxide, and / or molybdenum oxide. In other embodiments, the intermediate layer 22 includes an elemental metal (non-compound), such as Mo, Ta, Cr, Ni, Co, and / or Ir. In certain embodiments, the intermediate layer 22 is made of tantalum oxide (Ta2O5 or non-stoichiometric (e.g., oxygen-deficient) tantalum oxide). In some embodiments, the intermediate layer 22 is made of the same or similar material as the cap layer 27. In some embodiments, the intermediate layer 22 has a lower hydrogen diffusivity than Ru (a hydrogen barrier), and / or a lower carbon solubility or reactivity than Ru (a protective layer against carbon or hydrocarbon contamination).

[0036] In some embodiments, the intermediate layer 22 has a thickness of about 0.5 nm to about 5 nm, and in other embodiments, the thickness is in the range of about 1 nm to about 3 nm. In some embodiments, the intermediate layer 22 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film-forming method. In some embodiments, the intermediate layer 22 is used as an etch stop layer during the patterning operation of the absorber layer.

[0037] In other embodiments, the intermediate layer 22 is a photocatalytic layer that can catalyze hydrocarbon residues formed on the photomask into CO2 and / or H2O using EUV radiation. Thus, in-situ self-cleaning of the mask surface is performed. In some embodiments, in the EUV scanner system, oxygen and hydrogen are injected into the EUV chamber to maintain the chamber pressure (e.g., about 2 Pa). The chamber background gas can be a source of oxygen. In addition to the photocatalytic function, the photocatalytic layer is also designed to have sufficient durability and resistance to various chemicals and various chemical processes (e.g., cleaning and etching). In some examples, the ozonated water used to manufacture the EUV reflective mask in the subsequent process can damage the cap layer 20 made of Ru and cause a significant decrease in EUV reflectivity. In addition, after Ru oxidation, Ru oxide is easily etched away by an etchant such as C12 or CF4 gas. In some embodiments, the photocatalytic layer includes one or more of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO), and cadmium sulfide (CdS). In some embodiments, the thickness of the photocatalytic layer 22 is in a range from about 2 nm to about 10 nm, and in other embodiments, in a range from about 3 nm to about 7 nm. When the thickness is too thin, the photocatalytic layer may not be sufficient to serve as an etch stop layer. When the thickness is too large, the photocatalytic layer may absorb EUV radiation.

[0038] like Figure 2B As shown, after forming the circuit pattern 42 , the hard mask layer 30 is removed, and thus the EUV photomask does not include the hard mask layer.

[0039] In some embodiments, Figure 3A and Figure 3B As shown, no intermediate layer is formed between the cap layer 20 and the absorber layer 25, and the uppermost layer of the multilayer 15 is a Mo layer. In other words, the uppermost Si layer of the multilayer 15 is not in contact with the cap layer 20. Figure 3B As shown, after forming the circuit pattern 42 , the hard mask layer 30 is removed, and thus the EUV photomask does not include the hard mask layer.

[0040] When the Ru or Ru alloy layer is in direct contact with the Si layer, the adhesion of the Ru-based layer to the Si layer may be weak due to hydrogen diffusion and hydrogen accumulation at the interface between the Ru-based layer and the Si layer. Figure 3A and Figure 3B In the illustrated embodiment, where the multilayer stack 15 is terminated by a Mo layer, sufficient bonding or adhesion strength may be maintained between the cap layer and the multilayer stack 15 .

[0041] In some embodiments, Figure 4A and Figure 4BAs shown, no intermediate layer is formed between the cap layer 20 and the absorber layer 25, and the barrier layer 18 is formed between the multilayer 15 and the cap layer 20. In other words, even if the uppermost layer of the multilayer 15 is a Si layer, the Si layer is not in contact with the cap layer 20. In some embodiments, the barrier layer 18 includes a silicon compound, such as silicon oxide, silicon nitride, SiON and / or SiOCN. In other embodiments, the barrier layer 18 includes a metal oxide, such as niobium oxide, tantalum oxide, ruthenium oxide and / or molybdenum oxide. In other embodiments, the barrier layer 18 includes an elemental metal (not a compound), such as Be, Mo, Ta, Cr, Ni, Co and / or Ir.

[0042] In some embodiments, the thickness of barrier layer 18 is in the range of about 0.5 nm to about 5 nm, and in other embodiments, the thickness is in the range of about 1 nm to about 3 nm. In some embodiments, barrier layer 22 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, thermal oxidation or chemical oxidation, or any other suitable film forming method. Figure 4B As shown, after forming the circuit pattern 42, the hard mask layer 30 is removed, so the EUV photomask does not include the hard mask layer. In some embodiments, the uppermost layer of the multilayer 15 is a Si layer (eg, Figure 4A and Figure 4B shown) or Mo layer.

[0043] In some embodiments, Figure 5A and Figure 5B As shown, the intermediate layer 22 is formed between the cap layer 20 and the absorber layer 25, and the uppermost layer of the multilayer 15 is a Mo layer. In other words, the uppermost Si layer of the multilayer 15 is not in contact with the cap layer 20. Figure 5B As shown, after forming the circuit pattern 42 , the hard mask layer 30 is removed, and thus the EUV photomask does not include the hard mask layer.

[0044] In some embodiments, Fig. 6A and Figure 6B As shown, an intermediate layer 22 is formed between the cap layer 20 and the absorber layer 25, and a barrier layer 18 is formed between the multilayer 15 and the cap layer 20. In other words, even if the uppermost layer of the multilayer 15 is a Si layer, the Si layer does not contact the cap layer 20. Figure 6B As shown, after forming the circuit pattern 42, the hard mask layer 30 is removed, so the EUV photomask does not include the hard mask layer. In some embodiments, the uppermost layer of the multilayer 15 is a Si layer (as shown in FIGS. 6A and 6B). Figure 6B shown) or Mo layer.

[0045] Figure 7A-7F and Figure 8A-8DThe method for manufacturing an EUV photomask for extreme ultraviolet lithography (EUVL) is schematically shown. It should be understood that the method can be Figures 7A-8D Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable. Figure 7A-7F and Figure 8A-8D Involving Figure 2A , Figure 4A , Figure 5A and Fig. 6A A mask blank of the intermediate layer 22 is shown.

[0046] In the manufacture of the EUV photomask, a first photoresist layer 35 is formed on the hard mask layer 30 of the EUV photomask blank. Fig. 7A As shown, the photoresist layer 35 is selectively exposed to actinic radiation EB, as shown Figure 7B In some embodiments, before forming the first photoresist layer 35, the EUV photomask blank is inspected. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35, as shown in FIG. Figure 7C In some embodiments, the actinic radiation EB is an electron beam or an ion beam. In some embodiments, pattern 40 corresponds to the pattern of semiconductor device features that an EUV photomask will be used to form in a subsequent operation.

[0047] Next, the pattern 40 in the first photoresist layer 35 is extended into the hard mask layer 30, thereby forming a pattern 41 in the hard mask layer 30, exposing portions of the capping layer 27, such as Fig.7D In some embodiments, a pattern 41 extending into the hard mask layer 30 is formed by etching using a suitable wet or dry etchant that is selective to the cap layer 27. After forming the pattern 41 in the hard mask layer 30, the first photoresist layer 35 is removed using a photoresist stripper to expose the upper surface of the hard mask layer 30, as shown in FIG. Fig. 7E shown.

[0048] Then, the pattern 41 in the hard mask layer 30 is extended into the cap layer 27 and the absorber layer 25, thereby forming a pattern 42 in the cap layer 27 and the absorber layer 25 (see Fig. 8A ), exposing multiple portions of the intermediate layer 22, such as Figure 7F As shown, the hard mask layer 30 is then removed, as shown in FIG. Fig. 8AAs shown. In some embodiments, a pattern 42 extending into the capping layer 27 and the absorber layer 25 is formed by etching using a suitable wet or dry etchant that is selective to the intermediate layer 22. In some embodiments, plasma dry etching is used. In some embodiments, when the intermediate layer 22 is made of the same material or a similar material as the hard mask layer 30, or when the intermediate layer 22 and the hard mask layer 30 have similar etching resistance to the etching of the absorber layer 25, the etching is substantially stopped at the intermediate layer 22. In some embodiments, the capping layer 27 is patterned by using a patterned hard mask layer 30, and then the absorber layer 25 is patterned by using the patterned capping layer 27 as an etching mask with or without the hard mask layer 30 (i.e., the capping layer is used as a hard mask).

[0049] like Figure 8B As shown, a second photoresist layer 50 is formed on the absorber layer 25, filling the cap layer 27 and the pattern 42 in the absorber layer 25. The second photoresist layer 50 is selectively exposed to actinic radiation, such as an electron beam, an ion beam, or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a pattern 55 in the second photoresist layer 50, as shown in FIG. Figure 8B As shown. Pattern 55 corresponds to a black edge around the circuit pattern. The black edge is a frame-shaped area created by removing all the multiple layers on the EUV photomask in the area around the circuit pattern area. The frame-shaped area is created to prevent exposure of adjacent fields when the EUV photomask is printed on the wafer. In some embodiments, the width of the black edge is in the range from about 1 mm to about 5 mm.

[0050] Next, the pattern 55 in the second photoresist layer 50 is extended into the capping layer 27, the absorber layer 25, the capping layer 20 and the Mo / Si multilayer 15 to form the pattern 57 in the absorber layer 25, the capping layer 20 and the Mo / Si multilayer 15 (see Fig.8D ), exposing multiple portions of substrate 10, as shown in FIG8C. In some embodiments, pattern 57 is formed by etching using one or more suitable wet or dry etchants that are selective to each layer being etched. In some embodiments, plasma dry etching is used.

[0051] Then, the second photoresist layer 50 is removed using a suitable photoresist stripper to expose the upper surface of the absorber layer 25, such as Fig.8D In some embodiments of the present disclosure, the black edge pattern 57 in the capping layer 27, the absorber layer 25, the capping layer 20, and the Mo / Si multilayer 15 defines a black edge of the photomask.

[0052] Fig.9A, Fig. 9B and Fig. 9C FIG. 4 is a cross-sectional view showing a multilayer structure of an absorber layer according to another embodiment of the present disclosure. Fig.9A , Fig. 9B and Fig. 9C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for other embodiments of the method. The order of operations / processes may be interchangeable. The materials, configurations, processes, and / or dimensions explained with respect to the previous embodiments may be employed in the following embodiments, and their detailed description may be omitted. Fig.9A , Fig. 9B and Fig. 9C The embodiment is used for Figure 2A and Figure 3A The mask blank shown has no intermediate layer 22 formed therein.

[0053] Fig.9A shows the structure after the hard mask layer 30 is patterned, similar to Fig. 7E Then, the capping layer 27 and the absorber layer 25 are patterned (etched) by using the patterned hard mask layer 25, as shown in FIG. Fig. 9B In some embodiments, etching stops substantially at the cap layer 20. Then, as shown in FIG. Fig. 9C As shown, the hard mask layer 30 is removed.

[0054] Fig. 10A A process for manufacturing a semiconductor device is shown, and Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E Sequential manufacturing operations of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. A semiconductor substrate or other suitable substrate is provided, which is to be patterned to form an integrated circuit thereon. In some embodiments, the semiconductor substrate includes silicon. Alternatively or additionally, the semiconductor substrate includes germanium, silicon germanium, or other suitable semiconductor materials, such as III-V semiconductor materials. Fig. 10A In S101, a target layer to be patterned is formed on a semiconductor substrate. In some embodiments, the target layer is a semiconductor substrate. In some embodiments, the target layer includes a conductive layer such as a metallization layer or a polysilicon layer; a dielectric layer such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed on an underlying structure such as an isolation structure, a transistor, or a wiring. Fig. 10A In S102, a photoresist layer is formed on the target layer, such as Fig. 10BAs shown. In the subsequent photolithography exposure process, the photoresist layer is sensitive to radiation from the exposure source. In this embodiment, the photoresist layer is sensitive to EUV light used in the photolithography exposure process. The photoresist layer can be formed on the target layer by spin coating or other suitable techniques. The coated photoresist layer can be further baked to drive out the solvent in the photoresist layer. Fig. 10A S103, patterning the photoresist layer using the EUV reflective mask as described above, such as Fig. 10B As shown. Patterning the photoresist layer includes performing a photolithography exposure process using an EUV exposure system using an EUV mask. In the exposure process, the integrated circuit (IC) design pattern defined on the EUV mask is imaged to the photoresist layer to form a latent pattern thereon. Patterning the photoresist layer also includes developing the exposed photoresist layer to form a patterned photoresist layer with one or more openings. In an embodiment where the photoresist layer is a positive photoresist layer, the exposed portion of the photoresist layer is removed in the development process. Patterning the photoresist layer may also include other process steps, for example, various baking steps at different stages. For example, a post-exposure baking (PEB) process may be implemented after the photolithography exposure process and before the development process.

[0055] exist Fig. 10A S104, using the patterned photoresist layer as an etching mask to pattern the target layer, such as Fig. 10D In some embodiments, patterning the target layer includes applying an etching process to the target layer using the patterned photoresist layer as an etching mask. Portions of the target layer exposed within the openings of the patterned photoresist layer are etched, while the remaining portions are protected from being etched. In addition, the patterned photoresist layer can be removed by wet stripping or plasma ashing, such as Fig.10E shown.

[0056] In the present disclosure, in the case where an intermediate layer (protective layer) is provided on the cap layer, the cap layer can be effectively protected during the dry etching of the absorber layer. In addition, the use of the intermediate layer can reduce carbon or hydrocarbon contamination on the cap layer. In addition, in some embodiments of the present disclosure, a barrier layer is provided below the cap layer, which prevents the EUV mask from diffusing with hydrogen in the intermediate layer. In addition, in some embodiments of the present disclosure, the multilayer is terminated by a Mo layer, which prevents the cap layer from peeling off from the multilayer.

[0057] It will be understood that not all advantages are necessarily discussed herein, that no particular advantage is necessary for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0058] According to one aspect of the present application, a reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an intermediate layer disposed on the cap layer, an absorber layer disposed on the intermediate layer, and a covering layer disposed on the absorber layer. The intermediate layer includes a material having a lower hydrogen diffusion rate than the material of the cap layer. In one or more of the foregoing and following embodiments, the intermediate layer includes tantalum oxide. In one or more of the foregoing and following embodiments, the thickness of the intermediate layer is in the range of 0.5nm to 3nm. In one or more of the foregoing and following embodiments, the covering layer is made of the same material as the intermediate layer. In one or more of the foregoing and following embodiments, the intermediate layer and the covering layer include tantalum oxide. In one or more of the foregoing and following embodiments, the reflective mask also includes: an opening pattern formed in the covering layer and the absorber layer, and the intermediate layer is exposed at the bottom of the opening pattern. In one or more of the foregoing and following embodiments, the reflective multilayer includes Si layers and Mo layers stacked alternately, and the Si layer of the reflective multilayer is in contact with the cap layer. In one or more of the foregoing and following embodiments, the reflective multilayer includes Si layers and Mo layers stacked alternately, and the Mo layer of the reflective multilayer is in contact with the cap layer.

[0059] According to another aspect of the present disclosure, a reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a barrier layer disposed on the reflective multilayer, a cap layer disposed on the barrier layer, an absorber layer disposed on the cap layer, and a covering layer disposed on the absorber layer. The barrier layer includes one or more of SiON or SiN. In one or more of the foregoing and following embodiments, the thickness of the barrier layer is in the range of 0.5nm to 5nm. In one or more of the foregoing and following embodiments, the reflective mask also includes an intermediate layer between the cap layer and the absorber layer. In one or more of the foregoing and following embodiments, the intermediate layer includes at least one of tantalum oxide, niobium oxide, or ruthenium oxide. In one or more of the foregoing and following embodiments, the intermediate layer includes at least one of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO), or cadmium sulfide (CdS). In one or more of the foregoing and following embodiments, the reflective multilayer includes alternately stacked Si layers and Mo layers, and the Si layer of the reflective multilayer is in contact with the barrier layer. In one or more of the foregoing and following embodiments, the reflective multilayer includes Si layers and Mo layers stacked alternately, and the Mo layer of the reflective multilayer is in contact with the barrier layer.

[0060] According to another aspect of the present disclosure, a reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a barrier layer disposed on the reflective multilayer, a cap layer disposed on the barrier layer, an absorber layer disposed on the cap layer, and a covering layer disposed on the absorber layer. The reflective multilayer includes Si layers and Mo layers stacked alternately, and the uppermost Si layer of the reflective multilayer does not contact the cap layer. In one or more of the foregoing and following embodiments, the covering layer is made of tantalum oxide. In one or more of the foregoing and following embodiments, a silicon compound layer is inserted between the multilayer and the cap layer. In one or more of the foregoing and following embodiments, the uppermost Mo layer of the reflective multilayer does not contact the cap layer. In one or more of the foregoing and following embodiments, the cap layer is made of at least one of RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, or RuVN.

[0061] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a cap layer on the absorber layer, and a hard mask layer on the cap layer. Patterning the photoresist layer, patterning the hard mask layer by using the patterned photoresist layer, patterning the cap layer and the absorber layer by using the patterned hard mask layer to form an opening, and removing the hard mask layer. After removing the hard mask layer, a portion of the intermediate layer is exposed in the opening. In one or more of the foregoing and following embodiments, the cap layer is made of the same material as the intermediate layer. In one or more of the foregoing and following embodiments, the intermediate layer and the cap layer include tantalum oxide. In one or more of the foregoing and following embodiments, the hard mask layer includes CrO or CrON. In one or more of the foregoing and following embodiments, the absorber layer is made of TaBN. In one or more of the foregoing and following embodiments, the cap layer is made of Ru. In one or more of the foregoing and following embodiments, the thickness of the intermediate layer is in the range of 0.5 nm to 3 nm.

[0062] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a covering layer on the absorber layer, and a hard mask layer on the covering layer. Patterning the photoresist layer, patterning the hard mask layer by using the patterned photoresist layer, patterning the covering layer and the absorber layer by using the patterned hard mask layer to form an opening, and removing the hard mask layer. The reflective multilayer includes Si layers and Mo layers stacked alternately, and the uppermost Si layer of the reflective multilayer does not contact the cap layer. In one or more of the foregoing and following embodiments, after removing the hard mask layer, a portion of the intermediate layer is exposed in the opening. In one or more of the foregoing and following embodiments, at least one of the intermediate layer and the covering layer includes tantalum oxide. In one or more of the foregoing and following embodiments, a silicon compound layer is inserted between the multilayer and the cap layer. In one or more of the foregoing and following embodiments, the silicon compound layer comprises one or more of SiON or SiN. In one or more of the foregoing and following embodiments, the thickness of the silicon compound layer is in the range of 0.5 nm to 5 nm. In one or more of the foregoing and following embodiments, the uppermost Mo layer of the reflective multilayer is not in contact with the cap layer.

[0063] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, a covering layer on the absorber layer, and a hard mask layer on the covering layer. The photoresist layer is patterned, the hard mask layer is patterned by using the patterned photoresist layer, the covering layer and the absorber layer are patterned by using the patterned hard mask layer to form an opening, and the hard mask layer is removed. The reflective multilayer includes alternately stacked Si layers and Mo layers, the uppermost Si layer of the reflective multilayer does not contact the cap layer, and after removing the hard mask layer, a portion of the cap layer is exposed in the opening. In one or more of the foregoing and following embodiments, the covering layer includes tantalum oxide. In one or more of the foregoing and following embodiments, a barrier layer is inserted between the multilayer and the cap layer. In one or more of the foregoing and following embodiments, the barrier layer includes one or more of SiON or SiN. In one or more of the foregoing and following embodiments, the thickness of the barrier layer is in the range of 0.5 nm to 5 nm. In one or more of the foregoing and following embodiments, the uppermost layer of the reflective multilayer is a Mo layer.

[0064] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0065] Example 1 is a reflective mask comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; an intermediate layer disposed on the cap layer; an absorber layer disposed on the intermediate layer; and a covering layer disposed on the absorber layer, wherein the intermediate layer comprises a material having a lower hydrogen diffusion rate than that of the cap layer.

[0066] Example 2 is the reflective mask of Example 1, wherein the intermediate layer comprises tantalum oxide.

[0067] Example 3 is the reflective mask of Example 1, wherein the thickness of the intermediate layer is in a range of 0.5 nm to 3 nm.

[0068] Example 4 is the reflective mask of Example 1, wherein the cover layer is made of the same material as the intermediate layer.

[0069] Example 5 is the reflective mask of Example 4, wherein the intermediate layer and the capping layer include tantalum oxide.

[0070] Example 6 is the reflective mask of Example 1, further comprising: an opening pattern formed in the cover layer and the absorber layer, wherein the intermediate layer is exposed at a bottom of the opening pattern.

[0071] Example 7 is the reflective mask described in Example 1, wherein: the reflective multilayer includes Si layers and Mo layers stacked alternately, and the Si layer of the reflective multilayer is in contact with the cap layer.

[0072] Example 8 is the reflective mask described in Example 1, wherein: the reflective multilayer includes Si layers and Mo layers stacked alternately, and the Mo layer of the reflective multilayer is in contact with the cap layer.

[0073] Example 9 is a method for manufacturing a reflective mask, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a covering layer on the absorber layer, and a hard mask layer on the covering layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer; patterning the covering layer and the absorber layer to form an opening by using the patterned hard mask layer; and removing the hard mask layer, wherein, after removing the hard mask layer, a portion of the intermediate layer is exposed in the opening.

[0074] Example 10 is the method of Example 9, wherein the cover layer is made of the same material as the intermediate layer.

[0075] Example 11 is the method of Example 10, wherein the intermediate layer and the capping layer include tantalum oxide.

[0076] Example 12 is the method of Example 11, wherein the hard mask layer includes CrO or CrON.

[0077] Example 13 is the method of Example 12, wherein the absorber layer is made of TaBN.

[0078] Example 14 is the method of Example 13, wherein the capping layer is made of Ru.

[0079] Example 15 is the method of Example 9, wherein the thickness of the intermediate layer is in the range of 0.5 nm to 3 nm.

[0080] Example 16 is a method for manufacturing a reflective mask, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer arranged on the substrate, a cap layer arranged on the reflective multilayer, an intermediate layer arranged on the cap layer, an absorber layer arranged on the intermediate layer, a covering layer arranged on the absorber layer, and a hard mask layer arranged on the covering layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer as a mask; patterning the covering layer and the absorber layer by using the patterned hard mask layer as a mask to form an opening; and removing the hard mask layer, wherein: the reflective multilayer comprises alternately stacked Si layers and Mo layers, and the uppermost Si layer of the reflective multilayer is separated from the cap layer.

[0081] Example 17 is the method of Example 16, wherein after removing the hard mask layer, a portion of the intermediate layer is exposed in the opening.

[0082] Example 18 is the method of Example 16, wherein at least one of the intermediate layer and the capping layer includes tantalum oxide.

[0083] Example 19 is the method of Example 16, wherein a silicon compound layer is inserted between the reflective multilayer and the cap layer.

[0084] Example 20 is the method of Example 19, wherein the silicon compound layer includes one or more of SiON or SiN.

Claims

1. A reflective mask, comprising: substrate; a reflective multilayer disposed on the substrate; A cap layer, disposed on the reflective multilayer; An intermediate layer, disposed on the cap layer; an absorbent layer disposed on the intermediate layer; as well as a cover layer disposed on the absorbent layer, wherein the intermediate layer comprises a material having a lower hydrogen diffusion rate than the material of the cap layer; and Wherein, the reflective mask further comprises: an opening pattern formed in the cover layer and the absorber layer, wherein the intermediate layer is exposed at the bottom of the opening pattern.

2. The reflective mask according to claim 1, wherein: The intermediate layer includes tantalum oxide.

3. The reflective mask according to claim 1, wherein: The thickness of the intermediate layer is in the range of 0.5 nm to 3 nm.

4. The reflective mask according to claim 1, wherein: The cover layer is made of the same material as the intermediate layer.

5. The reflective mask according to claim 4, wherein: The intermediate layer and the capping layer include tantalum oxide.

6. The reflective mask according to claim 1, wherein: The reflective multilayer comprises Si layers and Mo layers stacked alternately, and The Si layer of the reflective multilayer is in contact with the cap layer.

7. The reflective mask according to claim 1, wherein: The reflective multilayer comprises Si layers and Mo layers stacked alternately, and The Mo layer of the reflective multilayer is in contact with the cap layer.

8. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an intermediate layer on the capping layer, an absorber layer on the intermediate layer, a capping layer on the absorber layer, and a hard mask layer on the capping layer; patterning the photoresist layer; patterning the hard mask layer by using a patterned photoresist layer; patterning the cap layer and the absorber layer to form openings by using a patterned hard mask layer; as well as removing the hard mask layer, wherein, after removing the hard mask layer, a portion of the intermediate layer is exposed in the opening; and The intermediate layer includes a material having a lower hydrogen diffusion rate than that of the cap layer.

9. The method according to claim 8, wherein: The cover layer is made of the same material as the intermediate layer.

10. The method according to claim 9, wherein: The intermediate layer and the capping layer include tantalum oxide.

11. The method according to claim 10, wherein: The hard mask layer includes CrO or CrON.

12. The method according to claim 11, wherein: The absorber layer is made of TaBN.

13. The method according to claim 12, wherein: The capping layer is made of Ru.

14. The method according to claim 8, wherein: The thickness of the intermediate layer is in the range of 0.5 nm to 3 nm.

15. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer disposed over the substrate, a cap layer disposed over the reflective multilayer, an intermediate layer disposed over the cap layer, an absorber layer disposed over the intermediate layer, a cap layer disposed over the absorber layer, and a hard mask layer disposed over the cap layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer as a mask; patterning the capping layer and the absorber layer by using the patterned hard mask layer as a mask to form an opening; as well as removing the hard mask layer, wherein: The reflective multilayer comprises Si layers and Mo layers stacked alternately, The uppermost Si layer of the reflective multilayer is separated from the cap layer, After removing the hard mask layer, a portion of the intermediate layer is exposed in the opening, and The intermediate layer includes a material having a lower hydrogen diffusion rate than a material of the cap layer.

16. The method according to claim 15, wherein: At least one of the intermediate layer and the capping layer includes tantalum oxide.

17. The method according to claim 15, wherein: A silicon compound layer is interposed between the reflective multilayer and the cap layer.

18. The method according to claim 17, wherein: The silicon compound layer includes one or more of SiON and SiN.

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