Device, System and Method for Error Correction

Abstract

The present invention relates to an apparatus, system, and method for error correction. A memory device may have a plurality of memory cells, each storing an information bit. A first latch may hold an encoded bit and provide it as a write parity bit to a memory array as part of a write operation. A second latch may hold a parity bit read from the memory array, and an ECC circuit may generate a command signal based on the parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate whether there is a mismatch between the parity bit and the encoded bit. Logic for handling generation of the syndrome bit may be separated from a logic tree.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly, to apparatuses, systems, and methods for error correction. Background Art

[0002] The present invention generally relates to semiconductor devices, such as semiconductor memory devices. A semiconductor memory device may include a number of memory cells for storing information. The stored information may be encoded as binary data, and each memory cell may store a single bit of the information. The information in the memory cells may decay or change due to various different errors, which may result in one or more incorrect information bits (e.g., a bit having a state different from the state in which the bit was originally written) being read out from the memory device.

[0003] In many applications, it is useful to ensure a high fidelity of the information read from the memory. The memory device may include an error correction circuit, which may be used to determine whether any errors are present in the information read from the memory cells as compared to the data written into the memory cells, and may correct the detected errors. Summary of the Invention

[0004] One aspect of the present invention provides an apparatus, where the apparatus includes: a logic tree configured to receive a plurality of data bits and provide an encoded bit based on the plurality of data bits; a read path configured to receive a parity bit and a timing signal from a memory array as part of a read operation and provide a selection signal based on the parity bit when the timing signal is valid; and a multiplexer latch configured to receive the encoded bit and provide a syndrome bit in a state same as or opposite to the state of the encoded bit based on the selection signal.

[0005] Another aspect of the present invention provides an apparatus, where the apparatus includes: a logic tree configured to receive a plurality of data bits and provide an encoded bit based on the plurality of data bits; a first latch configured to receive the encoded bit and provide it as a parity bit for storage in a memory array as part of a write operation; a second latch configured to receive the parity bit from the memory array and store the parity bit in response to a timing signal at an invalid level, where a selection signal is provided based on the stored parity bit when the timing signal is at a valid level; and a multiplexer latch configured to store the encoded bit and provide a syndrome bit based on the stored encoded bit and the selection signal as part of a read operation.

[0006] Another aspect of the present invention provides an apparatus, wherein the apparatus comprises: a memory array configured to store data bits and parity bits; and an error correction code (ECC) circuit configured to receive the data bits and the parity bits as part of a read operation, wherein the ECC circuit comprises: a logic tree configured to receive the data bits and generate encoded bits based on the data bits; a read path configured to store the parity bits in response to a timing signal in an invalid state and provide a selection signal in response to the timing signal in a valid state, wherein the ECC circuit is configured to provide syndrome bits based on the encoded bits and the selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

[0008] Figure 2 is a block diagram of a memory device according to some embodiments of the present invention.

[0009] Figure 3 is a schematic diagram of an error correction code (ECC) control circuit according to some embodiments of the present invention.

[0010] Figures 4A to 4C is a schematic diagram of a logic tree according to some embodiments of the present invention.

[0011] Figure 5 is a schematic diagram of an encoder / syndrome generator circuit according to some embodiments of the present invention.

[0012] Figure 6 is a timing diagram of read and write operations in a syndrome / encoder generator circuit according to some embodiments of the present invention. DETAILED DESCRIPTION

[0013] The following description of specific embodiments is merely exemplary in nature and is in no way intended to limit the scope of the invention or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings which form a part hereof and in which are shown, by way of illustration, specific embodiments in which the described system and method may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the invention. Additionally, for the sake of clarity, when the detailed description of a particular feature is obvious to those skilled in the art, that feature will not be described so as not to obscure the description of the embodiments of the invention. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the invention is defined only by the appended claims.

[0014] A memory device may include a memory array having a plurality of memory cells each positioned at an intersection of a word line (row) and a digit line (column). During a read or write operation, a row may be activated, and data may be read from or written to the memory cells along the activated row. Each row may include memory cells storing a plurality of data bits and a plurality of parity information bits (e.g., data bits and parity bits) that can be used to correct a particular number of errors in the data bits. For example, a row may include i data bits and k parity bits that can be used to correct up to j data bits. During a write operation, the parity bits may be generated by an error correction code circuit based on the data written to the memory cells of the row. During a read operation, the error correction code circuit may use the parity bits to determine whether the read data bits are correct and may correct any errors found.

[0015] An error correction code (ECC) circuit may be used to generate parity bits based on data written during a write operation and to compare read data with read parity bits to locate errors. As part of a read operation, the ECC circuit may generate new parity bits based on the read data in a manner similar to generating parity bits. The ECC circuit may then compare the new parity bits with the read parity bits in order to locate any errors. The process of generating the original parity bits for storage in the memory array and the new parity bits for comparison with the stored parity bits may generally be similar, and the ECC may use shared circuit components for both operations. For example, the ECC circuit may include a logic tree, such as a tree of XOR gates, that can be used to combine a set of written data or read data into parity bits or new parity bits. When the logic tree is shared, it can be used as part of a write operation to generate encoded bits that can be used as write parity bits (and / or for generating write parity bits), and it can also be used as part of a read operation to generate encoded bits that can be used with the read parity bits to determine whether any errors exist (e.g., the difference between the encoded bits and the read parity bits). Although sharing logic (such as a logic tree) can be useful for reducing the layout area or power consumption of the ECC circuit, it may be difficult to manage the timing of the ECC circuit operation when sharing components.

[0016] The present invention relates to an apparatus, system, and method for error correction. An ECC circuit may include a shared logic tree for both write operations (to generate write parity bits) and read operations (to generate new parity bits to compare with read parity bits). The logic tree may receive data bits and generate encoded bits. The encoded bits may be provided to a read path and a write path that may be separated from each other. The write path may store the encoded bits to be used as write parity bits. The read path may receive a read parity bit and compare the read parity bit with the encoded bits to generate a syndrome bit, which may indicate whether an error exists in the read data. The read parity bit may be received separately from the logic tree and the write path (e.g., the read parity bit may be received 'downstream' of the logic tree). Since the read parity bit is decoupled from the logic tree (and since the read path and the write path are decoupled from each other), the generation of the encoded bits may be separated from receiving the parity bit and comparing it with the encoded bits.

[0017] For example, the read path of an ECC circuit may include a timing signal that may be active to indicate that a syndrome bit should be provided. When the timing signal is active, the read parity data stored in a latch may be compared with the encoded bits. As part of read and write operations, the logic tree may receive read and write data. However, the latch that holds the read parity bit is not part of the write operation. Thus, the latch may hold the read parity bit for a desired duration and may not need to dump the held read parity bit when the operation switches to a subsequent write operation. This may increase the timing margin of the circuit because the data may be in the latch for all times (or a longer portion of the times) when the timing signal is active.

[0018] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0019] The semiconductor device 100 includes a memory array 118. The memory array 118 may be shown as including a plurality of banks. In Figure 1 the embodiment, the memory array 118 is shown as including eight banks BANK0 to BANK7. More or fewer banks may be included in the memory array 118 of other embodiments. Each bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In Figure 1In an embodiment, the row decoder 108 includes a corresponding row decoder for each bank, and the column decoder 110 includes a corresponding column decoder for each bank. The bit lines BL are coupled to corresponding sense amplifiers (SAMP). Data read from the bit lines BL is amplified by the sense amplifiers SAMP and transmitted to the read / write amplifier through complementary local input / output lines (LIOT / B), transfer gates (TG), and complementary main input / output lines (MIOT / B) coupled to the error correction code (ECC) control circuit 120. Conversely, write data output from the ECC control circuit 120 is transmitted to the sense amplifiers SAMP through the complementary main input / output lines MIOT / B, transfer gates TG, and complementary local input / output lines LIOT / B, and is written into the memory cells MC coupled to the bit lines BL.

[0020] The semiconductor device 100 may employ a plurality of external terminals, which include command and address (C / A) terminals coupled to command and address buses to receive commands and addresses, clock terminals for receiving clocks CK and / CK, data terminals DQ for providing data, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0021] The clock terminals are supplied with external clocks CK and / CK provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of circuits included in the input / output circuit 122, e.g., provided to the data receiver to time the reception of write data.

[0022] The C / A terminals may be supplied with memory addresses. The memory addresses supplied to the C / A terminals are transmitted to the address decoder 104 through the command / address input circuit 102. The address decoder 104 receives the addresses and supplies the decoded row address XADD to the row decoder 108, and supplies the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply the decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD. The C / A terminals may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The access commands may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0023] Commands can be provided as internal command signals to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide a row command signal for selecting word lines and a column command signal for selecting bit lines.

[0024] The semiconductor device 100 can receive an access command as a read command. When the read command is received and the bank address, row address, and column address are supplied in a timely manner together with the read command, read data is read from the memory cells in the memory array 118 corresponding to the row address and column address. The read command is received by the command decoder 106, which provides internal commands such that the data read from the memory array 118 is provided to the ECC control circuit 120. The read command can also cause one or more parity bits associated with the read data to be provided to the ECC control circuit 120 along the MIOT / B. The ECC control circuit 120 can use the parity bits to determine whether the read data contains any errors, and if any errors are detected, the errors can be corrected to generate corrected read data. The corrected read data is output from the data terminal DQ to the outside of the semiconductor device 100 via the input / output circuit 122.

[0025] The semiconductor device 100 can receive an access command as a write command. When the write command is received and the bank address, row address, and column address are supplied in a timely manner together with the write command, write data is supplied to the ECC control circuit 120 through the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cells in the memory array 118 corresponding to the row address and column address. The write command is received by the command decoder 106, which provides internal commands such that the write data is received by the data receiver in the input / output circuit 122. A write clock can also be provided to the external clock terminal for timing the reception of the write data by the data receiver in the input / output circuit 122. The write data is supplied to the ECC control circuit 120 via the input / output circuit 122. The ECC control circuit 120 can generate several parity bits based on the write data, and the write data and the parity bits can be provided to the memory array 118 to be written to the memory cells MC.

[0026] The ECC control circuit 120 can be used to ensure the fidelity of data read from a particular group of memory cells and data written to the memory cells of that group. The semiconductor device 100 can include several different ECC control circuits 120, each of which is responsible for a different portion of the memory cells MC of the memory array 118. For example, there can be one or more ECC control circuits 120 for each bank of the memory array 118.

[0027] Each ECC control circuit 120 can include specific components shared between the read path and the write path and specific components not shared. For example, each ECC circuit can include a logic tree, which can be a group of logic circuits coupled together to receive a first number of data bits and provide a second number of encoded bits, where the number of encoded bits is less than the number of data bits, and the state of the encoded bits is based on the state of the data bits. The logic tree can be shared between the read path and the write path. Because it is shared, the logic tree may need to switch between receiving read data and write data and may need to change specific control signals and values (e.g., values stored in latches). The portion of the read path that receives the read parity bits is not shared and may not need to change signals / values when the ECC control circuit 120 switches between a write operation and a read operation. This can help increase the timing margin of the read operation.

[0028] Each ECC control circuit 120 can receive a specific number of data bits (from the IO circuit 122 or the memory array 118) and can use several parity bits to correct potential errors in the data bits based on the number of data bits. For example, as part of a write operation, the ECC control circuit 120 can receive 128 data bits from the IO circuit 122 and can generate 8 parity bits based on those 128 data bits. The 128 data bits and 8 parity bits (e.g., a total of 136 bits) can be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 can receive 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 can use the 8 parity bits to determine if there are any errors in the 128 read data bits, and if any errors are found, it can correct the errors. For example, the ECC control circuit 120 may be able to locate and correct up to one error in the 128 data bits based on the 8 parity bits. Although various embodiments may be discussed with reference to an ECC circuit that uses 8 parity bits to find one error in 128 data bits, it should be understood that these are for illustrative purposes only, and in other example embodiments, other numbers of data bits, error bits, and parity bits may be used. Example ECC circuits are discussed in Figure 3 in more detail.

[0029] The semiconductor device 100 may also receive a command that causes it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be externally issued to the semiconductor device 100. In some embodiments, the self-refresh mode command may be periodically generated by components of the device. In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal AREF may also be activated. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated once immediately after the command input and may thereafter be activated cyclically at a desired internal timing. The refresh signal AREF may be used to control the timing of the refresh operation during the self-refresh mode. Thus, the refresh operation may continue automatically. A self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to an idle state. The refresh signal AREF is supplied to the refresh control circuit 116. The refresh control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which may refresh one or more word lines WL indicated by the refresh row address RXADD.

[0030] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many other peripheral circuit blocks.

[0031] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present invention, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present invention, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 such that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0032] Figure 2is a block diagram of a memory device according to some embodiments of the present invention. Memory device 200 shows an example layout of specific components that serve as part of the access operations in memory device 200. For clarity, other components may be omitted. In some embodiments, memory device 200 may be included in Figure 1 semiconductor device 100.

[0033] Memory device 200 includes a plurality of banks 240, which are part of a memory array. Banks 240 may be divided into a first part 240a of the banks and a second part 240b of the banks, with a row decoder 208 positioned between the sections. Two sections of a given bank 240 and row decoder 208 may be arranged along a first direction (e.g., the y-axis). Each bank 240 may be separated from another bank by a column decoder 210 associated with the first bank, an error correction region 220, and a column decoder 210 associated with the second bank. The banks, column decoders 210, and error correction regions 220 may be laid out along a second axis (e.g., the x-axis) orthogonal to the first axis. The banks of memory device 200 may be arranged in an array along the x-y plane.

[0034] An error correction region 220 and a column decoder 210 may exist for each part of a given bank 240. Error correction region 220 may be coupled to one or more DQ pads 226 (e.g., via an I / O circuit) to transmit and receive data external to device 200. DQ pads 226 (and I / O circuits, etc.) may be located in the PERIDQ region between banks 240, and other components of memory device 200 (e.g., command address input circuitry) may be located in the PERICA region between banks 240.

[0035] ECC region 220 includes one or more ECC control circuits for correcting data bits stored in bank 240 associated with that ECC region 220. For example, each ECC region 220 may include an ECC control circuit that manages a portion of the bank on either side of that ECC region 220. For example, a first ECC region 220 may be associated with part 240a, and a second ECC region 220 may be associated with part 240b. In some embodiments, ECC region 220 may include an ECC control circuit that corrects data in either of the memories depending on which of the banks associated with that ECC region 220 is valid. In some embodiments, ECC region 220 may be extended (e.g., in the y direction) and may include one or more ECC control circuits that may manage two parts of the bank (e.g., 240a and 240b).

[0036] Figure 3Schematic diagram of an error correction code (ECC) control circuit according to some embodiments of the present invention. In some embodiments, Figure 3 the ECC control circuit 300 may be included in Figure 1 the ECC control circuit 120 and / or Figure 2 220 of. As part of a write operation, the ECC control circuit 300 may receive write data bits WD and may generate write parity bits WP. These may be provided to the memory array as data bits D and parity bits P and may be stored in the memory array for later retrieval. As part of a read operation, the ECC control circuit 300 may receive data D as read data RD from the memory array and receive parity bit P as read parity bit PR and may generate corrected data bits CRD based on bits RD and PR. The corrected data bits CRD may then be provided to an I / O circuit (such as Figure 1 122 of) and read out from the device.

[0037] During an example read operation, a sense amplifier 301 is activated to amplify the read parity bit PR and the read data RD. The amplified bits PR and RD are provided to an encoder / syndrome generator circuit 315. The encoder / syndrome generator circuit 315 provides a syndrome bit S based on the read bits RD and PR. In some embodiments, several syndrome bits S may match several parity bits PR. The syndrome bit S is provided to an error locator circuit 330.

[0038] The error locator circuit 330 provides a first set of error determination signals EBST and a second set of error determination bits EDQ based in part on the syndrome bit S. In some embodiments, the data provided to the DQ terminals / received at the DQ terminals may be organized into bursts on several different DQ terminals (e.g., a burst of 8 bits on each of 16 different DQ terminals for a total of 128 bits). The first set of error determination signals EBST may indicate the location of the error bits within the burst. In some embodiments, there may be one bit for each bit in the burst, and the signal EBST may be provided to the DQ terminals jointly. The second set of error determination signals EDQ may indicate which terminal of the DQ terminals the error bit is being provided to. In some embodiments, there may be one bit for each DQ terminal, and the signal EDQ may be provided to the burst bits jointly.

[0039] The error determination signals EBST and EDQ may be provided to a second error locator circuit 340. The second error locator circuit 340 may decode the signals EBST and EDQ to identify the location of the error bits in the read data RD. The location of the error bits may be specified by an error location signal EL. In some embodiments, based on the number of bits of the read data RD, there may be several bits of the error location signal EL, where each bit of the error location signal EL is associated with a bit of the read data RD.

[0040] An error location signal EL is provided to an error corrector circuit 350. The error corrector circuit 350 also receives read data RD and corrects one or more error bits in RD based on the error location signal EL. For example, if the nth bit of the error location signal EL is at a high logic level, then the error corrector circuit 350 may change the state of the nth read bit RD. The error corrector circuit 350 may provide corrected read data CRD. The corrected read data CRD may be provided to the DQ pads and read out from the device.

[0041] In an example write operation to the memory device, the ECC control circuit 300 may receive write data WD and a data mask signal DM. A first multiplexer 303 may synthesize the write data WD and the corrected read data CRD based on the data mask signal DM. The first multiplexer 303 may provide data D to a write amplifier 302, which may provide amplified data D to the memory array. In some embodiments, the data mask signal DM may be associated with different burst bits received at the data terminals. When one (or more) of the data mask bits DM is active, then the write data WD associated with that data mask bit may be replaced by the corrected read data CRD in the data D.

[0042] A second multiplexer 304 may synthesize the write data WD and the read data RD based on the data mask signal. The second multiplexer 304 may provide parity write data PWD. The parity write data PWD may be provided to an encoder / syndrome generator circuit 315, which may encode the parity write data PWD into a write parity WP'. The write parity WP' is provided to a converter circuit 305 that generates a write parity WP, and the write parity WP is written to the memory array as a parity bit P.

[0043] The converter circuit 305 includes an XOR logic gate 305a and a third multiplexer 305b. The XOR logic gate 305a has input terminals coupled to a syndrome bit S and a write parity bit WP'. The XOR logic gate 305a provides an output that is at a high logic level when the syndrome bit S is different from the associated write parity bit WP'. The third multiplexer 305b provides the output of the XOR logic gate 305a or the write parity WP' as the write parity WP. The third multiplexer 305b selects the source of the write parity WP bit based on a conversion signal EDM. When the conversion signal EDM is active, the write parity WP is the output of the XOR gate 305a. When the conversion signal EDM is inactive, the signal WP' is provided as the signal WP.

[0044] The masked error detector circuit 360 provides a signal EDM based on the syndrome bit S and the data mask DM. The masked error detector circuit 360 can determine whether the burst data to which the error bit belongs is consistent with the burst data masked by the data mask signal DM. If they are consistent, then the signal EDM can be activated. If they are inconsistent, then the signal EDM can remain inactive.

[0045] The encoder / syndrome generator circuit 315 includes a logic tree 316 that receives read data RD (as part of a read operation) or parity write data PWD. The logic tree 316 can encode the received data into one or more encoded bits ENC. Both the read data RD and the parity write data PWD can have a number of bits. In some embodiments, the read data RD and the parity write data PWD can have the same number of bits. The number of bits of RD and PWD can be based on the memory read / write word length. For example, the read data RD and the parity write data PWD can each include 128 bits. The encoded bits can include a number of bits. In some embodiments, the number of encoded bits ENC can generally be less than the number of input data bits (e.g., PWD or RD). For example, if the input data PWD or RD includes 128 bits, then there can be 16 encoded bits. Thus, the input data PWD or RD can be organized into sets, where each is associated with a single encoded bit ENC. For example, 128 bits of input data can be organized into 8 sets of 16 bits each, where each is associated with one encoded bit ENC. The logic tree 316 is discussed in more detail in FIG. 4.

[0046] The encoded bits ENC are provided to both the read path 317 and the write path 318. The write path 318 can generally store the encoded bits ENC and provide them as write parity bits WP'. The write parity bits WP' can be used to generate write parity bits WP that can then be stored in the memory. The read path 317 can receive the encoded bits ENC from the logic tree 316 and can also receive read parity bits PR. The read path 317 can store the read parity bits PR and then can compare them with the encoded bits ENC. Since the read parity bits PR can represent a set of previously encoded bits associated with the data when the data was written to the memory. When the data and the parity bits are read from the memory and the read data RD is fed through the logic tree 316 again, the encoded bits ENC should generally match the read parity bits PR (e.g., assuming no errors). Thus, the read path 317 can include logic that compares the read parity bits PR with the encoded bits ENC and can generate a syndrome bit S based on the comparison.

[0047] Although for clarity in Figure 3Although not shown in the figure, various components can be activated by one or more timing and control signals, which can help indicate whether a write operation or a read operation is being performed. For example, the encoder / syndrome generator circuit 315 can receive a write status signal that can be at a first level if a write operation is being performed and at a second level if a read operation is being performed. The components of the ECC control circuit 300 can also receive various timing signals that can be provided in sequence to various components to trigger the activation of the various components in the appropriate order to ensure that the write and read operations are properly performed.

[0048] Figures 4A to 4C is a schematic diagram of a logic tree according to some embodiments of the present invention. Figure 4A Displays a diagram 400 depicting a specific logic arrangement for generating encoded bits. Figure 4B and 4C Displays logic circuits 401 and 410 of a logic tree that can be used to implement all or part of diagram 400. In some embodiments, the logic circuits 401 and 410 can be included in Figure 3 the logic tree 316. It should be understood that other logic arrangements and logic trees can be used in other example embodiments.

[0049] The logic diagram 400 and the logic circuits 401 and 410 can represent a part of a logic tree that is part of a write operation for generating a write parity (e.g., Figure 3 WP’). In some embodiments, the logic circuits 401 and 410 can also be used to generate syndrome bits during a read operation. In some embodiments, a part of the logic circuits 401 and 410 can be shared between the read operation and the write operation, while another part of the logic circuits 401 and 410 is not shared.

[0050] Diagram 400 shows write bits arranged in columns along the left side. Each row represents one of the write bits WD provided on the data terminal DQ. The write bits WD are arranged to correspond to the data terminal DQ and the bits received as a burst on that data terminal. In the Figures 4A to 4C embodiment shown, there can be 8 data terminals, each of which can receive a burst of 8 bits. In other embodiments, other numbers of terminals and bits are possible. The columns SH0 to SH7 of diagram 400 show different syndromes that can be used as an encoding of the data bits to generate parity bits. The columns arranged in the first determinant H1 are associated with the logic circuit 401, while the columns arranged in the second determinant H2 are associated with the logic circuit 410.

[0051] The logic circuit 401 includes a first logic circuit block 402 and a second logic circuit block 403. Blocks 402 and 403 receive write data bits WD indicated by '1' in the first column SHO of the diagram 400. The write data bits are grouped together in groups of four (e.g., WD1, WD3, WD5, and WD7) and are provided to four input terminals of an exclusive-OR (XOR) gate. The XOR gate provides an output based on the four inputs. Four such XOR gates (e.g., coupled to 16 WD bits) each provide an output to an XOR gate in a third block 404. The second block 403 is similar to the first block 402 and has four XOR gates coupled to 16 write data WD bits and provides four outputs to the inputs of an XOR gate in the third block 404. The third block 404 includes two four-input XOR gates coupled to the four outputs of the first block 402 and the four outputs of the second block 403, respectively. These two XOR gates in turn provide outputs that are XORed together to produce a write parity bit WP'0, which corresponds to the connection of column SH0 of the diagram 400. Similar logic to the logic circuit 401 can be used to generate parity bits WP'1 and WP'2 for the next two columns SH1 and SH2 of the diagram 400.

[0052] The logic circuit 410 shows an example logic circuit that can be used to generate parity bits WP'3 to WP'7 associated with columns SH3 to SH7 of the diagram 400. In the logic circuit 401, there are a set number of inputs (e.g., 32 bits) that are valid (e.g., marked with a 1) in each column of the diagram 400. However, in the logic circuit 410, there can be a different number of inputs in different columns. The logic circuit 410 includes a first block 411 that includes a number of XOR gates coupled to different input bits WD indicated by the diagram 400. The outputs of the XOR gates in the first block 411 are in turn provided as inputs to XOR gates 412. Each of the XOR gates 412 provides one of the write parity bits WP'.

[0053] Figure 5 is a schematic diagram of an encoder / syndrome generator circuit according to some embodiments of the present invention. In some embodiments, the encoder / syndrome generator circuit 500 can be included in Figure 3 the encoder / syndrome generator circuit 315. The encoder / syndrome generator circuit 500 can have components that function in a manner similar to an encoder circuit and components that function in a manner similar to a syndrome generator.

[0054] Figure 5The encoder / syndrome generator circuit 500 can represent the circuitry and logic for the data value of a single parity bit. For example, the encoder / syndrome generator circuit 500 can receive 16 data bits and generate a single parity bit based on those 16 data bits. Thus, the encoder / syndrome generator circuit 500 can represent a part of the overall encoder / syndrome generator circuit 500, and the encoder / syndrome generator circuit 500 can be replicated to handle increased data bus widths. For example, if 16 data bits are associated with one parity bit and the data bus contains 128 bits, then the encoder / syndrome generator circuit 500 can be replicated 8 times. In other instances, other numbers of data bits and parity bits and other numbers of replications of the encoder / syndrome generator circuit 500 can be used.

[0055] The encoder / syndrome generator circuit 500 includes a logic tree 501 that receives read data (e.g., RD) or write data (e.g., PWD) and provides an encoded bit poutp00 based on the received data. The logic tree 501 can be a tree of XOR logic gates that can be coupled together in different patterns to generate the encoded bit (e.g., similar to the logic diagram 400 of FIG. 4). The encoded bit poutp00 (e.g., which can be one of the encoded bits ENC of Figure 3 ) can represent the encoded information based on the received data RD / PWD.

[0056] The encoded bit poutp00 is provided to a first latch 502 that stores the value of the encoded bit poutp00. In some embodiments, the first latch 502 can be included in Figure 3 the write path 318. The first latch 502 provides a write parity bit WP having the value of the encoded bit poutp00. Thus, in an example write operation, the logic tree 501 can receive write data (WD) and generate an encoded bit poutp00 that can be saved in the first latch 502 and provided as the write parity bit WP. Then, the write data WD and the associated WP bit can be written to the memory array. The write parity bit WP provided by the first latch 502 can be Figure 3 the write parity bit WP’ of

[0057] The encoder / syndrome generator circuit 500 can also be used as a syndrome generator circuit as part of a read operation. The logic tree 501 can receive read data (e.g., RD) and provide an encoded bit poutp00. The encoded bit poutp00 can be saved in a second latch 503. In some embodiments, the second latch 503, logic gates 506 and 507, and multiplexer latch 505 can be included in, for example Figure 3in the read path 317 of the read path. In some embodiments, the logic tree 501 can be reconfigured when used as part of read and write operations. For example, the read data RD can be coupled through a first sequence of logic gates of the logic tree 501, and the write data PWD can be coupled through a second sequence of logic gates of the logic tree 501. In some embodiments, some of the individual logic gates can be shared between the first sequence and the second sequence.

[0058] In some embodiments, the second latch 503 can be coupled to a control signal such as the write state signal Write State, which can be used to determine whether the second latch 503 should be active (e.g., store the value poutp00). For example, the signal Write State can be at an active level when a write operation is being performed and can be at an inactive level when no write operation is being performed. The second latch 503 can have an inverted enable terminal (e.g., an inverted clock terminal) coupled to the signal Write State that activates the second latch 503 when the signal Write State is inactive. The second latch 503 can provide the stored encoded bit poutp00 as the encoded bit zpout.

[0059] The multiplexer latch 505 can store the encoded bit zpout and can store the inversion of the encoded bit zpout provided by the second latch 503 (e.g., zpoutF). The multiplexer latch 505 can provide the encoded bit zpout or the inverted zpoutF as the syndrome bit S based on the timing signal syn0CapD and the state of the read parity bit PR. Two bit selection signals syn0CapD’ are preferably provided based on the state of the read parity bit PR when the timing signal syn0CapD is active. The multiplexer latch 505 provides the syndrome bit S based on the encoded bit zpout and the state of syn0CapD’ when syn0CapD’ is provided.

[0060] The latch circuit 504 may store the value of the read parity bit PR in response to the state of the timing signal syn0CapD. The timing signal syn0CapD may be coupled to the inverted clock terminal of the latch 504. Thus, when the timing signal syn0CapD is inactive (e.g., at a low logic level), the read parity bit PR may be stored in the latch 504. The latch may provide the saved value of the read parity bit PR to the input terminal of the AND gate 507. The other input terminal of the AND gate 507 may be coupled to the timing signal syn0CapD. The latch 504 also provides the inversion of the stored bit to the input terminal of the AND gate 506, which has another input terminal coupled to the timing signal syn0CapD. Thus, the output of the gate 506 may be at a high logic level when the timing signal syn0CapD is at a high logic level and the stored parity bit PR is at a low logic level (e.g., because the AND gate 506 receives the inversion of the stored parity bit PR). The output of the gate 507 may be at a high logic level when the timing signal syn0CapD is at a high logic level and the parity bit PR stored in the latch is at a high logic level. The outputs of the AND gates 506 and 507 may be the select signal syn0CapD’.

[0061] The multiplexer latch 505 can provide a syndrome bit based on the stored bit zpout (and its inverse) and the state of the select signal syn0CapD’. The select signal syn0CapD’ can have a first bit that is the output of the AND gate 506 and a second bit that is the output of the AND gate 507. Since both AND gates depend on the state of the bits stored in the latch 504, only one of the two bits of the signal syn0CapD’ can be valid (e.g., high) at a given time. When the first bit of the signal syn0CapD’ (e.g., the output of the AND gate 506) is at a high logic level (e.g., indicating that the stored read parity PR is at a low logic level), the multiplexer latch 505 can provide a syndrome bit S at a low logic level if the stored bit zpout is at a low logic level, and can provide a syndrome bit S at a high logic level if the stored bit zpout is at a high logic level. When the second bit of the signal syn0CapD’ (e.g., the output of the AND gate 507) is at a high logic level (e.g., indicating that the stored read parity PR is at a high logic level), the multiplexer latch 505 can provide a syndrome bit S at a low logic level if the stored bit zpout is at a high logic level, and can provide a syndrome bit S at a high logic level if the stored bit zpout is at a low logic level. In this way, the multiplexer latch 505 can act in a manner similar to an “exclusive OR” (XOR) logic gate, and the syndrome bit S can be at a low logic level when the bits PR and zpout have the same state, and can be at a high logic level when the bits PR and zoupt do not match.

[0062] Figure 6 is a timing diagram of read and write operations in a syndrome / encoder generator circuit according to some embodiments of the present invention. In some embodiments, the timing diagram 600 can represent Figure 3 the encoder / syndrome generator circuit 315 of Figure 5 and / or the operation of the encoder / syndrome generator circuit 500 of

[0063] The first trace of the timing diagram 600 represents in the logic tree (e.g., Figure 3 316 of Figure 5The read or write data received at, for example, 501). For example, when the read / write data is marked W, it may represent the write data PWD, and when it is marked R, it may represent the read data RD. The second trace represents the encoded bits (e.g., poutp00) provided by the logic tree. At an initial time t0, the memory may switch from a write operation to a read operation. As can be noted from the timing diagram, there is a slight delay after the start of the read operation (and the read / write data switches to the read data R) before the value of poutp00 switches to the read output R. This delay may account for the time it takes for the logic tree to generate and provide the encoded bits from the read data RD.

[0064] The third trace of the timing diagram 600 represents the parity bit P read from or written to the memory. When the trace indicates W, the parity trace may represent the write parity WP. When the trace indicates R, the parity trace may represent the read parity PR. At time t0, the read parity may switch to the R state to indicate that the parity bit is the read parity PR. Since the data (e.g., the read data RD) and the parity are read out of the memory array together, the data and the parity typically may switch to the read information at approximately the same time (e.g., at the initial time t0).

[0065] The fourth trace represents the timing signal syn0CapD. At time t0 (and before this), the timing signal syn0CapD may be at an inactive level (e.g., because no read operation is being performed). At a time t1 after time t0, the timing signal syn0CapD may switch to an active level (e.g., switch to a high logic level) to activate the circuitry of the read path.

[0066] The fifth trace represents the signal Write State, which is at an inactive level between time t0 and t1 (because no write operation is being performed). The signal Write State may rise to an active level after time t1 (but before time t2) to ready the encoder / syndrome generator circuitry for a subsequent write operation, which starts after time t2.

[0067] The sixth trace represents the value zpout, which is the encoded value poutp00 after it has been saved in a latch (e.g., Figure 5 the second latch 503) along the read path. The value of zpout may switch to the read state R between time t0 and t1 (e.g., approximately at the time when the value of poutp00 switches to the read state R). Even after the value of poutp00 switches to the write state W (e.g., after time t2), the value of zpout may still continue to be in the read state because the value of the signal Write State rises to an active level, which prevents the latch holding zpout from latching a new value.

[0068] The seventh trace represents a signal syn0CapD’ provided along the read path to assist in determining the state of the output syndrome bit S. The signal syn0CapD’ transitions from inactive to active at time t1 (e.g., at approximately the same time as the signal syn0CapD becomes valid) and returns to inactive between times t1 and t2 (e.g., at approximately the same time as syn0CapD becomes inactive). The last trace represents the state of the syndrome bit S, which switches to a valid output value (e.g., the R state) after time t1 (but before time t2).

[0069] Timing diagram 600 shows a bar labeled 'hold' which may represent the time during which various latches are storing valid read data (e.g., in the R state) and the timing signal syn0CapD can be used to cause the circuit to provide a valid syndrome bit S. The hold time can extend from slightly before time t1 (e.g., from approximately the time when poutp00 switches to the R state) to just after time t2 (e.g., from approximately the time when the parity bit P stops having a valid state R to switch to the write state W). Since the parity bit is held in a path separate from the write state, the stored value of the parity bit can remain valid even when the signal WriteState is activated, which can allow the hold time to increase.

[0070] Of course, it should be understood that any one of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or performed among separate devices or device parts in accordance with the present system, apparatus, and method.

[0071] Ultimately, the foregoing discussion is intended only to illustrate the system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the system has been described in specific detail with reference to exemplary embodiments, it should also be understood that those of ordinary skill in the art may envision numerous modifications or alternative embodiments without departing from the broader and intended spirit and scope of the system as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. An apparatus for error correction, comprising: a logic tree configured to receive a plurality of data bits and provide encoded bits based on the plurality of data bits; a read path configured to receive parity bits and timing signals from a memory array as part of a read operation, and configured to provide a selection signal based on the parity bits when the timing signals are valid; and a multiplexer latch configured to receive the encoded bits and provide syndrome bits in a state the same as or opposite to the state of the encoded bits based on the selection signal.

2. The apparatus according to claim 1, further comprising a write path configured to receive the encoded bits, wherein the write path is configured to provide the encoded bits as parity bits to the memory array as part of a write operation.

3. The apparatus according to claim 1, wherein during the read operation, the plurality of data bits include a plurality of data bits read from the memory array.

4. The apparatus according to claim 1, wherein if the received parity bit is at a high logic level, the selection signal has a first state, and if the received parity bit is at a low logic level, the selection signal has a second state.

5. The apparatus according to claim 1, wherein the read path includes a latch configured to store the value of the parity bit received from the memory array in response to the timing signal being at an active level.

6. The apparatus according to claim 5, further comprising a second latch configured to store the encoded bits and provide the stored encoded bits to the multiplexer latch in response to a write status signal being inactive.

7. The apparatus according to claim 1, wherein an error in the plurality of data bits is located and corrected based on the syndrome bits.

8. An apparatus for error correction, comprising: a logic tree configured to receive a plurality of data bits and provide encoded bits based on the plurality of data bits; a first latch configured to receive the encoded bits and provide them as parity bits for storage in a memory array as part of a write operation; a second latch configured to receive the parity bits from the memory array and store the parity bits in response to the timing signal being at an inactive level, wherein a selection signal is provided based on the stored parity bits when the timing signal is at an active level; and a multiplexer latch configured to store the encoded bits and provide syndrome bits based on the stored encoded bits and the selection signal as part of a read operation.

9. The apparatus according to claim 8, further comprising a third latch configured to store the encoded bits in response to a write status signal being inactive, and wherein the third latch is configured to provide the stored parity bits to the multiplexer latch.

10. The apparatus according to claim 9, wherein the multiplexer latch is configured to store the stored encoded bits from the third latch and the inversion of the stored encoded bits, and provide either the stored encoded bits or the inversion of the stored encoded bits as the syndrome bits based on the selection signal.

11. The apparatus according to claim 8, further comprising: A first logic gate having a first input terminal coupled to the timing signal and a second input terminal coupled to the inversion of the parity bit stored in the second latch; And A second logic gate having a first input terminal coupled to the timing signal and a second input terminal coupled to the parity bit stored in the second latch, Wherein the first logic gate and the second logic gate provide the selection signal.

12. The apparatus according to claim 8, wherein the logic tree includes a plurality of logic gates, and wherein a first portion of the plurality of logic gates is used during the write operation, and wherein a second portion of the plurality of logic gates is used during the read operation.

13. The apparatus according to claim 8, wherein as part of the write operation, the plurality of data bits and the parity bit are written to the memory array, and wherein as part of the read operation, the plurality of data bits and the parity bit are read from the memory array and corrected based on the syndrome bits.

14. An apparatus for error correction, comprising: A memory array configured to store data bits and parity bits; And An error correction code (ECC) circuit configured to receive the data bits and the parity bit as part of a read operation, wherein the ECC circuit includes: A logic tree configured to receive the data bits and generate encoded bits based on the data bits; And A read path configured to store the parity bit in response to a timing signal in an invalid state and provide a selection signal in response to the timing signal in a valid state, Wherein the ECC circuit is configured to provide syndrome bits based on the encoded bits and the selection signal.

15. The apparatus according to claim 14, further comprising an input / output circuit configured to receive data bits for a write operation at a plurality of input / output terminals and provide the data bits read from the memory array to the input / output terminals as part of a read operation.

16. The apparatus according to claim 14, wherein the ECC circuit is configured to detect and correct errors in the received data bits based on the syndrome bits.

17. The apparatus according to claim 14, wherein the ECC circuit is further configured to receive data bits as part of a write operation, wherein the logic tree is configured to receive the data bits and provide encoded bits based on the data bits, and wherein the ECC circuit further includes a write path configured to provide the encoded bits as parity bits.

18. The apparatus according to claim 17, wherein the read path and the write path jointly receive the encoded bits.

19. The apparatus according to claim 14, wherein the read path is configured to store the encoded bits in response to a write status signal being in an invalid state.

20. The apparatus according to claim 19, wherein the read path includes a multiplexer latch configured to provide the syndrome bits based on the stored encoded bits and the selection signal.

Images