Semiconductor package and method of manufacturing the same

Abstract

Semiconductor packages described herein include thermal capacitors and / or recessed pad features designed to absorb transient heat pulses from a power semiconductor die and subsequently release the transient heat pulses to the surrounding environment. Corresponding production methods are also described.

Description

Background Art

[0001] Cooling capabilities are disadvantageous for SMD (surface mount device) based power electronics. However, SMD based systems offer high efficiency and are therefore widely used. Certain power SMD packaging solutions provide low thermal resistance for both the top and bottom sides of the package and instead of using bond wires or clip interconnects, solder bumps are used for source and gate connections. The drain connection is formed by a copper plated pot (lid) that is bonded to the drain side of the power semiconductor die. The pot / lid provides low thermal resistance for the top side of the package and is well suited for cooling through the top side of the package, providing a double-sided cooling solution.

[0002] However, the can / lid approach requires a relatively large gate pad size, which reduces the active area of ​​the power semiconductor device and, therefore, increases die cost and reduces overall efficiency. In addition, the can / lid solution does not easily support thin semiconductor dies (e.g., 40 μm to 60 μm thick or thinner) due to bond wire thickness issues that occur when thermal material creeps up the sidewalls of thin power semiconductor dies. Excessive creepage can cause electrical problems, which are difficult to avoid in the case of thin semiconductor dies.

[0003] Therefore, there is a need for an improved SMD-based power semiconductor package and related manufacturing method thereof. Summary of the invention

[0004] According to an embodiment of a semiconductor package, the semiconductor package includes: an insulating substrate having a first main side and a second main side opposite to the first main side; a power semiconductor die embedded in the insulating substrate and thinner than or as thick as the insulating substrate, and the power semiconductor die includes: a first load terminal bonding pad at a first side facing the same direction as the first main side of the insulating substrate, a second load terminal bonding pad at a second side facing the same direction as the second main side of the insulating substrate, and a control terminal bonding pad at the first side or the second side; a conductive first via extending through the insulating substrate in a peripheral area laterally surrounding the power semiconductor die; a first metallization portion connecting the first load terminal bonding pad of the power semiconductor die to the first via at the first main side of the insulating substrate; a solderable first contact pad at the second main side of the insulating substrate and formed by the first via; and a solderable second contact pad at the second main side of the insulating substrate and formed by the second load terminal bonding pad of the power semiconductor die.

[0005] According to an embodiment of a method for producing a semiconductor package, the method includes: embedding a power semiconductor die in an insulating substrate, the insulating substrate having a first main side and a second main side opposite to the first main side, the power semiconductor die being thinner than the insulating substrate or as thick as the insulating substrate, and including: a first load terminal bonding pad at a first side facing in the same direction as the first main side of the insulating substrate, a second load terminal bonding pad at a second side facing in the same direction as the second main side of the insulating substrate, and a control terminal bonding pad at the first side or the second side; and forming a first metallization portion at the first main side of the insulating substrate, the first metallization portion connecting the first load terminal bonding pad of the power semiconductor die to a conductive first via, the conductive first via extending through the insulating substrate in a peripheral area laterally surrounding the power semiconductor die, wherein the first via forms a solderable first contact pad at the second main side of the insulating substrate, wherein the second load terminal bonding pad of the power semiconductor die forms a solderable second contact pad at the second main side of the insulating substrate.

[0006] According to an embodiment of a method for producing a plurality of semiconductor packages, the method comprises: adhering a core insulating panel having a plurality of openings to a temporary bonding tape at a second main side of the core insulating panel opposite to the first main side; inserting a power semiconductor die in each opening of the core insulating panel, each power semiconductor die being thinner than the core insulating panel or as thick as the core insulating panel and comprising: a first load terminal bonding pad at a first side facing in the same direction as the first main side of the core insulating panel, a second load terminal bonding pad at a second side facing in the same direction as the second main side of the core insulating panel, and a control terminal bonding pad at the first side or the second side, wherein each power semiconductor die is adhered to the temporary bonding tape at the second side of the power semiconductor die; forming a first metallization layer at a first main side of the core insulating panel, the first metallization layer being patterned into a plurality of first metallization portions, each first metallization portion being associated with one of the power semiconductor dies and connecting a first load terminal bonding pad of the power semiconductor die to a corresponding conductive first via extending through the core insulating panel in a peripheral region laterally surrounding the power semiconductor die; and singulating the core insulating panel into a plurality of packages, wherein, for each package, the first via included in the package forms a solderable first contact pad at a second main side of the singulated core insulating panel, and the second load terminal bonding pad of the power semiconductor die included in the package forms a solderable second contact pad at the second main side of the singulated core insulating panel.

[0007] According to another embodiment of a semiconductor package, the semiconductor package includes: a substrate having a first main surface, a second main surface opposite to the first main surface, an electrically insulating core between the first main surface and the second main surface, and a conductive first via extending through a peripheral area of ​​the core, the peripheral area defining an opening in the core; a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core or as thick as the core, the power semiconductor die including a first load terminal bonding pad at a first side facing the same direction as the first main surface of the substrate, a second load terminal bonding pad at a second side facing the same direction as the second main surface of the substrate, and a control terminal bonding pad at the first side or the second side; a plated first contact pad at the second main surface of the substrate and provided by the first via; a plated second contact pad at the second main surface of the substrate and provided by the second load terminal bonding pad of the power semiconductor die; and a thermal capacitor attached to the first main surface of the substrate, the thermal capacitor being designed to absorb transient heat pulses from the power semiconductor die and subsequently release the transient heat pulses to the surrounding environment.

[0008] According to an embodiment of a method for mass producing a plurality of semiconductor packages, the method includes: aligning a first panel with a second panel, the first panel including a plurality of interconnected substrates having openings and a power semiconductor die embedded in each opening, the second panel including a plurality of interconnected thermal capacitors aligned with corresponding ones of the substrates; attaching each thermal capacitor to a corresponding substrate aligned with the thermal capacitor by attaching material applied to the substrate of the first panel and / or the thermal capacitor of the second panel; and after attaching, cutting through an area of ​​the first panel interconnecting the substrates, and cutting through an area of ​​the second panel interconnecting the thermal capacitors to form individual packages, each individual package including a substrate, a power semiconductor die embedded in the substrate, and a thermal capacitor attached to the substrate, the thermal capacitor being designed to absorb transient heat pulses from a power semiconductor die included in the same package as the thermal capacitor, and subsequently release the transient heat pulses to the surrounding environment.

[0009] According to another embodiment of a semiconductor package, the semiconductor package includes: an electrically insulating core having a first side, a second side opposite the first side and configured for mounting to another substrate, and a conductive first via extending through a peripheral region of the core, the peripheral region defining an opening in the core, the core including glass fibers interwoven with an epoxy material, the core having one or more regions at the second side in which the glass fibers are exposed from the epoxy material; a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core and including a conductive first via at the first side facing in the same direction as the first side of the core. a first load terminal bonding pad, a second load terminal bonding pad at the second side facing the same direction as the second side of the core, and a control terminal bonding pad at the first side or the second side of the power semiconductor die; a resin filling the opening in the core and encapsulating the power semiconductor die; a plated first contact pad at the first side of the core and provided by the first via; a plated second contact pad at the second side of the core and provided by the first load terminal bonding pad of the power semiconductor die; and a solder mask partially covering one or more areas at the second side of the core where glass fibers are exposed from the epoxy resin material.

[0010] According to another embodiment of a method for producing a semiconductor package, the method includes: positioning an electrically insulating core with a first side of the core facing downward and a second side of the core facing upward, the second side being configured for mounting to another substrate, wherein a conductive first via extends through a peripheral region of the core, the peripheral region defining an opening in the core, wherein the core includes glass fibers interwoven with an epoxy material; placing a power semiconductor die in the opening in the core, the power semiconductor die being thinner than the core and including a first load terminal bonding pad facing downward in the same direction as the first side of the core, and a second load terminal bonding pad facing upward in the same direction as the second side of the core; on the second side of the core: filling the opening in the core with a resin enveloping the power semiconductor die; reducing the thickness of the resin in an area covering the second load terminal bonding pad of the power semiconductor die; and after the reduction, thinning the resin to expose the first via and the second load terminal bonding pad of the power semiconductor die, the thinning exposing the glass fibers from the epoxy material in one or more areas at the second side of the core; and partially covering one or more areas at the second side of the core with a solder mask, in which the glass fibers are exposed from the epoxy material.

[0011] According to another embodiment of the method for producing a semiconductor package, the method includes: positioning an electrically insulating core with a first side of the core facing upward and a second side of the core facing downward, the second side being configured for mounting to another substrate, wherein a conductive first via extends through a peripheral area of ​​the core, the peripheral area defining an opening in the core, wherein the core includes glass fibers interwoven with an epoxy resin material; placing a power semiconductor die in the opening in the core, the power semiconductor die being thinner than the core and including a first load terminal bonding pad facing upward in the same direction as the first side of the core, and a second load terminal bonding pad facing downward in the same direction as the second side of the core; and on the first side of the core: filling the opening in the core with a resin enveloping the power semiconductor die; thinning the resin; forming a mask on the thinned resin, the mask having a first opening aligned with the first via and a second opening aligned with the first load terminal bonding pad of the power semiconductor die; etching the resin through the first opening to expose the first via, and etching the resin through the second opening to expose the first load terminal bonding pad of the power semiconductor die.

[0012] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and described in detail in the following description.

[0014] Figure 1 A cross-sectional view of an embodiment of a semiconductor package is shown.

[0015] Figure 2 A cross-sectional view of another embodiment of a semiconductor package is shown.

[0016] Figure 3A and Figure 3B Shows production Figure 1 An embodiment of a method for semiconductor packaging is shown.

[0017] Figure 4A and Figure 4B Shows production Figure 2 An embodiment of a method for semiconductor packaging is shown.

[0018] Figure 5 A cross-sectional view of another embodiment of a semiconductor package is shown.

[0019] Fig. 6A and Figure 6B Shows production Figure 5 An embodiment of a method for semiconductor packaging is shown.

[0020] 7A to 7I Various cross-sectional views of an embodiment of a method of mass producing semiconductor packages are shown.

[0021] Figure 8 A cross-sectional view illustrating another embodiment of a method for mass producing semiconductor packages.

[0022] Fig. 9 A cross-sectional view of another embodiment of a semiconductor package is shown.

[0023] Fig.10 A graph is shown which shows the Fig. 9 The relationship between the energy capacity and thickness of a packaged thermal capacitor is shown.

[0024] Fig.11 A cross-sectional view of another embodiment of a semiconductor package is shown.

[0025] Fig.12 A partial cross-sectional view of another embodiment of a semiconductor package is shown.

[0026] Fig.13 Shows mass production Fig. 9 , Fig.11 and Fig.12 Embodiments of any of the methods of semiconductor packaging shown.

[0027] Fig.14 shows an enlarged top view of the first panel; and Fig.15 Shown in Fig.13 The second panel is an enlarged top view of the method used.

[0028] Fig.16 Shown according to Fig.13 A top view of an interconnected thermal capacitor after being attached to a corresponding substrate.

[0029] Fig.17 A cross-sectional view of another embodiment of a semiconductor package is shown.

[0030] Fig.18 Shows production Fig.17 An embodiment of a method for semiconductor packaging is shown.

[0031] FIG. 19A to FIG. 19D Shows production Fig. 9 An embodiment of a method for semiconductor packaging is shown in FIG. DETAILED DESCRIPTION

[0032] The described embodiments provide a semiconductor package having one or more solderable contact pads formed by at least one terminal bonding pad of a power semiconductor die and a method for manufacturing the same. The semiconductor package has improved heat dissipation, a smaller form factor, provides direct pad contact between the die and the mounting surface, and provides gate terminal wiring. The method described herein is a process flow compatible with large panels typically used in PCB (printed circuit board) processing and provides a lower cost scale. The package also improves thermal performance at the top side of the package. Instead of welding between the die and the top side metallization, the connection can be a direct copper-to-copper connection. In the case of a power semiconductor transistor device, since the surface of the insulating substrate body of the package can be used to expand / route the source / emitter (or drain / collector) and gate pad connections, the footprint of the package can be standardized between different die sizes.

[0033] Figure 1 A cross-sectional view of an embodiment of a semiconductor package 100 is shown. The semiconductor package 100 includes an insulating substrate 102 having a first main side 104 and a second main side 106 opposite to the first main side 104. The insulating substrate 102 may be a laminate such as a PCB substrate. The package 100 also includes a power semiconductor die 108, which is embedded in the insulating substrate 102 and is thinner than the insulating substrate 102 or as thick as the insulating substrate 102. That is, the thickness T_sub of the insulating substrate 102 is equal to or greater than the thickness T_die of the power semiconductor die 108, thereby eliminating the bonding wire thickness problem associated with the thin semiconductor die. Therefore, the power semiconductor die 108 embedded in the insulating substrate 102 can be relatively thin, for example, T_die can be in the range of 40μm to 60μm or even smaller.

[0034] In one embodiment, the power semiconductor die 108 is positioned in an opening 110 in the insulating substrate 102, and the opening 110 is at least partially filled with an insulating material 112 such as epoxy, resin, etc. The insulating substrate 102 having the opening 110 and the insulating material 112 at least partially filling the opening 110 can be made of the same material or different materials. For example, the insulating substrate 102 having the opening 110 can include glass fibers embedded in epoxy, and the insulating material 112 at least partially filling the opening 110 can include resin. In another example, the insulating substrate 102 having the opening 110 and the insulating material 112 at least partially filling the opening 110 can both be resin materials. These are just a few examples of the composition of the insulating substrate 102 and the insulating material 112, and other material combinations are also possible.

[0035] The power semiconductor die 108 embedded in the insulating substrate 102 has a first load terminal bonding pad 114 at a first side 116 of the die 108 and facing the same direction as the first main side 104 of the insulating substrate 102. The power semiconductor die 108 also has a second load terminal bonding pad 118 at a second side 120 of the die 108 and facing the same direction as the second main side 106 of the insulating substrate 102. Figure 1 In the illustrated embodiment, the power semiconductor die 108 also has a control terminal bond pad 122 at the second side 120 of the die 108 .

[0036] For example, in the case of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, a HEMT (High Electron Mobility Transistor) device, etc., the first load terminal bonding pad 114 of the power semiconductor die 108 can be a drain terminal bonding pad, and the second load terminal bonding pad 118 of the die 108 can be a source terminal bonding pad. For example, in the case of an IGBT (Insulated Gate Bipolar Transistor) device, the first load terminal bonding pad 114 of the power semiconductor die 108 can be a collector terminal bonding pad, and the second load terminal bonding pad 118 of the die 108 can be an emitter terminal bonding pad. In each example, the control terminal bonding pad 122 at the second side 120 of the power semiconductor die 108 can be a gate terminal bonding pad.

[0037] Regardless of the type of power semiconductor die 108 embedded in the insulating substrate 102, the semiconductor package 100 further includes an electrically conductive first via 124, such as a plated through hole, a copper via, a metal block, etc., extending through the insulating substrate 102 in a peripheral region laterally surrounding the power semiconductor die 108. The semiconductor package 100 further includes a first metallization 126, such as a copper metallization, connecting a first load terminal bonding pad 114 of the power semiconductor die 108 to the first via 124 at the first main side 104 of the insulating substrate 102.

[0038] In one embodiment, the first via 124, the first metallization 126, and the first load terminal bonding pad 114 of the power semiconductor die 108 all include copper. The second load terminal bonding pad 118 and the control terminal bonding pad 122 of the power semiconductor die 108 may also all include copper. Other conductive materials may be used for the first via 124, the first metallization 126, and the terminal bonding pads 114, 118, 122 of the power semiconductor die 108. In general, any metal or metal compound (e.g., Cu, NiPdAu, etc.) may be used for the first load terminal bonding pad 114 at the first side 116 of the power semiconductor die 108. For the terminal bonding pads 118, 122 at the second side 120 of the power semiconductor die 108, the metal or metal compound used should be solderable, such as Cu. As used herein, the term "solderable" means that a suitable solder joint can be made to the material. For example, the solderable contact pads described herein may include standard leaded or lead-free solder materials or alloys used in electronic device manufacturing and contain at least one of the following materials: Sn, Pb, Sb, Bi, Ag, Cu, Zn and / or In.

[0039] A solderable first contact pad 128 on the second main side 106 of the insulating substrate 102 is formed by a first via 124 extending through the insulating substrate 102. In one embodiment, a standard pre-plated via is used, but is made wide / large enough so that the first via 124 has enough surface contact area to serve as a final / direct pad 128 at the second main side 106 of the insulating substrate 102.

[0040] In the example given above where the first load terminal bonding pad 114 of the power semiconductor die 108 is a drain (or collector) terminal bonding pad, this means that the first via 124 can be used as a final / direct bonding pad 128 for providing a drain (or collector) connection at the second main side 106 of the insulating substrate 102. If the first load terminal bonding pad 114 of the power semiconductor die 108 is instead a source (or emitter) terminal bonding pad, the first via 124 can be used as a final / direct bonding pad 128 for providing a source (or emitter) connection at the second main side 106 of the insulating substrate 102.

[0041] The solderable second contact pad 130 at the second main side 106 of the insulating substrate 102 is formed by the second load terminal bonding pad 118 of the power semiconductor die 108, and the solderable third contact pad 132 at the second main side 106 of the insulating substrate 102 is formed by the Figure 1 The control terminal bonding pad 122 of the die 108 is formed. Thus, at least two terminal bonding pads 118, 122 of the power semiconductor die 108 form a Figure 1The first vias 124 form some of the final I / O pads of the semiconductor package 100 of the illustrated embodiment, while the first vias 124 form additional final I / O pads of the package.

[0042] In one embodiment, at the second main side 106 of the insulating substrate 102, a solderable second contact pad 130 formed by the second load terminal bonding pad 118 of the power semiconductor die 108 is coplanar with a solderable first contact pad 128 formed by the first via 124. At the second main side 106 of the insulating substrate 102, a solderable third contact pad 132 formed by the control terminal bonding pad 122 of the power semiconductor die 108 may also be coplanar with the solderable first contact pad 128 formed by the first via 124.

[0043] All electrical connections for the power semiconductor die 108 are provided at the second main side 106 of the insulating substrate 102 in the form of corresponding solderable contact pads 128, 130, 132, so that the semiconductor package 100 has an SMD construction. The semiconductor package 100 can be cooled at the second main side 106 of the insulating substrate 102, for example by a board / substrate (not shown) to which the package 100 is to be mounted. A heat sink 134 can be attached to the first metallization 126 at the first main side 104 of the insulating substrate 102 to provide double-sided cooling. The heat sink 134 can be omitted, and instead the first metallization 126 at the first main side 104 of the insulating substrate 102 is thickened to provide double-sided cooling. In the case of single-sided cooling, the heat sink 134 is omitted and thus Figure 1 Any gap 136 between the heat sink 134 and the first metallization 126 at the first main side 104 of the insulating substrate 102 may be filled with a thermal interface material such as thermal grease, thermal glue, etc. Alternatively, the gap 136 may be eliminated by covering a portion of the first metallization 126 at the first main side 104 of the insulating substrate 102 and increasing the thickness of the uncovered first metallization 126, for example, by additional Cu plating and / or ECD (electrochemical deposition).

[0044] The first solder mask 138 may at least partially cover the first metallization 126 at the first main side 104 of the insulating substrate 102. In case of single-sided cooling, the first solder mask 138 may completely cover the first metallization 126 at the first main side 104 of the insulating substrate 102. A second solder mask 140 may be provided at the second main side 106 of the insulating substrate 102 to define the exposed surface area of ​​the respective solderable contact pads 128, 130, 132 provided at the second main side 106 of the insulating substrate 102 for surface mounting of the semiconductor package 100.

[0045] Figure 2A cross-sectional view of another embodiment of a semiconductor package 200 is shown. Figure 2 The embodiment shown is Figure 1 The embodiment shown is similar. However, the difference is that Figure 2 In the embodiment, the control terminal bonding pad 122 of the power semiconductor die 108 is at the first side 116 of the die 108, rather than at the second side 120. In order to provide an electrical connection for the control terminal bonding pad 122 of the power semiconductor die 108 at the second main side 106 of the insulating substrate 102, Figure 2 The semiconductor package 200 in the embodiment includes a conductive second via 202 extending through the insulating substrate 102 in the peripheral region, and a second metallization 204 connecting the control terminal bonding pad 122 of the power semiconductor die 108 to the second via 202 at the first main side 104 of the insulating substrate 102. The second metallization 204 at the first main side 104 of the insulating substrate 102 is separated from the first metallization 126 to prevent an electrical short circuit between the control terminal bonding pad 122 of the power semiconductor die 108 and the first load terminal bonding pad 114.

[0046] A solderable third contact pad 206 at the second main side 106 of the insulating substrate 102 is formed by the second via 202. Therefore, only the second load terminal bonding pad 118 at the second side 120 of the power semiconductor die 108 needs to include a solderable metal or metal compound, such as Cu, while the control terminal bonding pad 122 and the first load terminal bonding pad 114 at the first side 116 of the power semiconductor die 108 may or may not include a solderable metal or metal compound. The first via 124 and the second via 202 both include a solderable metal or metal compound, such as Cu, and the second via 202 may have the same or similar composition as the first via 124. Figure 2 , the first solder mask 138 is shown as covering the entire first main side 104 of the insulating substrate 102, but may alternatively only partially cover the first main side 104 of the insulating substrate 102, or may be omitted entirely, for example to achieve double-sided cooling.

[0047] Figure 3A and Figure 3B Shows production Figure 1 An embodiment of a method for semiconductor packaging 100 is shown. Figure 3A and Figure 3B , the left side of each figure shows a plan view of a first main side 104 of the insulating substrate 102 , and the right side of each figure shows a plan view of a second main side 106 of the insulating substrate 102 .

[0048] Figure 3AThe semiconductor package 100 is shown after embedding a power semiconductor die 108 in the insulating substrate 102 of the package 100, but before forming a first metallization 126 at the first main side 104 of the insulating substrate 102. Figure 3A As shown and as previously explained herein, a solderable first contact pad 128 at the second main side 106 of the insulating substrate 102 is formed by the first via 124, a solderable second contact pad 130 at the second main side 106 of the insulating substrate 102 is formed by the second load terminal bonding pad 118 of the power semiconductor die 108, and a solderable third contact pad 132 at the second main side 106 of the insulating substrate 102 is formed by the control terminal bonding pad 122 of the die 108.

[0049] Since the terminal bonding pads 118, 122 at the second side 116 of the power semiconductor die 108 are solderable and serve as final / direct bonding pads 130, 132 for the semiconductor package 100 at the second main side 106 of the insulating substrate 102, the manufacturing method of producing the package 100 does not require additional processing / metallization layers to provide corresponding contact points for the package 100. For example, the following processing as part of the package manufacturing process: depositing a seed layer and subsequently plating Cu on the terminal bonding pads 118, 122 at the second side 116 of the power semiconductor die 108 can be eliminated.

[0050] Figure 3B The semiconductor package 100 is shown after forming a first metallization 126 at the first main side 104 of the insulating substrate 102. The first metallization 126 is formed by forming a first solder mask 136 on the first main side 104 of the insulating substrate 102. The first solder mask 126 has one or more openings 300 that expose at least a portion of the first load terminal bonding pad 114 at the first side 116 of the power semiconductor die 108 and expose at least a portion of the first via 124 extending through the insulating substrate 102. Copper is then deposited in the openings 300 of the first solder mask 126. The term "copper" as used herein refers to Cu and Cu alloys. Since the first via 124 and the first load terminal bonding pad 114 are covered by the first metallization 126 and thus on Figure 3B The first via 124 and the first load terminal bonding pad 114 at the first side 116 of the power semiconductor die 108 are blocked in the left plan view of FIG. Figure 3B It is shown as a dotted box in the left plan view.

[0051] Figure 3BThe right side plan view of shows the second side 106 of the insulating substrate 102 after providing a second solder mask 140 at the second main side 106 of the insulating substrate 102. The second solder mask 140, if provided, defines the exposed surface area of ​​respective solderable contact pads 128, 130, 132 provided at the second main side 106 of the insulating substrate 102 for surface mounting of the semiconductor package 100, as previously explained herein.

[0052] Figure 4A and Figure 4B Shows production Figure 2 An embodiment of a method for semiconductor packaging 200 is shown. Figure 4A and Figure 4B , the left side of each figure shows a plan view of a first main side 104 of the insulating substrate 102 , and the right side of each figure shows a plan view of a second main side 106 of the insulating substrate 102 .

[0053] Figure 4A The semiconductor package 200 is shown after embedding the power semiconductor die 108 in the insulating substrate 102 of the package 200, but before forming the first metallization 126 at the first main side 104 of the insulating substrate 102. Figure 4A As shown and as previously explained herein, a solderable first contact pad 128 at the second main side 106 of the insulating substrate 102 is formed by the first via 124, a solderable second contact pad 130 at the second main side 106 of the insulating substrate 102 is formed by the second load terminal bonding pad 118 of the power semiconductor die 108, and a solderable third contact pad 206 at the second main side 106 of the insulating substrate 102 is formed by the second via 202.

[0054] Since the second load terminal bonding pads 118 at the second side 116 of the power semiconductor die 108 are solderable and serve as final / direct bonding pads 130 for the semiconductor package 100 at the second main side 106 of the insulating substrate 102, the manufacturing method of producing the package 100 does not require additional processing / metallization layers to provide corresponding contact points for the package 100. For example, as explained above, the following processing as part of the package manufacturing process: depositing a seed layer and subsequently plating Cu on the second load terminal bonding pads 118 at the second side 116 of the power semiconductor die 108 can be eliminated.

[0055] Figure 4BThe semiconductor package 200 is shown after forming the first and second metallizations 126, 204 at the first main side 104 of the insulating substrate 102. The first metallization 126 connects the first load terminal bonding pads 114 at the first side 116 of the power semiconductor die 108 to the first vias 124 at the first main side 104 of the insulating substrate 102, and the second metallization 204 connects the control terminal bonding pads 122 of the power semiconductor die 108 at the first side 116 of the die 108 to the second vias 202 at the first main side 104 of the insulating substrate 102, as previously explained herein.

[0056] The first and second metallizations 126, 204 are formed by forming a first solder mask 136 on the first main side 104 of the insulating substrate 102. The first solder mask 126 has a first opening 400 that exposes at least a portion of the first load terminal bonding pad 114 at the first side 116 of the power semiconductor die 108 and exposes at least a portion of the first via 124 extending through the insulating substrate 102. The first solder mask 126 also has a second opening 402 that exposes at least a portion of the control terminal bonding pad 122 at the first side 116 of the power semiconductor die 108 and exposes at least a portion of the second via 202 extending through the insulating substrate 102. Copper is then deposited in the first and second openings 400, 402 of the first solder mask 126. Since the first via 124 and the first load terminal bonding pad 114 are covered by the first metallization 126 and the control terminal bonding pad 122 is covered by the second metallization 204 and thus Figure 4B The first via 124 and the first load terminal bonding pad 114 and the control terminal bonding pad 122 at the first side 116 of the power semiconductor die 108 are blocked in the left plan view of FIG. Figure 4B The left side plan view shows the

[0057] Figure 4B The right side plan view of shows the second side 106 of the insulating substrate 102 after providing a second solder mask 140 at the second main side 106 of the insulating substrate 102. The second solder mask 140, if provided, defines the exposed surface area of ​​the respective solderable contact pads 128, 130, 206 provided at the second main side 106 of the insulating substrate 102 for surface mounting of the semiconductor package 200, as previously explained herein.

[0058] Figure 5 A cross-sectional view of another embodiment of a semiconductor package 500 is shown. Figure 5 The embodiment shown is Figure 1 and Figure 2 The embodiment shown is similar. However, the difference is that Figure 5 The semiconductor package 500 in Figure 5 also includes an additional power semiconductor die 502, which is embedded in the insulating substrate 102 and is thinner than the insulating substrate 102 (i.e., T_die2 < T_sub) or has the same thickness as the insulating substrate 102 (i.e., T_die2 = T_sub). The additional power semiconductor die 502 has a first load terminal bonding pad 504 at one side 506 of the additional die 502 facing the same direction as the second major side 106 of the insulating substrate 102. The additional power semiconductor die 502 also has a second load terminal bonding pad 508 at one side 510 of the additional die 502 facing the same direction as the first major side 104 of the insulating substrate 102. The additional power semiconductor die 502 also has control terminal bonding pads 512 at either side 506, 510 of the additional die 502, although in Figure 5 as an example in Figure 5 , the control terminal bonding pads 512 are at the second side 506 of the additional die 502.

[0059] In one embodiment, the first metallization 126 connects the first load terminal bonding pad 114 of the (first) power semiconductor die 108 to the second load terminal bonding pad 508 of the additional power semiconductor die 502 in a half-bridge configuration on the first major side 104 of the insulating substrate 102. Figure 5 The upper right corner of Figure 5 includes a circuit schematic of a half-bridge circuit, where the transistor Q1 corresponds to the first power semiconductor die 108 and the transistor Q2 corresponds to the additional power semiconductor die 502. The switching node "SW" formed by the coupled connection of the power semiconductor dies 108, 502 and formed by the first metallization 126 is brought to the second major side 106 of the insulating substrate through the first via 124. In Figure 5 the cross-sectional view of Figure 5 , the entire connection between the first metallization 126 and the first via 124 cannot be seen. For a duty cycle of less than 50%, the additional power semiconductor die 502 forming the high-side switch of the half-bridge circuit can be smaller than the first power semiconductor die 108 forming the low-side switch of the half-bridge circuit, because the period during which the low-side switch conducts in the half-bridge switching cycle is longer than the period during which the high-side switch conducts. To emphasize this point, in Figure 5 the cross-sectional view of Figure 5 , the additional power semiconductor die 502 is shown as smaller than the first power semiconductor die 108. Figure 5 The diodes D1, D2 shown in the schematic diagram of Figure 5 can be monolithically integrated in the corresponding dies 108, 502, or can be discrete components.

[0060] The additional metallization 514 at the first main side 106 of the insulating substrate 102 connects the control terminal bond pads 512 at the second side 510 of the additional power semiconductor die 502 to one or more corresponding conductive vias 516 extending through the insulating substrate 102. Figure 5 The entire connection between the additional metallization 514 and the additional via 124 is not visible in the cross-sectional view of FIG.

[0061] A solderable contact pad 518 is formed by an additional via 516 at the second main side 106 of the insulating substrate 102. Another solderable contact pad 520 is formed at the second main side 106 of the insulating substrate 102 by a first load terminal bonding pad 504 at the first side 506 of the additional power semiconductor die 502. In this way, all electrical connections for the power semiconductor die 108, 502 are provided at the second main side 106 of the insulating substrate 102 in the form of corresponding solderable contact pads 128, 130, 132, 518, 520, thereby providing an SMD construction for the semiconductor package 500. Figure 5 As shown, the solderable contact pads 130, 132, 520 formed of at least the respective terminal bond pads 118, 122, 504 of the power semiconductor die 108, 502 may have an additional Cu plating layer 522, 524, 526. Alternatively, as previously described herein, the additional plating layer may be omitted.

[0062] An insulating layer 528 such as polyimide may be provided at the first main side 104 of the insulating substrate 102 to provide suitable insulation at this side of the package 500 , and may include one or more openings 530 exposing corresponding one or more of the metallizations 126 , 514 .

[0063] Fig. 6A and Figure 6B Shows the manufacturing Figure 5 An embodiment of a method for semiconductor packaging 500 is shown. Fig. 6A and Figure 6B , the left side of each figure shows a plan view of the first main side 104 of the insulating substrate 102 , and the right side of each figure shows a plan view of the second main side 106 of the insulating substrate 102 .

[0064] Fig. 6A The semiconductor package 500 is shown after embedding the power semiconductor die 108, 502 in the insulating substrate 102 of the package 500, but before forming the metallization 126, 514 at the first main side 104 of the insulating substrate 102. Fig. 6AAs shown in and as previously explained herein, a solderable first contact pad 128 for the half-bridge switch node SW at the second main side 106 of the insulating substrate 102 is formed by a first via 124, a solderable second contact pad 130 at the second main side 106 of the second insulating layer 102 is formed by the second load terminal bonding pad 118 of the power semiconductor die 108, a solderable third contact pad 520 at the second main side 106 of the insulating substrate 102 is formed by the first load terminal bonding pad 504 of the additional power semiconductor die 108, a solderable fourth contact pad 132 at the second main side 106 of the insulating substrate 102 is formed by the control terminal bonding pad 122 of the first die 108, and a solderable fifth contact pad 518 at the second main side 106 of the insulating substrate 102 is formed by a corresponding additional via 516.

[0065] Figure 6B The semiconductor package 500 is shown after forming the metallization 126, 514 at the first main side 104 of the insulating substrate 102. A first solder mask 136 is formed on the first main side 104 of the insulating substrate 102. The first solder mask 126 has a first opening 600 that defines a layout / footprint area for the first metallization 126. The first opening 600 in the first solder mask 126 exposes at least a portion of the first load terminal bonding pad 114 at the first side 116 of the first power semiconductor die 108, exposes at least a portion of the second load terminal bonding pad 508 at the second side 510 of the additional power semiconductor die 108, and exposes at least a portion of the first via 124 extending through the insulating substrate 102.

[0066] The first solder mask 126 also has second openings 602 that define a layout / footprint area for the second metallization 514. The second openings 602 in the first solder mask 126 expose at least a portion of the control terminal bond pads 512 at the second side 510 of the additional power semiconductor die 502 and expose at least a portion of the corresponding vias 516 extending through the insulating substrate 102.

[0067] Then, copper is deposited in the openings 600, 602 of the first solder mask 126. Since the vias 124, 516 and the terminal bonding pads 114, 508, 512 are covered by the metallization 126, 514 and thus Figure 6B 108, the first load terminal bonding pad 114 at the first side 116 of the power semiconductor die 108, the second load terminal bonding pad 508 at the second side 510 of the additional power semiconductor die 108, and the control terminal bonding pad 510 at the second side 510 of the additional power semiconductor die 108 and the corresponding via 516 are blocked in the left plan view of FIG. Figure 6B It is shown as a dotted box in the left plan view.

[0068] Figure 6B The right side plan view of the insulating substrate 102 shows the second side 106 of the insulating substrate 102 after the second solder mask 140 is disposed at the second main side 106 of the insulating substrate 102. As previously explained herein, the second solder mask 140 defines the exposed surface area of ​​the corresponding solderable contact pads 128, 130, 132, 518, 520 disposed at the second main side 106 of the insulating substrate 102 for surface mounting of the semiconductor package 500.

[0069] 7A to 7I Corresponding cross-sectional views of an embodiment of a method of mass-producing semiconductor packages of the kind previously described herein are shown.

[0070] Fig. 7A A core insulation panel 700 is shown adhered to a temporary bonding tape 702 at a second main side 704 of the core insulation panel 700 opposite the first main side 706. The core insulation panel 700 has a plurality of openings 708, each sized to accommodate a power semiconductor die. 7A to 7I Only one opening 708 is shown in the figure. The core insulation panel 700 also has a conductive via 710 extending through the panel 700. The via 710 is wide / large enough so that the via 710 has sufficient surface contact area to serve as a final / direct pad at the second main side 704 of the panel 700. The core insulation panel 700 can be a laminate in which the via 710 is embedded in the laminate as a Cu block. In another example, the core insulation panel 700 can be a standard PCB laminate in which the via 710 is filled as a Cu via. In yet another example, the core insulation panel 700 can be a molded panel in which the via 710 is an embedded Cu via, block, lead frame component, etc. Fig. 7A The via 710 in may correspond to Figures 1 to 6B Any of the vias 124, 202, 516 shown in .

[0071] Figure 7B A power semiconductor die 712 is shown inserted into each opening 708 of the core insulating panel 700. Each power semiconductor die 712 is thinner than or as thick as the core insulating panel 700 and includes a first load terminal bonding pad 714 at a first side facing in the same direction as the first major side 706 of the core insulating panel 700, a second load terminal bonding pad 716 at a second side facing in the same direction as the second major side 704 of the core insulating panel 700, and a control terminal bonding pad 718 at the first side or the second side of the die 712. Figure 7BThe left side of FIG. 7 shows a control terminal bonding pad 718 at the side of the die 712 facing the temporary bonding tape 702 (eg, a source-up configuration), and Figure 7B The right side of exemplifies control terminal bonding pads 718 (eg, source-down configuration) at the side of die 712 facing away from temporary bonding tape 702. In either case, each power semiconductor die 712 is adhered to temporary bonding tape 702 at the side of die 712 facing tape 702.

[0072] Figure 7C It is shown that after inserting a power semiconductor die 712 into each opening 708 of the core-insulation panel 700, each opening 708 is filled and each power semiconductor die 712 is covered with a resin film 720. Any standard resin film lamination process may be used.

[0073] Fig.7D It is shown that after filling each opening 708 and covering each power semiconductor die 712 with a resin film 720, the temporary bonding tape 702 is removed and the resin film 720 is planarized at the first main side 706 of the core-insulation panel 700. Standard planarization techniques may be used, such as CMP (chemical mechanical polishing).

[0074] Fig. 7E The resin film 720' is shown removed from at least a portion of the first load terminal bonding pad 714 at the side of each power semiconductor die 712 facing the same direction as the first main side 706 of the core insulation layer 700. In one embodiment, the resin portion 720" remaining after exposing the first load terminal bonding pad 714 of each power semiconductor die 712 is Figure 1 , Figure 2 and Figure 5 Insulating material 112 is shown.

[0075] Figure 7F It is shown that a seed layer 722 for Cu growth is formed on the first main side 706 of the core insulation panel 700 and on the portion of the first load terminal bonding pad 714 of each power semiconductor die 712 exposed by removing the resin film 720″. For example, the seed layer 722 can be sputtered on the first main side 706 of the core insulation panel 700 and on the exposed portion of the first load terminal bonding pad 714 of each power semiconductor die 712.

[0076] Figure 7G Copper 724 is shown plated on the seed layer 722. Any standard Cu plating process may be used, such as ECD.

[0077] Figure 7HThe plated copper 724 is shown patterned to define at least a first metallization 726. For example, the plated copper 724 may be patterned to define Figures 1 to 6B Any metallization 126, 204, 514 as shown. The plated copper 724 may be patterned using any standard patterning process such as photolithography and etching.

[0078] Fig.7I The core insulating panel 700 is shown singulated into individual (individual) packages 728. The core insulating panel 700 may be singulated along the diced / cut regions 730 to form the individual packages 728 using any standard singulation process such as sawing, laser cutting, etc. For example, one or more solder masks ( Fig.7I not shown).

[0079] Fig.7I The individual packages 728 in may correspond to Figure 1 , Figure 2 and Figure 5 Any of the packages 100, 200, 500 shown in FIG. That is, the singulated portions of the core insulation panel 700 may correspond to the following: Figures 1 to 6B The insulating substrate 102 is shown. Moreover, the second load terminal bonding pad 716 at the side of each die 712 facing the same direction as the second main side 704 of the singulated core insulating panel 700 forms a solderable contact pad 730 at the second main side 704 of the singulated core insulating panel 700. Figure 7B In the source-up configuration shown on the left side of FIG. 1 , the control terminal bonding pad 718 of each die 712 also forms a solderable contact pad 732 at the second main side 704 of the singulated core insulating panel 700, as shown in FIG. Fig.7I as shown in , and similar to Figure 1 For Figure 7B In the drain-up configuration shown on the right side of FIG. 7 , the control terminal bonding pad 718 is at the other side of the die 712, similar to Figure 2 The kind shown.

[0080] Figure 8 A cross-sectional view of another embodiment of a method for batch producing a semiconductor package of the type previously described herein is shown. According to this embodiment, the method previously described herein in conjunction with 7A to 7ITwo core insulation panels 700 of the type described are stacked perpendicular to each other to improve processability and yield. The core insulation panels 700 can be stacked using double-sided release tape, temporary glue / wax, or other types of temporary carrier structures 800 (e.g., carrier 802 between two temporary bonding tapes 804). Instead, the core insulation panels 700 are clamped together under vacuum using clamps, screws, etc., or by lamination, sputtering, plating, etc. before die placement. The power semiconductor die 712 is inserted into the openings 708 of the two core insulation panels 700, as shown. Figure 8 As shown, and then, the processing of the two panels 700 continues as FIG. 7C to FIG. 7I shown.

[0081] Fig. 9 A cross-sectional view of another embodiment of a semiconductor package 900 is shown. According to this embodiment, the semiconductor package 900 includes a substrate 902 having a first major surface 904, a second major surface 906 opposite the first major surface 904, an electrically insulating core 908 between the first and second major surfaces 904, 906, and at least one electrically conductive first via 910 extending through a peripheral region 912 of the core 908, the peripheral region 912 defining an opening 914 in the core 908, the opening 914 being at least partially filled with an insulating material 915, such as an epoxy, a resin, etc. For example, the insulating material 915 can be a resin including glass fibers interwoven with an epoxy material.

[0082] At least one power semiconductor die 916 is embedded in an opening 914 in an electrically insulating core 908 of the substrate 902. The power semiconductor die 916 is thinner than the core 908 or as thick as the core 908 (T_die≤T_core). The power semiconductor die 916 includes a first load terminal (e.g., drain) bonding pad 918 at a first side facing the same direction as the first main surface 904 of the substrate 902. The power semiconductor die 916 also includes a second load terminal (e.g., source) bonding pad 920 at a second side facing the same direction as the second main surface 906 of the substrate 902. The power semiconductor die 916 also includes a control terminal bonding pad 922 at the first side or the second side of the die 916.

[0083] Fig. 9The semiconductor package 900 shown also includes at least one plated first contact pad 924 at the second main surface 906 of the substrate 902 and provided by the first via 910. In one embodiment, the plated first contact pad 924 is also provided in part by a metallization 926 at the second main surface 906 of the substrate 902. For example, the substrate 902 can be a DBC (direct bonded copper) substrate, an AMB (active metal brazing) substrate, an IMS (insulated metal substrate), a PCB, a PCB laminate, etc., and has copper sheets 926, 928 bonded to one or both sides 104, 106 of the electrically insulating core 908. One or both copper sheets 926, 928 can be patterned or unpatterned. For example, the metallization 926 at the second main surface 906 of the substrate 902 can be patterned to form a plated second contact pad 930 at the second main surface 906 of the substrate 902, and the metallization 926 is provided by the second load terminal bonding pad 920 of the power semiconductor die 916. The plated contact pads 924 , 930 may be separated from one another by a solder mask 931 applied at the second main surface 906 of the substrate 902 .

[0084] Fig. 9 The semiconductor package 900 shown also includes a thermal capacitor 932 attached to the first major surface 904 of the substrate 902. The thermal capacitor 932 should not be confused with a standard heat sink. A standard heat sink is a passive heat exchanger that can transfer heat generated by an electronic or mechanical device to a fluid medium (e.g., air or a liquid coolant) where the heat is dissipated from the device, thereby allowing the device temperature to be regulated. In contrast, the term "thermal capacitor" as used herein means that the thermal capacitor 932 is designed to absorb transient heat pulses from the power semiconductor die 916 and subsequently release the transient heat pulse to the surrounding environment. A standard heat sink would have to be oversized to handle such transient heat pulses, thereby increasing the package size and cost.

[0085] Under certain application conditions, the power semiconductor die 916 may have to be robust against peak current events for a short period of time. A typical application example is a battery-powered drilling rig, in which the power semiconductor die 916 forms part of an inverter placed around the rotor of the drill motor. A fan provides air cooling to the inverter while the motor is turning. When the rotor begins to lock due to excessive torque, a worst-case thermal load condition occurs because the motor current reaches a maximum peak, and at the same time, no cooling is provided because the fan on the rotor is no longer rotating. However, energy still needs to be stored to avoid overheating and potential damage or destruction of the power semiconductor die 916. The thermal capacitor 932 is designed to absorb transient thermal pulses from the power semiconductor die 916 during the worst-case thermal load condition. After the drill returns to normal operation, the thermal capacitor 932 is also designed to release the transient thermal pulse to the surrounding environment. In a specific example, the power semiconductor die 916 can be a 60V device with a package size of 6.3mm×4.74mm and Ron (on-state resistance)=1 milliohm at operating temperature. For t=250ms, the maximum peak current Imax_peak may be 300A.

[0086] In this example, thermal capacitor 932 is designed to store 6.25e-6 kWh or 22.5 J of energy in the form of a transient heat pulse from power semiconductor die 916 and subsequently release the energy to the surrounding environment. Fig.10 As shown, the thermal capacitor 932 in this example is designed to store 6.25e-6 kWh or 22.5 J of energy ("E_store") at a thickness ("T_therm_cap") of approximately 2200 μm.

[0087] More generally, the thickness "T_therm_cap" of the thermal capacitor 932 is based on the magnitude of the transient thermal pulse generated by the power semiconductor die 916 during the worst-case thermal load condition. In one embodiment, the magnitude of the transient thermal pulse is in the range of 5 to 25 Joules, and the thickness T_therm_cap of the thermal capacitor 932 is in the range of 500 to 2500 μm. In another embodiment, the thickness T_therm_cap of the thermal capacitor 932 is in the range of 100 to 500 μm.

[0088] like Fig. 9As shown, a thermal capacitor 932 can be attached to a metallization 928 at a first major surface 904 of a substrate 902 or to a plated (e.g., Au) surface 934 of the metallization 928 using a thermally conductive material 936. According to this embodiment, the metallization 928 at the first major surface 904 of the substrate 902 connects the first load terminal bonding pad 918 of the power semiconductor die 916 to the first via 910. The thermally conductive material 936 can be electrically insulating or electrically conductive. For example, the thermally conductive material 936 can be solder, adhesive glue, or tape, etc. In the case where the conductive material 936 is used to attach the thermal capacitor 932, the thermal capacitor 932 can also improve the electrical performance of the package 900 by distributing the current and thus reducing the package resistance.

[0089] The surface 938 of the thermal capacitor 932 facing away from the substrate 902 can be structured to increase the surface contact with the surrounding environment. For example, the surface 938 of the thermal capacitor 932 facing away from the substrate 902 can have fins, bumps, etc. that improve the transfer of thermal energy to the surrounding environment.

[0090] The thermal capacitor 932 may have a lateral dimension (in the region of 1000 Å) that may be smaller than a lateral dimension of the electrically insulating core 908 of the substrate 902. Fig. 9 908). Thus, (lateral) boundaries 940 of thermal capacitor 932 are spaced inwardly from (lateral) boundaries 942 of core 908. In one embodiment, (lateral) boundaries 940 of thermal capacitor 932 are spaced inwardly from (lateral) boundaries 942 of core 908 by a distance in the range of 100 to 250 μm.

[0091] Fig.11 A cross-sectional view of another embodiment of a semiconductor package 1100 is shown. Fig.11 The embodiment shown is similar to Fig. 9 910 and the second main surface 906 of the substrate 902. In contrast, the metallization 928 and the corresponding plated surface 934 are omitted at the first main surface 904 of the substrate 902. Instead, the thermal capacitor 932 is attached to the first via 910 and the first load terminal bonding pad 918 of the power semiconductor die 916 by a thermally conductive material 936. According to this embodiment, the thermally conductive material 936 that attaches the thermal capacitor 932 to the first via 910 and the first load terminal bonding pad 918 of the power semiconductor die 916 is also electrically conductive. For example, the material 936 can be solder. Therefore, the thermal capacitor 932 electrically connects the first load terminal bonding pad 918 to the first via 910. In this way, the thermal capacitor 932 helps to bring about an electrical connection from the back side of the power semiconductor die 916 to the second main surface 906 of the substrate 902.

[0092] Fig.12A cross-sectional view of an embodiment of an edge region of a semiconductor package 1200 is shown. According to this embodiment, the thermally conductive material 936 attaching the thermal capacitor 932 to the substrate 902 is solder, and the (lateral) border 940 of the thermal capacitor 932 has a protrusion 1202, which prevents a solder fillet 1204 from reaching a surface 938 of the thermal capacitor 932 facing away from the substrate 902. The protrusion 1202 can be formed by stamping, etching, etc. In one embodiment, the length or extension range "L_ext" of the protrusion 1202 is in the range of 25% to 75% of the thickness T_therm_cap of the thermal capacitor 932.

[0093] Fig.13 Shows mass production Fig. 9 , Fig.11 and Fig.12 An embodiment of a method of any of the semiconductor packages 900, 1100, 1200 shown in . The method includes providing (a) a first panel 1300 and a second panel 1302. The first panel 1300 includes a substrate 902 having a plurality of interconnects with openings and a power semiconductor die embedded in each opening, such as Fig. 9 , Fig.11 and Fig.12 As shown. Fig.13 Only the top metallization 928 of each interconnected substrate 902 is visible. The second panel 1302 includes a plurality of interconnected thermal capacitors 932. The interconnected thermal capacitors 932 may be formed of a highly thermally conductive metal material such as Cu, AlSiCu, etc. The surface of the interconnected thermal capacitors 932 may be plated with another thin metal layer, such as Ni, NiAu, Ag, etc. Fig.14 An enlarged top view of the first panel 1300 is shown, and Fig.15 An enlarged top view of the second panel 1302 is shown. Fig.15 As shown in FIG. 1 , the thermal capacitors 932 may be interconnected to each other by narrow metal bridges 1303. Instead of interconnecting, the thermal capacitors 932 may be individually mounted using standard surface mount processes, for example, as separate Cu blocks mounted to the respective substrates 902 of the first panel 1300.

[0094] The method also includes applying (b) an attaching material 1304 such as solder paste to the substrate 902 of the first panel 1300 and / or the thermal capacitors 932 of the second panel 1302, for example, by screen printing.

[0095] The method also includes aligning the first panel 130 with the second panel 1302 (c) such that the interconnected thermal capacitors 932 are aligned with corresponding ones of the substrates 902 .

[0096] The method also includes attaching (d) each thermal capacitor 932 to a corresponding substrate 902 aligned with the thermal capacitor 932 via an attaching material 1304 previously applied to the substrate 902 of the first panel 1300 and / or the thermal capacitors 932 of the second panel 1302. Depending on the type of attaching material 1304 used, the attaching material 1304 may be cured, reflowed, etc. to attach the thermal capacitor 932 to the corresponding substrate 902.

[0097] Fig.16 A top view of one of the interconnected thermal capacitors 932 is shown after being attached to the corresponding substrate 902. As an example, Fig.16 Mapping different edges of the stacked structure to Fig.12 Exemplary embodiment shown.

[0098] The method also includes, after attachment, cutting (e) through the area of ​​the first panel 1300 interconnecting the substrate 902 and through the area of ​​the second panel 1302 interconnecting the thermal capacitors 932 to form individual packages 1306. Each individual package 1306 includes a substrate 902, a power semiconductor die (not visible) embedded in the substrate, and a thermal capacitor 932 attached to the substrate 902, the thermal capacitor 932 being designed to absorb transient heat pulses from the power semiconductor die included in the same package 902 as the thermal capacitor 932, and subsequently release the transient heat pulses to the surrounding environment, for example, as previously described herein in conjunction with Figures 9 to 12 described.

[0099] exist Fig.13 The panels 1300, 1302 are cut in the x and y directions. Fig.13 908, and the cutting can be accomplished by sawing, laser etching, stamping, etc. For example, in the case of stamping, the cutting can be performed continuously (one row at a time in the x and y directions) or simultaneously. As previously explained herein, the (lateral) boundaries of each thermal capacitor 932 can be spaced inwardly from the (lateral) boundaries of each substrate core 908 to prevent damage / contamination of the thermal capacitors 932 during the cutting / packaging singulation process.

[0100] Fig.17 1 shows a cross-sectional view of another embodiment of a semiconductor package 1700. According to this embodiment, the semiconductor package 1700 includes an electrically insulating core 1702 having a first side 1704, a second side 1706 opposite the first side 1704 and configured for mounting to another substrate (not shown), and at least one electrically conductive first via 1708 extending through a peripheral region 1710 of the core 1702. The peripheral region 1710 defines an opening 1712 in the core 1702. As shown in FIG. Fig.17As shown in the upper enlarged view of , the core 1702 includes glass fibers 1714 interwoven with an epoxy material 1716. The core 1702 has one or more areas 1718 at the second (mounting) side 1706 in which the glass fibers 1714 are exposed from the epoxy material 1716.

[0101] At least one power semiconductor die 1720 is embedded in the opening 1712 in the core 1702. The power semiconductor die 1720 is thinner than the core 1702 (“T_die” ≤ “T_core”) and has a first load terminal (e.g., drain) bonding pad 1722 at a first side facing in the same direction as the first side 1704 of the core 1702, a second load terminal (e.g., source) bonding pad 1724 at a second side facing in the same direction as the second (mounting) side 1706 of the core 1702, and a control terminal bonding pad 1726 at the first side or the second side of the power semiconductor die 1720.

[0102] The resin 1728 fills the opening 1712 in the core 1702 and encases the power semiconductor die 1720. At least one plated first contact pad 1730 at the second (mounting) side 1706 of the core 1702 is provided by the first via 1708. The plated second contact pad 1732 at the first side 1704 of the core 1702 is provided by the first load terminal bond pad 1722 of the power semiconductor die 1720. The plated third contact pad 1734 at the second side 1706 of the core 1702 is provided by the second load terminal bond pad 1724 of the power semiconductor die 1720. The plated fourth contact pad 1736 is provided by the control terminal bond pad 1726 of the power semiconductor die 1720.

[0103] The optional solder mask 1738 covers one or more areas 1710 at the second side 1706 of the core 1702 where the glass fibers 1714 are exposed from the epoxy material 1716. Thus, when the package 1700 is subsequently mounted to a substrate (e.g., a circuit board) with the second side 1706 of the core 1702 facing the substrate, the exposed glass fibers 1714 will not be easily visible. With an optimal die design, the solder mask 1738 may be omitted.

[0104] The glass fibers 1714 are exposed from the epoxy material 1716 during the removal of the resin material 1728 from the second side 1706 of the core 1702, which is accomplished by a dry plasma process. Thus, the resin 1728 is formed coplanar with the first side 1704 of the core 1702, so that the resin 1728 does not need to be removed by dry plasma etching at the first side 1704 of the core 1702 (which is the visible side after the package 700 is mounted).

[0105] according to Fig.17 In the illustrated embodiment, there is a depression 1740 on the second (mounting) side 1706 of the package 1700. The depression 1740 is deeper than the other pad areas. Since larger solder balls may sink into the depression 1740, which may result in reduced thermal and / or electrical performance of the device, solder balls (not shown) may be added under carefully controlled conditions before the package is shipped. In this way, the package can be shipped. Fig.17 The semiconductor package 1700 shown in FIG. 1 previously solves any problems associated with larger solder balls.

[0106] Next is the description of production Fig.17 An embodiment of a method of semiconductor packaging 1700 is shown.

[0107] Fig.18 Shows production Fig.17 1700. The method includes positioning an electrically insulating core 1702 (a) with a first side 1704 of the core 1702 facing downward and a second side 1706 of the core 1702 facing upward. As previously explained herein, the second side 1706 of the core 1702 is configured for mounting to another substrate, and at least one conductive first via 1708 extends through a peripheral region 1710 of the core 1702. The peripheral region 1710 defines an opening 1712 in the core 1702, and the core 1702 includes glass fibers interwoven with an epoxy material. In one embodiment, the core 1702 is a FR4 prepreg (prepreg) material.

[0108] The method also includes placing (a) at least one power semiconductor die 1720 in the opening 1712 in the core 1702. The power semiconductor die 1720 is thinner than the core 102 and has a first load terminal bonding pad 1722 facing downward in the same direction as the first side 1704 of the core 1702, a second load terminal bonding pad 1724 facing upward in the same direction as the second side 1706 of the core 1702, and a control terminal bonding pad 1726 at the first side or the second side of the power semiconductor die 1720.

[0109] The method also includes filling (a) the opening 1712 in the core 1702 with a resin material 1728 encasing the power semiconductor die 1720 at the second side 1706 of the core 1702 .

[0110] The method further includes reducing (b) the thickness of the resin 1728 in the area overlying the second load terminal bonding pad 1724 of the power semiconductor die 1720 at the second side 1706 of the core 1702. If the control terminal bonding pad 1726 is disposed on the same side of the die 1720 as the second load terminal bonding pad 1724, the thickness of the resin 1728 in the area overlying the control terminal bonding pad 1726 of the power semiconductor die 1720 is also reduced. In one embodiment, the thickness of the resin 1728 in the area overlying the second load terminal bonding pad 1724 of the die 1720 is (partially) reduced by laser etching / drilling 1800 the area of ​​the resin 1728 overlying the second load terminal bonding pad 1724 of the die 1720 at the second side 1706 of the core 1702. If the control terminal bond pads 1726 are disposed on the same side of the die 1720 as the second load terminal bond pads 1724 , areas of the resin 1728 covering the control terminal bond pads 1726 of the power semiconductor die 1720 are also laser etched at the second side 1706 of the core 1702 .

[0111] The method further includes, after reducing the thickness of the resin 1728 in the target area, thinning (c) the resin 1728 to expose the first via 1708 and the second load terminal bonding pad 1724 of the power semiconductor die 1720. If the control terminal bonding pad 1726 is disposed on the same side of the die 1720 as the second load terminal bonding pad 1724, thinning (c) the resin 1728 also exposes the control terminal bonding pad 1726. In one embodiment, the resin 1728 is thinned at the second side 1706 of the core 1702 to expose the first via 1708, the second load terminal bonding pad 1724 of the power semiconductor die 1720, and optionally the control terminal bonding pad 1726 of the die 1720 by plasma etching the resin 1728 at the second side 1706 of the core 1720. The plasma etching process exposes glass fibers 1714 from epoxy material 1716 of core 1702 in one or more areas 1718 at second side 1706 of core 1702. However, since second side 1706 of core 1702 is the mounting side, the exposed fibers will not be visible after package mounting.

[0112] The method may further include: plating (d) the first via 1708 at the second side 1706 of the core 1702 to form a plated first contact pad 1730 at the second side 1706 of the core 1702. In one embodiment, the first via 1708 at the second side 1706 of the core 1702 is plated with Cu. Surface non-uniformities present at one or more regions 1718 at the second (mounting) side 1706 of the core 1702, where the glass fibers 1714 are exposed from the epoxy material 1716, may be transferred to the plated first contact pad 1730 at the second side 1706 of the core 1702. The second load terminal bonding pad 1724 of the power semiconductor die 1720 is also plated (d) to form a plated second contact pad 1734 at the second side 1706 of the core 1702. If the control terminal bond pad 1726 is disposed on the same side of the die 1720 as the second load terminal bond pad 1724 , the control terminal bond pad 1726 may also be plated (d) to form a plated third contact pad 1736 on the second side 1706 of the core 1702 .

[0113] The method may further include plating (d) an unmasked area on the first side 1704 of the core 1702 to form a metallization 1732 electrically connecting the first load terminal bonding pad 1722 of the power semiconductor die 1720 to the first via 1708 at the first side 1704 of the core 1702. In one embodiment, the metallization 1732 is formed by plating Cu onto the unmasked area at the first side 1704 of the core 1702.

[0114] The method also includes partially covering (e) one or more regions 1710 at the second side 1706 of the core 1702 with a solder mask 1802, where the glass fibers 1714 are exposed from the epoxy material 1716. Thus, the surface of the plated first contact pad 1730 is not uniform and portions that are not contacted by interconnects such as solder balls, Cu pillars, etc. are covered by the solder mask 1802.

[0115] FIG. 19A to FIG. 19D An alternative embodiment is shown, in which Fig. 9 The non-mounting side of the package 900 shown is processed, but there is no Fig.18 The laser thinning step shown in (b). FIG. 19A to FIG. 19D Each of the figures includes a cross-sectional view (a) and a corresponding top view (b) of a package during different production stages.

[0116] exist Fig.19A In the embodiment, the core 908 is processed with the second (mounting) side 906 facing downward so that the resin 915 covers the first side 904 of the core 908. Fig.19A1 and 2. The resin 915, which in this case comprises glass fibers interwoven with an epoxy material, has been thinned by a plasma process. If preferred, the resin 915 may be completely removed from the first side 904 of the core 908 so that only thinned areas of the resin 915 remain over the first load terminal bonding pads 918 of the power semiconductor die 916. A mask 1900 is formed over the thinned resin 915, for example by sputtering a layer of material over the thinned resin 915.

[0117] As previously combined Fig. 9 As described, at least one power semiconductor die 916 is placed in an opening 914 in the core 915. The power semiconductor die 916 is thinner than the core 915 (“T_die” ≤ “T_core”) and includes a first load terminal (e.g., drain) bonding pad 918 facing upward in the same direction as the first side 904 of the core 908, and a second load terminal (e.g., source) bonding pad 920 facing downward in the same direction as the second side 906 of the core 908. The opening 914 in the core 908 is filled with a resin 915 that encapsulates the power semiconductor die 916.

[0118] exist Fig.19B In the embodiment of the present invention, a photoresist 1902 is formed on the sputtered layer 1900. The photoresist 1902 has a first opening 1904 aligned with the first via 910 and a second opening 1906 aligned with the first load terminal bonding pad 918 of the power semiconductor die 916.

[0119] exist Fig.19C In the process, the first opening 1904 and the second opening 1906 in the photoresist 1902 are transferred to the underlying mask 1900, for example by etching, in which the etching chemistry depends on the material of the mask 1900. The mask 1900 now has a first opening 1904 aligned with the first via 910, and a second opening 1906 aligned with the first load terminal bonding pad 918 of the power semiconductor die 916.

[0120] exist Fig.19D 908, the photoresist 1902 is removed, and the resin 915 is etched through the first opening 1904 to expose the first via 910, and is etched through the second opening 1906 to expose the first load terminal bonding pad 918 of the power semiconductor die 916. After the etching of the resin 915, the sputtered layer 1900 can be removed from the thinned resin 915. The exposed first via 910 and the exposed first load terminal bonding pad 918 of the power semiconductor die 916 can be plated, for example, with Cu to connect the first load terminal bonding pad 918 of the die 916 to the first via 910 at the first side 904 of the die 908. For example, as Fig. 9As shown, the first via 910 and the bonding pads 920 , 922 on the other side of the power semiconductor die 916 may also be plated, for example, with Cu, to form corresponding contact pads on the second side 906 of the core 908 .

[0121] Although the present disclosure is not limited in this regard, the following numbered examples illustrate one or more aspects of the present disclosure.

[0122] Example 1. A semiconductor package, comprising: an insulating substrate having a first main side and a second main side opposite to the first main side; a power semiconductor die embedded in the insulating substrate and thinner than or as thick as the insulating substrate, the power semiconductor die comprising a first load terminal bonding pad on a first side facing in the same direction as the first main side of the insulating substrate, a second load terminal bonding pad at a second side facing in the same direction as the second main side of the insulating substrate, and a control terminal bonding pad at the first side or the second side; a conductive first via extending through the insulating substrate in a peripheral area laterally surrounding the power semiconductor die; a first metallization portion connecting the first load terminal bonding pad of the power semiconductor die to the first via at the first main side of the insulating substrate; a solderable first contact pad at the second main side of the insulating substrate and formed by the first via; and a solderable second contact pad at the second main side of the insulating substrate and formed by the second load terminal contact pad of the power semiconductor die.

[0123] Example 2. A semiconductor package according to Example 1, wherein the control terminal bonding pad is at the second side of the power semiconductor die, and the semiconductor package further comprises: a solderable third contact pad, which is at the second main side of the insulating substrate and is formed by the control terminal bonding pad of the power semiconductor die.

[0124] Example 3. A semiconductor package according to Example 1, wherein the control terminal bonding pad is at the first side of the power semiconductor die, and the semiconductor package further includes: a conductive second via extending through the insulating substrate in the peripheral region; a second metallization portion connecting the control terminal bonding pad of the power semiconductor die to the second via at the first main side of the insulating substrate; and a solderable third contact pad at the second main side of the insulating substrate and formed by the second via.

[0125] Example 4. The semiconductor package of any one of Examples 1 to 3, wherein the insulating substrate includes a first material in which the power semiconductor die is embedded and a second material that is different from the first material and forms a peripheral region.

[0126] Example 5. The semiconductor package of any of Examples 1 to 4, wherein the first via, the first metallization, and the first load terminal bond pad of the power semiconductor die each comprise copper.

[0127] Example 6. The semiconductor package of any of Examples 1 to 3, wherein the second solderable contact pad is coplanar with the first solderable contact pad at the second main side of the insulating substrate.

[0128] Example 7 The semiconductor package of any one of Examples 1 to 3, further comprising: a solder mask at least partially covering the first metallization at the first main side of the insulating substrate.

[0129] Example 8. The semiconductor package of Example 7, wherein the solder mask covers the entire first main side of the insulating substrate.

[0130] Example 9. The semiconductor package of any one of Examples 1 to 3, further comprising: a heat sink attached to the first metallization at the first main side of the insulating substrate.

[0131] Example 10. A semiconductor package according to any one of Examples 1 to 3, further comprising: an additional power semiconductor die embedded in an insulating substrate and thinner than the insulating substrate or as thick as the insulating substrate, the additional power semiconductor die comprising a first load terminal bonding pad at a first side facing in the same direction as a second main side of the insulating substrate, a second load terminal bonding pad at a second side facing in the same direction as the first main side of the insulating substrate, and a control terminal bonding pad at the first side or the second side; and a solderable additional contact pad at the second main side of the insulating substrate and formed by the first load terminal bonding pad of the additional power semiconductor die, wherein a first metallization portion connects the first load terminal bonding pad of the power semiconductor die to the second load terminal bonding pad of the additional power semiconductor die in a half-bridge configuration at the first main side of the insulating substrate.

[0132] Example 11. A method for producing a semiconductor package, the method comprising: embedding a power semiconductor die in an insulating substrate, the insulating substrate having a first main side and a second main side opposite to the first main side, the power semiconductor die being thinner than the insulating substrate or as thick as the insulating substrate, and comprising a first load terminal bonding pad at a first side facing in the same direction as the first main side of the insulating substrate, a second load terminal bonding pad at a second side facing in the same direction as the second main side of the insulating substrate, and a control terminal bonding pad at the first side or the second side; and forming a first metallization portion at the first main side of the insulating substrate, the first metallization portion connecting the first load terminal bonding pad of the power semiconductor die to a conductive first via, the conductive first via extending through the insulating substrate in a peripheral area laterally surrounding the power semiconductor die, wherein the first via forms a solderable first contact pad at the second main side of the insulating substrate, and wherein the second load terminal bonding pad of the power semiconductor die forms a solderable second contact pad at the second main side of the insulating substrate.

[0133] Example 12. A method according to Example 11, wherein forming the first metallization portion includes: forming a solder mask on a first main side of an insulating substrate, the solder mask having an opening, the opening exposing at least a portion of a first load terminal bonding pad of the power semiconductor die and exposing at least a portion of a first via; and depositing copper in the opening of the solder mask.

[0134] Example 13. The method of Example 12, wherein the control terminal bonding pad is at a second side of the power semiconductor die, and wherein the control terminal bonding pad of the power semiconductor die forms a solderable third contact pad at the second main side of the insulating substrate.

[0135] Example 14. A method according to Example 12, wherein the control terminal bonding pad is on the first side of the power semiconductor die, wherein a conductive second via extends through the insulating substrate in the peripheral region and forms a solderable third contact pad at the second main side of the insulating substrate, the method further comprising: forming a second metallization portion at the first main side of the insulating substrate, the second metallization portion connecting the control terminal bonding pad of the power semiconductor die to the second via at the first main side of the insulating substrate.

[0136] Example 15. The method according to any one of Examples 11 to 14 further includes: embedding an additional power semiconductor die in an insulating substrate, wherein the additional power semiconductor die is thinner than the insulating substrate or as thick as the insulating substrate, and includes a first load terminal bonding pad at a first side facing in the same direction as the second main side of the insulating substrate, a second load terminal bonding pad at a second side facing in the same direction as the first main side of the insulating substrate, and a control terminal bonding pad at the first side or the second side, wherein the first load terminal bonding pad of the additional power semiconductor die forms a solderable additional contact pad at the second main side of the insulating substrate, and wherein the first metallization portion connects the first load terminal bonding pad of the power semiconductor die to the second load terminal bonding pad of the additional power semiconductor die in a half-bridge configuration at the first main side of the insulating substrate.

[0137] Example 16. A method according to any one of Examples 11 to 15, wherein embedding a power semiconductor die into an insulating substrate includes: adhering the insulating substrate to a temporary bonding tape at a second main side of the insulating substrate; inserting the power semiconductor die into an opening of the insulating substrate so that the power semiconductor die adheres to the temporary bonding tape at the second side of the power semiconductor die; and after inserting the power semiconductor die into the opening of the insulating substrate, filling the opening and covering the power semiconductor die with a resin film.

[0138] Example 17. The method according to Example 16 further includes: removing the temporary bonding tape after filling the opening and covering the power semiconductor die with a resin film; flattening the resin film at the first main side of the insulating substrate; and removing the resin film from at least a portion of the first load terminal bonding pad at the first side of the power semiconductor die.

[0139] Example 18. A method according to Example 17, wherein forming a first metallization portion at a first main side of an insulating substrate includes: forming a seed layer on the first main side of the insulating substrate and on a portion of a first load terminal bonding pad of a power semiconductor die exposed by removing a resin film; plating copper on the seed layer; and patterning the plated copper to define the first metallization portion.

[0140] Example 19. The method according to any one of Examples 11 to 18, further comprising: adhering an additional insulating substrate to a side of a temporary bonding tape opposite to the insulating substrate, or to a temporary carrier between the insulating substrate and the additional insulating substrate; inserting an additional power semiconductor die into an opening of the additional insulating substrate so that the additional power semiconductor die adheres to the temporary bonding tape or the temporary carrier; and after inserting the additional power semiconductor die into the opening of the additional insulating substrate, filling the opening of the additional insulating substrate and covering the additional power semiconductor die with an additional resin film.

[0141] Example 20. A method of manufacturing a plurality of semiconductor packages, the method comprising: adhering a core insulating panel having a plurality of openings to a temporary bonding tape at a second main side of the core insulating panel opposite to the first main side; inserting a power semiconductor die into each opening of the core insulating panel, each power semiconductor die being thinner than the core insulating panel or as thick as the core insulating panel and comprising a first load terminal bonding pad at a first side facing in the same direction as the first main side of the core insulating panel, a second load terminal bonding pad at a second side facing in the same direction as the second main side of the core insulating panel, and a control terminal bonding pad at the first side or the second side, wherein each power semiconductor die is adhered to the temporary bonding tape at the second side of the power semiconductor die; A first metallization layer is formed at a first main side of the board, the first metallization layer being patterned into a plurality of first metallization portions, each first metallization portion being associated with one of the power semiconductor die and connecting a first load terminal bonding pad of the power semiconductor die to a corresponding conductive first via extending through the core insulating panel in a peripheral region laterally surrounding the power semiconductor die; and the core insulating panel is singulated into a plurality of packages, wherein, for each package, the first via included in the package forms a solderable first contact pad at a second main side of the singulated core insulating panel, and the second load terminal bonding pad of the power semiconductor die included in the package forms a solderable second contact pad at the second main side of the singulated core insulating panel.

[0142] Example 21. A semiconductor package comprising: a substrate having a first main surface, a second main surface opposite to the first main surface, an electrically insulating core between the first and second main surfaces, and a conductive first via extending through a peripheral area of ​​the core, the peripheral area defining an opening in the core; a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core or as thick as the core, the power semiconductor die comprising a first load terminal bonding pad at a first side facing in the same direction as the first main surface of the substrate, a second load terminal bonding pad at a second side facing in the same direction as the second main surface of the substrate, and a control terminal bonding pad at the first side or the second side; a plated first contact pad at the second main surface of the substrate and provided by the first via; a plated second contact pad at the second main surface of the substrate and provided by the second load terminal bonding pad of the power semiconductor die; and a thermal capacitor attached to the first main surface of the substrate, the thermal capacitor being designed to absorb transient heat pulses from the power semiconductor die and subsequently release the transient heat pulses to the surrounding environment.

[0143] Example 22. The semiconductor package of Example 21, wherein a thickness of the thermal capacitor is based on a magnitude of the transient thermal pulse.

[0144] Example 23. The semiconductor package of Example 22, wherein the magnitude of the transient heat pulse is in a range of 5 to 25 Joules, and wherein the thickness of the thermal capacitor is in a range of 500 to 2500 μm.

[0145] Example 24. A semiconductor package according to any one of Examples 21 to 23, wherein a first metallization at a first major surface of the substrate electrically connects a first load terminal bonding pad of the power semiconductor die to a first via, and wherein a thermal capacitor is attached to the first metallization or a plated surface of the first metallization.

[0146] Example 25. A semiconductor package according to any one of Examples 21 to 24, wherein the thermal capacitor is attached to the first via and to the first load terminal bonding pad of the power semiconductor die, and wherein the thermal capacitor electrically connects the first load terminal bonding pad to the first via.

[0147] Example 26. The semiconductor package of any of Examples 21 to 25, wherein the thermal capacitor has a lateral dimension that is smaller than a lateral dimension of the core such that a boundary of the thermal capacitor is spaced inwardly from a boundary of the core.

[0148] Example 27. A semiconductor package according to any one of Examples 21 to 26, wherein the thermal capacitor is attached to the first main surface of the substrate by solder, and wherein a boundary of the thermal capacitor has a protrusion that prevents the solder from reaching a surface of the thermal capacitor facing away from the substrate.

[0149] Example 28. The semiconductor package of any of Examples 21 to 27, wherein a surface of the thermal capacitor facing away from the substrate is structured to increase surface contact with the surrounding environment.

[0150] Example 29. A method for batch producing a plurality of semiconductor packages, the method comprising: aligning a first panel with a second panel, the first panel comprising a plurality of interconnected substrates having openings and a power semiconductor die embedded in each opening, the second panel comprising a plurality of interconnected thermal capacitors aligned with corresponding ones of the substrates; attaching each thermal capacitor to the corresponding substrate aligned with the thermal capacitor by attaching material applied to the substrate of the first panel and / or the thermal capacitor of the second panel; and after attaching, cutting through the area of ​​the first panel interconnecting the substrates, and cutting through the area of ​​the second panel interconnecting the thermal capacitors to form individual packages, each individual package comprising a substrate, a power semiconductor die embedded in the substrate, and a thermal capacitor attached to the substrate, the thermal capacitor being designed to absorb transient thermal pulses from the power semiconductor die included in the same package as the thermal capacitor, and subsequently release the transient thermal pulses to the surrounding environment.

[0151] Example 30. A semiconductor package comprising: an electrically insulating core having a first side, a second side opposite the first side and configured for mounting to another substrate, and a conductive first via extending through a peripheral region of the core, the peripheral region defining an opening in the core, the core comprising glass fibers interwoven with an epoxy material; the core having one or more regions at the second side in which the glass fibers are exposed from the epoxy material; a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core and comprising a first load terminal at the first side facing in the same direction as the first side of the core a sub-bonding pad, a second load terminal bonding pad at the second side facing the same direction as the second side of the core, and a control terminal bonding pad at the first side or the second side of the power semiconductor die; a resin that fills the opening in the core and encapsulates the power semiconductor die; a plated first contact pad that is on the first side of the core and provided by the first via; a plated second contact pad that is on the second side of the core and provided by the first load terminal bonding pad of the power semiconductor die; and a solder mask that partially covers one or more areas at the second side of the core where the glass fibers are exposed from the epoxy resin material.

[0152] Example 31. A method for producing a semiconductor package, the method comprising: positioning an electrically insulating core with a first side of the core facing downward and a second side of the core facing upward, the second side being configured for mounting to another substrate, wherein a conductive first via extends through a peripheral region of the core, the peripheral region defining an opening in the core, wherein the core comprises glass fibers interwoven with an epoxy resin material; placing a power semiconductor die in the opening in the core, the power semiconductor die being thinner than the core and comprising a first load terminal bonding pad facing downward in the same direction as the first side of the core, and a second load terminal bonding pad facing upward in the same direction as the second side of the core; on the second side of the core: filling the opening in the core with a resin enveloping the power semiconductor die; reducing the thickness of the resin in the region covering the second load terminal bonding pad of the power semiconductor die; and after the reduction, thinning the resin to expose the first via and the second load terminal bonding pad of the power semiconductor die, the thinning exposing the glass fibers from the epoxy resin material in one or more regions at the second side of the core; and partially covering one or more regions at the second side of the core with a solder mask, in which the glass fibers are exposed from the epoxy resin material.

[0153] Example 32. A method according to Example 31, wherein reducing the thickness of the resin in the area covering the second load terminal bonding pad of the power semiconductor tube core includes: laser etching the area of ​​the resin covering the second load terminal bonding pad of the power semiconductor tube core at the second side of the core.

[0154] Example 33. The method of Example 31 or 32, wherein thinning the resin at the second side of the core to expose the first via and the second load terminal bonding pad of the power semiconductor die comprises plasma etching the resin at the second side of the core.

[0155] Example 34. The method of any one of Examples 31 to 33, further comprising: plating the first via at the second side of the core to form a plated first contact pad at the second side of the core.

[0156] Example 35. The method of Example 34, further comprising: plating the second load terminal bonding pad of the power semiconductor die to form a plated second contact pad at the second side of the core.

[0157] Example 36. The method of any one of Examples 31 to 35, further comprising: plating an unmasked area at the first side of the core to form a metallization that electrically connects a first load terminal bonding pad of the power semiconductor die to the via on the first side of the core.

[0158] Example 37. A method for producing a semiconductor package, the method comprising: positioning an electrically insulating core with a first side of the core facing upward and a second side of the core facing downward, the second side being configured for mounting to another substrate, wherein a conductive first via extends through a peripheral area of ​​the core, the peripheral area defining an opening in the core, wherein the core comprises glass fibers interwoven with an epoxy resin material; placing a power semiconductor die in the opening in the core, the power semiconductor die being thinner than the core and comprising a first load terminal bonding pad facing upward in the same direction as the first side of the core, and a second load terminal bonding pad facing downward in the same direction as the second side of the core; and on the first side of the core: filling the opening in the core with a resin enveloping the power semiconductor die; thinning the resin; forming a mask on the thinned resin, the mask having a first opening aligned with the first via, and a second opening aligned with the first load terminal bonding pad of the power semiconductor die; etching the resin through the first opening to expose the first via, and etching the resin through the second opening to expose the first load terminal bonding pad of the power semiconductor die.

[0159] Example 38. The method of Example 37, wherein forming a mask on the thinned resin comprises: sputtering a layer on the thinned resin; and forming a photoresist on the sputtered layer, the photoresist having a first opening and a second opening.

[0160] Example 39. The method of Example 38 further includes: after etching the resin, removing the sputtered layer from the thinned resin.

[0161] Example 40. The method of any one of Examples 37 to 39, wherein thinning the resin comprises completely removing the resin from the first side of the core such that only a thinned area of ​​the resin remains over the first load terminal bonding pad of the power semiconductor die.

[0162] Terms such as "first", "second", etc. are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, similar terms refer to similar elements.

[0163] As used herein, the terms "having", "comprising", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0164] It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0165] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: a substrate having a first major surface, a second major surface opposite the first major surface, an electrically insulating core between the first major surface and the second major surface, and an electrically conductive first via extending through a peripheral region of the core, the peripheral region defining an opening in the core; a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core or as thick as the core, the power semiconductor die comprising a first load terminal bonding pad at a first side facing in the same direction as the first major surface of the substrate, a second load terminal bonding pad at a second side facing in the same direction as the second major surface of the substrate, and a control terminal bonding pad at the first side or the second side; a plated first contact pad at the second major surface of the substrate and provided by the first via; a plated second contact pad at the second major surface of the substrate and provided by the second load terminal bond pad of the power semiconductor die; as well as a thermal capacitor attached to the first major surface of the substrate, the thermal capacitor being designed to absorb transient heat pulses from the power semiconductor die and subsequently discharge the transient heat pulses to an ambient environment, wherein the thermal capacitor is attached to the first main surface of the substrate by solder, and wherein a boundary of the thermal capacitor has a protrusion that prevents the solder from reaching a surface of the thermal capacitor facing away from the substrate.

2. The semiconductor package according to claim 1, wherein The thickness of the thermal capacitor is based on the magnitude of the transient thermal pulse.

3. The semiconductor package according to claim 2, wherein: The amplitude of the transient heat pulse is in the range of 5 to 25 Joules, and wherein the thickness of the thermal capacitor is in the range of 500 to 2500 μm.

4. The semiconductor package according to claim 1, wherein: A first metallization at the first major surface of the substrate electrically connects the first load terminal bonding pad of the power semiconductor die to the first via, and wherein the thermal capacitor is attached to the first metallization or to a plated surface of the first metallization.

5. The semiconductor package according to claim 1, wherein The thermal capacitor is attached to the first via and the first load terminal bond pad of the power semiconductor die, and wherein the thermal capacitor electrically connects the first load terminal bond pad to the first via.

6. The semiconductor package according to claim 1, wherein The thermal capacitor has a lateral dimension that is less than a lateral dimension of the core such that a boundary of the thermal capacitor is spaced inwardly from a boundary of the core.

7. The semiconductor package according to claim 1, wherein: The surface of the thermal capacitor facing away from the substrate is structured to increase the surface contact with the surrounding environment.

Images