Semiconductor switch with esd protection circuit

Abstract

Embodiments according to the present disclosure relate to semiconductor switches with ESD protection circuits. In the following a clamping circuit for protection against ESD events is described. According to one embodiment the circuit has a first transistor with a control terminal and a load current path, the first transistor being connected between a first contact and a second contact, an amplifier circuit with an amplifier input and an amplifier output, the amplifier circuit being connected with the control terminal of the transistor, and a trigger circuit connected between the first contact and the second contact and having a second transistor. The trigger circuit is designed to generate a voltage swing at the amplifier input in response to a discharge current at the first contact by driving a control terminal of the second transistor with at least a part of the discharge current through an intrinsic capacitance of the second transistor.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of semiconductor switches, in particular to a semiconductor switch with an active clamping circuit for protection against electrostatic discharges (ESD). BACKGROUND

[0002] Active clamping circuits, also called active clamping, are commonly used to activate a low-resistance current path between two pins of a semiconductor chip and to discharge the charge in case of an electrostatic discharge (ESD event). In particular, this scheme is commonly used in so-called high-voltage (HV) pins. In addition to the original function as a protection circuit in case of an ESD event, the clamping circuit should also fulfill other requirements, such as low chip area demand and low clamping voltage. It is also desirable that the clamping circuit is not switched on at high DC voltages, but only at a momentary electrostatic discharge. These requirements mean that the goals are in conflict, so that a compromise must be found. The inventors set the goal to improve the known clamping circuits. SUMMARY

[0003] The above-mentioned object is achieved by a circuit according to the invention. Different exemplary embodiments are the subject of the dependent claims. In the following, a clamping circuit for protection against ESD events is explained. According to one embodiment, the circuit has the following: a first transistor with a control terminal and a load current path, which is connected between a first contact and a second contact; an amplifier circuit with an amplifier input and an amplifier output, which is connected with the control terminal of the transistor; and a trigger circuit, which is connected between the first contact and the second contact and has a second transistor. The trigger circuit is designed to generate a voltage swing at the amplifier input in response to a discharge current at the first contact by driving the control terminal of the second transistor by at least a part of the discharge current through an intrinsic capacitance of the second transistor.

[0004] According to another embodiment, the circuit has the following: a first transistor with a control terminal and a load current path, which is connected between a first contact and a second contact; a first resistor, which is connected between the control terminal of the first transistor and the second contact; a second transistor with a control terminal and a load current path, which is connected between the control terminal of the first transistor and the first contact; a second resistor, which is connected between the control terminal of the second transistor and the first contact; a third transistor with a load current path, which is connected between the control terminal of the second transistor and the second contact; and a third resistor, which is connected between the control terminal of the third transistor and the second contact. BRIEF DESCRIPTION OF DRAWINGS

[0005] Embodiments are explained in more detail below with reference to the drawings. The drawings do not necessarily show the aspects to scale, and the embodiments are not limited to the aspects shown. Instead, the focus is on explaining the principles on which the embodiments are based. Among others:

[0006] Figure 1 An example of a semiconductor switch with a clamping circuit for protection in case of electrostatic discharge is shown.

[0007] Figure 2 A first embodiment of a semiconductor switch with an improved clamping circuit is shown.

[0008] Figure 3 A second embodiment is shown, which is an extension of the example in Figure 2

[0009] Figure 4 Another embodiment is shown, in which two clamping circuits according to Figure 2 are connected in series ("stacked").

[0010] Figure 5 A chip with three input / output pins is shown, which are protected by means of a clamping circuit in case of an ESD event. DETAILED DESCRIPTION

[0011] Figure 1 An example of a semiconductor switch with an active clamping circuit for protection in case of electrostatic discharge is shown. The semiconductor switch can be a power semiconductor switch and is in Figure 1 denoted M L in the figures. The semiconductor switch M L ​Connected between two pins PIN1 and PIN2 of the semiconductor chip, and implemented in this example as a MOS field-effect transistor (e.g., a DMOS transistor) (MOS = Metal-Oxide-Semiconductor, DMOS = Double-Diffused Metal-Oxide-Semiconductor). The semiconductor switch is adjusted according to the amount of material fed to transistor M. L The control signal of the control electrode is used to turn the transistor on and off. In the case of a MOS transistor, the control signal is the gate voltage V of the MOS transistor. G The gate voltage V G It is applied to the gate of the MOS transistor. For simplicity of illustration, Figure 1 Basically contains only transistor M L And active clamping circuit.

[0012] according to Figure 1 The clamping circuit has an amplifier circuit, which mainly consists of a resistor and another MOS transistor M. P It is constructed and operates as a source circuit. The amplifier circuit has an amplifier input terminal and an amplifier output terminal. The amplifier output terminal is connected to a semiconductor switch M. L The control electrode is connected. Specifically, the MOS transistor M... P The load current path (drain-source current path) is connected to the semiconductor switch M. L Between the gate and the first pin PIN1, and resistor R GSn Connected to semiconductor switch M L Between the gate and the second pin PIN2. MOS transistor M P It is a p-channel transistor; its drain is connected to the semiconductor switch M. L The gate connection. MOS transistor M P The gate of the MOS transistor is the amplifier input terminal. P The drain of the amplifier is the output terminal.

[0013] resistor R GSn The voltage drop across the terminals can be considered as the amplifier output signal, which is fed as the gate voltage to the semiconductor switch M. L The gate of the amplifier. In summary, the signal applied to the amplifier input (in this example, i.e., the MOS transistor M) P Gate-source voltage V IN The signal is amplified, and the amplified signal is used as a control signal (gate voltage V). G It is fed to semiconductor switch M L The control electrode.

[0014] The input signal (voltage V) of the amplifier circuit is generated by means of a trigger circuit. IN The trigger circuit is inFigure 1 The example uses an RC circuit. An RC circuit is a series circuit of a resistor and a capacitor. In this example, the resistor R... GSp Connect the first pin PIN1 and the amplifier input (in this example, i.e., the MOS transistor M). P The capacitor C is connected between the amplifier input and the second pin PIN2.

[0015] like Figure 1 As shown, in the event of electrostatic discharge between pins PIN1 and PIN2, a current i will be generated flowing from the first pin PIN1 to the second pin PIN2. ESD For the following description, assume that the semiconductor switch M... L Initially in the off state. In this case, the discharge current i ESD (This may be due to electrostatic discharge at pin PIN1) will first flow through the trigger circuit (i.e., through the RC circuit R). GSp (C), thereby generating an input voltage V at the amplifier input terminal. IN (i.e., discharge current i) ESD Multiply by resistor R GSp The resistance value), the input voltage V IN Transistor M P Amplification. The amplified signal (gate voltage V) G The resulting gate current then causes the semiconductor switch M to... L When the circuit is closed, the semiconductor switch M... L Establish a low-resistance current path between pins PIN1 and PIN2, and make the discharge current i ESD It can flow out without causing damage.

[0016] Zener diode chain D GSp and D GSn It is used solely to limit voltage and protect the gate (and especially the gate oxide) from excessive voltage. Zener diodes used to protect the gate from overvoltage are known in themselves and will not be described further here.

[0017] It should be mentioned in this regard that the RC circuit (trigger circuit) enables the dynamic activation of the clamping circuit. That is, through the discharge current i ESD The rapid rise in voltage activates the clamping circuit. The on-time of the clamping circuit is essentially determined by the time constant τ = R. GSpThe designation C dictates that capacitor C must be designed to withstand the maximum possible voltage (HV capacitor) between pins PIN1 and PIN2. In the case of HV pins (i.e., designed for voltages above 20V), this capacitor must be implemented using a metal plate disposed within the chip's metallization layer. Such capacitors occupy a considerable amount of chip area. For example, capacitor C can occupy 20% to 30% of the clamping circuit area.

[0018] Static activation via a DC voltage between pins PIN1 and PIN2 is not possible (and is not desirable). Such a DC voltage would only charge capacitor C without turning on the MOS transistor M for a considerable period of time. P (Except for the short period during the rapid rising edge).

[0019] As a first embodiment, Figure 2 A semiconductor switch M with an improved clamping circuit is shown. L . Figure 2 The circuits in Figure 1 The main difference in the circuit lies in the implementation of the trigger circuit, which in... Figure 2 The symbol is TRIG. The remaining circuit components (especially the amplifier circuit AMP, Zener diode chain D) GSn D GSp and the semiconductor switch M connected between pins PIN1 and PIN2. L The pins PIN1 and PIN2 are the same, and refer to the description above. PIN1 and PIN2 can be any chip contact of the semiconductor chip. The shape of the pins depends on the chip package used. Depending on the chip package, the contacts can be designed as, for example, solder pins or solder balls.

[0020] according to Figure 2 In the embodiment described, the trigger circuit TRIG of the clamping circuit includes a resistor R. GSp The resistor R GSp Connect to the first pin PIN1 and the amplifier input (e.g., MOS transistor M). P Between the gates. However, the trigger circuit TRIG does not include a capacitor as a separate dedicated device, especially not an HV capacitor, which, as mentioned above, would occupy a relatively large area. Instead, the trigger circuit TRIG includes another MOS transistor M. X The other MOS transistor M X The load current path is connected between the amplifier input and the second pin PIN2, where the MOS transistor M X The gate is connected to another resistor R. GSn,2It is also coupled to the second pin, PIN2. Like every MOS transistor, the MOS transistor M... X It has inherent capacitance C GS and C DG (Gate-source capacitance and gate-drain capacitance), however, these inherent capacitances are not independent devices and, in particular, do not require additional chip area. The inherent capacitances and other parasitic capacitances different from inherent capacitances are too small to be accounted for. Figure 1 The function of capacitor C in the example. However, in response to an ESD event (discharge current i... ESD Through inherent capacitance, especially drain-gate capacitance C DG Transistor M can be X The control enters the conduction state. When transistor M... X When the circuit begins to conduct, at the input terminal of the amplifier circuit AMP (i.e., at the transistor M) P The gate of the input voltage V generates a voltage swing. IN This voltage swing—amplified by the amplifier circuit—causes power transistor M to... L Connected.

[0021] As in the previous example, for the following description, assume that the semiconductor switch M L Initially in the off state. In this state, if an ESD event occurs, the discharge current i ESD The current will first flow through the trigger circuit because the MOS transistor M P Initially, it was not conducting. This was due to the capacitive coupling between the drain and gate (gate-drain capacitance C). GD Discharge current i ESD The rapid instantaneous rise will cause the MOS transistor M X The circuit is switched on. Therefore, the current i... ESD It can flow through resistor R GSp and MOS transistor M X This generates a voltage signal V at the amplifier input. IN The amplified signal (gate voltage V) G The resulting gate current then causes the semiconductor switch M to... L When the semiconductor switch M is turned on, then the semiconductor switch M L Establish a low-resistance current path between pins PIN1 and PIN2, and make the discharge current i ESD It can flow out without causing damage. For ESD protection purposes, the semiconductor switch M can be... L Consider the discharge current i as derived through a low-resistance current path. ESD The splitter.

[0022] The trigger circuit TRIG allows for dynamic activation of the clamping circuit, which can be activated by the discharge current i. ESD The rapid rise is used for activation. In this example, the time constant τ is τ = R. GSn,2 ·C GS C GS This represents the gate-drain capacitance. It is determined by the resistor R. GSn,2 Properly designed resistor values ​​can set the desired time constant. Static activation of the clamping circuit will not occur.

[0023] Because the clamping circuit can be dynamically activated, it is not necessary to exceed a static (predefined) threshold voltage to activate the clamp. The trigger circuit responds to the current i at pin PIN1. ESD The steep edges. No large capacitors are needed (in terms of area requirements), therefore the clamping circuit can be implemented on a relatively small chip area overall. The MOS transistor M in the TRIG trigger circuit. X It can have a semiconductor switch M L The same transistor type. Therefore, the maximum allowable voltage between pins PIN1 and PIN2 is determined by transistor M. X M L The breakdown voltage is determined, rather than by other components (such as in...). Figure 1 In the example, this is determined by capacitor C. Furthermore, simple deactivation of the trigger circuit (and thus deactivation of the clamping circuit) can be achieved relatively easily. An example of this is in... Figure 3 As shown in the image.

[0024] Figure 3 It shows Figure 2 Modification / expansion of the circuit. Figure 3 The circuits in Figure 2 The circuit is the same, but it includes three additional transistors M. P0 M X0 and M L0 The following discussion will focus solely on these additional transistors and their functions. For the remainder, please refer to [link to relevant information]. Figure 2 Explanation of transistor M. P0 The load current path will be transistor M P Gate and transistor M P The source is connected. When transistor M... P0 When switched on, the gate and source are shorted, and the transistor M in the amplifier circuit AMP... P It can no longer be driven to conduct. In other words, transistor M P0 Coupled to the amplifier circuit and configured such that the transistor M P0 This can deactivate the amplifier circuit AMP and prevent the activation of the clamping circuit. Transistor M P0It can be a p-channel MOSFET and can receive the logic signal EN as a gate signal.

[0025] Transistor M X0 The load current path will be transistor M X Gate and transistor M X The source is connected. When transistor M... X0 When switched on, the gate and drain are shorted, and the transistor M of the trigger circuit TRIG is activated. X It can no longer be driven to conduct. In other words, transistor M X0 Coupled with the trigger circuit TRIG and configured to cause transistor M X0 The trigger circuit TRIG can be deactivated and the clamping circuit can be prevented from being activated. Transistor M X0 It can be an n-channel MOSFET and can receive logic signals. This logic signal serves as the gate signal. It is the inverted form of the logic signal EN. Figure 3 In the example shown, transistor M L0 The load current path will be transistor M L The gate of the (semiconductor switch) and the transistor M L The source connection. Transistor M L0 Similarly, logic signals can be used. Turn on, thereby turning on transistor M L The gate and source are shorted, preventing transistor M from being turned on. L The low level of the logic signal EN (corresponding to the inverting logic signal) A high level (EN signal) deactivates the clamping circuit. The signal will deactivate the clamping circuit, optionally via transistor M. P0 M L0 Or M X0 It can be implemented using one of the transistors, or by using a combination of two or more of these transistors.

[0026] It should be understood that in the examples described here, the MOS transistor can be replaced by other types of transistors. For example, a bipolar transistor, particularly an insulated-gate bipolar transistor (IGBT), can be used instead of a MOS transistor. In this case, the terms source and drain refer to the emitter and collector of the corresponding IGBT.

[0027] Figure 4 Another embodiment is shown, in which two clamping circuits 1a and 1b are connected in series (stacked configuration). ReferenceFigure 3 The described extension can also be used in the example of Figure 4 The clamping circuit 1a comprises a semiconductor switch M L,1 , and a corresponding amplifier circuit AMP1 and a trigger circuit TRIG1, connected between the first pin PIN1 and a circuit node N. The clamping circuit 1a is identical to the clamping circuit 1 in Figure 2 and the only difference is that the clamping circuit 1a is not connected between two pins (PIN1 and PIN2), but between the first pin PIN1 and an internal circuit node N. The clamping circuit 1b comprises a semiconductor switch M L,2 , and a corresponding amplifier circuit AMP2 and a trigger circuit TRIG2, connected between the circuit node N and the second pin PIN2. The clamping circuit 1b is likewise identical to the clamping circuit 1 in Figure 2 but, as mentioned above, the clamping circuit 1b is connected between the internal circuit node N and the second pin PIN2. It is to be understood that more than two clamping circuits can also be connected in series to further increase the voltage strength of the component.

[0028] Generally, a clamping circuit is connected between an input pin (or an output pin, e.g. PIN1) and a ground pin (e.g. PIN2) to protect the electronic device coupled to the input pin from potentially harmful ESD events. Figure 5 The example in 1A shows the clamping circuit 1b for protecting multiple pins PIN 1B , PIN 1C from ESD events. To this end, the clamping circuit 1b is connected between a circuit node N and a chip pin (e.g. a ground pin) Figure 5 in 1A , PIN 1B , PIN 1C (input / output pins) are each coupled to the circuit node N via a diode D1 and the pin PIN2 is coupled to the pins PIN 1A , PIN 1B , PIN 1C via a diode D2, wherein the cathode of the diode D1 and the anode of the diode D2 are connected to the clamping circuit 1b. When an ESD event occurs, for example at the pin PIN 1A , a discharge current i ESD may flow, for example via the corresponding diode D1 and the clamping circuit 1b, to the pin PIN2, which is connected to ground.

Claims

1. A circuit comprising: a first transistor comprising a control terminal and a load current path connected between a first contact and a second contact; an amplifier circuit comprising an amplifier input and an amplifier output, the amplifier circuit connected with the control terminal of the first transistor; a trigger circuit connected between the first contact and the second contact, the trigger circuit comprising: a first resistor connected between the amplifier and the first contact; a second transistor comprising a control terminal, a first node, and a second node, the second transistor comprising an intrinsic capacitance coupling the first node of the second transistor to the control terminal of the second transistor, wherein the second node of the second transistor is coupled to the second contact; and a second resistor connected between the control terminal of the second transistor and the second contact, wherein the trigger circuit is configured to operate the second transistor in a conductive state in response to a voltage developed across the second resistor due to a discharge current from the first contact, the discharge current flowing from the first resistor to the control terminal of the second resistor via the intrinsic capacitance of the second transistor, and from the control terminal of the second resistor to the second contact via the second resistor, and wherein operating the second transistor in the conductive state generates a voltage swing at the amplifier input.

2. The circuit of claim 1, further comprising: an enable circuit comprising a first enable transistor, the first enable transistor comprising a load current path connected between the first contact and the amplifier input, wherein the first enable transistor is configured to deactivate the amplifier circuit based on a logic signal.

3. The circuit of claim 2, wherein the enable circuit further comprises: a second enable transistor comprising a load current path connected between the control terminal of the second transistor and the second contact, wherein the second enable transistor is configured to deactivate the second transistor based on the logic signal.

4. The circuit of claim 3, wherein the enable circuit further comprises: a third enable transistor comprising a load current path connected between the control terminal and the second contact, wherein the third enable transistor is configured to deactivate the first transistor based on the logic signal.

5. The circuit of claim 1, wherein the circuit comprises a third resistor coupling the second contact to the amplifier output of the amplifier circuit.

6. The circuit of claim 5, wherein the second transistor is a MOS transistor, the control terminal of the second transistor coupled to the second node of the second transistor via a second intrinsic capacitance.

7. The circuit of any one of claims 1 to 5, wherein the trigger circuit comprises only the intrinsic capacitance and a parasitic capacitance of the second transistor.

8. The circuit of any one of claims 1 to 5, wherein the amplifier circuit comprises a third transistor, the third transistor being a MOS transistor and operating as a common-source connection.

9. A circuit comprising: a first transistor comprising a first control terminal and a first load current path connected between a first contact and a second contact; a first resistor connected between the first control terminal of the first transistor and the second contact; a second transistor comprising a second control terminal and a second load current path connected between the first control terminal of the first transistor and the first contact, a second resistor connected between the second control terminal of the second transistor and the first contact; a third transistor comprising a third control terminal and a third load current path connected between the second control terminal of the second transistor and the second contact; and a third resistor connected between the third control terminal of the third transistor and the second contact, wherein the third transistor comprises an intrinsic capacitance coupling the third control terminal of the third transistor to the second control terminal of the second transistor; wherein the third transistor is configured to operate in an on state in response to a voltage generated across the third resistor due to a discharge current from the first contact, the discharge current flowing from the second resistor to the third control terminal of the third transistor via the intrinsic capacitance of the third transistor, and from the third control terminal of the third transistor to the second contact via the third resistor; and wherein the third transistor operating in the on state generates a voltage swing at the second control terminal of the second transistor.

10. The circuit of claim 9, wherein the third transistor is a MOS transistor, wherein the intrinsic capacitance comprises a drain-gate capacitance acting between the second control terminal of the second transistor and the third control terminal of the third transistor, and wherein the third transistor comprises a gate-source capacitance acting between the third control terminal of the third transistor and the second contact.

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