Organic light emitting display device

Abstract

An organic light-emitting display device may include: a substrate; a first active layer arranged on the substrate; a gate insulating layer; a first gate electrode; a first insulating interlayer and a second insulating interlayer; a first source electrode, which is arranged on the second insulating interlayer and contacts the first active layer via a contact hole formed by removing parts of the gate insulating layer, the first insulating interlayer, and the second insulating interlayer; a protective insulating layer, which is arranged on the first source electrode; a first drain electrode, which is arranged on the protective insulating layer and contacts the first active layer via a contact hole formed by removing parts of the gate insulating layer, the first insulating interlayer, the second insulating interlayer, and the protective insulating layer; and a sub-pixel structure, which is arranged on the first drain electrode.

Description

Technical Field

[0001] Embodiments generally relate to organic light emitting display devices and more particularly to organic light emitting display devices including transistors of different types from each other. Background Art

[0002] Flat panel display devices are used as display devices replacing cathode ray tube display devices due to their light weight and thin characteristics. As typical examples of such flat panel display devices, there are liquid crystal display devices and organic light emitting display devices.

[0003] Recently, an organic light-emitting display device including a silicon-based semiconductor element and a metal oxide-based semiconductor element has been developed. In order to drive an organic light-emitting display device with a high resolution, the organic light-emitting display device may include a relatively large number of signal wirings. When the organic light-emitting display device includes a relatively large number of signal wirings, the width of the signal wirings is relatively reduced to arrange the signal wirings in a limited space, and the specific resistance of the signal wirings is increased. In addition, two data wirings may be included in the sub-pixel circuit to drive the organic light-emitting display device at a high speed. When the sub-pixel circuit includes two data wirings, the characteristics of the driving transistor disposed adjacent to the data wirings may change due to the variable voltage level of the data wirings. Summary of the invention

[0004] Problem to be solved

[0005] An object of the present invention is to provide an organic light emitting display device including transistors of different types from each other.

[0006] However, the purpose of the present invention is not limited thereto. Therefore, the purpose of the present invention can be expanded without departing from the spirit and scope of the present invention.

[0007] Ways to solve the problem

[0008] In order to achieve the above-mentioned purpose of the present invention, an organic light-emitting display device according to an embodiment of the present invention includes a light-emitting area, wherein the light-emitting area includes a first area and a second area; wherein the organic light-emitting display device also includes: a substrate; a first active layer having a source region and a drain region, wherein the first active layer is arranged on the substrate in the first area; a gate insulating layer arranged on the first active layer; a first gate electrode arranged on the gate insulating layer; a first insulating interlayer arranged on the first gate electrode; a second insulating interlayer arranged on the first insulating interlayer; a first source electrode arranged on the second insulating interlayer, wherein the first source electrode is formed by removing a portion of the gate insulating layer, the first insulating interlayer and the second insulating interlayer a protective insulating layer, which is arranged on the first source electrode; a first drain electrode, which is arranged on the protective insulating layer, and the first drain electrode is connected to the drain region of the first active layer via a contact hole formed by removing the gate insulating layer, the first insulating interlayer, the second insulating interlayer and a part of the protective insulating layer, and the first drain electrode, together with the first active layer, the first gate electrode and the first source electrode, constitute a driving transistor; a switching transistor, which is arranged between the substrate and the protective insulating layer in the second region; a lower electrode, which is arranged on the switching transistor and the driving transistor; a light-emitting layer, which is arranged on the lower electrode; and an upper electrode, which is arranged on the light-emitting layer.

[0009] In an embodiment, the first drain electrode may extend in a first direction on the protective insulating layer, the first direction being a direction from the first region to the second region.

[0010] In an embodiment, a portion of the first drain electrode may overlap the first source electrode.

[0011] In an embodiment, a portion of the first drain electrode may overlap the first gate electrode.

[0012] In an embodiment, the first source electrode may include a single layer, and the first drain electrode may include a plurality of layers.

[0013] In an embodiment, the first source electrode may include molybdenum, and the first drain electrode may have a stack structure of titanium / aluminum / titanium.

[0014] In an embodiment, the organic light emitting display device may further include: a signal wiring disposed on the first drain electrode.

[0015] In an embodiment, a data signal may be applied to the signal wiring, and a high power supply voltage may be applied to the first drain electrode. A low power supply voltage may be applied to the upper electrode.

[0016] In an embodiment, the switch transistor may include: a second gate electrode; a second active layer disposed on the second gate electrode; and a second source electrode and a second drain electrode disposed at two lateral portions of the second active layer.

[0017] In an embodiment, the first drain electrode may not overlap the second active layer.

[0018] In an embodiment, the driving transistor may have a top gate structure, and the first active layer may include a silicon-based semiconductor. The switching transistor may have a bottom gate structure, and the second active layer may include a metal oxide-based semiconductor.

[0019] In an embodiment, the first active layer of the driving transistor may include amorphous silicon or polycrystalline silicon.

[0020] In an embodiment, the organic light emitting display device may further include a gate electrode pattern disposed on the first gate electrode.

[0021] In an embodiment, the gate electrode pattern and the second gate electrode may be located at the same layer.

[0022] In an embodiment, the substrate may include: a first organic layer; a first barrier layer disposed on the first organic layer; a second organic layer disposed on the first barrier layer; and a second barrier layer disposed on the second organic layer.

[0023] In an embodiment, the organic light emitting display device may further include: a bending region spaced apart from the light emitting region. The second barrier layer may have an opening exposing an upper surface of the second organic layer in the bending region.

[0024] In an embodiment, the organic light-emitting display device may further include a curved region spaced apart from the light-emitting region. The organic light-emitting display device may further include: a buffer layer disposed on the substrate in the first region and the second region and extending into the curved region, and the buffer layer has a first opening exposing an upper surface of the substrate in the curved region. The gate insulating layer may cover the first active layer in the first region on the buffer layer and extend into the curved region, and may have a second opening overlapping the first opening. The first insulating layer may cover the first gate electrode in the first region on the gate insulating layer and extend into the curved region, and may have a third opening overlapping the first opening and the second opening.

[0025] In an embodiment, the organic light emitting display device may further include a thin film encapsulation structure disposed on the upper electrode. The thin film encapsulation structure may include: a first thin film encapsulation layer including a flexible inorganic material; a second thin film encapsulation layer disposed on the first thin film encapsulation layer, the second thin film encapsulation layer including a flexible organic material; and a third thin film encapsulation layer disposed on the second thin film encapsulation layer, the third thin film encapsulation layer including a flexible inorganic material.

[0026] In an embodiment, the first source electrode may have a first thickness, and the first drain electrode may have a second thickness greater than the first thickness.

[0027] In order to achieve the above-mentioned purpose of the present invention, an organic light-emitting display device according to an embodiment of the present invention includes a bending area and a light-emitting area, and the light-emitting area includes a first area and a second area; wherein the organic light-emitting display device also includes: a substrate; a driving transistor, which is arranged on the substrate in the first area, and the driving transistor includes a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the first active layer has a source region and a drain region, the first gate electrode is arranged on the first active layer, the first source electrode is arranged on the first gate electrode, the first source electrode is connected to the source region of the first active layer through a first contact hole, the first source electrode has a first thickness, the first drain electrode is arranged on the first source electrode, the first drain electrode is connected to the drain region of the first active layer through a second contact hole, and the first drain electrode has a second thickness greater than the first thickness; a switching transistor, which is arranged on the substrate in the second area; and a sub-pixel structure, which is arranged on the switching transistor and the driving transistor.

[0028] Effects of the Invention

[0029] Since the organic light emitting display device according to an embodiment of the present invention includes a driving transistor having a first drain electrode and a first source electrode disposed on different layers from each other, the first drain electrode can be used as a wiring having a relatively wide width and a relatively large thickness. Therefore, the organic light emitting display device can be driven with high resolution.

[0030] In addition, since the organic light emitting display device according to the embodiment of the present invention includes the first drain electrode shielding the first active layer, no parasitic capacitance is formed between the signal wiring and the driving transistor, and thus the organic light emitting display device can maintain the characteristics of the driving transistor.

[0031] However, the effects of the present invention are not limited thereto. Therefore, the effects of the present invention can be expanded without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a plan view showing an organic light emitting display device according to an embodiment of the present invention.

[0033] Figure 2 It shows Figure 1 A plan view of an example of an organic light emitting display device.

[0034] Figure 3 It shows Figure 1 A perspective view of a curved shape of an organic light emitting display device.

[0035] Figure 4 is shown electrically connected to Figure 1 A block diagram of external devices of an organic light emitting display device.

[0036] Figure 5 It shows the settings in Figure 1 A circuit diagram of a sub-pixel circuit and an organic light emitting diode in a sub-pixel area.

[0037] Figure 6 It is along Figure 1 A cross-sectional view of an organic light emitting display device taken along line II'.

[0038] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 is a cross-sectional view illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.

[0039] Fig.14 is a cross-sectional view showing an organic light emitting display device according to an embodiment of the present invention.

[0040] Fig.15 It shows Fig.14 A cross-sectional view of an example of an organic light emitting display device. DETAILED DESCRIPTION

[0041] Hereinafter, an organic light emitting display device according to an embodiment of the present invention and a method of manufacturing the organic light emitting display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same or similar components.

[0042] Figure 1 is a plan view showing an organic light emitting display device according to an embodiment of the present invention, and Figure 2 It shows Figure 1 A plan view of an example of an organic light emitting display device. Figure 3 It shows Figure 1 A perspective view of a curved shape of an organic light emitting display device, and Figure 4 is shown electrically connected to Figure 1 A block diagram of external devices of an organic light emitting display device.

[0043] Reference Figure 1 , Figure 3 and Figure 4 , the organic light emitting display device 100 (eg, Figure 6 The substrate 110 of the embodiment of the present invention may include a display area 10 and a pad area 60. The display area 10 may include a light emitting area 30 having a plurality of sub-pixel circuit areas 20 and a peripheral area 40 surrounding the light emitting area 30, and the sub-pixel circuit areas 20 may be all arranged in the light emitting area 30. For example, Figure 5 The sub-pixel circuit SPC (for example, Figure 6 The driving transistor 250 and Figure 6 A switch transistor 255) may be provided in each sub-pixel circuit region 20, and Figure 5 Organic light emitting diodes OLED (e.g. Figure 6 The sub-pixel structure 200 may be disposed on the sub-pixel circuit SPC. An image may be displayed in the display area 10 through the sub-pixel circuit SPC and the organic light emitting diode OLED.

[0044] For example, a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit may be disposed in the sub-pixel circuit region 20. The first sub-pixel circuit may be connected to a first organic light emitting diode for emitting red light, the second sub-pixel circuit may be connected to a second organic light emitting diode for emitting green light, and the third sub-pixel circuit may be connected to a third organic light emitting diode for emitting blue light.

[0045] In an embodiment, the first organic light emitting diode may overlap with the first sub-pixel circuit, and the second organic light emitting diode may overlap with the second sub-pixel circuit. In addition, the third organic light emitting diode may overlap with the third sub-pixel circuit. Alternatively, the first organic light emitting diode may overlap with a portion of the first sub-pixel circuit and a portion of another sub-pixel circuit different from the first sub-pixel circuit, and the second organic light emitting diode may overlap with a portion of the second sub-pixel circuit and a portion of another sub-pixel circuit different from the second sub-pixel circuit. In addition, the third organic light emitting diode may overlap with a portion of the third sub-pixel circuit and a portion of another sub-pixel circuit different from the third sub-pixel circuit. For example, the first organic light emitting diode to the third organic light emitting diode may be arranged by using an RGB stripe scheme in which rectangles of the same size are arranged in sequence, an S stripe scheme including a blue organic light emitting diode having a relatively large area, a WRGB scheme further including a white organic light emitting diode, a five-piece tile (PenTile) scheme in which the RG-GB pattern is repeatedly arranged, and the like.

[0046] In addition, at least one driving transistor, at least one switching transistor, and at least one capacitor may be disposed in each sub-pixel circuit region 20. In an embodiment, a driving transistor (e.g., Figure 5 The first transistor TR1) and six switch transistors (eg, Figure 5 a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, and a seventh transistor TR7) and a storage capacitor (eg, Figure 5 A storage capacitor CST) or the like may be provided in each sub-pixel circuit region 20.

[0047] Although each of the display region 10, the peripheral region 40, and the sub-pixel circuit region 20 of the present invention has been described as having a rectangular planar shape, the shape is not limited thereto. For example, each of the display region 10, the peripheral region 40, and the sub-pixel circuit region 20 may have a triangular planar shape, a rhombus planar shape, a polygonal planar shape, a circular planar shape, an orbital planar shape, or an elliptical planar shape.

[0048] In addition, a plurality of wirings may be provided in the peripheral region 40. For example, the wirings may include data signal wirings, gate signal wirings, light emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, power supply voltage wirings, etc. The wirings may extend from the peripheral region 40 to the light emission region 30 and may be electrically connected to the sub-pixel circuit SPC and the organic light emitting diode OLED. In addition, a gate driver and a data driver, etc. may be provided in the peripheral region 40.

[0049] The pad region 60 may be disposed on one side of the display region 10, and the pad region 60 may include a bending region 50 and a pad electrode region 70. A pad electrode 470 electrically connected to an external device 101 may be disposed in the pad electrode region 70. In addition, the bending region 50 may be located between the display region 10 and the pad electrode region 70, and a connecting electrode may be disposed in the bending region 50. For example, the connecting electrode may electrically connect the pad electrode 470 and the sub-pixel circuit SPC. In an embodiment, the organic light-emitting display device 100 may have the same width in a horizontal direction (e.g., a third direction D3).

[0050] In other embodiments, Figure 2 As shown, the width of the pad region 60 may be smaller than the width of the display region 10. For example, the display region 10 may have a first width extending in a direction (e.g., a third direction D3) parallel to the upper surface of the organic light-emitting display device 100 in a plan view of the organic light-emitting display device 100, and the pad region 60 may have a second width extending in the third direction D3 that is smaller than the first width.

[0051] Despite Figure 1 , the peripheral region 40 surrounding the light-emitting region 30 is shown as having the same width, but the construction of the present invention is not limited thereto. For example, the peripheral region 40 may include a first peripheral region extending in the third direction D3 and a second peripheral region extending in the first direction D1 or the second direction D2 perpendicular to the third direction D3. In other words, the first peripheral region of the peripheral region 40 may be adjacent to the top of the light-emitting region 30 and the bending region 50, and the second peripheral region of the peripheral region 40 may be located on two lateral portions of the light-emitting region 30 (e.g., the left and right portions of the light-emitting region 30). Here, the width of the second peripheral region extending in the third direction D3 may be relatively smaller than the width of the first peripheral region extending in the first direction D1 or the second direction D2. Because the bending region 50 is bent around an axis along the third direction D3, the pad electrode region 70 may be located on the lower surface of the organic light-emitting display device 100 (refer to Figure 3 ). In other words, when the pad electrode region 70 is located on the lower surface of the organic light-emitting display device 100, the bending region 50 may have a bent shape.

[0052] The external device 101 may be electrically connected to the organic light-emitting display device 100 through a flexible printed circuit board or a printed circuit board. For example, one side of the flexible printed circuit board may be in direct contact with the pad electrode 470, and the opposite side of the flexible printed circuit board may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light-emitting control signal, a gate initialization signal, an initialization voltage, a power supply voltage, etc. to the organic light-emitting display device 100. In addition, a driver integrated circuit may be mounted in the flexible printed circuit board. In other embodiments, the driver integrated circuit may be mounted in the organic light-emitting display device 100 adjacent to the pad electrode 470.

[0053] Figure 5 It shows the settings in Figure 1 A circuit diagram of a sub-pixel circuit and an organic light emitting diode in a sub-pixel area.

[0054] Reference Figure 5 , a sub-pixel circuit SPC and an organic light emitting diode OLED (eg, Figure 6 The sub-pixel structure 200) can be set in each sub-pixel circuit area 20 of the organic light-emitting display device 100, and one sub-pixel circuit SPC can include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6 and a seventh transistor TR7, a storage capacitor CST, wiring for a high power supply voltage ELVDD, wiring for a low power supply voltage ELVSS, wiring for an initialization voltage VINT, wiring for a data signal DATA, wiring for a gate signal GW, wiring for a gate initialization signal GI, wiring for a light-emitting control signal EM, wiring for a diode initialization signal GB, and the like.

[0055] The organic light emitting diode OLED may output light based on the driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In an embodiment, the second terminal of the organic light emitting diode OLED may be supplied with a low power supply voltage ELVSS. For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal. In an embodiment, the anode terminal of the organic light emitting diode OLED may correspond to Figure 6 The lower electrode 290 of the organic light emitting diode OLED may correspond to the cathode terminal of the organic light emitting diode OLED. Figure 6 The upper electrode 340 is provided.

[0056] The first transistor TR1 (eg, corresponding to Figure 6The driving transistor 250 may include a gate terminal, a first terminal, and a second terminal. In an embodiment, the first terminal of the first transistor TR1 may be a source terminal, and the second terminal of the first transistor TR1 may be a drain terminal.

[0057] The first transistor TR1 may generate a driving current ID. In an embodiment, the first transistor TR1 may operate in a saturation region. In this case, the first transistor TR1 may generate a driving current ID based on a voltage difference between a gate terminal and a source terminal. In addition, a grayscale may be represented based on the magnitude of the driving current ID supplied to the organic light emitting diode OLED. Alternatively, the first transistor TR1 may operate in a linear region. In this case, a grayscale may be represented based on the sum of the time during which the driving current ID is supplied to the organic light emitting diode OLED during one frame.

[0058] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor TR2 may be provided with a gate signal GW. The first terminal of the second transistor TR2 may be provided with a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. For example, a gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the second transistor TR2 by wiring for the gate signal GW. In an embodiment, the first terminal of the second transistor TR2 may be a source terminal, and the second terminal of the second transistor TR2 may be a drain terminal. Alternatively, the first terminal of the second transistor TR2 may be a drain terminal, and the second terminal of the second transistor TR2 may be a source terminal.

[0059] The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 may operate in a linear region.

[0060] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may be provided with a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3 by wiring for the gate signal GW. In an embodiment, the first terminal of the third transistor TR3 may be a source terminal, and the second terminal of the third transistor TR3 may be a drain terminal. Alternatively, the first terminal of the third transistor TR3 may be a drain terminal, and the second terminal of the third transistor TR3 may be a source terminal.

[0061] The third transistor TR3 can connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the third transistor TR3 can operate in the linear region. That is, the third transistor TR3 can connect the first transistor TR1 in a diode manner during the activation period of the gate signal GW. Because the first transistor TR1 is connected in a diode manner, the voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1 can be as much as the threshold voltage of the first transistor TR1. Therefore, the voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1 during the activation period of the gate signal GW. That is, the data signal DATA can be compensated up to the threshold voltage of the first transistor TR1, and the compensated data signal DATA can be supplied to the gate terminal of the first transistor TR1. Because the threshold voltage compensation is performed, the problem of non-uniform drive current caused by the threshold voltage deviation of the first transistor TR1 can be solved.

[0062] An input terminal of the wiring for the initialization voltage VINT to which the initialization voltage VINT is supplied may be connected to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7 , and an output terminal of the wiring for the initialization voltage VINT may be connected to the second terminal of the fourth transistor TR4 and the first terminal of the storage capacitor CST.

[0063] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may be supplied with a gate initialization signal GI. The first terminal of the fourth transistor TR4 may be supplied with an initialization voltage VINT. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. In an embodiment, the first terminal of the fourth transistor TR4 may be a source terminal, and the second terminal of the fourth transistor TR4 may be a drain terminal. Alternatively, the first terminal of the fourth transistor TR4 may be a drain terminal, and the second terminal of the fourth transistor TR4 may be a source terminal.

[0064] The fourth transistor TR4 may supply the initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 may operate in a linear region. That is, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1. In other embodiments, the initialization voltage VINT may have a voltage level sufficiently higher than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage may be supplied to the gate terminal of the first transistor TR1.

[0065] In an embodiment, the gate initialization signal GI may be a signal substantially identical to the gate signal GW transmitted one horizontal time ago. For example, the gate initialization signal GI supplied to the sub-pixel circuit in the nth row (where n is an integer of 2 or greater) of the sub-pixel circuit SPC included in the organic light-emitting display device 100 may be a signal substantially identical to the gate signal GW supplied to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC. That is, by supplying the activated gate signal GW to the first sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC, the activated gate initialization signal GI may be supplied to the first sub-pixel circuit in the nth row of the sub-pixel circuit SPC. Therefore, while the gate terminal of the first transistor TR1 included in the sub-pixel circuit in the nth row of the sub-pixel circuit SPC is initialized to the initialization voltage VINT, the data signal DATA may be supplied to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC.

[0066] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a light emitting control signal EM. The first terminal may be connected to a wiring for a high power supply voltage ELVDD. The second terminal may be connected to a first terminal of the first transistor TR1. For example, a light emitting control signal EM may be provided from a light emitting control driver, and the light emitting control signal EM may be applied to the gate terminal of the fifth transistor TR5 through a wiring for the light emitting control signal EM. In an embodiment, the first terminal of the fifth transistor TR5 may be a source terminal, and the second terminal of the fifth transistor TR5 may be a drain terminal. Alternatively, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0067] The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the light emitting control signal EM. On the contrary, the fifth transistor TR5 may cut off the supply of the high power supply voltage ELVDD during the deactivation period of the light emitting control signal EM. In this case, the fifth transistor TR5 may operate in the linear region. The fifth transistor TR5 supplies the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the light emitting control signal EM, so that the first transistor TR1 may generate the driving current ID. In addition, the fifth transistor TR5 cuts off the supply of the high power supply voltage ELVDD during the deactivation period of the light emitting control signal EM, so that the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0068] The sixth transistor TR6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a light emitting control signal EM. The first terminal may be connected to the second terminal of the first transistor TR1. The second terminal may be connected to the first terminal of the organic light emitting diode OLED. In an embodiment, the first terminal of the sixth transistor TR6 may be a source terminal, and the second terminal of the sixth transistor TR6 may be a drain terminal. Alternatively, the first terminal of the sixth transistor TR6 may be a drain terminal, and the second terminal of the sixth transistor TR6 may be a source terminal.

[0069] The sixth transistor TR6 can supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emitting control signal EM. In this case, the sixth transistor TR6 can operate in a linear region. That is, the sixth transistor TR6 supplies the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emitting control signal EM, so that the organic light emitting diode OLED can output light. In addition, the sixth transistor TR6 electrically isolates the first transistor TR1 from the organic light emitting diode OLED during the deactivation period of the light emitting control signal EM, so that the data signal DATA supplied to the second terminal of the first transistor TR1 (more precisely, the data signal that has been subjected to threshold voltage compensation) can be supplied to the gate terminal of the first transistor TR1.

[0070] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a diode initialization signal GB. The first terminal may be supplied with an initialization voltage VINT. The second terminal may be connected to a first terminal of the organic light emitting diode OLED. In an embodiment, the first terminal of the seventh transistor TR7 may be a source terminal, and the second terminal of the seventh transistor TR7 may be a drain terminal. Alternatively, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0071] The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 can operate in the linear region. That is, the seventh transistor TR7 can initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0072] Alternatively, the gate initialization signal GI and the diode initialization signal GB may be signals substantially identical to each other. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may not affect each other. That is, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not generated separately, so that the economic benefits of the process can be improved.

[0073] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the wiring for the high power supply voltage ELVDD and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the wiring for the high power supply voltage ELVDD. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the deactivation period of the gate signal GW. The deactivation period of the gate signal GW may include the activation period of the light emitting control signal EM, and the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED during the activation period of the light emitting control signal EM. Therefore, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED based on the level maintained by the storage capacitor CST.

[0074] Although the sub-pixel circuit SPC of the present invention has been described as including seven transistors and one storage capacitor, the configuration of the present invention is not limited thereto. For example, the sub-pixel circuit SPC may have a configuration including at least one transistor and at least one storage capacitor.

[0075] Figure 6 It is along Figure 1 A cross-sectional view of an organic light emitting display device taken along line II'.

[0076] Reference Figure 6 , the organic light-emitting display device 100 may include a substrate 110, a buffer layer 115, a driving transistor 250, a switching transistor 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating interlayer 190, a second insulating interlayer 195, a protective insulating layer 400, a first planarization layer 270, a signal wiring 350, a connection pattern 370, a second planarization layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, etc. Here, the substrate 110 may include a first organic layer 111, a first barrier layer 112, a second organic layer 113, and a second barrier layer 114. Since the organic light-emitting display device 100 includes a display region 10 having a light-emitting region 30 and a peripheral region 40 and a pad region 60 having a bending region 50 and a pad electrode region 70, the substrate 110 may also be divided into the display region 10 and the pad region 60. In addition, the driving transistor 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the switching transistor 255 may include a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. In addition, the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340, and the thin film encapsulation structure 450 may include a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453.

[0077] Since the organic light-emitting display device 100 includes the flexible substrate 110 and the thin film encapsulation structure 450 , the organic light-emitting display device 100 may be used as a flexible organic light-emitting display device.

[0078] A first organic layer 111 may be provided. The first organic layer 111 may include a flexible organic material. In an embodiment, the first organic layer 111 may include polyimide or the like.

[0079] The first barrier layer 112 may be disposed on the first organic layer 111. The first barrier layer 112 may block moisture penetrating through the first organic layer 111. The first barrier layer 112 may include a flexible inorganic material. In an embodiment, the first barrier layer 112 may include silicon oxide, silicon nitride, or the like.

[0080] The second organic layer 113 may be disposed on the first barrier layer 112. The second organic layer 113 may be disposed on the entire first barrier layer 112. The second organic layer 113 may include a flexible organic material. In an embodiment, the second organic layer 113 may include polyimide or the like.

[0081] The second barrier layer 114 may be disposed on the second organic layer 113. In an embodiment, the second barrier layer 114 may have an opening exposing the upper surface of the second organic layer 113 located in the bending region 50. The second barrier layer 114 may block moisture that penetrates through the second organic layer 113. The second barrier layer 114 may include a flexible inorganic material. In an embodiment, the second barrier layer 114 may include silicon oxide, silicon nitride, etc. Alternatively, no opening is formed in the second barrier layer 114 in the bending region 50, or openings are formed in the second organic layer 113 and the second barrier layer 114 in the bending region 50.

[0082] Thus, a substrate 110 including a first organic layer 111, a first barrier layer 112, a second organic layer 113, and a second barrier layer 114 may be constructed. In an embodiment, the substrate 110 may have a first region 11 and a second region 12, and the first region 11 may be located adjacent to the second region 12. For example, the first region 11 may be a region where the driving transistor 250 is disposed, and the second region 12 may be a region where the switching transistor 255 is disposed. In an embodiment, because an opening is formed in the second barrier layer 114, the substrate 110 may have a groove in the bending region 50.

[0083] Although the substrate 110 is described as having four layers, the configuration of the present invention is not limited thereto. For example, in other embodiments, the substrate 110 may include a single layer or at least two layers.

[0084] In other embodiments, the substrate 110 may include a transparent or opaque material. For example, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, an alkali-free glass substrate, etc.

[0085] The buffer layer 115 may be disposed on the substrate 110. In an embodiment, the buffer layer 115 may be disposed on the substrate 110 in the first region 11 and the second region 12 and extend into the bending region 50, and may have a first opening that exposes an upper surface of the substrate 110 located in the bending region 50 (e.g., an upper surface of the second organic layer 113 located in the bending region 50). The buffer layer 115 may prevent metal atoms or impurities from diffusing from the substrate 110 into the driving transistor 250, the switching transistor 255, and the sub-pixel structure 200, and may control a heat transfer rate during a crystallization process for forming the first active layer 130 to obtain a substantially uniform first active layer 130. In addition, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be disposed on the substrate 110, or the buffer layer 115 may not be disposed on the substrate 110. For example, the buffer layer 115 may include an organic material or an inorganic material.

[0086] The first active layer 130 may be disposed on the buffer layer 115 in the first region 11. For example, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, an organic semiconductor, etc. In an embodiment, the first active layer 130 may include a silicon-based semiconductor and may be formed of amorphous silicon or polycrystalline silicon. In an embodiment, the first active layer 130 may have a source region and a drain region.

[0087] The gate insulating layer 150 may be disposed on the buffer layer 115 and the first active layer 130 in the first region 11 and the second region 12. In an embodiment, the gate insulating layer 150 may cover the first active layer 130 in the first region 11 on the buffer layer 115 and extend into the curved region 50, and may have a second opening overlapping the first opening. For example, the gate insulating layer 150 may fully cover the first active layer 130 on the buffer layer 115, and may have a substantially flat top surface without generating steps around the first active layer 130. Alternatively, the gate insulating layer 150 may cover the first active layer 130 on the buffer layer 115, and may be disposed to have a substantially uniform thickness along the contour of the first active layer 130. The gate insulating layer 150 may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y ), aluminum oxide (AlOx ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x )、ZrO x ), titanium oxide (TiO x ) etc. Alternatively, the gate insulating layer 150 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0088] The first gate electrode 170 may be disposed on the gate insulating layer 150 in the first region 11. For example, the first gate electrode 170 may be disposed on a portion of the gate insulating layer 150, and the first active layer 130 is located below the portion of the gate insulating layer 150. The first gate electrode 170 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0089] The first insulating interlayer 190 may be disposed on the gate insulating layer 150 and the first gate electrode 170 in the first region 11 and the second region 12. In an embodiment, the first insulating interlayer 190 may cover the first gate electrode 170 in the first region 11 on the gate insulating layer 150 and extend into the bending region 50, and may have a third opening overlapping the first opening and the second opening. For example, the first insulating interlayer 190 may fully cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface without generating steps around the first gate electrode 170. Alternatively, the first insulating interlayer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be disposed to have a substantially uniform thickness along the contour of the first gate electrode 170. The first insulating interlayer 190 may include a silicon compound, a metal oxide, and the like. Alternatively, the first insulating interlayer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0090] The gate electrode pattern 180 may be disposed on the first insulating interlayer 190 in the first region 11. The gate electrode pattern 180 may be disposed on a portion of the first insulating interlayer 190 under which the first gate electrode 170 is located. In another cross-sectional view of the organic light-emitting display device 100, the first gate electrode 170 and the gate electrode pattern 180 may be used as Figure 5 The gate electrode pattern 180 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Alternatively, the gate electrode pattern 180 may have a multi-layer structure including a plurality of layers.

[0091] The second gate electrode 175 may be disposed on the first insulating interlayer 190 in the second region 12. In other words, the second gate electrode 175 may be spaced apart from the gate electrode pattern 180. In an embodiment, the second gate electrode 175 and the gate electrode pattern 180 may be located at the same layer and may be formed simultaneously using the same material. The second gate electrode 175 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0092] The second insulating interlayer 195 may be disposed on the gate electrode pattern 180 and the second gate electrode 175 in the first region 11 and the second region 12. In an embodiment, the second insulating interlayer 195 may cover the gate electrode pattern 180 in the first region 11 on the first insulating interlayer 190 and the second gate electrode 175 in the second region 12 on the first insulating interlayer 190 and extend into the bending region 50, and may have a fourth opening overlapping the first opening, the second opening, and the third opening. For example, the second insulating interlayer 195 may fully cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may have a substantially flat upper surface without generating steps around the gate electrode pattern 180 and the second gate electrode 175. Alternatively, the second insulating interlayer 195 may cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may be disposed to have a substantially uniform thickness along the contours of the gate electrode pattern 180 and the second gate electrode 175. The second insulating interlayer 195 may include a silicon compound, a metal oxide, and the like. Alternatively, the second insulating interlayer 195 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0093] The first source electrode 210 may be disposed on the second insulating interlayer 195 in the first region 11. The first source electrode 210 may be connected to the source region of the first active layer 130 via a first contact hole 212 formed by removing a first portion of each of the gate insulating layer 150, the first insulating interlayer 190, and the second insulating interlayer 195. The first source electrode 210 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. For example, the first source electrode 210 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN), etc. x ), silver alloy, tungsten nitride (WN x ), copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN x ), chromium nitride (CrNx ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x )、Indium Tin Oxide (ITO), Tin Oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other.

[0094] In an embodiment, the first source electrode 210 may have a first thickness T1 and may be formed as a single layer. For example, the first source electrode 210 may include Mo. In addition, the first source electrode 210 may be used as an electrode. In other words, because the first source electrode 210 is used as an electrode, the first source electrode 210 may have a relatively higher specific resistance than the first drain electrode 230, the signal wiring 350, and the connection pattern 370 used as wiring. In other embodiments, the first source electrode 210 may have a multilayer structure including a plurality of layers.

[0095] The second active layer 135 may be disposed on the second insulating interlayer 195 in the second region 12. The second active layer 135 may be disposed on a portion of the second insulating interlayer 195, and the second gate electrode 175 is located below the portion of the second insulating interlayer 195. The second active layer 135 may include a metal oxide semiconductor. In other words, the second active layer 135 may be a semiconductor oxide layer including a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z ) etc. For example, the second active layer 135 may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), etc.

[0096] The second source electrode 215 and the second drain electrode 235 may be disposed on the second insulating interlayer 195 in the second region 12. The second source electrode 215 may cover a first side portion of the second active layer 135, and the second drain electrode 235 may cover a second side portion of the second active layer 135 that is different from the first side portion. In other words, the second source electrode 215 and the second drain electrode 235 may be disposed at two lateral portions of the second active layer 135, and a portion of the upper surface of the second active layer 135 may be exposed. Each of the second source electrode 215 and the second drain electrode 235 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0097] In an embodiment, the second source electrode 215 and the second drain electrode 235 may have a first thickness T1 and may be formed as a single layer. For example, each of the second source electrode 215 and the second drain electrode 235 may include Mo. In other words, because each of the second source electrode 215 and the second drain electrode 235 is used as an electrode, each of the second source electrode 215 and the second drain electrode 235 may have a relatively higher specific resistance than the first drain electrode 230, the signal wiring 350, and the connection pattern 370 used as wiring. In other embodiments, the second drain electrode 235 and the first source electrode 210 may be formed integrally.

[0098] In an embodiment, the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 may be located at the same layer and may be formed simultaneously using the same material. In other embodiments, each of the second source electrode 215 and the second drain electrode 235 may have a multilayer structure including a plurality of layers. Thus, a switching transistor 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235 may be constructed. Here, the switching transistor 255 may be used as a switching transistor including an oxide-based semiconductor. In addition, the switching transistor 255 may be used as a transistor having a top gate structure. For example, the switching transistor 255 may be Figure 5 One of the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6 and the seventh transistor TR7 shown in FIG.

[0099] The protective insulating layer 400 may be disposed on the second insulating interlayer 195, the first source electrode 210, the second source electrode 215, and the second drain electrode 235 in the first region 11 and the second region 12. In an embodiment, the protective insulating layer 400 may cover the first source electrode 210 in the first region 11 and the second source electrode 215 and the second drain electrode 235 in the second region 12 on the second insulating interlayer 195 and extend into the bending region 50, and may have a fifth opening overlapping the first opening to the fourth opening. For example, the protective insulating layer 400 may fully cover the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 195, and may have a substantially flat upper surface without generating steps around the first source electrode 210 and the second source electrode 215 and the second drain electrode 235. Alternatively, the protective insulating layer 400 may cover the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 195, and may be provided to have a substantially uniform thickness along the contours of the first source electrode 210 and the second source electrode 215 and the second drain electrode 235. The protective insulating layer 400 may include a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0100] The first drain electrode 230 may be disposed on the protective insulating layer 400 in the first region 11. In other words, the first source electrode 210 and the first drain electrode 230 may be disposed at different layers from each other. The first drain electrode 230 may be connected to the drain region of the first active layer 130 via a second contact hole 232 formed by removing a second portion of each of the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the protective insulating layer 400. In an embodiment, the first drain electrode 230 may have a second thickness T2 greater than the first thickness T1, and may be formed as a plurality of layers.

[0101] The first drain electrode 230 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first drain electrode 230 may have a stacked structure of Ti / Al / Ti. In addition, the first drain electrode 230 may be used as a wiring. In other words, because the first drain electrode 230 is used as a wiring, the first drain electrode 230 may have a relatively lower specific resistance than the first source electrode 210, the second source electrode 215, and the second drain electrode 235 used as electrodes.

[0102] For example, in order to drive a conventional organic light-emitting display device with high resolution, the conventional organic light-emitting display device must include a relatively large number of signal wirings. In this case, the signal wirings may be disposed on the second insulating interlayer 195. When the conventional organic light-emitting display device includes a relatively large number of signal wirings, the width of each signal wiring may be relatively reduced to arrange the signal wirings in a limited space, and the specific resistance of the signal wirings may be increased. That is, an organic light-emitting display device with high resolution may not be manufactured in a conventional manner.

[0103] In an embodiment of the present invention, the first drain electrode 230 of the driving transistor 250 included in the organic light-emitting display device 100 is disposed in a different layer from the first source electrode 210, so that the first drain electrode 230 can be formed as a wiring having a relatively large width and a relatively large thickness. That is, the first drain electrode 230 can have a relatively low specific resistance, and the organic light-emitting display device 100 can form a signal wiring on the protective insulating layer 400. Therefore, the organic light-emitting display device 100 has the driving transistor 250 including the first drain electrode 230 having a relatively large width and a relatively large thickness, so that the organic light-emitting display device 100 can be driven with high resolution.

[0104] In addition, in an embodiment, the first drain electrode 230 may extend in the first direction D1, which is a direction from the first region 11 to the second region 12. In other words, a portion of the first drain electrode 230 may overlap with the first gate electrode 170, the gate electrode pattern 180, and the first source electrode 210, and may not overlap with the second active layer 135 (e.g., the first drain electrode 230 does not overlap with the second active layer 135, thereby not affecting the driving of the switching transistor 255). A high power supply voltage (e.g., corresponding to Figure 5 The high power supply voltage ELVDD) may be applied to the first drain electrode 230. That is, the first drain electrode 230 may shield the driving transistor 250 from being applied with a data signal (eg, Figure 5 The signal wiring 350 of the data signal DATA) is affected.

[0105] For example, in a conventional organic light emitting display device, characteristics of a driving transistor disposed adjacent to a signal wiring may be changed due to a variable voltage level of the signal wiring.

[0106] In an embodiment of the present invention, since a constant voltage (e.g., a high power supply voltage ELVDD) is applied to the first drain electrode 230 of the driving transistor 250 included in the organic light-emitting display device 100 and the driving transistor 250 is shielded from the influence of the signal wiring 350, the characteristics of the driving transistor 250 can be maintained.

[0107] Thus, a driving transistor 250 including the first active layer 130, the first gate electrode 170, the first source electrode 210, and the first drain electrode 230 may be constructed. Here, the driving transistor 250 may be used as a driving transistor including a silicon-based semiconductor. In addition, the driving transistor 250 may be used as a transistor having a top gate structure. For example, the driving transistor 250 may correspond to Figure 5 The first transistor TR1 is shown in FIG.

[0108] Although the organic light-emitting display device 100 has been described as having a configuration including two transistors (eg, the driving transistor 250 and the switching transistor 255), the configuration of the present invention is not limited thereto. For example, the organic light-emitting display device 100 may have a configuration including at least two transistors and at least one capacitor.

[0109] The first planarization layer 270 may be disposed on the protective insulating layer 400 and the first drain electrode 230. The first planarization layer 270 may be disposed on the entire protective insulating layer 400. For example, the first planarization layer 270 may be disposed to have a relatively thick thickness to fully cover the first drain electrode 230, and in this case, the first planarization layer 270 may have a substantially flat upper surface. In addition, a planarization process may be added to the first planarization layer 270 to achieve a flat upper surface of the first planarization layer 270. In an embodiment, the first planarization layer 270 may fill the first opening to the fifth opening located in the bending region 50. In other words, the first planarization layer 270 may be in direct contact with the upper surface of the second organic layer 113 located in the bending region 50. The first planarization layer 270 may include an organic material or an inorganic material. In an embodiment, the first planarization layer 270 may include an organic material. For example, the first planarization layer 270 may include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, or the like.

[0110] The signal wiring 350 and the connection pattern 370 may be disposed on the first planarization layer 270. The data signal (eg, Figure 5 The data signal DATA shown in FIG. 1 may be applied to the signal wiring 350, and a high power supply voltage (eg, Figure 5 The high power supply voltage ELVDD shown in FIG. 1 may be applied to the connection pattern 370. In other words, the signal wiring 350 may correspond to Figure 5 , and the connection pattern 370 may correspond to the wiring for the data signal DATA shown in FIG. Figure 53. For example, the signal wiring 350 may transmit the data signal DATA to the switch transistor 255, and the data signal DATA transmitted to the switch transistor 255 (e.g., the second drain electrode 235 of the switch transistor 255) may be applied to the drive transistor 250 (e.g., the first gate electrode 170 of the drive transistor 250). In addition, the first drain electrode 230 of the drive transistor 250 may transmit the high power supply voltage ELVDD to the connection pattern 370 (e.g., Figure 5 The second terminal of the sixth transistor TR6 shown in FIG. 3 ), and the high power supply voltage ELVDD transmitted to the connection pattern 370 may be applied to the lower electrode 290.

[0111] Each of the signal wiring 350 and the connection pattern 370 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, each of the signal wiring 350 and the connection pattern 370 may be used as a wiring and may have a stacked structure of Ti / Al / Ti.

[0112] The second planarization layer 275 may be disposed on the first planarization layer 270, the signal wiring 350, and the connection pattern 370. The second planarization layer 275 may be disposed on the entire first planarization layer 270. For example, the second planarization layer 275 may be disposed to have a relatively thick thickness to fully cover the signal wiring 350 and the connection pattern 370, and in this case, the second planarization layer 275 may be a substantially flat upper surface. In addition, a planarization process may be added to the second planarization layer 275 to achieve such a flat upper surface of the second planarization layer 275. Alternatively, the second planarization layer 275 may not be disposed in the pad region 60. The second planarization layer 275 may include an organic material or an inorganic material. In an embodiment, the second planarization layer 275 may include an organic material.

[0113] The lower electrode 290 may be disposed on the second planarization layer 275. The lower electrode 290 may be connected to the connection pattern 370 via a contact hole formed by removing a portion of the second planarization layer 275. The lower electrode 290 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0114] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290 and the second planarization layer 275. The pixel defining layer 310 may cover two lateral portions of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In an embodiment, the pixel defining layer 310 may include an organic material. Alternatively, the lower electrode 290 may not be disposed in the pad region 60.

[0115] The light-emitting layer 330 may be disposed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of the light-emitting materials for emitting light of different colors (i.e., red light, green light, blue light, etc.) according to the sub-pixel. Alternatively, the light-emitting layer 330 may be formed by stacking a plurality of light-emitting materials for emitting light of different colors such as red light, green light, or blue light to emit white light as a whole. In this case, a color filter may be disposed on the light-emitting layer 330 (e.g., overlapping the light-emitting layer 330 on the upper surface of the thin film encapsulation structure 450). The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin, a color photoresist, and the like.

[0116] The upper electrode 340 may be disposed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be entirely disposed on the light emitting layer 330 and the pixel defining layer 310. In an embodiment, a low power supply voltage (e.g., Figure 5 The low power supply voltage ELVSS shown in FIG. 2 is applied to the upper electrode 340. The upper electrode 340 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Therefore, a sub-pixel structure 200 including a lower electrode 290, a light emitting layer 330, and an upper electrode 340 may be constructed.

[0117] The first thin film encapsulation layer 451 may be disposed on the upper electrode 340 in the light emitting region 30. The first thin film encapsulation layer 451 may cover the upper electrode 340 in the light emitting region 30, and may be disposed to have a substantially uniform thickness along the contour of the upper electrode 340. The first thin film encapsulation layer 451 may prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. In addition, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from external impact. The first thin film encapsulation layer 451 may include a flexible inorganic material.

[0118] The second thin film encapsulation layer 452 may be disposed on the first thin film encapsulation layer 451 in the light emitting region 30. The second thin film encapsulation layer 452 may improve the flatness of the organic light emitting display device 100 and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may include a flexible organic material.

[0119] The third thin film encapsulation layer 453 may be disposed on the second thin film encapsulation layer 452 in the light emitting region 30. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the light emitting region 30, and may be disposed along the contour of the second thin film encapsulation layer 452 to have a substantially uniform thickness. The third thin film encapsulation layer 453 may prevent the sub-pixel structure 200 from being degraded due to the infiltration of moisture, oxygen, etc. together with the first thin film encapsulation layer 451. In addition, the third thin film encapsulation layer 453 may be used to protect the sub-pixel structure 200 from external impact together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may include a flexible inorganic material. Therefore, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453 may be constructed. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first thin film encapsulation layer to the fifth thin film encapsulation layer or a seven-layer structure formed by stacking the first thin film encapsulation layer to the seventh thin film encapsulation layer.

[0120] Since the organic light-emitting display device 100 according to the embodiment of the present invention includes the driving transistor 250 having the first drain electrode 230 and the first source electrode 210 disposed on different layers from each other, the first drain electrode 230 can be used as a wiring having a relatively large width and a relatively large thickness. Therefore, the organic light-emitting display device 100 can be driven with high resolution.

[0121] In addition, since the organic light-emitting display device 100 according to the embodiment of the present invention includes the first drain electrode 230 shielding the first active layer 130, no parasitic capacitance is formed between the signal wiring 350 and the driving transistor 250. Therefore, the organic light-emitting display device 100 can maintain the characteristics of the driving transistor 250.

[0122] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 is a cross-sectional view illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.

[0123] Reference Figure 7, a rigid glass substrate 105 may be provided. A first organic layer 111 may be formed on the glass substrate 105. The first organic layer 111 may be formed on the entire glass substrate 105, and may be formed using a flexible organic material such as polyimide.

[0124] The first barrier layer 112 may be formed on the entire first organic layer 111. The first barrier layer 112 may block moisture permeating through the first organic layer 111. The first barrier layer 112 may be formed using a flexible inorganic material such as silicon oxide, silicon nitride, or the like.

[0125] The second organic layer 113 may be formed on the first barrier layer 112. The second organic layer 113 may be formed on the entire first barrier layer 112, and may be formed using a flexible organic material such as polyimide.

[0126] The second barrier layer 114 may be formed on the entire second organic layer 113. The second barrier layer 114 may block moisture that penetrates through the second organic layer 113. The second barrier layer 114 may be formed using a flexible inorganic material such as silicon oxide, silicon nitride, etc. Thus, the substrate 110 including the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114 may be formed.

[0127] Because the substrate 110 is thin and flexible, the substrate 110 can be formed on the rigid glass substrate 105 to support the formation of an upper structure (e.g., a driving transistor, a switching transistor, a sub-pixel structure, etc.). For example, after the upper structure is formed on the substrate 110, the glass substrate 105 can be removed. In other words, due to the flexible physical properties of the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114, it may be difficult to directly form the upper structure on the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114. In view of the above points, the upper structure is formed using the glass substrate 105, and then the glass substrate 105 is removed, so that the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114 can be used as the substrate 110.

[0128] A buffer layer 115 may be formed on the substrate 110. In an embodiment, the buffer layer 115 may be formed on the substrate 110 in the first region 11 and the second region 12, and may extend into the bending region 50. That is, the buffer layer 115 may be formed on the entire substrate 110. The buffer layer 115 may prevent metal atoms or impurities from diffusing from the substrate 110 into the driving transistor, the switching transistor, and the sub-pixel structure, and may control the heat transfer rate during the crystallization process for forming the first active layer 130 to obtain a substantially uniform first active layer 130. In addition, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be formed on the substrate 110. For example, the buffer layer 115 may be formed using an organic material or an inorganic material.

[0129] The first active layer 130 may be formed on the buffer layer 115 in the first region 11. For example, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, an organic semiconductor, etc. In an embodiment, the first active layer 130 may include a silicon-based semiconductor and may be formed using amorphous silicon or polycrystalline silicon. In an embodiment, the first active layer 130 may have a source region and a drain region.

[0130] Reference Figure 8 , a gate insulating layer 150 may be formed on the buffer layer 115 and the first active layer 130 in the first region 11 and the second region 12. For example, the gate insulating layer 150 may cover the first active layer 130 in the first region 11 on the buffer layer 115, and may extend into the bending region 50. That is, the gate insulating layer 150 may be formed on the entire buffer layer 115. For example, the gate insulating layer 150 may fully cover the first active layer 130 on the buffer layer 115, and may have a substantially flat upper surface without generating steps around the first active layer 130. Alternatively, the gate insulating layer 150 may cover the first active layer 130 on the buffer layer 115, and may be formed to have a substantially uniform thickness along the contour of the first active layer 130. The gate insulating layer 150 may be formed using a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 150 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfOx 、ZrO x 、TiO x Etc. Alternatively, the gate insulating layer 150 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0131] The first gate electrode 170 may be formed on the gate insulating layer 150 in the first region 11. For example, the first gate electrode 170 may be formed on a portion of the gate insulating layer 150 under which the first active layer 130 is located. The first gate electrode 170 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0132] The first insulating interlayer 190 may be formed on the gate insulating layer 150 and the first gate electrode 170 in the first region 11 and the second region 12. For example, the first insulating interlayer 190 may cover the first gate electrode 170 in the first region 11 on the gate insulating layer 150, and may extend into the bending region 50. That is, the first insulating interlayer 190 may be formed on the entire gate insulating layer 150. For example, the first insulating interlayer 190 may fully cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface without generating steps around the first gate electrode 170. Alternatively, the first insulating interlayer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be formed to have a substantially uniform thickness along the contour of the first gate electrode 170. The first insulating interlayer 190 may be formed using a silicon compound, a metal oxide, or the like. Alternatively, the first insulating interlayer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0133] A gate electrode pattern 180 may be formed on the first insulating interlayer 190 in the first region 11. The gate electrode pattern 180 may be formed on a portion of the first insulating interlayer 190 under which the first gate electrode 170 is located. The gate electrode pattern 180 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Alternatively, the gate electrode pattern 180 may have a multilayer structure including a plurality of layers.

[0134] A second gate electrode 175 may be formed on the first insulating interlayer 190 in the second region 12. In an embodiment, the second gate electrode 175 and the gate electrode pattern 180 may be located at the same layer and may be formed simultaneously using the same material. The second gate electrode 175 may be formed using metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0135] The second insulating interlayer 195 may be formed on the gate electrode pattern 180 and the second gate electrode 175 in the first region 11 and the second region 12. For example, the second insulating interlayer 195 may cover the gate electrode pattern 180 in the first region 11 on the first insulating interlayer 190 and cover the second gate electrode 175 in the second region 12 on the first insulating interlayer 190, and may extend into the bending region 50. That is, the second insulating interlayer 195 may be formed on the entire first insulating interlayer 190. For example, the second insulating interlayer 195 may fully cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may have a substantially flat upper surface without generating steps around the gate electrode pattern 180 and the second gate electrode 175. Alternatively, the second insulating interlayer 195 may cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may be formed to have a substantially uniform thickness along the contours of the gate electrode pattern 180 and the second gate electrode 175. The second insulating interlayer 195 may be formed using a silicon compound, a metal oxide, etc. Alternatively, the second insulating interlayer 195 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0136] A second active layer 135 may be formed on the second insulating interlayer 195 in the second region 12. The second active layer 135 may be formed on a portion of the second insulating interlayer 195, and the second gate electrode 175 is located below the portion of the second insulating interlayer 195. The second active layer 135 may be formed using a metal oxide semiconductor. In other words, the second active layer 135 may be a semiconductor oxide layer including a binary compound, a ternary compound, or a quaternary compound including In, Zn, Ga, Sn, Ti, Al, Hf, Zr, Mg, etc. For example, the second active layer 135 may include ZnO x 、GaO x 、TiO x SnO x 、InO x ,IGO,IZO,ITO,GZO,ZMO,ZTO,ZnZr x O y , IGZO, IZTO, IGHO, TAZO, IGTO, etc.

[0137] After forming the second active layer 135 , a first contact hole 212 exposing a source region of the first active layer 130 may be formed by removing a first portion of each of the gate insulating layer 150 , the first insulating interlayer 190 , and the second insulating interlayer 195 .

[0138] Reference Fig. 9 , the first source electrode 210 can be connected to the source region of the first active layer 130 through the first contact hole 212. The first source electrode 210 can be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first source electrode 210 may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, an aluminum alloy, AlN x , silver alloy, WN x , copper alloy, molybdenum alloy, TiN x CrN x 、TaN x 、SrRu x O y 、ZnO x 、ITO、SnO x 、InO x 、GaO x , IZO, etc. These may be used alone or in combination with each other.

[0139] In an embodiment, the first source electrode 210 may have a first thickness T1 and may be formed as a single layer. For example, the first source electrode 210 may be formed using Mo. In other embodiments, the first source electrode 210 may have a multilayer structure including a plurality of layers.

[0140] A second source electrode 215 and a second drain electrode 235 may be formed on the second insulating interlayer 195 in the second region 12. The second source electrode 215 may cover a first side portion of the second active layer 135, and the second drain electrode 235 may cover a second side portion of the second active layer 135 that is different from the first side portion. In other words, the second source electrode 215 and the second drain electrode 235 may be formed at two lateral portions of the second active layer 135, and a portion of the upper surface of the second active layer 135 may be exposed. Each of the second source electrode 215 and the second drain electrode 235 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0141] In an embodiment, the second source electrode 215 and the second drain electrode 235 may have a first thickness T1 and may be formed as a single layer. For example, each of the second source electrode 215 and the second drain electrode 235 may include Mo. In addition, the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 may be located at the same layer and may be formed simultaneously using the same material. In other embodiments, each of the second source electrode 215 and the second drain electrode 235 may have a multilayer structure including a plurality of layers. Therefore, a switching transistor 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215 and a second drain electrode 235 may be formed.

[0142] The protective insulating layer 400 may be formed on the second insulating interlayer 195, the first source electrode 210, the second source electrode 215, and the second drain electrode 235 in the first region 11 and the second region 12. For example, the protective insulating layer 400 may cover the first source electrode 210 in the first region 11 on the second insulating interlayer 195 and the second source electrode 215 and the second drain electrode 235 in the second region 12 on the second insulating interlayer 195, and may extend into the bending region 50. That is, the protective insulating layer 400 may be formed on the entire second insulating interlayer 195. For example, the protective insulating layer 400 may fully cover the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 195, and may have a substantially flat upper surface without generating steps around the first source electrode 210 and the second source electrode 215 and the second drain electrode 235. Alternatively, the protective insulating layer 400 may cover the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 195, and may be formed to have a substantially uniform thickness along the contours of the first source electrode 210 and the second source electrode 215 and the second drain electrode 235. The protective insulating layer 400 may be formed using a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0143] Reference Fig.10 After forming the protective insulating layer 400, a second contact hole 232 exposing the drain region of the first active layer 130 can be formed by removing a second portion of each of the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195 and the protective insulating layer 400, and an opening 102 exposing the upper surface of the second organic layer 113 located in the bending area 50 can be formed by removing a portion of each of the second blocking layer 114, the buffer layer 115, the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195 and the protective insulating layer 400.

[0144] Reference Fig.11 , the first drain electrode 230 may be connected to the drain region of the first active layer 130 through the second contact hole 232. In an embodiment, the first drain electrode 230 may have a second thickness T2 greater than the first thickness T1, and may be formed into a plurality of layers. The first drain electrode 230 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first drain electrode 230 may have a stacked structure of Ti / Al / Ti. In addition, the first drain electrode 230 may extend in a first direction D1, which is a direction from the first region 11 to the second region 12. In other words, a portion of the first drain electrode 230 may overlap with the first gate electrode 170, the gate electrode pattern 180, and the first source electrode 210, and may not overlap with the second active layer 135. Therefore, a driving transistor 250 including the first active layer 130, the first gate electrode 170, the first source electrode 210, and the first drain electrode 230 may be formed.

[0145] A first planarization layer 270 may be formed on the protective insulating layer 400 and the first drain electrode 230. The first planarization layer 270 may be formed on the entire protective insulating layer 400. For example, the first planarization layer 270 may be formed to have a relatively thick thickness to fully cover the first drain electrode 230, and in this case, the first planarization layer 270 may have a substantially flat upper surface. In addition, a planarization process may be added to the first planarization layer 270 to achieve a flat upper surface of the first planarization layer 270. In an embodiment, the first planarization layer 270 may fill the opening 102 located in the bending region 50. In other words, the first planarization layer 270 may be in direct contact with the upper surface of the second organic layer 113 located in the bending region 50. The first planarization layer 270 may include an organic material or an inorganic material. In an embodiment, the first planarization layer 270 may be formed using an organic material. For example, the first planarization layer 270 may include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, or the like.

[0146] Reference Fig.12 , a signal wiring 350 and a connection pattern 370 may be formed on the first planarization layer 270. Each of the signal wiring 350 and the connection pattern 370 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, each of the signal wiring 350 and the connection pattern 370 may be formed simultaneously using the same material and may have a stacked structure of Ti / Al / Ti.

[0147] A second planarization layer 275 may be formed on the first planarization layer 270, the signal wiring 350, and the connection pattern 370. The second planarization layer 275 may be formed on the entire first planarization layer 270. For example, the second planarization layer 275 may be formed to have a relatively thick thickness to sufficiently cover the signal wiring 350 and the connection pattern 370, and in this case, the second planarization layer 275 may be a substantially flat upper surface. In addition, a planarization process may be added to the second planarization layer 275 to achieve such a flat upper surface of the second planarization layer 275. Alternatively, the second planarization layer 275 may not be formed in the pad region 60. The second planarization layer 275 may include an organic material or an inorganic material. In an embodiment, the second planarization layer 275 may be formed using an organic material.

[0148] A lower electrode 290 may be formed on the second planarization layer 275. The lower electrode 290 may be connected to the connection pattern 370 via a contact hole formed by removing a portion of the second planarization layer 275. The lower electrode 290 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0149] A pixel defining layer 310 may be formed on a portion of the lower electrode 290 and the second planarization layer 275. The pixel defining layer 310 may cover two lateral portions of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In an embodiment, the pixel defining layer 310 may be formed using an organic material. Alternatively, the lower electrode 290 may not be formed in the pad region 60.

[0150] Reference Fig.13 , a light emitting layer 330 may be formed on the lower electrode 290 exposed by the pixel defining layer 310. The light emitting layer 330 may be formed using at least one of the light emitting materials for emitting light of different colors (i.e., red light, green light, blue light, etc.) according to the sub-pixel. Alternatively, the light emitting layer 330 may be formed by stacking a plurality of light emitting materials for emitting light of different colors such as red light, green light, or blue light to emit white light as a whole. In this case, a color filter may be formed on the light emitting layer 330. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin, a color photoresist, or the like.

[0151] The upper electrode 340 may be formed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be formed entirely on the light emitting layer 330 and the pixel defining layer 310. The upper electrode 340 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with one another. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Thus, a sub-pixel structure 200 including a lower electrode 290, a light emitting layer 330, and an upper electrode 340 may be formed.

[0152] A first thin film encapsulation layer 451 may be formed on the upper electrode 340 in the light emitting region 30. The first thin film encapsulation layer 451 may cover the upper electrode 340 in the light emitting region 30, and may be formed to have a substantially uniform thickness along the contour of the upper electrode 340. The first thin film encapsulation layer 451 may prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. In addition, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from external impact. The first thin film encapsulation layer 451 may be formed using a flexible inorganic material.

[0153] A second thin film encapsulation layer 452 may be formed on the first thin film encapsulation layer 451 in the light emitting region 30. The second thin film encapsulation layer 452 may improve the flatness of the organic light emitting display device and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may be formed of a flexible organic material.

[0154] A third thin film encapsulation layer 453 may be formed on the second thin film encapsulation layer 452 in the light emitting region 30. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the light emitting region 30, and may be formed to have a substantially uniform thickness along the contour of the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. together with the first thin film encapsulation layer 451. In addition, the third thin film encapsulation layer 453 may be used to protect the sub-pixel structure 200 from external impact together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may include a flexible inorganic material. Therefore, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453 may be formed. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first to fifth thin film encapsulation layers or a seven-layer structure formed by stacking the first to seventh thin film encapsulation layers.

[0155] After forming the thin film encapsulation structure 450, the glass substrate 105 may be removed from the substrate 110, and the Figure 6 The organic light emitting display device 100 is shown in FIG.

[0156] Fig.14 is a cross-sectional view showing an organic light emitting display device according to an embodiment of the present invention, and Fig.15 It shows Fig.14 In addition to the first signal wiring 350 and the second signal wiring 355, Fig.14 The organic light emitting display device 500 shown in FIG. Figures 1 to 6 The organic light emitting display device 100 described above has substantially the same or similar structure. Fig.14 In the example, the reference to Figures 1 to 6 Redundant description of elements where the elements described are substantially the same or similar.

[0157] Reference Fig.14 The organic light-emitting display device 500 may include a substrate 110, a buffer layer 115, a driving transistor 250, a switching transistor 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating intermediate layer 190, a second insulating intermediate layer 195, a protective insulating layer 400, a first planarization layer 270, a first signal wiring 350, a second signal wiring 355, a connection pattern 370, a second planarization layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, etc.

[0158] The first signal wiring 350 and the second signal wiring 355 may be disposed on the first planarization layer 270 and may be spaced apart from each other. A data signal may be applied to the first signal wiring 350 and the second signal wiring 355. For example, in order to drive the organic light emitting display device 500 at a high speed, Figure 5 The sub-pixel circuit SPC may include two data wirings. For example, because the sub-pixel circuit SPC included in the organic light-emitting display device 500 includes two data wirings, the speed of transmitting a data signal may be doubled, and the organic light-emitting display device 500 may be driven at a high speed.

[0159] Even though the first signal wiring 350 and the second signal wiring 355 are provided, the organic light emitting display device 500 has a relatively increased width and includes the first drain electrode 230 to which a constant voltage is applied, so that the characteristics of the driving transistor 250 may be maintained.

[0160] In other embodiments, Fig.15 As stated above, Fig.14 In contrast, the shape of the first source electrode 210 and the shape of the first drain electrode 230 may be changed. In other words, the first source electrode 210 may be formed of a wiring having a relatively large width and a relatively large thickness.

[0161] The foregoing is an illustration of an embodiment and is not to be construed as limiting the embodiments. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications can be made in the embodiments without departing substantially from the novel teachings and advantages of the inventive concept. Therefore, it is intended that all such modifications be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and is not to be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

[0162] Industrial Applicability

[0163] The present invention can be applied to various electronic devices including organic light-emitting display devices. For example, the present invention can be applied to many electronic devices, such as vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0164] Description of Reference Numerals

[0165] 10: Display area 11: First area

[0166] 12: Second area 20: Sub-pixel circuit area

[0167] 30: Luminous area 40: Peripheral area

[0168] 50: bending area 60: pad area 70: pad electrode area 100, 500: organic light emitting display device 101: external device 102: opening

[0169] 105: Glass substrate 110: Substrate

[0170] 111: first organic layer 112: first barrier layer

[0171] 113: second organic layer 114: second barrier layer

[0172] 115: buffer layer 130: first active layer

[0173] 135: second active layer 150: gate insulating layer

[0174] 170: first gate electrode 175: second gate electrode

[0175] 180: gate electrode pattern 190: first insulating interlayer 195: second insulating interlayer 200: sub-pixel structure 210: first source electrode 215: second source electrode

[0176] 230: first drain electrode 235: second drain electrode

[0177] 250: driving transistor 255: switching transistor

[0178] 270: first planarization layer 275: second planarization layer 290: lower electrode 310: pixel definition layer

[0179] 330: Light-emitting layer 340: Upper electrode

[0180] 350: first signal wiring 370: connection pattern

[0181] 400: Protective insulation layer 450: Thin film encapsulation structure

[0182] 451: first thin film encapsulation layer 452: second thin film encapsulation layer 453: third thin film encapsulation layer 470: pad electrode

Claims

1. An organic light emitting display device, comprising: A light-emitting area, the light-emitting area comprising a first area and a second area; Wherein, the organic light emitting display device further comprises: substrate; a first active layer having a source region and a drain region, wherein the first active layer is disposed on the substrate in the first region; A gate insulating layer, disposed on the first active layer; A first gate electrode, disposed on the gate insulating layer; A first insulating interlayer, disposed on the first gate electrode; A second insulating intermediate layer, disposed on the first insulating intermediate layer; a first source electrode disposed on the second insulating interlayer, the first source electrode being connected to the source region of the first active layer via a contact hole formed by removing a portion of the gate insulating layer, the first insulating interlayer, and the second insulating interlayer; a protective insulating layer, disposed on the first source electrode; a first drain electrode disposed on the protective insulating layer, the first drain electrode being connected to the drain region of the first active layer via a contact hole formed by removing a portion of the gate insulating layer, the first insulating interlayer, the second insulating interlayer and the protective insulating layer, the first drain electrode constituting a driving transistor together with the first active layer, the first gate electrode and the first source electrode; a switching transistor disposed between the substrate and the protective insulating layer in the second region; A lower electrode, disposed on the switch transistor and the drive transistor; a light-emitting layer, disposed on the lower electrode; and an upper electrode, disposed on the light-emitting layer, The organic light emitting display device further comprises: a gate electrode pattern, which is arranged on the first gate electrode. wherein the first drain electrode extends on the protective insulating layer in a first direction, the first direction being a direction from the first region to the second region, and a portion of the first drain electrode overlaps the first gate electrode, the gate electrode pattern, and the first source electrode, Wherein, a high power supply voltage is applied to the first drain electrode.

2. The organic light emitting display device according to claim 1, wherein: The first source electrode includes a single layer, and the first drain electrode includes a plurality of layers.

3. The organic light emitting display device according to claim 2, wherein: The first source electrode includes molybdenum, and the first drain electrode has a stack structure of titanium / aluminum / titanium.

4. The organic light emitting display device according to claim 1, further comprising: The signal wiring is arranged on the first drain electrode.

5. The organic light emitting display device according to claim 4, wherein: A data signal is applied to the signal wiring, and Therein, a low power supply voltage is applied to the upper electrode.

6. The organic light emitting display device according to claim 1, wherein: The switching transistor comprises: a second gate electrode; a second active layer disposed on the second gate electrode; and A second source electrode and a second drain electrode are disposed at two lateral portions of the second active layer.

7. The organic light emitting display device according to claim 6, wherein: The first drain electrode does not overlap the second active layer.

8. The organic light emitting display device according to claim 6, wherein: The driving transistor has a top gate structure, and the first active layer includes a silicon-based semiconductor, and Wherein, the switch transistor has a bottom gate structure, and the second active layer includes a metal oxide-based semiconductor.

9. The organic light emitting display device according to claim 8, wherein: The first active layer of the driving transistor includes amorphous silicon or polycrystalline silicon.

10. The organic light emitting display device according to claim 6, wherein: The gate electrode pattern and the second gate electrode are located at the same layer.

11. The organic light emitting display device according to claim 1, wherein: The substrate comprises: A first organic layer; A first barrier layer, disposed on the first organic layer; a second organic layer disposed on the first barrier layer; and The second barrier layer is disposed on the second organic layer.

12. The organic light emitting display device according to claim 11, wherein: The organic light emitting display device further comprises: a curved region spaced apart from the light emitting region, and The second barrier layer has an opening exposing an upper surface of the second organic layer in the bent region.

13. The organic light emitting display device according to claim 1, wherein: The organic light emitting display device further comprises: a curved region, spaced apart from the light emitting region, Wherein, the organic light emitting display device further comprises: a buffer layer disposed on the substrate in the first region and the second region and extending into the bending region, the buffer layer having a first opening exposing an upper surface of the substrate in the bending region, The gate insulating layer covers the first active layer in the first region on the buffer layer and extends into the curved region, and has a second opening overlapping the first opening, and The first insulating interlayer covers the first gate electrode in the first region on the gate insulating layer and extends into the bending region, and has a third opening overlapping the first opening and the second opening.

14. The organic light emitting display device according to claim 1, further comprising: A thin film encapsulation structure is arranged on the upper electrode, Wherein, the thin film encapsulation structure comprises: A first thin film encapsulation layer includes a flexible inorganic material; a second thin film encapsulation layer, disposed on the first thin film encapsulation layer, wherein the second thin film encapsulation layer comprises a flexible organic material; and The third thin film encapsulation layer is disposed on the second thin film encapsulation layer, and the third thin film encapsulation layer includes a flexible inorganic material.

15. The organic light emitting display device according to claim 1, wherein: The first source electrode has a first thickness, and the first drain electrode has a second thickness greater than the first thickness.

16. An organic light emitting display device, comprising: A bending area and a light emitting area, wherein the light emitting area includes a first area and a second area; Wherein, the organic light emitting display device further comprises: substrate; A driving transistor is disposed on the substrate in the first region, the driving transistor comprising: A first active layer having a source region and a drain region; a first gate electrode, disposed on the first active layer; a first source electrode disposed on the first gate electrode, the first source electrode being connected to the source region of the first active layer through a first contact hole, the first source electrode having a first thickness; and a first drain electrode disposed on the first source electrode, the first drain electrode being connected to the drain region of the first active layer through a second contact hole, the first drain electrode having a second thickness greater than the first thickness; a switching transistor disposed on the substrate in the second region; and A sub-pixel structure is arranged on the switch transistor and the drive transistor, The organic light emitting display device further comprises: a gate electrode pattern, which is arranged on the first gate electrode. wherein the first drain electrode extends on the first source electrode in a first direction, the first direction being a direction from the first region to the second region, and a portion of the first drain electrode overlaps with the first gate electrode, the gate electrode pattern and the first source electrode, wherein a high power supply voltage is applied to the first drain electrode.

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