Hybrid self-tracking reference circuit for RRAM cells

Abstract

An automatic tracking reference circuit is provided that compensates for IR drop and achieves a target resistance state at different temperatures after a write operation. The disclosed self-tracking reference circuit includes a replica access path that tracks PVT variations to provide a PVT tracking level for an RRAM verify operation, a configurable resistor network, a replica selector mini-array, and a step current generator.

Description

Technical Field

[0001] An embodiment of the present invention relates to a hybrid self-tracking reference circuit for a RRAM cell. Background Art

[0002] Memory devices are used to store information in semiconductor devices and systems. A resistive random access memory (RRAM) cell is a memory cell that stores information based on changes in resistance. Generally speaking, an RRAM cell includes a bottom electrode, a resistive switching layer, and a storage node of a top electrode that can be stacked in sequence. The resistance of the resistive switching layer changes according to the applied voltage. The RRAM cell can be in multiple states with different resistances. Each different state can represent digital information. The state can be changed by applying a predetermined voltage or current between the electrodes. The state can be maintained as long as the predetermined operation is not performed. Summary of the invention

[0003] An embodiment of the present invention provides a current reference circuit for a resistive random access memory (RRAM) cell, comprising: a configurable resistor network, wherein the configurable resistor network is configured to simulate a resistive element of the RRAM cell; a replica access path, wherein the replica access path is connected to a first terminal of the configurable resistor network, and wherein the replica access path simulates an access path associated with the RRAM cell; a replica selector circuit, which is connected to a second terminal of the configurable resistor network, and wherein the replica selector circuit simulates a selector circuit associated with the RRAM cell; a step current generator circuit, which is connected to the configurable resistor network, wherein the step current generator is used to adjust a reference current level provided by the current reference circuit; and wherein the replica access path, the configurable resistor network, the replica selector circuit, and the step current generator circuit are configured to track process, voltage, and temperature (PVT) variations.

[0004] An embodiment of the present invention provides a system, comprising: a resistive random access memory (RRAM) device, wherein the RRAM device includes: an RRAM cell; a first terminal of an access path connected to the first terminal of the RRAM cell; and a selector circuit connected to the second terminal of the RRAM cell; a current reference circuit; and a sense amplifier circuit including two input terminals. The current reference circuit includes: a configurable resistor network, wherein the configurable resistor network is configured to simulate a resistive element of the RRAM cell; a replica access path, wherein the first terminal of the replica access path is connected to the first terminal of the configurable resistor network, and wherein the replica access path simulates the access path associated with the RRAM cell; and a replica selector circuit connected to the second terminal of the configurable resistor network, and wherein the replica selector circuit simulates the selector circuit associated with the RRAM cell. The second terminal of the access path is connected to one input terminal of the sense amplifier circuit, and the second terminal of the replica access path is connected to another input terminal of the sense amplifier circuit.

[0005] An embodiment of the present invention provides a method, comprising: selectively connecting one of a first RRAM device or a second RRAM device to a first input terminal of a sense amplifier, wherein each of the first RRAM device and the second RRAM device comprises an RRAM cell; configuring a reference circuit to simulate the selected first RRAM device or the selected second RRAM device; generating a reference current through the reference circuit that tracks process, voltage, and temperature (PVT) changes; selectively connecting the reference circuit to a second input terminal of the sense amplifier; and comparing a current value of the selected first RRAM device or the selected second RRAM device with the reference current through the sense amplifier to read data from the first RRAM cell or the second RRAM cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram is shown of an example self-tracking reference circuit for a memory device in accordance with some embodiments.

[0007] Figure 2 A circuit diagram illustrating an example self-tracking reference circuit for a memory device in accordance with some embodiments.

[0008] Figure 3a and Figure 3b Circuit diagrams showing two example configurations of the configurable resistor network 112 .

[0009] Figure 4a , Figure 4b as well as Figure 4cCircuit diagrams showing three example configurations of replica selector mini-array 116.

[0010] Figure 5 Graph 500 shows an example relationship between RRAM cell current and bit count and the effect of step current injection on the relationship.

[0011] Figure 6 An example method of reading data from a RRAM cell using a self-tracking reference circuit is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another (some) or more elements or features as shown in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0014] RRAM is a promising non-volatile memory technology for embedded applications due to its low cost and compatibility with logic processes. However, the reliability of RRAM is related to its resistance state or filament size. A write / verify process is often used to achieve the target resistance state. A read sense amplifier can be used to perform the verification process and ensure that the read margin (readwindow) has been established.

[0015] Prior art uses a constant current source for read / verify operations. However, using a constant current source for verification over a wide temperature range can result in over / under writing of RRAM elements. Once the RRAM is over-set / reset, the endurance of the RRAM is reduced and the RRAM cell can only be written with fewer counts. Once the RRAM is weakly set / reset, the retention of the RRAM is reduced and the RRAM cell data can be easily lost. Therefore, using a constant current level over a wide temperature range may affect the reliability of the RRAM.

[0016] The disclosed example provides a self-tracking reference circuit that compensates for IR drop after a write operation and achieves a target resistance state at different temperatures. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array, and a step current generator to provide process, voltage, and temperature (PVT) tracking levels to perform verification and normal read operations.

[0017] Figure 1 A block diagram 100 of an example self-tracking reference circuit for a memory device according to some embodiments is shown. In some examples, the self-tracking reference circuit is used in a resistive memory cell 102, such as a resistive random access memory (RRAM) cell. Other examples are also possible. The resistive memory cell includes a resistive element having a high-k dielectric material layer arranged between conductive electrodes, wherein the conductive electrodes are disposed within a back-end-of-the-line (BEOL) metallization stack. The resistive memory cell is configured to operate based on a reversible switching process between resistive states. This reversible switching is achieved by selectively forming a conductive filament in the high-k dielectric material layer. For example, a voltage can be applied across the conductive electrodes to form a conductive filament extending through the high-k dielectric material layer to make the normally insulating high-k dielectric material layer conductive. A resistive memory cell having a first (e.g., high) resistive state (HRS) or reset corresponds to a first data value (e.g., logic '0'), and a resistive memory cell having a second (e.g., low) resistive state (LRS) or set corresponds to a second data value (e.g., logic '1').

[0018] In the disclosed example, one terminal of the RRAM cell 102 is connected to an access path 104 that connects the RRAM cell 102 to a sense amplifier circuit 108. Another terminal of the RRAM cell 102 is connected to a selector circuit 106. Typically, the access path 104 is configured to be switched using one or more transistors to achieve greater control over the operation of the sense amplifier circuit 108. In RRAM memory devices, selector devices are typically used to suppress leakage currents that may reduce sensing margins. In some examples, the selector circuit 106 is connected in series with the RRAM memory cell 102 and may be implemented using one or more transistors. In other examples, the selector circuit may be implemented using a diode. Other implementations are also possible.

[0019] In some examples, in order to read the current of the RRAM cell and decrypt the data bit stored in the RRAM cell, a sense amplifier circuit 108 may be used. The sense amplifier circuit 108 may be a current-mode sense amplifier circuit that may be designed to have a low input impedance so that most of the RRAM current may be conducted into the sense amplifier circuit 108 itself. The sense amplifier circuit receives the current from the RRAM cell 102 and compares the current to a reference threshold current. Based on the comparison, the state of the RRAM cell 102 may be determined. Typically, a constant reference current is used as a threshold current that is compared to the RRAM device current at the sense amplifier circuit 108. The use of a constant reference current to establish a read margin during the verification process does not account for PVT variations. The disclosed examples use a self-tracking reference circuit that accounts for PVT variations and thus increases the reliability of the RRAM.

[0020] In some examples, a self-tracking reference circuit 110 including a configurable resistor network 112, a replica access path 114, a replica selector mini-array 116, and a step current generator 118 is used to provide PVT tracking levels for verify and normal read operations. Figures 2 to 5 Each component of the self-tracking reference circuit 110 is described in further detail.

[0021] Figure 2 A circuit diagram 200 of an example self-tracking reference circuit for a memory device according to some embodiments is shown. The example circuit 200 shows two RRAM devices sharing a self-tracking reference circuit. For example, in the disclosed example 200, the two RRAM devices include a left RRAM device and a right RRAM device sharing a central self-tracking reference circuit. Other configurations are also possible.

[0022] In some examples, the left RRAM device includes an RRAM_L cell 202 connectable to an access path 204 and a selector_L device 210, the right RRAM device includes an RRAM_R cell 212 connectable to an access path 214 and a selector_R device 220, and the center self-tracking reference circuit includes a configurable resistor network 112, a replica access path 114, and a replica selector mini-array 116. In some examples, the self-tracking reference circuit architecture also includes a step current generator circuit 118.

[0023] In some examples, RRAM_L 202 and RRAM_R 212 are connected to sense amplifier circuit 108 through access path 204 and access path 214, respectively. A self-tracking reference circuit including a configurable resistor network 112 is also connected to sense amplifier circuit 108 through a replica access path 114.

[0024] In some examples, the access path 204 utilized by the left RRAM device (also including the RRAM_L cell 202) and the selector_L circuit 210 includes two NMOS transistor switches 206 and an NMOS transistor switch 208. The two NMOS transistors (one clamp device 206 and one switch 208) are controlled by a clamp voltage VCL and a control signal SC_L. In some other examples, the access path 214 utilized by the right RRAM device (also including the RRAM_R cell 212) and the selector_R circuit 220 includes two NMOS transistor switches 216 and an NMOS transistor switch 218. The two NMOS transistors (one clamp device 216 and one switch 218) are controlled by a clamp voltage VCL and a control signal SC_R.

[0025] In some examples, the replica access path 114 utilized by the self-tracking reference circuit including the configurable resistor network 112 and the replica selector mini-array circuit 116 includes an NMOS transistor switch 222 and an NMOS transistor switch 224 controlled by a control signal SR_L and a control signal SR_R, respectively. The NMOS transistor switch 222 may be matched to the same size as the NMOS transistor switch 208, and the NMOS transistor switch 224 may be matched to the same size as the NMOS transistor switch 218. The access path 204, the access path 214, and the replica access path 114 ultimately connect the RRAM_L cell 202, the RRAM_R cell 212, and the configurable resistor network 112 to the sense amplifier circuit 108. Although the disclosed embodiment uses NMOS switches, other devices may also be used in the configuration of the access path 204 and the access path 214.

[0026] In some examples, the sense amplifier circuit 108 may use, for example, Figure 2However, other sense amplifier circuit architectures may also be used.

[0027] In some examples, the sense amplifier circuit 108 operates at one time to compare the current value of RRAM_L 202 with the current value of the self-tracking reference circuit. Alternatively, the sense amplifier circuit 108 may operate to compare the current value of RRAM_R 212 with the current value of the self-tracking reference circuit. The clamp devices 206, 216 and the transistor switches 208, 218, 222, 224 may be controlled using the clamp voltage VCL and the control signals SC_L, SC_R, SR_L, and SR_R to select the RRAM device current input to the sense amplifier circuit 108 at any time.

[0028] For example, if the sense amplifier circuit 108 is configured to perform a read operation on the RRAM_L cell 202, the sense amplifier circuit 108 receives the left RRAM device path and the self-tracking reference circuit as two inputs. The clamp device 206 and the clamp device 216 are turned on by VCL to define the read voltage level. Such a configuration can be achieved by turning on the transistor device 208 to enable the access path 204 to connect the RRAM_L cell 202 to the sense amplifier circuit 108. In addition, the self-tracking reference circuit path can be configured as the second input of the sense amplifier circuit 108 by turning on the transistor device while turning off the transistor device 222 and the transistor device 218. Such a configuration produces a path in which the configurable resistor network 112 is connected to the sense amplifier circuit 108 through the access path including the transistor device 224 and the transistor device 216. The access path 214 connecting the RRAM_R cell 212 to the sense amplifier circuit 108 is disabled.

[0029] On the other hand, for example, if the sense amplifier circuit 108 is configured to perform a read operation on the RRAM_R cell 212, the sense amplifier circuit 108 receives the right RRAM device path and the self-tracking reference circuit as two inputs. The clamp device 206 and the clamp device 216 are turned on by VCL to define the read voltage level. Such a configuration can be achieved by turning on the transistor device 218 to enable the access path 214 to connect the RRAM_R cell 212 to the sense amplifier circuit 108. In addition, the self-tracking reference circuit path can be configured as the second input of the sense amplifier circuit 108 by turning on the transistor device 222 while turning off the transistor device 224 and the transistor device 208. Such a configuration produces a path in which the configurable resistor network 112 is connected to the sense amplifier circuit 108 through the access path including the transistor device 222 and the transistor device 206. The access path 204 of the RRAM_L cell 202 connected to the sense amplifier 108 is disabled.

[0030] In some examples, the configurable resistor network 112 is configured to emulate a resistive element of the RRAM_L cell 202 or the RRAM_R cell 212. The configurable resistor network 112 can be configured to emulate an RRAM element of the resistive element of the RRAM_L cell 202 or the RRAM_R cell 212 by adjusting one or more resistors in the configurable resistor network 112 so that the total resistance value of the configurable resistor network 112 matches the resistance value of the RRAM cell in a particular state. The configurable resistor network 112 can be implemented using a series configuration or a parallel configuration. Figure 3a and Figure 3b The configurable resistor network 112 is described in further detail.

[0031] Selector_L circuit 210 and selector_R circuit 220 are selector circuits that can be implemented using one or more transistors. Selector circuit mini-array 116 is configured to emulate RRAM select transistor design and reflect temperature effects to track cell resistance. Selector circuit mini-array 116 can be composed of a series and parallel network of transistors to minimize device process variations. Reference Figure 4a , Figure 4b as well as Figure 4c The replica selector mini-array 116 is described in further detail.

[0032] In some examples, the step current generator circuit 118 can be used to generate a small current difference for writing verification levels of the RRAM cells 202 and 212 to achieve gradual boundary fine-tuning. For example, the step current generator circuit 118 can include a current generator circuit and a current mirror circuit to generate a current, which can then be injected into the reference circuit path and can be controlled using a switch. The switch can be implemented using NMOS transistor devices 226 and NMOS transistor devices 228. For example, when RRAM_R 212 is enabled and SC_L 208 is disabled, the NMOS transistor 226 can be used to enable current to be injected from the step current generator circuit 118 and injected into the reference circuit path. The control signal SM_L is controlled when the NMOS transistor device 226 is enabled / disabled. When the RRAM_L 202 is enabled and the SC_R 218 is disabled, the NMOS transistor 228 can be used to enable current to be injected from the step current generator circuit 118 and injected into the reference circuit path. The control signal SM_R controls when the NMOS transistor device 228 is enabled / disabled. Other ways of implementing the switch are also possible. Figure 5 The operation of the step current generator circuit 118 is described in further detail.

[0033] Figure 3a and Figure 3b A circuit diagram 300 is shown of two example configurations of a configurable resistor network 112. The configurable resistor network 112, which has less temperature dependency than an RRAM resistive element, emulates an RRAM element and provides a set verify level, a reset verify level, and a normal read level. The configurable resistor network includes a plurality of resistors including trimmable resistors that can be configured to provide a verify level with minimal PVT variation.

[0034] Figure 3aA parallel configuration for a configurable resistor network 112 is shown. In some examples, the parallel configuration of the configurable resistor network includes three resistors 302, 306, and 310 connected in parallel, each of which can be configured to connect to or disconnect from the network using a transmission gate switch 304, a transmission gate switch 308, and a transmission gate switch 312. Each transmission gate switch includes a PMOS transistor device and an NMOS transistor device connected in parallel. For example, when the transmission gate switch 304 is enabled, the resistor 302 can contribute to the configurable resistor network 112 resistance by supplying RH (high resistance) to generate a reset verification level or HRS level. When the transmission gate switch 312 is enabled, the resistor 310 can contribute to the configurable resistor network 112 resistance by supplying RL (low resistance) to generate a set verification level or LRS level. When the transmission gate switch 308 is enabled, the resistor 306 can contribute to the configurable resistor network 112 resistance by supplying an intermediate resistance to generate a normal read level.

[0035] In some examples, in addition to supplying resistance values ​​through resistors 302, 306, or 310, trimmable step resistors 314 also contribute to the overall resistance of configurable resistor network 112. The trimmable step resistors may be configured to provide a smaller step resistance to provide a trim value to the RH, R_NR, or RL resistance values.

[0036] Figure 3b A series configuration for the configurable resistor network 112 is shown. Figure 3a The described configurable resistor network 112 can also be implemented using a series configuration. For example, resistor 316, resistor 318, and resistor 320 can be implemented in series by connecting to a shunt between each resistor of the copy access path. Enable all three resistors 316, 318, and 320 to supply a resistance value of RH (which is a high resistance) to generate a reset verification level. Enable two resistors 318, resistor 320 in the three resistors and enable the shunt connected to the copy access path (and thus bypass resistor 316) to supply a resistance value of R_NR (which is an intermediate resistance) to generate a normal read level. Enable one resistor 320 in the three resistors and enable the shunt between the resistor 316 and resistor 318 connected to the access path and the shunt between the resistor 318 and resistor 320 (and thus bypass resistor 316 and resistor 318) to supply a resistance value of RL (which is a low resistance) to generate a set verification level. Resistors 316, 318, and 320 are further connected in series to a trimmable step resistor 322 which provides a reference voltage. Figure 3a Similar trimming values ​​are discussed for trimmable step resistor 314 .

[0037] In some examples, the configurable resistor network can be used Figure 3a In other examples, the configurable resistor network may be implemented using the parallel configuration described in Figure 3b However, regarding Figure 3b The described series configuration can reduce area by up to 36 percent or even more depending on the technology and the size of the resistor values.Other configurations of the configurable resistor network 112 are also possible.

[0038] Figure 4a , Figure 4b as well as Figure 4c A circuit diagram 400 is shown of three example configurations of the replica selector mini-array 116. The replica selector mini-array may be configured to track the selector circuits 210, 220 associated with the RRAM cells 202, 212.

[0039] In some examples, the replica selector mini-array 116 can be configured to minimize RRAM cell current variation across PVT. Figures 4a to 4c Various implementations for replica mini-array circuit 116 are shown. For example, Figure 4a An embodiment of a replica selector mini-array circuit 116 including a single NMOS transistor device is shown. In a single NMOS transistor configuration, the implemented NMOS transistor device matches the selector circuit 210 or the selector circuit 220. It is also possible that other types of devices can be used to implement the single device replica selector mini-array circuit 116.

[0040] Although the replica selector mini-array 116 may use Figure 4a , but increasing the density of the replica selector mini-array 116 can reduce the reference current variation across PVT. A reference current that includes minimal variation across PVT can provide a verification level to set / reset the RRAM cell to the same resistance. However, increasing the density of the replica selector mini-array 116 comes with an increase in layout area. The trade-off between smaller current variation and smaller layout area can be evaluated by the implementer to determine the ideal density of the replica selector mini-array circuit 116 for the following application.

[0041] For example, Figure 4b FIG. 1 shows an embodiment of a replica selector mini-array circuit 116 including four NMOS transistor devices. Figure 4bAs shown in , a four-transistor configuration can be implemented using two sets of two NMOS transistors connected in a parallel configuration in a series configuration. The four-transistor configuration provides a topology that can be represented as (R / / R)+(R / / R), where "R" refers to the resistance associated with each transistor in the four-transistor configuration. The resistor value is related to the size of the transistor and can be adjusted by adjusting the resistor size. In the disclosed example, the transistor size is set to be the same so that the resistance value of each of the transistors in the four-transistor configuration is also the same.

[0042] For example, Figure 4c FIG. 1 shows an embodiment of a replica selector mini-array circuit 116 comprising nine NMOS transistor devices. Figure 4c As shown in , a nine-transistor configuration can be implemented using nine transistors connected in a series and parallel configuration. The nine-transistor configuration provides a topology that can be represented as (R / / R / / R)+(R / / R / / R)+(R / / R / / R). Similar to the four-transistor configuration, the nine-transistor configuration also uses "R" to designate the resistance associated with each transistor in the nine-transistor configuration.

[0043] In some examples, the nine-transistor replica selector mini-array circuit 116 provides a current variation that is 1-sigma less than that of the four-transistor replica selector mini-array circuit 116, and the four-transistor replica selector mini-array circuit 116 provides a current variation that is 1-sigma less than that of the single-transistor replica selector mini-array circuit 116. However, the number of transistors directly affects the layout area. For most applications, such as Figure 4b The four-transistor implementation shown in FIG. 4 can provide the best trade-off between smaller current variation and minimum layout area. Different implementations can also provide the best trade-off between current variation and layout area for different applications.

[0044] Figure 5 A graph 500 showing an example relationship between RRAM cell current and bit count and the effect of step current injection on the relationship. In some examples, the x-axis of the graph 500 shows the RRAM cell current and the y-axis of the graph shows the bit count. Curve 502 represents the RRAM cell current during a reset state or HRS. Curve 504 represents the RRAM cell during a set state or LRS during ideal operation. IR0 or RH level 506 can be the maximum RRAM cell current that can still represent a reset verification level, and IR1 or RL level 508 can be the minimum RRAM cell current that can still represent a set verification level. INR level 510 is an intermediate resistance level representing a normal read level. ΔI 512 represents the read margin and is the difference between the RRAM cell current at RH,IR0 506 and the RRAM cell current at RL,IR1 508.

[0045] In some examples, during normal operation of the RRAM device, the RRAM cell may frequently switch between HRS and LRS. However, each operation may cause permanent damage, sometimes referred to as degradation. Endurance or electrical fatigue is the number of set / reset cycles that can be sustained before the HRS and LRS are no longer distinguishable. When the RRAM cell is over-set / reset, the boundaries of the reset curve 502 and the set curve 504 deviate further, and the LRS may no longer reset to the HRS and the HRS may no longer set to the LRS.

[0046] The step current generator 116 can generate a small temperature constant current that can be injected to shift the boundaries of the reset curve 502 and the set curve 504, so that IR0 at RH 506 and IR1 at RL 508 can be shifted within the range of IR0 boundary current represented by dashed line 514 and within the range of IR1 boundary current represented by dashed line 516. Therefore, the step current generator 116 can generate a small current difference of the RRAM write verification level to achieve step boundary fine tuning. The injection of current is performed by Figure 2 The transistor switches 226 and 228 described in and the control signals SM_L and SM_R are controlled. In some examples, the stepwise boundary fine-tuning and the tailing bit can be set / reset by the proposed write bias and thus avoid the problem of over-set / reset.

[0047] Figure 6 An example method 600 is shown for reading data from an RRAM cell using a self-tracking reference circuit. The steps of the example method 600 may use, for example, a reference circuit. Figure 2 The example circuit described is implemented as a self-tracking reference circuit.

[0048] At example step 602, method 600 includes selectively connecting one of a first RRAM device or a second RRAM device to a sense amplifier circuit 108. For example, the first RRAM device and the second RRAM device each include: an RRAM cell; an access path connecting the RRAM cell to the sense amplifier circuit 108; and a selector circuit also connected to the RRAM cell. In some examples, the RRAM cell may include an RRAM cell, such as reference Figure 2 The RRAM_L cell 202 and the RRAM_R cell 204 are depicted. One of the terminals of the RRAM cell is connected to an access path, which can be accessed through one or more transistor devices (e.g., as described in reference Figure 2The selector circuit may be implemented by NMOS transistor device 206, NMOS transistor device 208 or NMOS transistor device 216, NMOS transistor device 218 as described above. The selector circuit may be a selector circuit, for example, as described in reference Figure 2 The selector_L 210 or the selector_R 220 described above can be selected using one or more switching devices to connect the first RRAM device or the second RRAM device to the first input terminal of the sense amplifier circuit, for example, using a switch as described in reference Figure 2 Embodiments of NMOS transistor device switch 208 , NMOS transistor device switch 222 , NMOS transistor device switch 214 , and NMOS transistor device switch 224 are described.

[0049] At example step 604 , the method 600 includes configuring a reference circuit to emulate the selected first RRAM device or second RRAM device. In some examples, the reference circuit includes a replica access path 114 , a configurable resistor network 112 , and a replica selector mini-array circuit 116 .

[0050] For example, the reference circuit can be configured to simulate the selected first RRAM device or the second RRAM device by configuring the configurable resistor network 112 to simulate the resistive element of the RRAM cell of the selected RRAM device. In some examples, the configurable resistor network 112 provides a set verification level, a reset verification level, and a normal read level. The configurable resistor network 112 can be composed of series and parallel combinations of resistors to provide a wide range of verification levels. The resistive element of the simulated RRAM cell includes a configuration resistor device (resistor 302, resistor 306, resistor 310 in the case of a parallel configuration and resistor 316, resistor 318, resistor 320 in the case of a series configuration) and a step resistor device 314 or a step resistor device 322 of the reference circuit to have a resistance that matches the resistance of the RRAM cell of the selected RRAM device. Reference Figure 2 , Figure 3a as well as Figure 3b The configurable resistor network 112 is described in further detail.

[0051] Additionally, in some examples, the reference circuit may be configured to emulate the selected first RRAM device or second RRAM device by configuring the replica access path 114 and the replica selector circuit 116 to emulate the access path 104 and the selector circuit 106 of the selected RRAM device.

[0052] In some examples, the replica access path 114 may be implemented to track one or more logic device resistances, metal line resistances, and leakages along an access path associated with the first RRAM device or the second RRAM device. The simulated access path 104 includes using a reference Figure 2 One or more transistor devices are described to match the impedance value of access path 104 .

[0053] In other examples, the replica selector mini-array circuit 116 is configured to reflect temperature effects to track the cell resistance. The replica selector mini-array 116 may be constructed from a series and parallel network of transistors to minimize device process variations. The analog selector circuit 106 includes a reference circuit such as Figure 2 , Figure 4a , Figure 4b as well as Figure 4c One or more transistor devices are described to match the impedance value of the selector circuit 106 .

[0054] At example step 606, method 600 includes generating a reference current that tracks process, voltage and temperature (PVT) variations. In some examples, during manufacturing, the physical layout of the reference circuit is typically placed close to the RRAM device. Therefore, the reference circuit will experience and track the PVT variations experienced by the RRAM device.

[0055] At example step 608, method 600 includes selectively connecting a reference circuit to a second input terminal of sense amplifier circuit 108. In some examples, the reference circuit may be connected to the second input terminal of sense amplifier circuit 108.

[0056] At example step 610, method 600 includes comparing a current value of the first RRAM device or the second RRAM device (which has been selected to be connected to the first input terminal of the sense amplifier circuit 108) with a current value of a reference circuit. Based on the comparison of the current values, a data value stored in the RRAM cell may be read. For example, a high resistance state may represent a logical "0" value, and a low resistance state may represent a logical "1" value. Other methods of reading RRAM cell data are also possible.

[0057] The present disclosure therefore includes an embodiment of a current reference circuit for a resistive random access memory (RRAM) cell. The current reference circuit includes a configurable resistor network, a replica access path, a replica selector circuit, and a step current generator circuit. The configurable resistor network is configured to simulate a resistive element of an RRAM cell. The replica access path is connected to a first terminal of the configurable resistor network and is configured to simulate an access path associated with an RRAM cell. The replica selector circuit is connected to a second terminal of the configurable resistor network and is configured to simulate a selector circuit associated with an RRAM cell. The step current generator circuit is connected to the configurable resistor network and is used to adjust a reference current level provided by the current reference circuit. In addition, the replica access path, the configurable resistor network, the replica selector circuit, and the step current generator circuit are configured to track process, voltage, and temperature (PVT) variations.

[0058] In some embodiments, the replica access path includes one or more transistor devices that match the resistance of the logic device, the metal line resistance, and the leakage associated with the RRAM cell. In some embodiments, the configurable resistor network is configured to match one of the following: a low resistance state (LRS), a high resistance state (HRS), and a normal resistance state. In some embodiments, the low resistance state (LRS) is used to represent a logic value of 0, and the high resistance state (HRS) is used to represent a logic value of 1. In some embodiments, the configurable resistor network includes: a first terminal of a first resistor device, which is connected to the replica access path; a second terminal of the first resistor device, which is connected to a first terminal of a second resistor device; a second terminal of the second resistor device, which is connected to a first terminal of a third resistor device; a second terminal of the third resistor device, which is connected to a first terminal of a step resistor device; a second terminal of the step resistor device, which is connected to the replica selector circuit. In some embodiments, it provides a high resistance (RH) that matches the high resistance state (HRS) verification level. In some embodiments, the first terminal of the third resistor device is switched to be directly connected to the replica access path to provide a low resistance (RL) matching the low resistance state (LRS) verification level; the first terminal of the second resistor device is switched to be directly connected to the replica access path to provide an intermediate resistance matching the normal resistance state; and the step resistor device is adjusted to provide additional adjustment to the resistance value provided by the configurable resistor network. In some embodiments, the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor device connected to the replica access path; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network connected to the replica access path; a second terminal of the third resistor device connected to a first terminal of a third switch device; second terminals of the first switch device, the second switch device, and the third switch device connected to a first terminal of a step resistor device; and a second terminal of the step resistor device connected to the replica selector circuit.In some embodiments, the second switch device and the third switch device are disabled to provide a high resistance (RH) matching the high resistance state (HRS) verification level; the first switch device and the third switch device are disabled to provide an intermediate resistance matching the normal resistance state; the first switch device and the second switch device are disabled to provide a low resistance (RL) matching the low resistance state (LRS) verification level; and the step resistor device is adjusted to provide additional adjustment to the resistance value provided by the configurable resistor network. In some embodiments, the replica selector circuit is a single NMOS transistor device that tracks the selector circuit associated with the RRAM cell. In some embodiments, the replica selector circuit is an array of transistor devices, wherein the array includes one of the following: four transistor devices or nine transistor devices. In some embodiments, the four transistor devices include two groups of two transistors, wherein the two transistors from each group of two transistors are connected in a parallel configuration, and the two groups of two transistors are connected in a series configuration. In some embodiments, the step current generator circuit includes: a current generator circuit; a current mirror circuit connected to the current generator circuit; and a first terminal of a switching device connected to the current mirror circuit, and a second terminal of the switching device connected to the configurable resistor network, wherein: after enabling the switching device, the current generated by the current generator circuit and mirrored by the current mirror circuit is used to adjust the reference current level provided by the current reference circuit.

[0059] According to another embodiment, a system for reading RRAM data is disclosed. The system includes a resistive random access memory (RRAM) device, wherein the RRAM device includes: an RRAM cell; a first terminal of an access path connected to the first terminal of the RRAM cell; and a selector circuit connected to a second terminal of the RRAM cell. The system further includes a current reference circuit, wherein the current reference circuit includes: a configurable resistor network, wherein the configurable resistor network is configured to simulate a resistive element of the RRAM cell; a replica access path, wherein the first terminal of the replica access path is connected to the first terminal of the configurable resistor network, and wherein the replica access path simulates an access path associated with the RRAM cell; and a replica selector circuit connected to the second terminal of the configurable resistor network, and wherein the replica selector circuit simulates a selector circuit associated with the RRAM cell. The system also includes a sense amplifier circuit, including two input terminals, wherein the second terminal of the access path is connected to one input terminal of the sense amplifier circuit, and the second terminal of the replica access path is connected to the other input terminal of the sense amplifier circuit.

[0060] In some embodiments, the system further comprises: a step current generator circuit connected to the configurable resistor network, wherein the step current generator is used to adjust the reference current level provided by the current reference circuit. In some embodiments, the replica access path, the configurable resistor network, the replica selector circuit, and the step current generator circuit are configured to track process, voltage, and temperature (PVT) changes. In some embodiments, the sense amplifier senses a change in current between the RRAM device and the reference current level provided by the current reference circuit to determine a data value stored in the RRAM cell. In some embodiments, the configurable resistor network is configured to match one of the following: a low resistance state (LRS), a high resistance state (HRS), and a normal resistance state. In some embodiments, the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor device connected to the replica access path; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network connected to the replica access path; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device, and the third switch device connected to a first terminal of a step resistor device; and a second terminal of the step resistor device connected to the replica selector circuit.

[0061] According to yet another embodiment, a method for reading data from an RRAM device using a self-tracking reference circuit is disclosed. The method includes selectively connecting one of a first RRAM device or a second RRAM device to a first input of a sense amplifier, wherein each of the first RRAM device and the second RRAM device includes an RRAM cell. The method also includes configuring a reference circuit to simulate the selected first RRAM device or the second RRAM device, and generating a reference current by the reference circuit that tracks process, voltage, and temperature (PVT) variations. The method further includes selectively connecting the reference circuit to a second input of the sense amplifier, and comparing a current value of the selected first RRAM device or the second RRAM device with the reference current by the sense amplifier to read data from the first RRAM cell or the second RRAM cell.

[0062] In some embodiments, configuring the reference circuit to emulate the selected first RRAM device or the selected second RRAM device includes: configuring a resistor network to match a resistive element of the RRAM cell; configuring a replica access path to match an access path associated with the RRAM cell; and configuring a replica selector circuit to match a selector circuit associated with the RRAM cell.

[0063] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A current reference circuit for a resistive random access memory (RRAM) cell, comprising: a configurable resistor network, wherein the configurable resistor network is configured to emulate a resistive element of the RRAM cell such that a resistance value of the configurable resistor network matches a resistance value of the RRAM cell; a replica access path, wherein the replica access path is connected to a first terminal of the configurable resistor network, and wherein the replica access path emulates an access path associated with the RRAM cell; a replica selector circuit connected to a second terminal of the configurable resistor network, and wherein the replica selector circuit emulates a selector circuit associated with the RRAM cell, wherein the replica selector circuit is an array of transistor devices, wherein the array includes nine transistor devices, wherein the nine transistor devices include three groups of three transistors, wherein the three transistors from each group of three transistors are connected in a parallel configuration, and wherein the three groups of three transistors are connected in a series configuration; a step current generator circuit connected to the configurable resistor network, wherein the step current generator is used to adjust a reference current level provided by the current reference circuit; as well as Wherein the replica access path, the configurable resistor network, the replica selector circuit, and the step current generator circuit are configured to track process, voltage, and temperature (PVT) variations.

2. The current reference circuit for a resistive random access memory (RRAM) cell of claim 1 , wherein the replica access path comprises one or more transistor devices that match logic device resistance, metal line resistance, and leakage of the access path associated with the RRAM cell.

3. The current reference circuit for a resistive random access memory (RRAM) cell of claim 1 , wherein the configurable resistor network is configured to match one of: a low resistance state (LRS), a high resistance state (HRS), and a normal resistance state.

4. The current reference circuit for a resistive random access memory (RRAM) cell of claim 3, wherein the low resistance state (LRS) is used to represent a logic value of 0, and the high resistance state (HRS) is used to represent a logic value of 1.

5. The current reference circuit for a resistive random access memory (RRAM) cell of claim 3, wherein the configurable resistor network comprises: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to the first terminal of the second resistor device; a second terminal of the second resistor device connected to a first terminal of a third resistor device; a second terminal of the third resistor device connected to the first terminal of the step resistor device; A second terminal of the step resistor device is connected to the replica selector circuit.

6. The current reference circuit for a resistive random access memory (RRAM) cell of claim 5, providing a high resistance (RH) matching the high resistance state (HRS) verify level.

7. The current reference circuit for a resistive random access memory (RRAM) cell according to claim 5, wherein: switching the first terminal of the third resistor device to connect directly to the replica access path to provide a low resistance (RL) matching the low resistance state (LRS) verify level; switching the first terminal of the second resistor device to connect directly to the replica access path, providing an intermediate resistance matching the normal resistance state; and The step resistor device is adjusted to provide additional adjustment to the resistance value provided by the configurable resistor network.

8. The current reference circuit for a resistive random access memory (RRAM) cell of claim 3, wherein the configurable resistor network comprises: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to the first terminal of the first switching device; a first terminal of a second resistor device connected to the replica access path; a second terminal of the second resistor device connected to the first terminal of the second switching device; a first terminal of a third resistor device connected to the replica access path; a second terminal of the third resistor device connected to the first terminal of the third switch device; second terminals of the first, second and third switching devices connected to a first terminal of a step resistor device; as well as A second terminal of the step resistor device is connected to the replica selector circuit.

9. The current reference circuit for a resistive random access memory (RRAM) cell according to claim 8, wherein: disabling the second switching device and the third switching device to provide a high resistance (RH) matching the high resistance state (HRS) verify level; disabling the first switching device and the third switching device to provide an intermediate resistance matching the normal resistance state; disabling the first switching device and the second switching device to provide a low resistance (RL) matching the low resistance state (LRS) verify level; as well as The step resistor device is adjusted to provide additional adjustment to the resistance value provided by the configurable resistor network.

10. The current reference circuit for a resistive random access memory (RRAM) cell of claim 1, wherein the replica selector circuit is an NMOS transistor device that tracks the selector circuit associated with the RRAM cell.

11. The current reference circuit for a resistive random access memory (RRAM) cell of claim 1 , the step current generator circuit comprising: a current generator circuit; a current mirror circuit connected to the current generator circuit; and A first terminal of a switching device is connected to the current mirror circuit, and a second terminal of the switching device is connected to the configurable resistor network, wherein: After enabling the switching device, the current generated by the current generator circuit and mirrored by the current mirror circuit is used to adjust the reference current level provided by the current reference circuit.

12. A system comprising: A resistive random access memory (RRAM) device, wherein the RRAM device comprises: RRAM cell; a first terminal of an access path connected to a first terminal of the RRAM cell; and a selector circuit connected to the second terminal of the RRAM cell; A current reference circuit, wherein the current reference circuit comprises: a configurable resistor network, wherein the configurable resistor network is configured to emulate a resistive element of the RRAM cell such that a resistance value of the configurable resistor network matches a resistance value of the RRAM cell; a replica access path, wherein a first terminal of the replica access path is connected to a first terminal of the configurable resistor network, and wherein the replica access path emulates the access path associated with the RRAM cell; as well as a replica selector circuit connected to a second terminal of the configurable resistor network, and wherein the replica selector circuit emulates the selector circuit associated with the RRAM cell, wherein the replica selector circuit is an array of transistor devices, wherein the array includes four transistor devices, wherein the four transistor devices include two groups of two transistors, wherein the two transistors from each group of two transistors are connected in a parallel configuration, and the two groups of two transistors are connected in a series configuration; and A sense amplifier circuit includes two input terminals, wherein a second terminal of the access path is connected to one input terminal of the sense amplifier circuit and a second terminal of the replica access path is connected to another input terminal of the sense amplifier circuit.

13. The system of claim 12, further comprising: A step current generator circuit is connected to the configurable resistor network, wherein the step current generator is used to adjust a reference current level provided by the current reference circuit.

14. The system of claim 13, wherein the replica access path, the configurable resistor network, the replica selector circuit, and the step current generator circuit are configured to track process, voltage, and temperature (PVT) variations.

15. The system of claim 13, wherein the sense amplifier senses a change in current between the RRAM device and the reference current level provided by the current reference circuit to determine a data value stored in the RRAM cell.

16. The system of claim 12, wherein the configurable resistor network is configured to match one of: a low resistance state (LRS), a high resistance state (HRS), and a normal resistance state.

17. The system of claim 12, wherein the configurable resistor network comprises: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to the first terminal of the first switching device; a first terminal of a second resistor device connected to the replica access path; a second terminal of the second resistor device connected to the first terminal of the second switching device; a first terminal of a third resistor device connected to the replica access path; a second terminal of the third resistor device connected to the first terminal of the third switch device; the second terminals of the first switching device, the second switching device, and the third switching device connected to a first terminal of a step resistor device; as well as A second terminal of the step resistor device is connected to the replica selector circuit.

18. A method comprising: selectively connecting one of a first RRAM device or a second RRAM device to a first input of a sense amplifier, wherein each of the first RRAM device and the second RRAM device comprises an RRAM cell; configuring a reference circuit to emulate the selected first RRAM device or the selected second RRAM device, comprising: configuring a replica selector circuit to match a selector circuit associated with the RRAM cell, wherein the replica selector circuit is an array of transistor devices, wherein the array comprises nine transistor devices, wherein the nine transistor devices comprise three groups of three transistors, wherein the three transistors from each group of three transistors are connected in a parallel configuration, and the three groups of three transistors are connected in a series configuration; generating a reference current by the reference circuit that tracks process, voltage, and temperature (PVT) variations; selectively connecting the reference circuit to a second input terminal of the sense amplifier; as well as comparing a current value of the selected first RRAM device or the selected second RRAM device with a reference current through the sense amplifier to read data from the first RRAM cell or the second RRAM cell among the RRAM cells, The reference circuit includes at least a configurable resistor network configured to emulate a resistive element of the RRAM cell such that a resistance value of the configurable resistor network matches a resistance value of the RRAM cell.

19. The method of claim 18, wherein configuring the reference circuit to simulate the selected first RRAM device or the selected second RRAM device further comprises: A replica access path is configured to match an access path associated with the RRAM cell.

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