Film-on-chip package, display module, and electronic device

Abstract

A chip-on-film (COF) package, a display module, and an electronic device are provided. The COF package includes: a film including a reinforcing region, a bending region, and a chip mounting region; a conductive pattern layer disposed on the film in the reinforcing region and in the bending region, and at least partially disposed on the film in the chip mounting region; a chip mounted on a portion of the conductive pattern layer located in the chip mounting region; a first insulating layer having a first elastic modulus and extending above the conductive pattern layer in the reinforcing region; and a second insulating layer having a second elastic modulus and extending above the conductive pattern layer in the bending region, wherein the first elastic modulus is greater than the second elastic modulus, and the film is intact in the chip mounting region.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2020 - 0020547, filed on Feb. 19, 2020, with the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. Technical field

[0003] The present inventive concept generally relates to a chip - on - film (COF) package. More specifically, the present inventive concept relates to a COF package in which at least a portion of the COF package is bendable. Background art

[0004] A display driver integrated circuit chip may be packaged in a tape - carrier - package (TCP) or a chip - on - film (COF) package. Both TCP and COF packages are structures in which a chip may be mounted on a film on which a conductive pattern is formed. Summary of the invention

[0005] Embodiments of the present inventive concept provide a COF package that enables an electronic device including the COF package to have a reduced bezel length. Embodiments of the present inventive concept provide a COF package in which the risk of separation between a display panel and the COF package is significantly reduced. Embodiments of the present inventive concept provide a COF package that uses a reduced film thickness, which is advantageous for safe handling and assembly of the COF package.

[0006] According to an aspect of the present inventive concept, there is provided a chip - on - film (COF) package including: a film including a reinforcing region, a bending region, and a chip mounting region; a conductive pattern layer disposed on the film in the reinforcing region and in the bending region, and at least partially disposed on the film in the chip mounting region; a chip mounted on a portion of the conductive pattern layer located in the chip mounting region; a first insulating layer having a first elastic modulus and extending over the conductive pattern layer in the reinforcing region; and a second insulating layer having a second elastic modulus and extending over the conductive pattern layer in the bending region, wherein the first elastic modulus is greater than the second elastic modulus, and the film is intact in the chip mounting region.

[0007] According to an aspect of the inventive concept, there is provided a chip-on-film (COF) package including: a film including a first pad region at one end of the film, a second pad region at the other end of the film, a chip mounting region between the first pad region and the second pad region, a first reinforcing region between the chip mounting region and the first pad region, a second reinforcing region between the chip mounting region and the second pad region, and a bending region between the second reinforcing region and the second pad region; a first conductive pad disposed on the first pad region; a second conductive pad disposed on the second pad region; a first conductive wire extending from the chip mounting region through the first reinforcing region and connected to the first conductive pad respectively; a second conductive wire extending from the chip mounting region through the second reinforcing region and the bending region and connected to the second conductive pad respectively; a chip mounted on a portion of the first conductive wire in the chip mounting region and / or a portion of the second conductive wire in the chip mounting region; conductive bumps disposed between the first conductive wire and the chip and between the second conductive wire and the chip; a sealing member covering at least a part of a top surface of the chip mounting region and at least partially surrounding the conductive bumps; a first insulating layer having a first elastic modulus, exposing the first conductive pad, and covering the first conductive wire in the first reinforcing region and covering the second conductive wire in the second reinforcing region; and a second insulating layer having a second elastic modulus, exposing the second conductive pad, and covering the second conductive wire in the bending region, wherein the first elastic modulus is greater than the second elastic modulus, and the sealing member does not contact a bottom surface of the film in the chip mounting region.

[0008] According to an aspect of the inventive concept, there is provided an electronic device including: a housing; and the display module according to the above, the display module being disposed in the housing, wherein the bending region is bent such that the second conductive pad is attached to a top surface of the display panel, and the chip is disposed between the film and a bottom surface of the display panel.

[0009] According to an aspect of the inventive concept, there is provided a chip-on-film (COF) package including: a film; a first conductive pattern layer disposed on a top surface of the film; a second conductive pattern layer disposed on a bottom surface of the film; vias penetrating the film and connecting the first conductive pattern layer and the second conductive pattern layer; a chip mounted on the first conductive pattern layer; a first insulating layer having a first elastic modulus and covering at least a portion of the first conductive pattern layer adjacent to the chip; a second insulating layer having a second elastic modulus and covering at least a portion of the first conductive pattern layer spaced apart from the chip; and a third insulating layer having a third elastic modulus and covering at least a portion of the bottom surface, wherein the first elastic modulus is greater than the second elastic modulus. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing a COF package according to an embodiment of the inventive concept;

[0012] Figure 2 is a further cross-sectional view of the COF package taken along line A-A'; Figure 1 of the COF package;

[0013] Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A and Figure 7B are cross-sectional views respectively showing a COF package according to an embodiment of the inventive concept;

[0014] Figure 8 and Figure 9 are plan views respectively showing a display module according to an embodiment of the inventive concept;

[0015] Figure 10 is a plan view showing an electronic device according to an embodiment of the inventive concept;

[0016] Figure 11 is a further cross-sectional view of the electronic device taken along line B-B'; Figure 10 of the electronic device; and

[0017] Figure 12A and Figure 12B are cross-sectional views respectively showing an electronic device according to an embodiment of the inventive concept. Detailed implementation manners

[0018] Throughout the written description and the drawings, the same reference numerals and labels are used to indicate the same or similar elements and / or features. Throughout the written description, specific geometric terms may be used to emphasize the relative relationships between elements, components, and / or features of a particular embodiment with respect to the inventive concept. Those skilled in the art will recognize that such geometric terms are inherently relative, arbitrary in terms of the described relationships, and / or refer to aspects of the illustrated embodiments. Geometric terms may include, for example: height / width; vertical / horizontal; top / bottom; higher / lower; nearer / farther; thicker / thinner; close to / far from; above / below; beneath / over; up / down; center / side; around; on top of / underneath; and so on.

[0019] As described above, the display driver integrated circuit chip can be packaged using tape carrier package (TCP) or chip on film (COF) packaging. Both TCP and COF packaging allow a semiconductor chip to be mounted on a film including a conductive pattern. However, TCP typically forms holes in the chip mounting area of the film. Accordingly, a portion of the conductive pattern (e.g., internal leads) extending above the holes may not be supported by the film. In contrast, COF packaging does not form holes in the chip mounting area of the film, such that the conductive pattern is entirely supported by the film. Thus, compared to TCP, COF packaging can be advantageously used to miniaturize the conductive pattern in the context of the inventive concept.

[0020] Figure 1 is a plan view (or top view) showing a chip on film (COF) package 100 according to an embodiment of the inventive concept. Figure 2 is along Figure 1 a cross-sectional view of the COF package 100 taken along line A-A' in

[0021] Referring to Figure 1 and Figure 2 , the COF package 100 may include: a film 110, a conductive pattern layer 120 located on the film 110, a chip 130 at least partially located on the conductive pattern layer 120, a first insulating layer 160 located on the conductive pattern layer 120, and a second insulating layer 170 located on the conductive pattern layer 120. In some embodiments, the COF package 100 may further include conductive bumps 140 located between the chip 130 and the conductive pattern layer 120. In some embodiments, the COF package 100 may further include a sealing member 150 at least partially surrounding the conductive bumps 140.

[0022] In Figure 1In the illustrated example, it is assumed that the conductive pattern layer 120 extends laterally over the entire length of the film 100 (including, for example, regions R1, R2, R3, R4, R5, and R6), but this is not necessarily always the case.

[0023] The film 110 can be understood to include: a first pad region R1 located at one end of the film 110, a second pad region R6 located at the other end of the film 110 opposite to the one end, a chip mounting region R3 located between the first pad region R1 and the second pad region R6, a first reinforcement region R2 located between the chip mounting region R3 and the first pad region R1, a second reinforcement region R4 located between the chip mounting region R3 and the second pad region R6, and a bending region R5 located between the second reinforcement region R4 and the second pad region R6. Here, the first reinforcement region R2 and the second reinforcement region R4 can be adjacent to the chip mounting region R3, the first pad region R1 can be adjacent to the first reinforcement region R2, the bending region R5 can be adjacent to the second reinforcement region R4, and the second pad region R6 can be adjacent to the bending region R5. In Figure 1 the illustrated example, the first reinforcement region R2 and the second reinforcement region R4 are spaced apart from each other. However, in other embodiments, the first reinforcement region R2 and the second reinforcement region R4 can be adjacent to each other in a configuration that at least partially surrounds the chip mounting region R3.

[0024] As will be described additionally with respect to the Figure 11 illustrated embodiment, the thickness t1 of the film 110 can be less than about 35 μm, which is the typical thickness of a comparative film used in a conventional COF package. Here, it should be noted that a thickness of about 35 μm or less prevents the COF package 100 from separating from the display panel due to the elasticity of the film 110. In this regard, a polyimide film with a thickness of 25 μm can be used, which is the thinnest film 110 for currently available COF packages.

[0025] The thickness t1 of the film 110 can be in the range of about 10 μm to about 30 μm. However, when the thickness t1 of the film 110 is less than about 10 μm, the assembly and handling of the COF package 100 may be difficult. However, when the thickness t1 of the film 110 is greater than about 30 μm, the COF package 100 may separate from the display panel due to the elasticity of the film 110. In this regard, the term "thickness" used in the description of a layer or film refers to the average thickness. Thus, the thickness of a layer or film can refer to the result value obtained by dividing the volume of the layer or film by the horizontal (or lateral) area of the layer or film.

[0026] The film 110 may include one or more materials that generally have insulating and flexible properties. The film 110 may include, for example, polyimide, polyester, or a combination thereof. The film 110 may have a top surface on which a conductive pattern layer 120 is formed and a bottom surface opposite to the top surface.

[0027] The conductive pattern layer 120 may be positioned (or disposed) on the top surface of the film 110. In some embodiments, the conductive pattern layer 120 may include: one or more first conductive pads P1 (hereinafter referred to as "the first conductive pads P1"), one or more first conductive lines L1 (hereinafter referred to as "the first conductive lines L1"), one or more second conductive lines L2 (hereinafter referred to as "the second conductive lines L2"), and one or more second conductive pads P2 (hereinafter referred to as "the second conductive pads P2"), wherein the first conductive pads P1 are disposed on the first pad region R1, and the second conductive pads P2 are disposed on the second pad region R6.

[0028] The first conductive lines L1 may extend from the chip mounting region R3 through the first reinforcement region R2 to be respectively connected to the first conductive pads P1, and the second conductive lines L2 may extend from the chip mounting region R3 through the second reinforcement region R4 and the bending region R5 to be respectively connected to the second conductive pads P2. At least a part of the conductive pattern layer 120 (e.g., the first conductive pads P1, the first conductive lines L1, the second conductive lines L2, and / or the second conductive pads P2) may include at least one conductive material, and the at least one conductive material includes, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), and / or tungsten (W). In some embodiments, the thickness of the conductive pattern layer 120 may be in the range of from about 5 μm to about 15 μm (e.g., about 8 μm). In this regard, when the thickness of the conductive pattern layer 120 is less than about 5 μm, the resistance of the conductive pattern layer 120 will increase, and fine patterning of the conductive pattern layer 120 may be difficult. However, when the thickness of the conductive pattern layer 120 is greater than about 15 μm, the flexibility of the COF package will be disadvantageously reduced, and / or the total thickness of the COF package will increase.

[0029] The chip 130 may be mounted on a portion of the conductive pattern layer 120 located in the chip mounting region R3. For example, the chip 130 may be mounted on a portion of the first conductive lines L1 located in the chip mounting region R3 and / or a portion of the second conductive lines L2 located in the chip mounting region R3.

[0030] In some embodiments, the chip 130 may be a display driver integrated circuit (DDI) chip. In this case, the chip 130 may be used to control the operation of pixels in a display panel. That is, the chip 130 may include a gate driver integrated circuit for driving gate lines and / or a data driver integrated circuit for driving data lines. In some embodiments, in addition to the display driver integrated circuit, the chip 130 may further include a timing controller, a graphics random access memory (RAM) (GRAM), and / or a power driver.

[0031] In some embodiments, one or more conductive bumps 140 may be disposed between the chip 130 and the conductive pattern layer 120. For example, the conductive bumps 140 may be respectively disposed between the first conductive line L1 and the chip 130 and between the second conductive line L2 and the chip 130. The conductive bumps 140 may include one or more conductive materials, which include, for example, tin (Sn), lead (Pb), copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), and / or tungsten (W). With this exemplary configuration, the chip 130 may be connected to the first conductive pad P1 through the conductive bump 140 and the first conductive line L1, and may be connected to the second conductive pad P2 through the conductive bump 140 and the second conductive line L2.

[0032] In some embodiments, the sealing member 150 may be used to surround (or cover) the conductive bumps 140. That is, the sealing member 150 may be used to cover at least a part of the top surface of the chip mounting area R3 including the conductive bumps 140, a part of the first conductive line L1, and / or a part of the second conductive line L2. In some embodiments, the sealing member 150 may further cover at least a part of the first insulating layer 160.

[0033] The sealing member 150 may include one or more materials, which include, for example, epoxy resin, silicone resin, polymethyl methacrylate (PMMA), polyethylene, and / or polystyrene. Different from certain tape carrier packages (TCPs), Figure 1In the chip mounting region R3 of the film 110 in the COF package 100, there will be no holes that vertically penetrate the film 110 (i.e., structures that penetrate the film 110 in the direction defining the thickness of the film). Thus, in the chip mounting region R3, the sealing member 150 will not penetrate the film 110 or contact the bottom surface of the film 110. Accordingly, in some embodiments of the inventive concept, the portion of the film 110 that is substantially for mounting the chip 130 (i.e., the chip mounting region R3) can be said to be "intact" (i.e., remains undamaged or unpenetrated by vertical (or partially vertical) features or elements). In this regard, the term "vertical" assumes that the main surface, top surface, and bottom surface of the film 110 extend in a "horizontal" direction. However, those skilled in the art will recognize that these geometric descriptions are relative in nature.

[0034] The first insulating layer 160 may cover portions of the conductive pattern layer 120 that are located in the first reinforcing region R2 and the second reinforcing region R4. For example, the first insulating layer 160 may cover the first reinforcing region R2, the portion of the first conductive line L1 that traverses the first reinforcing region R2, the second reinforcing region R4, and the portion of the second conductive line L2 that traverses the second reinforcing region R4. However, the first insulating layer 160 may expose the first conductive pad P1.

[0035] The second insulating layer 170 may cover the bending region R5 and the portion of the conductive pattern layer 120 that traverses the bending region R5. For example, the second insulating layer 170 may cover the bending region R5 and the portion of the second conductive line L2 that traverses the bending region R5. However, the second insulating layer 170 may expose the second conductive pad P2.

[0036] With this exemplary configuration, the portion of the first conductive line L1 that traverses the first reinforcing region R2 may be covered by the first insulating layer 160, and the portions of the second conductive line L2 that traverse the second reinforcing region R4 and the bending region R5 may be covered by the second insulating layer 170.

[0037] Here, in some embodiments of the inventive concept, the first elastic modulus of the first insulating layer 160 may be greater than the second elastic modulus of the second insulating layer 170. For example, the first elastic modulus of the first insulating layer 160 may be in the range of about 5 GPa to about 20 GPa, and the second elastic modulus of the second insulating layer 170 may be in the range of about 0.5 GPa to about 2 GPa.

[0038] In this regard, the first insulating layer 160 (having a relatively high elastic modulus) may help prevent damage to the film 110 during the assembly and handling of the COF package 100 and facilitate the handling of the film 110. As referred to Figure 11As described in more detail below, the second insulating layer 170 (having a relatively low elastic modulus) can facilitate the bending of the bending region R5 of the film 110, and thus, even when the attachment length between the COF package and the display panel is reduced, separation of the COF package from the display panel can be prevented.

[0039] In addition, in this regard, when the first elastic modulus of the first insulating layer 160 is less than about 5 GPa, the film 110 may be damaged during the assembly and handling of the COF package 100, but when the first elastic modulus of the first insulating layer 160 is greater than about 20 GPa, the bendability of the bending region R5 may be insufficient. When the second elastic modulus of the second insulating layer 170 is less than about 0.5 GPa, the film 110 may be damaged during the assembly and handling of the COF package 100, but when the second elastic modulus of the second insulating layer 170 is greater than about 2 GPa, the bendability of the bending region R5 may be insufficient to prevent separation (or partial separation) of the display panel.

[0040] Furthermore, in this regard, the first material used to form the first insulating layer 160 may be different from the second material used to form the second insulating layer 170. In certain embodiments of the inventive concept, the first insulating layer 160 may include, for example, polyimide, and the second insulating layer 170 may include, for example, polyurethane. Here, polyimide may have a higher elastic modulus than polyurethane and may also exhibit relatively high resistance to chemicals (e.g., glass cleaner), thereby improving the reliability of the resulting COF package.

[0041] Referring again to Figure 2 , the thickness t6 of the first insulating layer 160 and the thickness t7 of the second insulating layer 170 may be in the range of about 5 μm to about 35 μm. However, when the thickness t6 of the first insulating layer 160 and / or the thickness t7 of the second insulating layer 170 is less than about 5 μm, the first insulating layer 160 and the second insulating layer 170 may not provide sufficient insulating properties. Also, when the thickness t6 of the first insulating layer 160 and the thickness t7 of the second insulating layer 170 are greater than about 35 μm, the total thickness of the COF package 100 may increase too much, and the flexibility of the resulting COF package 100 may be reduced to the extent of display panel separation.

[0042] In certain embodiments of the inventive concept, the thickness t6 of the first insulating layer 160 may be the same as the thickness t7 of the second insulating layer 170 (e.g., in the range of about 10 μm to about 20 μm). In some embodiments, the length d7 of the second insulating layer 170 may be in the range from about 1.5 mm to about 3.0 mm. However, when the length d7 of the second insulating layer 170 is greater than about 3.0 mm, the resulting size of the border for incorporating into an electronic device may become too large, and when the length d7 of the second insulating layer 170 is less than about 1.5 mm, the bending region R5 of the film 110 may become so short that the display panel is separated from the COF package 100.

[0043] Figure 3 is a cross-sectional view showing a COF package 100a according to an embodiment of the inventive concept. Hereinafter, Figure 2 the COF package 100 and Figure 3 the difference between the COF package 100a will be described.

[0044] Referring to Figure 3 , the thickness t6a of the first insulating layer 160a may be greater than the thickness t7a of the second insulating layer 170a. In some embodiments, the thickness t6a of the first insulating layer 160a may be in the range of about 15 μm to about 25 μm, and the thickness t7a of the second insulating layer 170a may be in the range of about 5 μm to about 15 μm. Since the insulating layer is generally formed on the film 110 in the COF package to have a thickness in the range of about 10 μm to about 20 μm, the thickness t7a of the second insulating layer 170a may be (e.g.) about 10 μm, while the thickness t6a of the first insulating layer 160a may be (e.g.) about 20 μm. When the first insulating layer 160a is thicker than the second insulating layer 170a, the first insulating layer 160a having a relatively thick thickness may prevent the film 110 from being damaged during the assembly and handling of the COF package 100a, thus facilitating the handling of the film 110. However, as will be described in further detail with reference to Figure 11 , the second insulating layer 170a having a relatively thin thickness may facilitate the bending of the bending region R5 of the film 110, thereby preventing the COF package 100a from being separated from the display panel even when the attachment length between the COF package 100a and the display panel is reduced.

[0045] In this regard, when the thickness t6a of the first insulating layer 160a is less than about 15 μm, it may be difficult to prevent damage to the film 110 during the assembly and handling of the COF package 100a. However, when the thickness t6a of the first insulating layer 160a is greater than about 25 μm, the overall thickness of the COF package 100a increases too much. In addition, in this regard, when the thickness t7a of the second insulating layer 170a is greater than about 15 μm, it may be difficult to facilitate the bending of the bending region R5 of the film 110, and the COF package 100a may become separated from the display panel. However, when the thickness t7a of the second insulating layer 170a is less than about 5 μm, it may be difficult to appropriately form the second insulating layer 170a with a uniform thickness.

[0046] Figure 4 is a cross-sectional view showing a COF package 100b according to an embodiment of the inventive concept. Hereinafter, Figure 2 the COF package 100 and Figure 4 the difference between the COF package 100b will be described.

[0047] Referring to Figure 4 , the second insulating layer 170b may also extend across portions of the conductive pattern layer 120 located in the first reinforcing region R2 and / or the second reinforcing region R4 of the film 110. In some embodiments, the second insulating layer 170b may also extend under the entire length of the first insulating layer 160b. That is, the first insulating layer 160b may be disposed on the top surface of the second insulating layer 170b in the first reinforcing region R2 and / or the second reinforcing region R4, thereby reducing the flexibility of the film 110 in the first reinforcing region R2 and / or the second reinforcing region R4 to facilitate the assembly and handling of the COF package 100b, while maintaining sufficient bendability in the bending region R5 to prevent the COF package 100b from separating from the display panel.

[0048] Figure 5 is a cross-sectional view showing a COF package 100c according to an embodiment of the inventive concept. Hereinafter, Figure 2 the COF package 100 and Figure 5 the difference between the COF package 100c will be described.

[0049] Referring to Figure 5, the second insulating layer 170c may also extend across the conductive pattern layer 120 in the first reinforcing region R2 and / or the second reinforcing region R4 of the film 110. In some embodiments, the second insulating layer 170c may also extend above the top surface of the first insulating layer 160c. That is, the first insulating layer 160c may extend between the conductive pattern layer 120 and the bottom surface of the second insulating layer 170c. Accordingly, the first reinforcing region R2 and / or the second reinforcing region R4 of the film 110 may exhibit reduced flexibility to facilitate the assembly and handling of the COF package 100c, while maintaining the bendability of the bending region R5 of the film 110 to prevent separation of the display panel.

[0050] Figure 6A is a cross-sectional view showing a COF package 200 according to an embodiment of the inventive concept. Hereinafter, the Figure 2 COF package 100 of Figure 6A and the

[0051] difference between the Figure 6A COF package 200 will be described. Referring to

[0052] , the COF package 200 may include: a film 110, a first conductive pattern layer 120a disposed on the top surface of the film 110, and a second conductive pattern layer 120b disposed on the bottom surface of the film 110 and connected to the first conductive pattern layer 120a through vias 190a to 190c penetrating the film 110. The COF package 200 further includes: a chip 130 disposed on the first conductive pattern layer 120a, a first insulating layer 160 covering a portion of the first conductive pattern layer 120a adjacent to the chip 130, a second insulating layer 170 covering a portion of the first conductive pattern layer 120a spaced apart from the chip 130, and a third insulating layer 180 covering the bottom surface of the film 110 and the bottom surface of the second conductive pattern layer 120b.

[0052] The vias 190a to 190c connecting the first conductive pattern layer 120a and the second conductive pattern layer 120b may include one or more conductive materials, which include, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), and / or tungsten (W).

[0053] In some embodiments, the first insulating layer 160 may cover portions of the first conductive pattern layer 120a that are on the top surfaces of the first enhancement region R2 and the second enhancement region R4. However, the first insulating layer 160 may expose the first conductive pad P1. In some embodiments, the second insulating layer 170 may cover portions of the first conductive pattern layer 120a that are on the top surfaces of the bending region R5 and the second pad region R6. The third insulating layer 180 may cover portions of the second conductive pattern layer 120b that are on the bottom surfaces of the first pad region R1, the first enhancement region R2, the chip mounting region R3, the second enhancement region R4, and the bending region R5. The third insulating layer 180 may also cover the bottom surface of the film 110. However, the third insulating layer 180 may expose the second conductive pad P2.

[0054] In some embodiments of the inventive concept, a third elastic modulus of the third insulating layer 180 may be less than a first elastic modulus of the first insulating layer 160, thereby facilitating bendability of the bending region R5. For example, the third insulating layer 180 may include the same material as the second insulating layer 170 (e.g., polyurethane). In some embodiments, a thickness t8 of the third insulating layer 180 may be in a range of about 5 μm to about 15 μm. However, when the thickness t8 of the third insulating layer 180 is less than about 5 μm, the third insulating layer 180 may not be properly formed with a uniform thickness, and when the thickness t8 of the third insulating layer 180 is greater than about 15 μm, bendability of the bending region R5 may be insufficient. In some embodiments, the thickness t8 of the third insulating layer 180 may be the same as a thickness t7 of the second insulating layer 170. For example, the thickness t8 of the third insulating layer 180 and the thickness t7 of the second insulating layer 170 may both be (e.g.) about 10 μm. The thickness t8 of the third insulating layer 180 may be equal to or less than a thickness t6 of the first insulating layer 160.

[0055] Figure 6B is a cross-sectional view showing a COF package 200a according to an embodiment of the inventive concept. Hereinafter, Figure 6A of the COF package 200 and Figure 6B the difference between the COF package 200a will be described.

[0056] Referring to Figure 6B, the first conductive pattern layer 120a may include, for example: a first conductive pad P1 disposed on the top surface of the first pad region R1, and a first conductive line L1 and a second conductive line L2 extending on the top surface of the chip mounting region R3 of the film 110. The first conductive line L1 and the second conductive line L2 may be connected to the chip 130 through respective conductive bumps 140. Here, the second conductive pattern layer 120b may include, for example, a second conductive pad P2 disposed on the bottom surface of the second pad region R6 of the film 110. In some embodiments, the second conductive pattern layer 120b may further include a fourth conductive line L4 connecting the second conductive pad P2 of the second conductive pattern layer 120b to the second conductive line L2 of the first conductive pattern layer 120a. In some embodiments, the second conductive pattern layer 120b may further include a third conductive line L3 connecting the first conductive pad P1 of the first conductive pattern layer 120a.

[0057] The first conductive line L1 may be electrically connected to the first conductive pad P1. In some embodiments, the first conductive line L1 may be electrically connected to the third conductive line L3 of the second conductive pattern layer 120b using a first via 190a, and electrically connected to the first conductive pad P1 using a second via 190b. In another embodiment, without passing through the second conductive pattern layer 120b and vias 190a and 190b, the first conductive line L1 may be directly connected to the first conductive pad P1 and may further extend on the top surface of the first enhanced region R2.

[0058] The second conductive line L2 may be electrically connected to the second conductive pad P2. In some embodiments, the second conductive line L2 may be connected to the second conductive pad P2 of the second conductive pattern layer 120b through a third via 190c and the fourth conductive line L4 of the second conductive pattern layer 120b. Alternatively, in some embodiments where the second conductive line L2 further extends on the second enhanced region R4, the bending region R5, and the second pad region R6 of the film 110 and the third via 190c penetrates in the second pad region R6 of the film 110, the second conductive line L2 may be connected to the second conductive pad P2 only through the third via 190c without passing through the fourth conductive line L4.

[0059] The first conductive pattern layer 120a and the second conductive pattern layer 120b can be connected to each other using vias 190a to 190c. For example, the first via 190a can be connected between the first conductive line L1 of the first conductive pattern layer 120a and the third conductive line L3 of the second conductive pattern layer 120b. Additionally, the second via 190b can be connected between the third conductive line L3 of the second conductive pattern layer 120b and the first conductive pad P1 of the first conductive pattern layer 120a. Additionally, the third via 190c can be connected between the second conductive line L2 of the first conductive pattern layer 120a and the fourth conductive line L4 of the second conductive pattern layer 120b.

[0060] Although Figure 6B it is shown that the first via 190a is disposed within the chip mounting region R3, in some embodiments, the first via 190a can be disposed within the first reinforcing region R2 of the film 110. In these embodiments, the first conductive line L1 can further extend into the first reinforcing region R2. Additionally, although FIG. 6 shows that the second via 190b is disposed within the first pad region R1 of the film 110, in some embodiments, the second via 190b can be disposed within the first reinforcing region R2. In these embodiments, the first conductive pattern layer 120a can further include a fifth conductive line that can be located on the top surface of the first reinforcing region R2 of the film 110 and can connect the first conductive pad P1 to the second via 190b.

[0061] Additionally, Figure 6B it is shown that the third via 190c is disposed within the chip mounting region R3 and the second conductive line L2 only extends to the top surface of the chip mounting region R3. Alternatively, in other embodiments, the third via 190c can be disposed within the second reinforcing region R4. In such embodiments, the second conductive line L2 can further extend to the top surface of the second reinforcing region R4. Alternatively, the third via 190c can be disposed within the bending region R5. In such embodiments, the second conductive line L2 can further extend to the top surface of the bending region R5. Alternatively, the third via 190c can be disposed within the second pad region R6. In such embodiments, the second conductive line L2 can further extend to the top surface of the second pad region R6 and the second conductive line L2 can be connected to the second conductive pad P2 through the third via 190c without passing through the fourth conductive line L4.

[0062] In some embodiments, the first insulating layer 160 may cover the top surfaces of the first reinforcing region R2 and the second reinforcing region R4 of the film 110. In some embodiments, the first insulating layer 160 may also cover the first conductive pattern layer 120a. However, the first insulating layer 160 may expose the first conductive pad P1. In some embodiments, the second insulating layer 170 may cover the top surfaces of the bending region R5 and the second pad region R6 of the film 110. In some embodiments, the second insulating layer 170 may also cover the first conductive pattern layer 120a. The third insulating layer 180 may cover the bottom surfaces of the first pad region R1, the first reinforcing region R2, the chip mounting region R3, and the second reinforcing region R4 of the film 110 and the bottom surface of the second conductive pattern layer 120b. However, the third insulating layer 180 may expose the second conductive pad P2.

[0063] Figure 7A is a cross-sectional view of a COF package 200b according to an embodiment of the inventive concept. Hereinafter, Figure 6A the COF package 200 of Figure 7A and the difference between

[0064] Referring to Figure 7A , the first insulating layer 160 and the second insulating layer 170 may cover the bottom surfaces of the film 110 and the second conductive pattern layer 120b, while the third insulating layer 180 may cover the first conductive pattern layer 120a. However, the second insulating layer 170 may expose the second conductive pad P2, and the third insulating layer 180 may expose the first conductive pad P1.

[0065] Certain embodiments of the inventive concept may be incorporated into some aspects of the COF package 200 and the COF package 200b. That is, the first insulating layer 160 may cover not only the portions of the first conductive pattern layer 120a located on the top surfaces of the first reinforcing region R2 and the second reinforcing region R4, but also the bottom surface of the chip mounting region R3 and the portions of the second conductive pattern layer 120b located on the bottom surfaces of the first pad region R1, the first reinforcing region R2, the chip mounting region R3, and the second reinforcing region R4. The second insulating layer 170 may cover not only the portions of the first conductive pattern layer 120a located on the top surfaces of the bending region R5 and the second pad region R6, but also the portion of the second conductive pattern layer 120b located on the bottom surface of the bending region R5. However, the first insulating layer 160 may still expose the first conductive pad P1, and the second insulating layer 170 may expose the second conductive pad P2.

[0066] Figure 7B is a cross-sectional view of a COF package 200c according to an embodiment of the inventive concept. Hereinafter, Figure 6Bbetween the COF package 200a and Figure 7B the COF package 200c.

[0067] Referring to Figure 7B , the first insulating layer 160 and the second insulating layer 170 may cover the second conductive pattern layer 120b, and the third insulating layer 180 may cover the first conductive pattern layer 120a. For example, the first insulating layer 160 may cover portions of the second conductive pattern layer 120b on the bottom surfaces of the first pad region R1, the first reinforcing region R2, the chip mounting region R3, and the second reinforcing region R4. In some embodiments, the second insulating layer 170 may cover a portion of the second conductive pattern layer 120b on the bottom surface of the bending region R5. However, the second insulating layer 170 may expose the second conductive pad P2. In some embodiments, the third insulating layer 180 may cover the top surfaces of the first reinforcing region R2, the second reinforcing region R4, the bending region R5, and the second pad region R6. In some embodiments, the third insulating layer 180 may also cover the first conductive pattern layer 120a. However, the third insulating layer 180 may expose the first conductive pad P1.

[0068] In some aspects of the inventive concept, some aspects of the COF package 200a and the COF package 200c may be combined. That is, the first insulating layer 160 may cover portions of the second conductive pattern layer 120b not only on the top surfaces of the first reinforcing region R2 and the second reinforcing region R4 but also on the bottom surfaces of the first pad region R1, the first reinforcing region R2, the chip mounting region R3, and the second reinforcing region R4 of the film 110. The second insulating layer 170 may cover portions of the second conductive pattern layer 120b on the bottom surface of the bending region R5 of the film 110 and on the bending region R5 and the second pad region R6. However, the first insulating layer 160 may still expose the first conductive pad P1, and the second insulating layer 170 may expose the second conductive pad P2.

[0069] Figure 8 is a top view showing a display module 1000 according to an embodiment of the inventive concept.

[0070] Referring to Figure 8 , the display module 1000 may include a COF package 1100, a display panel 1202 connected to one end of the COF package 1100, and a circuit board 1300 connected to the other end of the COF package 1100. In some embodiments, the display module 1000 may further include a protective layer 1201 on the top surface of the display panel 1202. In some embodiments, the display module 1000 may further include a touch panel between the display panel 1202 and the protective layer 1201.

[0071] The COF package 1100 may include one of the COF packages 100, 100a, 100b, 100c, 200, 200a, 200b, and 200c according to the embodiments described with reference to Figures 1 to 7B . The second conductive pad P2 of the COF package 1100 (see Figures 1 to 7B ) may be attached to and connected to the top surface of the display panel 1202. The first conductive pad P1 of the COF package 1100 (see Figures 1 to 7B ) may be attached to and connected to the circuit board 1300.

[0072] The display panel 1202 may include any type of display panel, including a liquid crystal display panel and an organic light emitting diode panel. In some embodiments where the display panel 1202 is a liquid crystal display panel, the display panel 1202 may include a thin film transistor substrate and a color filter substrate facing each other, and liquid crystal may be injected between the thin film transistor substrate and the color filter substrate. The display panel 1202 may display an image by adjusting the light transmittance of the liquid crystal using thin film transistors as switching elements. In some embodiments, a backlight assembly may be further provided to supply light to the display panel 1202. In some embodiments where the display panel 1202 is an organic light emitting diode panel, the display panel 1202 may include a passive matrix type or an active matrix type organic light emitting diode panel.

[0073] The circuit board 1300 may include a printed circuit board (PCB). The circuit board 1300 may include a rigid PCB or a flexible printed circuit board (FPCB). The circuit board 1300 may receive various signals from an external circuit and output various control signals. The COF package 1100 may output a driving signal for driving the display panel 1202 in response to a control signal input from the circuit board 1300. The display panel 1202 may display an image in response to the driving signal input from the COF package 1100.

[0074] The protective layer 1201 may protect the display panel 1202 from physical and / or chemical environments. A touch panel may be located between the display panel 1202 and the protective layer 1201. The touch panel may include one or more touch sensing devices, where the touch sensing device may include a touch driving electrode and a conductive matrix. A touch driving unit may be provided at one end of the touch panel. The touch driving unit may include a touch panel chip for controlling the touch panel and a touch panel connection unit for connecting the touch panel chip to the touch panel.

[0075] Figure 9 is a top view of a display module 1000a according to an embodiment of the inventive concept. Hereinafter, the difference between the display module 1000 of Figure 8 and the display module 1000a of Figure 9 will be described.

[0076] Referring to Figure 9 , when the display panel 1202 is relatively large, multiple COF packages 1100 can be attached to and connected to the display panel 1202. In some embodiments, some of the COF packages 1100 can be connected to the first circuit board 1300a, while other COF packages 1100 can be connected to the second circuit board 1300b. In Figure 9 , six (6) COF packages 1100 are connected to the first circuit board 1300a, and three (3) COF packages 110 are connected to the second circuit board 1300b, but the number of circuit boards and / or the COF packages 1100 connected respectively can be changed by design.

[0077] Figure 10 FIG. is a top view of an electronic device 10000 according to an embodiment of the inventive concept, Figure 11 and FIG. is a cross-sectional view of the electronic device 10000 taken along line B-B' in Figure 10 .

[0078] Referring to Figure 10 and Figure 11 , the electronic device 10000 can be changed in design and function. For example, the electronic device 10000 can be a portable electronic device such as a smart phone or a tablet computer, a wearable electronic device such as smart glasses or a smart watch, or a household appliance such as a refrigerator, a television, a monitor, a laptop computer, and a vacuum cleaner. The electronic device 10000 generally may include a housing 12000 and a display module 11000 associated with the housing 12000.

[0079] The housing 12000 can accommodate the display module 11000 and other electronic components, such as circuit boards, batteries, memories, processors, infrared sensors, fingerprint sensors, gyro sensors, cameras, and speakers. In Figure 10 and 11 , the housing 12000 is shown as being integrally formed, but the housing 12000 can be formed by assembling multiple components. For example, the housing 12000 can be formed by a rear portion, a front portion, and side wall portions between the rear and front portions, or can be formed by a front portion and the remaining portion having a bottom and side walls. The housing 12000 can have a window through which the display module 11000 is exposed. The front surface of the housing 12000 can include a window area ED exposing the display module 11000 and a border area BZ surrounding the window area ED.

[0080] The display module 11000 can include (for example) referring to Figure 8 and Figure 9One or more display modules 1000 and 1000a described. The COF package 1100 may include one of the COF packages 100, 100a, 100b, and 100c according to the embodiments shown in Figures 1 to 5 In the display modules 1000 and 1000a, a first conductive pad P1 may be attached to the circuit board 1300, and a second conductive pad P2 may be attached to the top surface of the display panel 1202. The display module 11000 may include a first adhesion portion AH1 that attaches the first conductive pad P1 to the circuit board 1300 and a second adhesion portion AH2 that attaches the second conductive pad P2 to the top surface of the display panel 1202. In some embodiments, the second adhesion portion AH2 may also contact the second conductive pad P2 and a portion of the second insulating layer 170. In some embodiments, the first adhesion portion AH1 and the second adhesion portion AH2 may include anisotropic conductive films. The anisotropic conductive film may include conductive particles that serve as electrical channels and an insulating material that fixes the conductive particles.

[0081] The second pad region R6 and the bending region R5 of the film 110 may be disposed in the border region BZ of the housing 12000. The first pad region R1, the first reinforcement region R2, the chip mounting region R3, and the second reinforcement region R4 of the film 110 may be disposed within the window region ED. The bending region R5 of the film 110 may be bent such that the second conductive pad P2 can be attached to the top surface of the display panel 1202, and the chip 130 is disposed between the chip mounting region R3 of the film 110 and the bottom surface of the display panel 1202. The bending radius r1 of the bending region R5 of the film 110 may be in the range of about 200 μm to about 800 μm (e.g., about 400 μm). When the bending radius r1 of the bending region R5 is greater than about 800 μm, the length of the border region BZ may be too long, and when the bending radius r1 of the bending region R5 of the film 110 is less than about 200 μm, the COF package 1100 may be separated from the display panel 1202.

[0082] To reduce the length of the border region BZ of the housing 12000, the attachment length d2 between the display panel 1202 and the COF package 1100 may be reduced. In some embodiments, the attachment length d2 may be in the range of about 200 μm to about 600 μm. When the attachment length d2 is greater than 600 μm, the length of the border region BZ becomes too long, and when the attachment length d2 is 200 μm or less, the COF package 1100 may be separated from the display panel 1202 due to weak adhesion and excessive elasticity. For example, the attachment length d2 between the display panel 1202 and the COF package 1100 may be about 400 μm, which is less than half of a comparative conventional example having a length of (e.g.) about 850 μm.

[0083] According to the inventive concept, a first elastic modulus of the first insulating layer 160 may be greater than a second elastic modulus of the second insulating layer 170. Accordingly, even if the thickness of the film 110 is relatively very thin, the risk of damage to the film 110 during the assembly and handling of the COF package 1100 is significantly reduced. Additionally, even if the attachment length d2 between the COF package 1100 and the display panel 1202 is reduced because the second insulating layer 170 has a relatively low elastic modulus and the film 110 has a reduced thickness, the COF package 1100 does not separate from the display panel 1202. Accordingly, an electronic device 10000 having a bezel region BZ with a reduced length can be provided. Additionally, compared with materials (e.g., polyurethane) previously used as an insulating layer in the COF package 1100, the first insulating layer 160 may exhibit higher resistance to a cleaning solution (e.g., glass cleaner). Accordingly, the reliability of the COF package 1100, the display module 11000, and the electronic device 10000 including the same can be improved.

[0084] Figure 12A is a cross-sectional view of an electronic device 10000a according to an embodiment of the inventive concept, Figure 12B is a cross-sectional view of an electronic device 10000b according to an embodiment of the inventive concept. Hereinafter, Figure 11 the electronic device 10000, Figure 12A the electronic device 10000a, and Figure 12B the electronic device 10000b

[0085] will be described with reference to Figure 12A and Figure 12B . The COF package 1100a (and / or Figure 12B the COF package 1100b) may include at least one COF package according to an embodiment of the inventive concept (e.g., Figure 6A the COF package 200 and / or Figure 7A the COF package 200b).

[0086] In some embodiments, the display panel 1202 may be attached to a second conductive pad P2 of the second conductive pattern layer 120b, and the circuit board 1300 may be attached to a first conductive pad P1 of the first conductive pattern layer 120a. A bending region R5 of the film 110 may be bent such that the second conductive pattern layer 120b is attached to a top surface of the display panel 1202, the first conductive pattern layer 120a is attached to the circuit board 1300, and a chip mounting region R3 of the film 110 is disposed between the chip 130 and the display panel 1202.

[0087] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A chip - on - film package, the chip - on - film package comprising: A film, the film comprising a reinforcing region, a bending region, and a chip mounting region; A conductive pattern layer, the conductive pattern layer being disposed on the film in the reinforcing region and in the bending region, and at least partially disposed on the film in the chip mounting region; A chip, the chip being mounted on a portion of the conductive pattern layer located in the chip mounting region; A first insulating layer, the first insulating layer having a first elastic modulus, extending above the conductive pattern layer in the reinforcing region, and not located in the bending region; And A second insulating layer, the second insulating layer having a second elastic modulus and extending above the conductive pattern layer in the bending region, the second insulating layer being disposed adjacent to the first insulating layer in the horizontal direction, wherein the first elastic modulus is greater than the second elastic modulus, and the film is integral in the chip mounting region.

2. The chip - on - film package according to claim 1, wherein, The first elastic modulus is in the range of 5 GPa to 20 GPa, and the second elastic modulus is in the range of 0.5 GPa to 2 GPa.

3. The chip - on - film package according to claim 1, wherein, The thickness of the film is in the range of 10 μm to 30 μm.

4. The chip - on - film package according to claim 1, wherein, The first insulating layer comprises polyimide, and the second insulating layer comprises polyurethane.

5. The chip - on - film package according to claim 1, wherein, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

6. The chip - on - film package according to claim 5, wherein, The thickness of the first insulating layer is in the range of 15 μm to 25 μm, and the thickness of the second insulating layer is in the range of 5 μm to 15 μm.

7. The chip - on - film package according to claim 1, wherein, The length of the second insulating layer is in the range of 1.5 mm to 3.0 mm.

8. The chip - on - film package according to claim 1, wherein, The second insulating layer also extends across the conductive pattern layer in the reinforcing region.

9. The chip - on - film package according to claim 8, wherein, The second insulating layer also extends on the top surface of the first insulating layer.

10. A chip - on - film package, the chip - on - film package comprising: A film, the film comprising: a first pad region at one end of the film, a second pad region at the other end of the film, a chip mounting region between the first pad region and the second pad region, a first reinforcing region between the chip mounting region and the first pad region, a second reinforcing region between the chip mounting region and the second pad region, and a bending region between the second reinforcing region and the second pad region; A first conductive pad, the first conductive pad being disposed on the first pad region; A second conductive pad, the second conductive pad being disposed on the second pad region; A first conductive wire, the first conductive wire extending from the chip mounting region through the first reinforcing region and respectively connected to the first conductive pad; A second conductive wire, the second conductive wire extending from the chip mounting region through the second reinforcing region and the bending region and respectively connected to the second conductive pad; A chip, the chip being mounted on a portion of the first conductive wire located in the chip mounting region and / or a portion of the second conductive wire located in the chip mounting region; A conductive bump, the conductive bump being disposed between the first conductive wire and the chip and between the second conductive wire and the chip; A sealing member that covers at least a part of the top surface of the chip mounting area and at least partially surrounds the conductive bumps; A first insulating layer having a first elastic modulus, exposing the first conductive pad, covering the first conductive wire in the first reinforcing area and covering the second conductive wire in the second reinforcing area, and not located in the bending area; and A second insulating layer having a second elastic modulus, exposing the second conductive pad, and covering the second conductive wire in the bending area, wherein the first insulating layer and the second insulating layer located on the top surface of the second conductive wire are arranged to be adjacent to each other at least in the horizontal direction, the first elastic modulus is greater than the second elastic modulus, and the sealing member does not contact the bottom surface of the film in the chip mounting area.

11. A display module, the display module comprising: The chip-on-film package according to claim 10; A circuit board attached to the first conductive pad; and A display panel attached to the second conductive pad.

12. The display module according to claim 11, wherein the display module further comprises: A first adhesion portion that attaches the first conductive pad to the circuit board; And A second adhesion portion that attaches the second conductive pad to the display panel.

13. The display module according to claim 11, wherein The attachment length between the chip-on-film package and the display panel is in the range of 200 μm to 600 μm.

14. An electronic device, the electronic device comprising: A housing; And The display module according to claim 11, the display module being disposed in the housing, wherein the bending area is bent such that the second conductive pad is attached to the top surface of the display panel, and the chip is disposed between the film and the bottom surface of the display panel.

15. The electronic device according to claim 14, wherein The bending radius of the bending area is in the range of 200 μm to 800 μm.

16. A chip - on - film package, the chip - on - film package comprising: A film including a reinforcing area, a bending area, and a chip mounting area; A first conductive pattern layer disposed on the top surface of the film; A second conductive pattern layer disposed on the bottom surface of the film; A via that penetrates the film and connects the first conductive pattern layer and the second conductive pattern layer; A chip mounted on a portion of the first conductive pattern layer located in the chip mounting area; A first insulating layer having a first elastic modulus, covering at least a portion of the first conductive pattern layer adjacent to the chip and located on the reinforcing area, and not covering the portion of the first conductive pattern layer located on the bending area; A second insulating layer having a second elastic modulus and covering at least a portion of the first conductive pattern layer spaced apart from the chip and located on the bending area, the second insulating layer being arranged to be adjacent to the first insulating layer in the horizontal direction; And A third insulating layer having a third elastic modulus and covering at least a part of the bottom surface, wherein the first elastic modulus is greater than the second elastic modulus.

17. The chip - on - film package according to claim 16, wherein The first insulating layer includes polyimide, and the second insulating layer includes polyurethane.

18. The chip - on - film package according to claim 16, wherein The length of the second insulating layer is in the range of 1.5 mm to 3.0 mm.

19. The chip - on - film package according to claim 16, wherein The first elastic modulus is greater than the third elastic modulus.

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