Semiconductor Manufacturing

Abstract

In-situ patterning of a semiconductor structure is performed using one or more "shadow walls" (408) in combination with an angled (110) deposition beam. The shadow wall protrudes outward from the surface of the substrate to define an adjacent shadow region in which deposition is prevented by the shadow wall inhibiting the passage of the angled deposition beam. Therefore, deposition does not occur on the surface portion of the semiconductor structure within the shadow region. The shadow wall can therefore be used to achieve selective patterning of the semiconductor structure. The shadow wall itself is formed of semiconductor. In one implementation, the semiconductor structure and one or more shadow walls used to selectively pattern the semiconductor structure can be formed using selective area growth (SAG).

Description

Technical Field

[0001] The present disclosure relates to semiconductor fabrication. By way of example and not limitation, an example application of the disclosed technology is in the fabrication of superconductor-semiconductor nanostructures for use in quantum computers. Background Art

[0002] Quantum computing is a type of computing that uses inherent quantum mechanical phenomena, such as quantum state superposition and entanglement, to perform certain calculations at speeds far exceeding any conventional computer can achieve. In a "topological" quantum computer, calculations are performed by manipulating quasi-particles that appear in certain physical systems, known as "non-Abelian anyons". Anyons have unique physical properties that distinguish them from both fermions and bosons. Non-Abelian anyons also have unique properties relative to Abelian anyons. These unique properties serve as the basis for topological quantum computing, in which information is encoded as the topological properties of non-Abelian anyons; in particular, encoded as the braiding of its space-time world lines. This has certain benefits relative to other models of quantum computing. A key benefit is stability, because quantum braiding is not affected by disturbances of a certain scale, which may cause quantum decoherence that causes errors in other types of quantum computers.

[0003] Broadly speaking, two types of physical systems have so far been considered as potential hosts for non-Abelian anyons, namely the "5 / 2 fractional quantum Hall" system in condensed matter physics, and (more recently) semiconductor-superconductor (SM / SC) nanowires. Regarding the latter, a key advance in the field has been the realization of non-Abelian anyons in the form of "Majorana zero modes" (MZMs), which can be formed in semiconductor (SM) nanowires (NWs) coupled to superconductors (SCs).

[0004] One of the problems encountered in the context of SM / SC nanowires is the presence of so-called "soft gap" states. The soft gap problem has been documented in the open literature and it is sufficient to state that these soft gap states (when present) are the source of decoherence for the MZM. Analytical and experimental results have shown that the source of the soft gap is disorder in the SM / SC interface and recent work in this area has been conducted to improve the quality of the SM / SC interface with the aim of providing more stable MZMs. Summary of the invention

[0005] Aspects of the present disclosure generally relate to in-situ patterning of semiconductor structures using one or more "shadow walls" in combination with an angled deposition beam. The shadow wall protrudes outward from the surface of the substrate to define an adjacent shadow region, in which deposition is prevented by the shadow wall inhibiting the passage of the angled deposition beam. Therefore, deposition does not occur on the surface portion of the semiconductor structure within the shadow region. The shadow wall can therefore be used to achieve selective patterning of semiconductor structures and has various advantages over alternative selective patterning techniques, such as template masks (which are difficult to align to the necessary level of accuracy) and selective etching (which may reduce the quality of the semiconductor structure). The shadow wall itself is formed of semiconductor, which has various advantages including those described below. In one implementation, a semiconductor structure and one or more shadow walls for selectively patterning the semiconductor structure can be formed by using selective area growth (SAG).

[0006] A first aspect of the present disclosure provides a semiconductor manufacturing method. In a masking stage, a mask layer is formed on a substrate. The mask layer exposes at least one wall region and at least one component region of the substrate, and the component region is adjacent to the wall region in the plane of the substrate. In a selective area growth (SAG) stage, a selective area of ​​a crystalline semiconductor is grown in the exposed region of the substrate, wherein the wall region and the component region have relative dimensions in the plane of the substrate that cause a shadow wall component formed by the crystalline semiconductor in the wall region to grow in the component region to a height higher than that of a device component formed by the crystalline semiconductor. In a deposition stage, a deposition material layer is selectively deposited on the device component using a deposition beam, the deposition beam having a non-zero incident angle relative to the normal of the plane of the substrate and an orientation in the plane of the substrate, so that the shadow wall component prevents deposition of deposition material on a surface region of the device component adjacent to the shadow wall component.

[0007] That is, both the shadow wall and the device components are formed from semiconductors under SAG conditions. In addition to not having to use a template mask or etching in a stage that may damage the semiconductor device components, there are additional benefits to using SAG to form the shadow wall from the semiconductor. For example, an alternative solution would be to form the shadow wall from a mask dielectric. However, it has been found that semiconductor shadow walls are less prone to loss of selectivity during the deposition stage than dielectric shadow walls. The loss of selectivity exhibited by dielectric shadow walls can significantly reduce the quality of the local deposited material layer formed during the deposition stage. In addition, compared to semiconductor shadow walls, large dielectric shadow walls can also inhibit the growth of semiconductors during the SAG stage.

[0008] A second aspect of the present disclosure provides a method for selectively patterning a semiconductor nanostructure with a deposition material, the method comprising: using a deposition beam to selectively deposit a deposition material layer on the semiconductor nanostructure, the semiconductor nanostructure being located on a substrate surface and adjacent to a semiconductor shadow wall on the substrate surface; wherein the semiconductor nanostructure and the adjacent semiconductor shadow wall are disconnected and separated at a non-zero distance within the plane of the substrate, and wherein the substrate surface is substantially parallel to the plane of the substrate, and the deposition beam has a non-zero incident angle relative to a normal to the plane of the substrate and an orientation in the plane of the substrate, so that the shadow wall assembly prevents deposition on a surface portion of the semiconductor nanostructure within a shadow area defined by the semiconductor shadow wall.

[0009] For example, the semiconductor structure and the deposited material layer selectively deposited thereon may be incorporated into a computer device (such as a quantum computer), the semiconductor nanostructure and the deposited material layer deposited thereon constituting a computing component of the computer device, which is controllable to perform computing operations. In this case, the semiconductor wall component may not be incorporated into the computer device, or may be incorporated into the computer device as a virtual component that does not perform any computing operations. For example, the computing component may include a set of qubits that can be controlled to perform quantum computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to better understand the present technology and to show how embodiments of the present technology may be implemented, reference is made to the following drawings by way of example only:

[0011] Figure 1 Schematic diagram showing a method for fabricating a SM / SC nanowire network;

[0012] Figure 2 shows a schematic perspective view of a SAG SM nanowire at the epitaxial growth stage, wherein superconducting material is deposited on and around the nanowire; and

[0013] Figure 3 shows a top view image of a SAG InAs nanowire network on a GaAs substrate;

[0014] Figure 4 An extension of the fabrication method is schematically shown, where in-situ patterning is used to create additional structures;

[0015] Figure 5 shows a schematic perspective view illustrating an example of in-situ patterning used to create a junction;

[0016] Figure 6 shows a schematic top view of in-situ patterning using multiple shadow walls;

[0017] Figure 7shows a schematic side view of a shadow wall adjacent to a nanowire of maximum height;

[0018] Fig. 8A and Figure 8B showing cross-sectional views of nanowires having different orientations relative to their crystal structures;

[0019] Fig.9A shows top-view images of semiconductor components having different orientations relative to their crystal structures;

[0020] Fig. 9B side-view images of semiconductor components having different orientations relative to their crystal structures are shown;

[0021] Fig. 9C shows a schematic top view of an arrangement in which the nanowire network is oriented at 45 degrees relative to an adjacent shadow wall;

[0022] Fig.9D Shows Fig. 9C a schematic perspective view of an arrangement of; and

[0023] Fig.10 Shown is a top-view image of the shadow wall and nanowires after selective semiconductor deposition. DETAILED DESCRIPTION

[0024] Embodiments of the present technique are described below. In the described embodiments, the technique is applied to the fabrication of SM-SC nanostructures. However, it should be noted that the technique has other useful applications and can generally be applied to any SAG semiconductor structure to selectively pattern with a deposited material layer.

[0025] Epitaxial semiconductor superconductor materials are promising platforms for gateable, low-dissipation superconducting electronics and superconducting quantum computing. In the context of topological quantum computing, superconducting nanowires (NWs) with strong spin-orbit coupling can support topological excitations, which can serve as the basis for fault-tolerant quantum information processing.

[0026] Current methods for synthesizing semiconductor superconducting materials for gateable superconducting nanowire electronics are based on two-dimensional planar materials (see, e.g., Shabani et al., PRB 93, 155402 (2016)) or bottom-up growth of nanowire materials (see, e.g., Krogstrup et al., Nature Mater. 14, 400-406 (2015)). Both approaches face challenges in scalability for different reasons. For the latter approach, very high quality SM / SC interfaces have been achieved. However, using this approach, the SM / SC nanowires that are to form part of the network must be grown individually, and once grown, must be placed individually on an insulating material to form the actual network. Therefore, extending this approach to larger networks presents very significant challenges.

[0027] In contrast, in the described embodiments of the present technology, the desired SM heterostructures such as SM nanowire networks are grown in situ on a substrate using selective area growth (SAG). In SAG, an amorphous mask layer - typically a dielectric oxide (SiOx, AlOx, etc.) - is formed on a substrate, which exposes one or more regions of the substrate (e.g., based on photolithography and selective etching). The SM material is then selectively grown only in one or more exposed regions by inducing appropriate growth conditions.

[0028] In a subsequent deposition stage, a SC layer is then formed epitaxially on the desired SM heterostructure.

[0029] To build a functional device, it may be necessary to only selectively pattern the desired SM heterostructure with a SC. One approach to achieve this goal is to epitaxially grow the SC in situ on the SM heterostructure so that the SC is deposited on the entire surface of the semiconductor, and then selectively remove (etch) the SC layer from the SM surface in certain areas to achieve the desired SC patterning. However, the techniques commonly used for selective removal of the SC (e.g., chemical etching, ion sputtering, reactive ion etching, anodization) can damage the underlying SM layer, resulting in poor quality of the SM and the entire device. Depending on the device, the degradation induced in the SM layer may have a serious impact on the device characteristics. In addition, the so-called "metal lift-off process" is not applicable to SC-SM devices that require the SC layer to be epitaxially grown on the SM surface.

[0030] In contrast, in the example of the manufacturing technology described herein, a specially made component is used to project a "shadow" that causes the material to form a patterned nanoscale structure during directional deposition on the substrate. The terms "shadow wall", "shadow mask", "smart wall" or simply "wall" are used interchangeably herein to refer to such components that protrude outward from the substrate. This allows a predetermined area of ​​the substrate to be excluded from the deposition of the material, thereby creating a nanoscale pattern. The area may be referred to as a "shadow area", which is an area where deposition is prevented because the shadow wall prevents the deposited material from entering these areas. These areas are exposed areas of the substrate surface adjacent to the shadow wall (i.e., they are next to the shadow wall on the substrate surface, not below them). The deposition beam is performed using an angled beam, and since the shadow wall protrudes outward from the substrate surface, they selectively prevent deposition in the exposed shadow area adjacent to the opposite side of the shadow wall where the beam is incident.

[0031] One option is to use the same mask dielectric to form the shadow wall on the SAG mask to a sufficiently large feature. The disadvantage of this technique is that the dielectric wall is prone to lose selectivity during SM growth. This can cause a large amount of parasitic polycrystalline to form on it, which in turn causes a significant degradation of the SC film quality during subsequent deposition.

[0032] When SAG is used, the large dielectric shadow wall can also prevent the growth of SM in the nearby area.

[0033] In contrast, in the described embodiments, the shadow wall is formed on the wafer by SM during selective area growth (SAG) of the semiconductor layer. That is, the shadow wall itself is a crystalline semiconductor component formed simultaneously and in the same manner (i.e., via SAG) as the semiconductor device component (e.g., nanowire) to be patterned.

[0034] For purposes of this disclosure, "wafer" will refer herein to the base layer, and "substrate" will refer to the wafer plus any other layers that have been deposited on the wafer at the current stage of the manufacturing process, including smart walls, masks, deposited materials, etc. However, it is important to note that references to layers, components, structures, etc. on a wafer do not necessarily mean that those layers / components / structures, etc. are necessarily in direct contact with the wafer surface (thus in a multi-layer substrate, all of these layers are referred to as being on a wafer).

[0035] It has been observed that SAG semiconductor systems under typical SAG conditions are "self-limiting" in that the height to which a SAG semiconductor component will grow depends on its size in the substrate plane, especially its width. This is used to grow the shadow wall to a height higher than the device component to be patterned in the SAG stage, thereby achieving the desired patterning effect in the subsequent deposition stage.

[0036] It has been demonstrated that under typical SAG conditions, the growth of thin area openings stops after the nanowires reach a pyramid shape, while it continues to grow over wider openings. This effect allows wide square mask openings to be intentionally grown near SAG nanowires in order to form SM walls suitable for shadow angled SC deposition.

[0037] This will be described in more detail below.First, some useful context is provided for the described embodiments.

[0038] Context:

[0039] refer to Figure 1 , an exemplary three-stage fabrication method will now be described. The fabrication method can be used to create SM / SC nanowire networks, which in turn can, for example, form the basis of quantum circuits (e.g., for quantum computers) or other hybrid semiconductor-superconductor platforms. In particular, the method is particularly suitable for fabricating SM / SC nanowire networks capable of hosting stable MZMs with no or significantly reduced soft-gap decoherence, which can form the basis of trouble-free topological quantum computing.

[0040] However, it is important to note that while the material platform is relevant to quantum computing, the gateable superconducting electronic products it provides may well have other applications outside of quantum computing or other applications not directly related to quantum computing, particularly in contexts requiring low energy consumption.

[0041] It is obvious that because the SM / SC nanowire network is created using SAG, the entire nanowire network can be manufactured as the entire substrate. The insulating mask layer and the nanowires can be directly incorporated into the final product without the need to transfer the nanowires to a different surface. Therefore, this method has greater scalability than existing methods.

[0042] 1) Masking stage

[0043] In the first phase P1 (masking phase), a patterned layer of dielectric material 102 (dielectric mask) is formed on top of wafer 104. Side and top views of wafer 104 with dielectric mask 102 are shown in FIG. Figure 1 . Wafer 104 may be formed of any suitable substrate material, such as InP (indium phosphide), GaAs (gallium arsenide), and in the depicted example is an insulating substrate (but in general may or may not be insulating depending on the application). In the depicted example, dielectric material 102 is an oxide, but it may be any dielectric material that promotes SAG in the second stage P2 of the manufacturing method (see below).

[0044] The oxide layer is patterned in that the oxide layer 102 is formed so that narrow strips of the substrate - in the intended area 106 - are exposed (i.e., not covered by the oxide 102). The pattern in this context refers to the structure of the intended area 106 that will eventually become the structure of the nanowire network, since it is the exposed area 106 in which the SM nanowires are grown. Thus, the size and structure of the nanowires match the size and structure of the exposed area 106. Although Figure 1 Only one exposed region 106 is shown, but nanowires can be grown in multiple regions simultaneously, and all descriptions about the intended region 106 apply equally to multiple such regions. Thus, the structure of the entire nanowire network can be defined by the structure of the (multiple) exposed regions. In this example, the strips and the resulting nanowires have a width on the order of tens or hundreds of nanometers.

[0045] The oxide layer 102 may be formed so as to expose the intended regions 106 in any suitable manner. For example, a uniform, continuous oxide layer may be deposited on the wafer 104, and the exposed regions 106 may then be formed by selectively etching away the oxide 102 from the intended regions 106 (in which case it is the etching that defines the final nanowire network structure). As another example, the oxide layer 102 may be selectively deposited on the wafer 104 through a mask that prevents the oxide 102 from being deposited in the intended regions 106 (in which case it is the mask that defines the final nanowire network structure).

[0046] The SAG nanowires are defined along a high symmetry in-plane crystal orientation on the substrate, which also gives well-defined cut faces of the nanowires. This makes the SC / SM interface flat, potentially atomically smooth, and well defined.

[0047] 2) SAG stage

[0048] In the second phase P2, the SAG phase, a semiconductor material 108 is selectively grown within the desired area 106 on top of the exposed portion of the wafer 104. Figure 1 An example is shown in the upper right portion of FIG, which shows a side view of the wafer 104. Due to the patterning of the oxide layer 102, the selectively grown semiconductor 108 forms in-plane nanowires (ie, the nanowires are located on the wafer 104).

[0049] SAG is a growth method that uses a crystal growth vacuum chamber. SAG refers to the local growth of a crystalline semiconductor (i.e., a semiconductor with a crystalline structure) in exposed areas of a substrate, where the growth conditions are selected to prevent such growth on the dielectric mask itself. For example, this can be based on chemical beam epitaxy (CBE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD). In the context of semiconductors, SAG refers to a specific class of epitaxial semiconductor growth (also known as selective area epitaxy) in which a patterned dielectric mask is used to define the intended structure of the semiconductor material to be grown (a form of lithography). The SAG process is adjusted so that semiconductor growth only occurs on areas of the substrate that are not covered by the dielectric mask, and not on the dielectric mask itself. This is completely different from other deposition / growth processes, such as bottom-up growth (in which no mask is used) and uniform deposition (epitaxial or otherwise), in which the material is deposited uniformly on the surface regardless of its material composition (such as stage P3 - see below). SAG is performed in a high vacuum or ultra-high vacuum and requires careful adjustment to achieve the desired selective semiconductor growth.

[0050] Any suitable SAG process may be used to create the desired SM nanowires in the exposed regions 106 in the second stage P2 .

[0051] SAG per-SM is known and will not be discussed in further detail herein. For further description of SAG, see, for example, GJ Davies, SPIE Conference Paper 2140, Epitaxial Growth Processes, 58 (May 11, 1994); doi: 10.1 117 / 12.175795; M Fahed, PhD Thesis: Selective Area Growth of In-Plane III-V Nanostructures Using Molecular Beam Epitaxy, 2016. http: / / www.theses.fr / 2016LIL 101 54; Fukui et al., Applied Physics Letters 58, 2018 (1991); doi: http: / / dx.doi.org / 10.1063 / 1.105026.

[0052] It can be said that the SAG phase P2 is such that the semiconductor material 108 fills the intended region 106 (i.e., the region 106 where the wafer 104 is not covered by the oxide mask 102) at the end of the phase, but does not extend beyond the boundaries of the intended region 106 in the plane of the wafer 104 (hereinafter the xy plane), as defined by the oxide layer 102. However, it can be seen that it does extend outwardly in an orientation (hereinafter the z orientation) in which the normal is oriented (perpendicular) to the plane of the wafer 104 so as to protrude outwardly from the oxide mask 102. That is, the semiconductor material 108 extends a greater distance from the wafer 104 in the z direction than the oxide layer 102. In this way, the semiconductor material 108 forms nanowires that are substantially located in the plane of the substrate 102 (in-situ nanowires).

[0053] The semiconductor material 108 may be any suitable semiconductor material, such as indium arsenide (InAs). The SAG semiconductor 108 may be, for example, a confined 2DEG (two-dimensional electron gas) semiconductor or a single material semiconductor.

[0054] 3) Superconductor growth stage

[0055] In the third stage P3, a superconducting material layer 112 is grown using a particle beam 110. Herein, a superconducting material refers to a material that exhibits superconducting properties at least under certain conditions. An example of such a material is aluminum (Al). In the following examples, a superconductor is epitaxially grown in the P3 stage, and the superconductor growth stage P3 may be referred to as an epitaxial growth stage in this context. However, the technology is not limited in this respect, and the desired results may be achieved via the non-epitaxial superconductor growth of the P3 stage. It will therefore be understood that although the following description relates to epitaxial superconductor growth by way of example, the related description is equally applicable to non-epitaxial semiconductor growth.

[0056] The P3 phase is generally referred to herein as a deposition phase, but may equally be referred to as an epitaxial growth phase or a semiconductor growth phase in the following description.

[0057] For example, the superconducting material 112 may be grown in stage P3 using molecular beam epitaxy (MBE) or electron gun epitaxy.

[0058] At least a portion of the superconductor layer 112 is deposited on top of the SM nanowires 108 such that the portion of the superconductor layer 112 ( Figure 1 116 in the figure) is in direct contact with the SM nanowire 108.

[0059] This is also a form of epitaxy, but not SAG. In particular, in the epitaxial growth stage P3, epitaxial growth does occur on the oxide layer 102 and on the SM nanowires 108.

[0060] As shown, the particle beam 110 is incident on the wafer 104 at a non-zero angle of incidence (deposition angle) relative to the z-direction. Due to this non-zero deposition angle and the protruding structure of the SM nanowire 108, the SM nanowire 108 is only partially coated by the superconductor layer 112; that is, a portion of the SM nanowire (labeled as 118) is not coated with the superconductor material. The main body of the oxide layer 102 is also coated with the superconductor layer 112, but due to the angle of the incident beam 110 and the protruding structure of the SM nanowire 108, some small areas of the oxide layer 102 adjacent to the protruding SM nanowire 108 are exposed, i.e., not coated with the SC material. One such area is Figure 1 The shadow gap 120 is marked as 120 in the figure. Such a region may be referred to herein as a "shadow gap". The shadow gap 120 separates the SM material 108 from a portion of the SC layer 112 in the "side gate" region 122. This portion of the SC layer 112 in the side gate region 122 can be used to form a gate for controlling the SM nanowires 108, or (more likely) the SC material can be etched away from this area and replaced with a more suitable gate material. Either way, the shadow gap 120 ensures that the gate operates as intended. Forming the shadow gap 120 using this "in situ" patterning in the SC epitaxy stage P3 (as described above) ensures that material does not need to be etched too close to the fine nanowires 108.

[0061] Figure 1 The lower right portion of shows a side view and a top view of the wafer 104 at the end of the third stage P3. Note that in the top view, the portion 116 of the superconductor layer 112 that partially coats the SM nanowires 108 is not distinguished from the uncoated portion 118 of the SM nanowires 108; instead, the combined nanowire structure formed by the nanowires 108 and the portion of the superconductor material 116 that (partially) covers those nanowires (i.e., is in direct contact with them) is depicted as a single element, labeled SM / / SC. This combined structure is similarly represented and labeled in subsequent figures, and references to "SM / SC nanowires" or "SM / / SC nanowires" herein refer to the SM nanowires 108 and the SC material 116 that (partially) covers the SM nanowires 108, unless otherwise specified.

[0062] To further help explain, Figure 2 A schematic perspective view of the first and second nanowires 108A, 108B during a third phase P3 is shown, which are partially coated by respective portions 116A, 116B of the superconductor layer 112. A shadow gap 120 of the type described above is shown, which is adjacent to the first nanowire 108A and separates the first nanowire 108A from a portion of the semiconductor layer 112 in the side gate region 122 in the manner described above.

[0063] The SAG stage P2 and the superconductor growth stage P3 can be performed in a vacuum chamber, preferably without moving the wafer 104 between stages. These stages can be performed under high vacuum or ultra-high vacuum conditions (~10 -8 –10 -12 Torr or less), and these vacuum conditions can be maintained between stages. This can, among other things, ensure that the SM / SC interface is clean and free of undesirable impurities.

[0064] It will be appreciated that both the SAG semiconductor growth in the P2 phase and the superconductor growth in the P3 phase require carefully calibrated conditions to enter the respective "growth windows" for the two phases, thereby achieving the desired semiconductor and superconductor growth, respectively. Depending on the material type, the growth conditions, temperature and flux need to be carefully selected. For example, for MBE (which can be used for the semiconductor SAG phase P2 and the superconductor growth phase P3), the substrate typically needs to be heated to a temperature of about 500 degrees Celsius or higher to clean the native oxide on the surface. However, in the SM SAG phase P2 and the SC growth phase P3, the respective temperature windows for the desired growth to occur depend on the composition of the SM material 108 and the SC material 112, respectively. The superconductor is grown / deposited in situ without breaking the vacuum. In this way, the surface of the SAG will not be oxidized in the air and remains clean until the SC is placed, thereby ensuring a clean SM-SC interface.

[0065] The wafer 104 and oxide layer 102 on which the SM / / SC nanowire network is grown can be combined with the SM / SC nanowire network in a final product, such as a quantum circuit or quantum computer, without transferring the nanowires from the substrate on which they were originally fabricated.

[0066] Embodiments of the disclosed technology include topologically protected quantum computing circuits that include nanowire networks formed using such mixed semiconductor and superconductor regions.

[0067] For ease of explanation, Figure 3 An image of a SAG InAS nanowire network grown on a GaAs substrate is shown.

[0068] In-situ patterning using SAG SM shadow wall

[0069] Embodiments of the present technology will now be described.

[0070] Figure 4 and Figure 5 Schematically shows Figure 1An extension of the method of wherein in the superconductor growth stage P3, a SAG SM shadow wall 408 is used in conjunction with the angled beam 110 to perform in-situ selective patterning of SAG SM nanostructures, such as nanowires 108. The shadow wall 408 is used to prevent deposition onto selected surface areas of the nanowires 108.

[0071] In the masking stage P1, the mask layer 102 exposes the wall region 406 adjacent to the nanowire region 106, except for the exposed region 106 where the nanowire 108 is to be formed. The widths of the wall region 406 and the nanowire region 106 are respectively W and W. SW and W NW Indicates that W SW >W NW .

[0072] In this context, the term "width" refers to the smallest dimension of the region in the xy plane. The exposed regions 106, 406 are shown as being substantially in the xy plane along their respective axes A. NW (Nanowire) and A SW (shaded wall axis) - represented by a dotted line -, and the width W of each zone SW ,W NW is the area perpendicular to its axis A in the xy plane SW , A NW range.

[0073] In SAG phase P2, crystalline semiconductor grows in exposed regions 106, 406 to form nanowires 108 and shadow walls 408 in wall and nanowire regions 106, 406, respectively. Nanowires 108 and shadow walls 408 are respectively formed along nanowire axes A. NW and the shadow wall axis A SW The larger width of wall region 408 causes the semiconductor in this region to grow to a height greater than its height (extent in the z-direction) grown in nanowire region 106, so shadow wall 408 has a greater height than adjacent nanowires 108. This is a result of the semiconductor crystal structure, as described in further detail below. Figure 4 4, the wall region 408 is adjacent to but not continuous with the nanowire region 106. Thus, the nanowire 108 is located near the shadow wall 408, but disconnected from it and separated from it by a non-zero distance (i.e., the nanowire 108 and the shadow wall 408 are not in contact with each other), but the distance is small enough that the surface portion of the nanowire 108 falls within the shadow region 404 defined by the shadow wall 408 and the direction of the angled beam 110 during the deposition stage P3.

[0074] In deposition phase P3, the superconductor layer 112 is formed as described above using the angled beam 110. However, the beam 110 has an orientation in the xy plane such that it is incident on the side(s) of the shadow wall 408 that is farthest from the nanowire 108. Due to this fact, and the fact that the beam 110 has a non-zero angle of incidence relative to the z-axis, the shadow wall prevents deposition in the shadow region 404 mentioned above where the surface portion of the nanowire 108 is located. In addition, the greater height of the shadow wall 408 causes the shadow region 404 to extend across the entire width of the nanowire 108. This creates a "junction", i.e., a section of the nanowire that is uncoated (i.e., uncoated over its entire width) that is located at the surface region of the nanowire 106 at both ends of the junction - at Figure 4 In the junction, the nanowire 106 is partially coated with the semiconductor material 112 (i.e., partially coated across its width). This can be Figure 4 A top view of a substrate in deposition stage P3 and a top view showing a substrate in deposition stage P3 Figure 5 as seen in the perspective view.

[0075] Note, however, that shadow region 408 does not generally have to extend across the entire width of nanowire 108 to form a junction. As discussed above, the shape of nanowire 108 and the angle of beam 110 means that even portions of the nanowire surface outside of shadow region 404 are only partially coated across their width (because beam 110 is only incident on one facet of nanowire 108). Thus, to form a junction region where the nanowire is only uncoated across its width, it is only necessary that shadow region 404 extend across the entire width of the surface region on which deposition would otherwise occur (if no shadow wall 408 were present). For example, Fig.10 A top view image of a SAG shadow wall 408 is shown defining a shadow region 404 extending at least approximately to the vertex 1002 of the nanowire 108, having a triangular profile in a plane perpendicular to its axis. That is, the shadow region 404 extends across the width of the facet of the nanowire 108 facing the incident beam 110, but does not extend across the opposing facet and need not do so since deposition will not occur on that facet in any case.

[0076] Figure 6 is a schematic top view showing how multiple SAG SM shadow walls 408 can be used to achieve more complex selective patterning of SAG SM nanowires 106.

[0077] Shadow wall height:

[0078] Figure 7 is a schematic cross-sectional view of a nanowire 108 and a shadow wall 408 , illustrating the high-level principle that causes the height of the shadow wall 408 to exceed the height of the adjacent nanowire 108 . Figure 7The vertical direction of the nanowire axis A is shown. NW During SAG phase P2, shadow wall 408 and nanowire 108 gradually grow in height. Nanowire 108 has side surfaces that taper inwardly, and during the initial portion of SAG phase P2, nanowire 108 will have a generally trapezoidal profile as it continues to grow in height. However, eventually the side surfaces of nanowire 108 will "meet" at time t1, forming a complete triangle. After time t1, even if SAG conditions persist, no significant further growth of nanowire 108 will occur: nanowire 108 has now reached its maximum height, as indicated by Figure 7 In contrast, at time t1, shadow wall 408 has not yet reached its maximum height due to its greater width, and thus can continue to grow after time t1. Figure 7 In the example of FIG. 4 , the SAG phase is terminated (ie, the SAG condition is terminated) at time t2 before the shadow wall 408 reaches its maximum achievable height, such that the shadow wall 408 has a substantially flat top surface.

[0079] Fig.10 The example image of shows the effect of such a shadow wall 408 on such a nanowire 108 during deposition stage P3. In this case, the greater height of the shadow wall 408 causes the shadow region 404 to extend all the way to the apex of the nanowire 108.

[0080] return Figure 7 , nanowire 108 and shadow wall 408 are shown as having substantially triangular and trapezoidal profiles, respectively, in a plane perpendicular to the nanowire axis. However, the profiles of shadow wall 408 and nanowire 108 may actually be based on their respective axes A. SW and A NW They are controlled relative to the orientation of the crystal structure of the semiconductor from which they are formed - or more generally, based on the orientation of their large-scale structure relative to their atomic, crystal structure (note that "large" in this context is relative, meaning on a scale of typically 10s or 100s of nanometers).

[0081] Now refer to 8A to 9D Describe this.

[0082] Fig. 8A Schematic cross-sections of nanowires with different orientations relative to their crystal structure are shown. Again, the cross-sections are taken perpendicular to the nanowire A. NW The plane of the axis.

[0083] exist Fig. 8A In the middle, the nanowire axis A NW(lying in a plane perpendicular to the page) oriented substantially parallel to directions having Miller indices [1-10] as defined by the crystal structure of the SM nanowire 108 .

[0084] exist Figure 8B In the middle, the nanowire axis A NW Oriented substantially parallel to the direction having the Miller index

[110] .

[0085] Miller indices are an established method for characterizing directions within a crystal structure that is defined by its intrinsic symmetry.

[0086] It should be understood that the [1-10] and

[110] directions are perpendicular to each other, so Fig. 8A and 8B The [1-10] and

[100] nanowires can form part of a network of mutually perpendicular nanowires (perpendicular to the plane of the substrate). Two examples of nanowire networks containing mutually perpendicular nanowires are described herein. In the first example, the nanowires within the network are oriented in the

[110] and [1-10] directions (e.g., Fig. 8A , Figure 8B and the following description Fig. 9B In the second example, the nanowires are oriented along the

[010] and

[100] directions (see Fig. 9C and 9D and described below).

[0087] It can be seen that the SAG[1-10] line has a substantially triangular profile when a cross section is taken along its width, while the SAG

[110] line has a substantially vertical underside surface (although the top tapers slightly inward to a substantially flat top surface). Fig. 8A and 8B For example, while the figures show that the angles of the cross-sections of the

[100] and

[110] wires are approximately the same, in reality the angle of the cross-sections of the

[100] and

[010] nanowires is approximately 45 degrees, while the angle of the cross-sections of the [1-10] nanowires is approximately 54.7 degrees.

[0088] This is the physical effect of atomic crystal structure orientation on the large-scale growth of semiconductors under SAG conditions. FIG. 9A to FIG. 9D Examples are given of how this physical effect can be exploited to optimize the growth of shadow walls and complex nanowire networks.

[0089] Fig. 9C A schematic top view of a network 900 of nanowires in a plane is shown. The network is formed by nanowires, each of which is located in one of two mutually perpendicular directions in the xy plane. These are chosen to be substantially parallel to the directions having Miller indices

[100] and

[010] , respectively.

[0090] The adjacent shadow walls are oriented at 45 degrees relative to the network of in-plane nanowires 900, thereby substantially along the direction having the Miller index

[110] .

[0091] Fig.9A Top view images of SAG SM assemblies grown in different directions relative to their crystal structure are shown. The left image shows a SAG SM assembly with its outer sides (sides) aligned with the

[100] and

[010] directions in the xy plane. It can be seen that all four sides taper gradually inward. Therefore, when the cross section is perpendicular to the

[100] or

[010] axis, the assembly will have a trapezoidal profile. The component has a substantially flat top surface because the SAG condition was terminated before reaching its maximum height. If the SAG stage continued long enough for the assembly to reach its maximum height, it would have a triangular profile in both cross sections. Return Fig. 9C , it is therefore clear that the nanowires in network 900 will have triangular profiles in the

[010] and

[100] directions, assuming they are grown all the way to their maximum height.

[0092] Fig.9A The right image of shows a semiconductor component with outer sides aligned with the

[110] and [1-10] directions, respectively, in the xy plane. It can be seen that the cross section of the component in the [1-10] direction will have a substantially trapezoidal profile, since the sides extending parallel to the [1-10] direction taper gradually inwards. Furthermore, if the component grows to its maximum height, it will become triangular: in fact, this can be seen in Fig. 9B This can be seen in the left image of , which shows a side view of a nanowire with its axis in the [1-10] direction and having grown to its maximum height.

[0093] However, returning to Fig.9A In the right image, it can be seen that the profile is different if the cross section is taken perpendicular to the

[110] axis. This is because the side surfaces extending parallel to the

[110] direction do not taper gradually inwards. To illustrate this, Fig. 9B The right image in shows a side view of a semiconductor component, with its axis parallel to the

[110] direction. It can be seen that the side surfaces (side surfaces) extending parallel to the

[110] direction are substantially vertical at the bottom of the semiconductor component and then taper to a flat top surface.

[0094] Now return to Fig.9A , it can be seen that the sides of the shadow wall parallel to the

[110] direction will be essentially vertical (i.e. Fig. 9B) - opposite to the tapered sides of the nanowire in the

[100] and

[010] directions. One benefit of this is that the resulting shadow junction will have a straight SC, rather than a tapered or angled SC, so the width of the resulting shadow region (shadow width) is the same at the top and bottom of the wire. That is, the vertical side surfaces of the shadow wall cause the boundary of the shadow region 404 to be substantially perpendicular to the nanowire A. NW The axis, such as Figure 4 Top view of the P3 stage and Figure 5 , thereby forming an uncoated junction region having a substantially uniform width across the width of the nanowire 108. Fig.10 In contrast to the example of , where the tapering profile of the trapezoidal shadow wall 408 causes the shadow region 404 to taper from the base of the nanowire 108 to its apex 1002, so the junction of the uncoated nanowire exhibits a corresponding taper.

[0095] This is Fig.9D is schematically shown in Fig.9D Shows Fig. 9C The shadow area defined in the shadow wall 408 is represented by the white dashed line superimposed on the perspective view.

[0096] As is apparent from the above description, the relative crystal orientations of the crystalline semiconductor components (nanowires and smart walls) are determined by the mask pattern, and in particular the relative orientations of the exposed areas in the substrate plane. The "absolute" crystal orientation of the semiconductor is determined by the crystal structure of the wafer 104 itself, on which the semiconductor is selectively grown. The selective area growth is epitaxial, meaning that each atom deposited in the SAG phase follows the same pattern as the existing atoms of the wafer 104. Thus, the crystal orientation of the semiconductor material will match that of the wafer 104. Thus, the

[100] and

[010] nanowires can grow perpendicular to the

[100] and

[010] directions of the crystal sheet 104 itself (i.e., as defined by the shell structure of the wafer 104), while the

[110] and [1-10] nanowires can grow perpendicular to the

[110] and [1-10] directions of the crystal sheet 104. This means that the desired vertical profile of the nanowires 108 and shadow walls 408 can be achieved by proper orientation of the exposed areas where they grow relative to the crystal structure of the wafer 104 .

[0097] The SM / SC nanostructure thus generated - that is, the nanowire 108 or the network portion of such nanowire is coated with a superconductor 112 - can be incorporated into a computer device, such as a quantum computer. The SM / SC nanostructure constitutes an operational computing component of a computer device, which is controllable (for example, through one or more gates) to perform useful computing operations. In the case of a quantum computer, these may be quantum calculations implemented by manipulating qubits. In the case of SM / SC nanowires, qubits are typically embodied as entangled quantum states of quasi-particles carried in SC / SM nanowires. In contrast, the shadow wall 408 can be completely excluded from the computer device (where feasible), or it can be incorporated into the computer device but as a virtual component that does not perform any useful computing operations. Assuming that the shadow wall 408 is separated from the SM / SC nanowire by a sufficient distance, the former will not significantly interfere with the operation of the latter.

[0098] Other aspects of the disclosure and example embodiments thereof are set forth below.

[0099] Please note that the above-mentioned first aspect of the present disclosure provides a semiconductor manufacturing method, which includes: in a masking stage, forming a mask layer on a substrate, wherein the mask layer exposes at least one wall region and at least one component region of the substrate, and the component region is adjacent to the wall region in the plane of the substrate; in a selective area growth (SAG) stage, inducing selective area growth of a crystalline semiconductor in the exposed region of the substrate, wherein the wall region and the component region have relative sizes in the plane of the substrate that cause a shadow wall component formed by the crystalline semiconductor in the wall region to grow in the component region to a height higher than that of a device component formed by the crystalline semiconductor; and in a deposition stage, selectively depositing a deposition material layer on the device component using a deposition beam, the deposition beam having a non-zero incident angle relative to the normal of the plane of the substrate and an orientation in the plane of the substrate so that the shadow wall component prevents deposition of deposition material on a surface region of the device component adjacent to the shadow wall component.

[0100] The surface area is the portion of the surface of the equipment component that is located in the shadow area defined by the shadow wall component.

[0101] In embodiments, the device components may be nanowires located within the plane of the substrate.

[0102] The nanowire may be part of a network of nanowires formed from a crystalline semiconductor, the network of nanowires lying in the plane of the substrate.

[0103] The height of the shadow walls may exceed the height of the nanowire in number such that no deposition occurs in the junction region extending across the entire width of the nanowire, including the surface region where deposition is prevented by the shadow walls.

[0104] This is not to say that the shaded region necessarily extends across the entire width of the nanowire (although this possibility is not excluded), as there may be a region of the nanowire where, due to the angle of incidence and the plane orientation of the beam, no deposition will occur anyway.

[0105] For example, the nanowire may have at least two opposing facets, and the incident angle and orientation of the beam are such that deposition occurs only on a first of these facets, wherein the shadow wall assembly is positioned closest to the first facet, such that the surface region extends from the bottom of the nanowire closest to the shadow wall assembly across the entire width of the first facet to at least one boundary of a second facet closest to the shadow wall. The surface region from which deposition is prevented may be located within a shadow region defined by the shadow wall assembly, wherein the shadow region may extend across the entire width of the first facet to at least the boundary of the second facet, but not across the entire width of the nanowire, and the junction region includes a surface region within the shadow region and another surface region of the second facet outside the shadow region, but in no case deposition occurs thereon (by way of example, refer to Fig.10 , and a description in text).

[0106] The deposited material may be a superconductor material.

[0107] The SAG phase may continue after the device assembly reaches a maximum assembly height (ie, SAG growth conditions may persist), wherein the height of the shadow wall assembly continues to grow until the SAG phase is terminated while the height of the device assembly remains substantially fixed.

[0108] The maximum component height may be defined by the width of the component region and the orientation of the component region in the plane of the substrate relative to the crystal structure of the crystalline semiconductor.

[0109] The SAG phase can be terminated before the shadow wall reaches a maximum wall height such that the shadow wall has a substantially flat upper surface that is substantially parallel to the plane of the substrate.

[0110] The maximum wall height is limited by the width of the wall region and the orientation of the wall region relative to the crystal structure of the crystalline semiconductor.

[0111] The substrate may be arranged in the SAG stage such that the component regions have an orientation relative to the crystal structure of the crystalline semiconductor such that the device component is formed having a substantially triangular profile composition across a width of the device component.

[0112] The substrate may be arranged in a SAG phase such that the wall region has an orientation relative to the crystal structure of the crystalline semiconductor, resulting in a wall component being formed having two substantially vertical side surfaces.

[0113] The SAG stage can be epitaxial so that the crystal structure of the deposited crystalline semiconductor has an orientation that matches the crystal structure orientation of the substrate formed thereon. In this case, the desired profile can be achieved by appropriate orientation of the exposed region relative to the crystal structure of the exposed substrate.

[0114] The device assembly may be an elongated assembly extending along an axis of the device assembly within the plane of the substrate, wherein vertical side surfaces of the shadow wall are positioned relative to the elongated device assembly such that a surface area of ​​the shadow wall that prevents deposition has a boundary substantially perpendicular to the axis of the device assembly.

[0115] The width of the wall region may be greater than the width of the component region.

[0116] The wall region and the component region may extend along respective axes that are perpendicular to their width in the plane of the substrate.

[0117] The wall region and the module region may be discontinuous.

[0118] In an embodiment of the second aspect above (or indeed, in any aspect of the present disclosure), the computing component may include at least one qubit that is controllable to perform quantum computation.

[0119] The semiconductor mask walls may have a height (extending in a direction perpendicular to the plane of the substrate) that is higher than the surface portion of the semiconductor nanostructure within the mask region.

[0120] Semiconductor nanostructures may include nanowires or nanowire networks located in the plane of a substrate.

[0121] A third aspect of the present disclosure provides a method for selectively patterning a semiconductor nanostructure with a deposited material, wherein the semiconductor nanodevice is partially coated with a superconductor material for topological quantum computing, the method comprising: in a masking stage, forming a mask layer on a substrate, wherein the mask layer exposes at least one wall region and at least one device region of the substrate, the device region being adjacent to the wall region in the plane of the substrate; in a selective area growth (SAG) stage, inducing selective area growth of a crystalline semiconductor in the exposed region of the substrate; and in a deposition stage, selectively depositing a layer of superconductor material on the semiconductor nanodevice using a deposition beam, the deposition beam having a non-zero incident angle relative to the normal of the plane of the substrate and an orientation in the plane of the substrate, so that a shadow wall component prevents superconductor material from being deposited on a surface portion of the semiconductor nanostructure within a shadow region defined by the shadow wall component, wherein both the shadow wall component and the semiconductor nanostructure are formed from the crystalline semiconductor material in the SAG stage in the wall region and at least one device region, respectively, wherein the wall region and the device region have relative sizes in the plane of the substrate, which causes the range of the shadow wall component in a direction perpendicular to the plane of the substrate to exceed the range of the surface portion where the shadow wall prevents deposition.

[0122] The disclosed methods, devices, and systems should not be interpreted as limiting in any way. The technology from any example can be combined with the technology described in any one or more other examples. In view of the many possible embodiments to which the principles of the disclosed technology can be applied, it should be recognized that the embodiments shown are examples of the disclosed technology and should not be regarded as limitations on the scope of the disclosed technology. Although the subject matter has been described in language specific to structural features and / or method actions, it should be understood that the subject matter defined in the attached claims is not necessarily limited to the above-mentioned specific features or actions. On the contrary, the above-mentioned specific features and actions are disclosed as example forms of implementing the claims.

Claims

1. A semiconductor manufacturing method, the method comprising: In a masking phase, a mask layer is formed on a substrate, wherein the mask layer exposes at least one wall region and at least one component region of the substrate, the component region being adjacent to the wall region in a plane of the substrate; In a selective area growth (SAG) phase, inducing selective area growth of a crystalline semiconductor in an exposed area of ​​the substrate, wherein the wall region and the component region have relative sizes in the plane of the substrate such that a shadow wall component formed by the crystalline semiconductor in the wall region grows to a height higher than a device component formed by the crystalline semiconductor in the component region; as well as During a deposition phase, a layer of deposition material is selectively deposited on the device component using a deposition beam having a non-zero angle of incidence relative to a normal to the plane of the substrate and an orientation in the plane of the substrate such that the shadow wall assembly prevents deposition of the deposition material on a surface area of ​​the device component adjacent to the shadow wall assembly.

2. The method of claim 1, wherein the device component is a nanowire located within the plane of the substrate.

3. The method of claim 2, wherein the nanowire is part of a nanowire network formed from the crystalline semiconductor, the nanowire network being located in the plane of the substrate.

4. The method of claim 2, wherein the height of the shadow wall assembly exceeds the height of the nanowire in number such that no deposition occurs in a junction region extending across the entire width of the nanowire, the junction region including the surface region on which deposition is prevented by the shadow wall assembly.

5. A method according to claim 4, wherein the nanowire has at least two opposing cut surfaces, and the incident angle and the orientation of the deposition beam are such that deposition occurs only on a first of these cut surfaces, wherein the shadow wall assembly is positioned closest to the first cut surface such that the surface region extends from the bottom of the nanowire closest to the shadow wall assembly across the entire width of the first cut surface to at least one boundary of a second cut surface closest to the shadow wall assembly.

6. A method according to claim 5, wherein the surface area where deposition is prevented is located in a shadow area defined by a shadow wall component, wherein the shadow area extends across the entire width of the first cut surface to at least the boundary of the second cut surface, but does not extend across the entire width of the nanowire, and the junction area includes the surface area within the shadow area and another surface area of ​​the second cut surface outside the shadow area, but in no case will deposition occur on the other surface area. The method of claim 1 , wherein the deposited material is a superconductor material.

8. The method of claim 1, wherein the SAG phase continues after the equipment assembly reaches a maximum assembly height, wherein the height of the shadow wall assembly continues to grow until the SAG phase is terminated while the height of the equipment assembly remains fixed.

9. The method of claim 8, wherein the maximum component height is defined by a width of the component region and an orientation of the component region in the plane of the substrate relative to a crystal structure of the crystalline semiconductor.

10. The method of claim 8, wherein the SAG phase is terminated before the shadow wall assembly reaches a maximum wall height such that the shadow wall assembly has a flat upper surface that is parallel to the plane of the substrate.

11. The method of claim 10, wherein the maximum wall height is defined by a width of the wall region and an orientation of the wall region relative to a crystal structure of the crystalline semiconductor.

12. The method of claim 1, wherein the substrate is arranged in the SAG stage such that the component region has an orientation relative to a crystal structure of the crystalline semiconductor causing the device component to form a triangular profile spanning a width of the device component.

13. The method of claim 1, wherein the substrate is arranged in the SAG stage such that the wall region has an orientation relative to a crystal structure of the crystalline semiconductor, causing the shadow wall assembly to be formed with two vertical side surfaces.

14. A method according to claim 13, wherein the device component is a slender component, which extends along an axis of the device component within the plane of the substrate, and wherein the vertical side surface of the shadow wall assembly is positioned relative to the slender device component so that the surface area where the shadow wall assembly prevents deposition has a boundary perpendicular to the axis of the device assembly.

15. The method of claim 1, wherein the wall region has a width greater than a width of the component region.

16. The method of claim 1, wherein the wall region and the component region are discontinuous.

17. A method for selectively patterning a semiconductor nanostructure with a deposited material, the method comprising: selectively depositing a layer of deposition material on the semiconductor nanostructure using a deposition beam, the semiconductor nanostructure being located on a substrate surface adjacent to a semiconductor shadow wall on the substrate surface; wherein the semiconductor nanostructure and adjacent semiconductor shadow walls are disconnected and separated by a non-zero distance within the plane of the substrate, and wherein the substrate surface is parallel to the plane of the substrate, and the deposition beam has a non-zero angle of incidence relative to a normal to the plane of the substrate and an orientation in the plane of the substrate, such that a shadow wall assembly prevents deposition on a surface portion of the semiconductor nanostructure within a shadow region defined by the semiconductor shadow wall.

18. The method of claim 17, wherein the semiconductor nanostructure and the layer of the deposition material selectively deposited on the semiconductor nanostructure are incorporated into a computer device, wherein the semiconductor nanostructure and the layer of the deposition material deposited on the semiconductor nanostructure constitute a computing component of the computer device, and the computing component is controllable to perform computing operations, wherein the shadow wall component is not included in the computer device, or the shadow wall component is included in the computer device as a virtual component that does not perform any computing operations.

19. The method of claim 18, wherein the computational component is embodied as a set of qubits that are controllable to perform quantum computations.

20. A method of manufacturing a semiconductor nanodevice, the semiconductor nanodevice being partially coated with a superconductor material for performing topological quantum computing, the method comprising: In a masking phase, a mask layer is formed on a substrate, wherein the mask layer exposes at least one wall region and at least one device region of the substrate, the device region being adjacent to the wall region in a plane of the substrate; In a selective area growth (SAG) phase, inducing selective area growth of a crystalline semiconductor in an exposed region of the substrate; as well as In a deposition phase, a layer of superconductor material is selectively deposited on the semiconductor nanodevice using a deposition beam having a non-zero incident angle relative to a normal to the plane of the substrate and an orientation in the plane of the substrate, so that a shadow wall component prevents the superconductor material from being deposited on a surface portion of a semiconductor nanostructure within a shadow region defined by the shadow wall component, wherein both the shadow wall component and the semiconductor nanostructure are formed from the crystalline semiconductor in a SAG phase in the wall region and the device region, respectively, wherein the wall region and the device region have relative sizes in the plane of the substrate, and the relative sizes cause the extent of the shadow wall component in a direction perpendicular to the plane of the substrate to exceed the extent of the surface portion where the shadow wall component prevents deposition.

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